Group III-nitride transistor using a regrown structure

The embodiments of the present disclosure relate broadly to the field of integrated circuits, especially to Group III nitride transistors using regrowth structures.

Currently, Group III nitride transistors, such as gallium nitride (GaN) -based high electron mobility transistors (HEMTs), typically have a negative gate to the supply voltage in order to reduce the current in the transistor channel. It is a depletion mode (D mode) device that uses voltage. However, enhancement mode (E mode) devices that use a positive gate voltage relative to the power supply voltage to reduce current may be desirable for applications such as power switching. E-mode devices are made by controlling the thickness of the supply layer so that it is less than the critical thickness so that two-dimensional electron gas (2DEG) is not generated in the channel under the gate during the operation of the transistor.

<p> However, conventional recessed and deposition processes that form E-mode devices can result in traps and other imperfections at the interface between gates and channels.</p>

The embodiments will be readily understood by the following detailed description and accompanying drawings. For ease of explanation, the same reference numerals indicate the same components. The embodiments are shown by way of example and do not limit the shape of the accompanying drawings.<figref num="1">FIG. 6 is a schematic cross-sectional view of an integrated circuit (IC) device according to various embodiments.</figref><figref num="2">FIG. 3 is a schematic cross-sectional view of another IC device according to various embodiments.</figref><figref num="3">It is a cross-sectional view of the IC device after forming a layer stack on a substrate according to various embodiments.</figref><figref num="4">FIG. 3 is a schematic cross-sectional view of an IC device after source and drain formation according to various embodiments.</figref><figref num="5">FIG. 6 is a schematic cross-sectional view of an IC device after deposition and patterning of a dielectric layer according to various embodiments.</figref><figref num="6">FIG. 5 is a schematic cross-sectional view of an IC device after removing the barrier layer material according to various embodiments.</figref><figref num="7">FIG. 5 is a schematic cross-sectional view of an IC device after forming a regrowth structure according to various embodiments.</figref><figref num="8">FIG. 3 is a schematic cross-sectional view of an IC device after forming a gate terminal according to various embodiments.</figref><figref num="9">It is a flow chart which shows the IC device manufacturing method by various embodiments.</figref><figref num="10">It is a schematic diagram of the system example including the IC device according to various embodiments.</figref>

Embodiments of the present disclosure provide techniques and structures for Group III nitride transistors using a regrowth structure. The following detailed description will refer to the accompanying drawings that form part of this specification. In the drawings, the same reference numerals indicate the same parts, and embodiments in which the subject matter of the present disclosure can be implemented are exemplified. It should be understood that other embodiments may be used and that structural and logical changes are possible without departing from the scope of the present disclosure. Therefore, the following detailed description is not taken in a limited sense and the scope of the embodiments is defined by the appended claims and their equivalents.

For the purposes of this disclosure, "A and / or B" means (A), (B) or (A and B). For the purposes of this disclosure, "A, B and or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A). , B and C).

In the following description, "in certain embodiments" or "in embodiments" are used, but these refer to one or more embodiments that may be the same or different, respectively. In addition, "prepare," "include," "have," and the like used with respect to the embodiments of the present disclosure are synonymous. Also, "connected" refers to direct connection, indirect connection or indirect transmission.

"Connected" and its derivatives are also used herein. This "connected" means one or more of the following: That is, two or more elements are in direct physical or electrical contact, or two or more elements are indirect contact with each other and even cooperate or interact with each other, or with each other. It means that one or more other elements are connected between the elements that are supposed to be connected.

In various embodiments, "a second layer formed, deposited or constructed on top of a first layer" means that the second layer is formed, deposited or constructed on top of the first layer. Means that at least a portion of the second layer is in direct contact (eg, physical and / or electrical direct contact) or indirect contact (eg, between the two layers) of at least a portion of the first layer. It can mean that it has one or more other layers).

FIG. 1 is a schematic cross-sectional view of an integrated circuit (IC) device 100 according to various embodiments. The IC device 100 may be formed on the substrate 102. Substrate 102 generally includes a support on which a layer stack (or simply "stack 101") is deposited. In one embodiment, the substrate 102 is made of silicon (Si), silicon carbide (SiC), aluminum oxide (Al).₂O₃) That is, "sapphire", gallium nitride (GaN) and / or aluminum nitride (AlN). In other embodiments, other materials, including suitable group II-VI semiconductor material systems and group III-V semiconductor material systems, are also used for the substrate 102. In certain embodiments, the substrate 102 may be constructed of any material or any combination of materials on which the material of the buffer layer 104 can epitaxially grow.

The stack 101 formed on the substrate 102 may include an epitaxial deposit layer composed of different material systems forming one or more heterojunctions / heterostructures. Layers of stack 101 may be formed in situ. That is, the stack 101 may be formed on the substrate 102 in a manufacturing apparatus (for example, a chamber) that forms a constituent layer thereof (for example, epitaxially grows) without taking out the substrate 102.

In one embodiment, the stack 101 of the IC device 100 includes a buffer layer 104 formed on the substrate 102. The buffer layer 104 may provide a crystal structure transition between the substrate 102 of the IC device 100 and other components (eg, the barrier layer 106), thereby acting as a buffer layer or an insulating layer between the two. For example, the buffer layer 104 can relieve stress between the substrate 102 and other lattice mismatched materials (eg, barrier layer 106). In some embodiments, the buffer layer 104 may function as a channel for the mobile charge carriers of the transistor. In some embodiments, the buffer layer 104 may be undoped. The buffer layer 104 may be epitaxially connected to the substrate 102. In other embodiments, a nucleation layer (not shown) may be interposed between the substrate 102 and the buffer layer 104. In some embodiments, the buffer layer 104 may be composed of a plurality of sedimentary membranes or layers.

In some embodiments, the buffer layer 104 may include a group III nitride-based material, such as gallium nitride (GaN) or aluminum nitride (AlN). The thickness of the buffer layer 104 may be 1-2 μm in a direction substantially perpendicular to the surface of the underlying substrate 102. In other embodiments, the buffer layer 104 may have other suitable materials and / or thicknesses.

The stack 101 may further include a barrier layer 106 (also referred to as a "supply layer") formed on the buffer layer 104. A heterojunction may be formed between the barrier layer 106 and the buffer layer 104. The bandgap energy of the barrier layer 106 may be higher than that of the buffer layer 104. The barrier layer 106 may be a wider bandgap layer that supplies the mobile charge carriers, and the buffer layer 104 may be a narrower bandgap layer that provides channels or pathways for the mobile charge carriers. In some embodiments, the bandgap energy of the barrier layer 106 may be less than or equal to the bandgap energy of the regrowth structure 110.

The barrier layer 106 may be composed of any of a variety of suitable material systems, such as Group III nitride-based materials. The barrier layer 106 may contain, for example, aluminum (Al), indium (In), gallium (Ga) and / or nitrogen (N). In some embodiments, the barrier layer 106 may be composed of a single layer of a single material. In one embodiment, for example, aluminum gallium nitride (Al)_xGa_1-xThe barrier layer 106 may be composed of a single layer of N) (x: a value of 0 to 1 representing the relative amount of aluminum and gallium). In other embodiments, the barrier layer 106 may be composed of a plurality of sedimentary films or layers. For example, as shown in FIG. 2, the IC device 200 has a barrier composed of a first barrier layer 107 arranged on the buffer layer 104 and a second barrier layer 108 arranged on the first barrier layer 107. Layer 106 may be provided. In some embodiments, aluminum nitride (AlN) constitutes the first barrier layer 107, and indium aluminum nitride (InAlN), aluminum gallium nitride (AlGaN), or indium gallium nitride aluminum (InGaAlN) forms the second barrier layer 108. It may be configured. In other embodiments, the barrier layer 106 may include other materials or more layers than those shown. The IC device 200 may conform to the embodiments described in relation to the IC device 100 of FIG.

Returning to FIG. 1, a two-dimensional electron gas (2DEG) is formed at the interface (for example, heterojunction) between the buffer layer 104 and the barrier layer 106, and the source terminal (hereinafter, source 112) and the drain terminal (hereinafter, drain 114) are formed. A current (for example, a movable charge carrier) may flow between them. In some embodiments, the IC device 100 may be an enhancement mode (E mode) device that uses a positive gate voltage with respect to the power supply voltage to allow current to flow through it. In these embodiments, the thickness T of the barrier layer 106 between the regrowth structure 110 and the buffer layer 104 is the critical thickness T for 2DEG formation.₀(For example, critical thickness T₀If less than 2DEG cannot occur), it may be less than. For example, the thickness T prevents the formation of 2DEG in the gate region of the channel located between the gate terminal (hereinafter "gate 118") and the buffer layer 104, while the gate region and the source 112 and the gate region. 2DEGs may be formed in the access area of the channel between and drain 114. In some embodiments, the thickness and / or aluminum content of the barrier layer 106 ensures that for device 100, which is either a Schottky gate device or a MIS gate device, all 2DEGs in the gate region. It may be selected to be removed. In another embodiment, the IC device 100 may be a depletion mode (D mode) device that uses a negative gate voltage with respect to the power supply voltage to reduce the current in it.

In some embodiments, the thickness T of the barrier layer 106 in the gate region is 30 Å or less. For example, the thickness T in the gate region of the barrier layer 106 composed of a single layer of AlGaN may be 20 Å or less. The thickness T at the gate region of the barrier layer 106 composed of AlN and / or InAlN may be 15 Å or less. In some embodiments, the thickness T of the barrier layer 106 may be 10 Å to 50 Å. In some embodiments, the thickness of the barrier layer 106 outside the gate region may be 160 Å to 300 Å in a direction substantially perpendicular to the surface of the buffer layer 104 below it. In other embodiments, the barrier layer 106 may have other suitable materials and / or thicknesses.

In various embodiments, the IC device 100 further comprises a regrowth structure 110 disposed within the barrier layer 106, as shown. The regrowth structure 110 may be referred to as "regrowth" to indicate that the material of the barrier layer 106 has been removed and the material of the regrowth structure 110 can be deposited or regrown there. In some embodiments, the regrowth structure 110 may function as an insulating layer of the gate 118 to obtain an E-mode device. A conventional recess process that protects the channel interface between the buffer layer 104 and the barrier layer 106 with an intervening barrier layer 106 (eg, the thickness T of the barrier layer 106) and exposes the channel interface as part of the gate recess / forming process. Alternatively, the insulating layer (eg, regrowth structure 110) may be allowed to form without the traps or other defects associated with the deposition process.

In some embodiments, as shown, the regrowth structure 110 may be epitaxially connected to barrier layer 106 (eg, first barrier layer 107 and second barrier layer 108 in FIG. 2). As shown, the regrowth structure 110 may be placed between the gate 118 and the buffer layer 104. In various embodiments, the bandgap energy of the regrowth structure 110 may be greater than that of the barrier layer 106 and the buffer layer 104. In certain embodiments, the bandgap of the regrowth structure 110 may be greater than or equal to 5 eV. For example, the bandgap energy of the regrowth structure 110 may be 5-6 eV. The bandgap energy of the regrowth structure 110 may be greater than that of the barrier layer 106 and / or the buffer layer 104. In some embodiments, the regrowth structure 110 may have an operating function that prevents the formation of 2DEGs in the gate region located between the gate 118 and the buffer layer 104. The regrowth structure 110 may be configured to block the channel of the IC device 100 to increase the area resistivity in the gate region (eg channel). For example, the area resistivity of a wafer having an AlGaN layer may be about 500 Ω / . After depositing a 100 Å thick GaN layer on top of the AlGaN layer using a low temperature process, the area resistivity may be about 1500 Ω / .

The regrowth structure 110 may be composed of any of a variety of suitable material systems, such as Group III nitride-based materials. The regrowth structure 110 may contain, for example, aluminum (Al), indium (In), gallium (Ga) and / or nitrogen (N). In some embodiments, the regrowth structure 110 may contain nitrogen (N) and at least one of aluminum (Al) or gallium (Ga). For example, gallium nitride (GaN), aluminum nitride (AlN), indium gallium nitride (InGaN), indium gallium nitride (InAlN), aluminum gallium nitride (AlGaN), or indium gallium nitride aluminum (InGaAlN) constitutes the regrowth structure 110. You may. In one embodiment, the regrowth structure 110 is made up of GaN and the barrier layer 106 is made up of AlGaN or AlN / InAlN (eg, the first barrier layer 107 in FIG. 2 is AlN and the second barrier layer 108 is InAlN. There is), and the buffer layer 104 is composed of GaN.

In various embodiments, Group III nitrides may be deposited using a high temperature (HT) process or a low temperature (LT) process to form the regrowth structure 110. The high temperature process is more crystalline (eg, for example) than the structure produced by the low temperature process by depositing Group III nitrides, such as GaN, at temperatures above 600 ° C (eg 700 ° C to 800 ° C). It may include a process of forming a structure (which is closer to a single crystal and less amorphous). The low temperature process is a process in which a group III nitride such as GaN is epitaxially deposited at a temperature of 600 ° C. or lower to form an amorphous or polycrystalline structure than the structure produced by the high temperature process. May be provided. For example, in one embodiment, the regrowth structure 110 may include GaN deposited by epitaxial deposition at a temperature of 350 ° C to 500 ° C. Since the high temperature process can produce a material with a piezoelectric regrowth structure 110 that makes it easier for the material to form ancillary traps, the high temperature process can be used to deposit the material to form the regrowth structure 110. Current collapse and gate leak in IC device 100 can increase. The formation of the regrowth structure 110 in a low temperature process results in a material with a more polycrystalline or amorphous lattice structure, which reduces trap formation and reduces current decay and gate leakage in the IC device 100. it can. In some embodiments, the regrowth structure 110 comprises a substantially polycrystalline or amorphous lattice structure formed by a low temperature process.

In various embodiments, the thickness of the regrowth structure 110 may be 200 Å or less. The thickness of the regrowth structure 110 may be, for example, 25 Å to 200 Å in a direction substantially perpendicular to the surface of the buffer layer 104 below the barrier layer 106. In other embodiments, the thickness and material of the regrowth structure 110 may be other.

The IC device 100 may further include a gate 118 disposed within the barrier layer 106 (eg, first barrier layer 107 and second barrier layer 108 in FIG. 2), as shown. The gate 118 may be configured to control a channel (eg, the on / off state of the IC device 100) as shown. The gate 118 may function as a connection terminal for the IC device 100, or may be in direct physical contact with the barrier layer 106 and the regrowth structure 110 as shown. In some embodiments, as shown, the gate 118 may be formed on a dielectric layer 116, such as, for example, silicon nitride (SiN) formed on the barrier layer 106 or another dielectric material.

As shown, the gate 118 separates from the trunk, or bottom, connected to the barrier layer 106 in the opposite direction, substantially parallel to the surface of the substrate 102 on which the stack 101 is formed. It may have a top that extends so as to. Such a configuration of the trunk and top of the gate 118 may be referred to as a T-shaped field plate gate. That is, in some embodiments, the gate 118 has an integrated field plate (eg, the top of the gate 118) that can increase the breakdown voltage between the gate 118 and the drain 114 and / or reduce its electric field. You may. The integrated field plate may facilitate high voltage operation of the IC device 100.

The gate 118 is provided between a gate electrode (eg, the gate electrode 118a in FIG. 8) that provides an electrical path to the threshold voltage of the IC device 100 and between the gate electrode and the barrier layer 106 and / or between the gate electrode and the regrowth structure 110. It may include a gate dielectric that can be arranged, that is, a gate insulator (hereinafter, referred to as a "gate insulator film", for example, the gate insulator film 118b in FIG. 8). The gate electrode may be made of a conductive material such as metal. In some embodiments, the gate electrode may be constructed of nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), gold (Au) and / or aluminum (Al). In one embodiment, a material containing Ni, Pt, Ir or Mo is placed within the trunk of the gate 118 to ensure gate contact with the barrier layer 106, ensuring the conductivity and low resistance of the gate 118. In addition, a material containing Au is placed within the top of the gate 118.

In various embodiments, the gate 118 may be configured to provide a Schottky junction or a metal-insulator-semiconductor (MIS) junction for the IC device 100. For example, if the gate insulating film is a gate dielectric or is not used at all, a Schottky junction may be formed, and if the gate insulating film is a gate insulator, a MIS junction is formed. May be done. In some embodiments, the gate dielectric may be a thin film that is smaller in thickness than the gate insulator. The gate insulating film is, for example, silicon nitride (SiN) or silicon oxide (SiO).₂), Aluminum oxide (Al₂O₃) And / or hafnium oxide (HfO)₂) May be included. In other embodiments, the gate insulator membrane may contain other materials.

The IC device 100 may include a source 112 and a drain 114 formed on the barrier layer 106. The source 112 and drain 114 may extend through the barrier layer 106 into the buffer layer 104, as shown. In various embodiments, the source 112 and drain 114 are ohmic contacts. The source 112 and drain 114 may be regrowth contacts, which may have relatively lower contact resistance than standard growth contacts.

The source 112 and drain 114 may be constructed of a conductive material such as metal. In certain embodiments, the source 112 and drain 114 may include titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au) and / or silicon (Si). In other embodiments, other materials are used.

In some embodiments, the distance D1 between the drain 114 and the gate 118 is greater than the distance S1 between the source 112 and the gate 118. In some embodiments, the distance D1 may be the shortest distance between the drain 114 and the gate 118, and the distance S1 may be the shortest distance between the source 112 and the gate 118. By making the distance S1 shorter than the distance D1, the breakdown voltage between the gate 118 and the drain 114 can be increased and / or the resistance of the source 112 can be reduced.

In some embodiments, the dielectric layer 122 may be formed on the gate 118 and / or the dielectric layer 116, as shown. The dielectric layer 122 may contain, for example, silicon nitride (SiN). In other embodiments, other materials are used for the dielectric layer 122. The dielectric layer 122 may substantially enclose the top of the gate 118. In some embodiments, the dielectric layer 122 may function as a protective layer for device 100.

The IC device 100 may further include a field plate 124 formed on the dielectric layer 122 to increase the breakdown voltage between the gate 118 and the drain 114 and / or reduce the electric field. The conductive material 126 may be used to electrically connect the field plate 124 to the source 112. The conductive material 126 may contain a metal such as gold (Au) deposited on the dielectric layer 122 as an electrode or a trace-like structure. In other embodiments, other suitable materials may be used for the conductive material 126.

The field plate 124 is made of a conductive material such as metal and may include the materials described in connection with the gate 118. The field plate 124 may be capacitively connected to the gate 118 through the dielectric layer 122. In some embodiments, the shortest distance between the field plate 124 and the gate 118 is 1000 Å to 2000 Å. The field plate 124 may be formed on top of the gate 118, as shown, so that a portion thereof is not directly formed on the top of the gate 118 so that an overhang region can be obtained. In some embodiments, the overhang region of the field plate 124 extends a distance H1 from the top end of the gate 118. In some embodiments, the distance H1 may be 0.2-1μ. In other embodiments, H1 may have other values.

In various embodiments, the IC device 100 may be a high electron mobility transistor (HEMT). In some embodiments, the IC device 100 may be a Schottky device. In other embodiments, it may be a MIS field effect transistor (MISFET). In some embodiments, the gate 118 may be configured to control switching of, for example, an E-mode switch device. IC device 100 may be used for radio frequency (RF) applications, logic applications and / or power conversion applications. For example, the IC device 100 provides an effective switch device for power switch applications, including power conditioning applications such as alternating current (AC) -direct current (DC) converters, DC-DC converters, DC-AC converters, etc. Can be done.

FIGS. 3-8 show devices after various manufacturing operations (eg, device 200 in FIG. 2). The methods and configurations described in relation to FIGS. 3-8 may be compatible with the embodiments described in relation to FIGS. 1-2, and vice versa.

FIG. 3 is a schematic cross-sectional view of the IC device 300 after forming a layer stack (for example, stack 101) on the substrate 102 according to various embodiments. In various embodiments, the IC device 300 may be made by depositing the buffer layer 104 on the substrate 102 and depositing the barrier layer 106 on the buffer layer 104. The barrier layer 106 may include a first barrier layer 107 deposited on the buffer layer 104 and a second barrier layer 108 deposited on the first barrier layer 107. In some embodiments, epitaxial deposition processes such as molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), chemical beam epitaxy (CBE) and / or metalorganic chemical vapor deposition (MOCVD) are used. The layers of stack 101 may be deposited. In other embodiments, other deposition processes may be used.

4, according to various embodiments, the source 112 and the drain is a schematic transverse sectional view of the in-114 after formation of the IC device 400. In various embodiments, the source 112 and drain 114 may be formed on the barrier layer 106 (eg, on the second barrier layer 108). In some embodiments, a material, such as one or more metals, is deposited on the barrier layer 106 within the region where the source 112 and drain 114 are formed, eg, using an evaporation process. The material for forming the source 112 and drain 114 may include metals deposited in the following order. Titanium (Ti), then aluminum (Al), then molybdenum (Mo), then titanium (Ti), then gold (Au). The deposited material is heated (eg, using a fast thermal annealing process at about 850 ° C × for about 30 seconds) to penetrate the material and the lower barrier layer 106 (eg, first barrier layer 107 and second barrier layer 107 and second). It may be melted with the barrier layer 108) and / or the buffer layer 104. In the embodiment, the source 112 and the drain 114 respectively extend into the buffer layer 104 via the barrier layer 106. The thickness of the source 112 and drain 114 may be 1000 Å to 2000 Å. In other embodiments, the thickness of the source 112 and the drain 114 may be other than this.

Source 112 and drain 114 may be formed in the regrowth process to obtain ohmic contacts with reduced contact resistance or reduced on-resistance. In the regrowth process, the material of the barrier layer 106 and / or the buffer layer 104 may be selectively removed (eg, etched) in the region where the source 112 and drain 114 are formed. High-concentration doped materials (eg, n ++ materials) may be deposited in areas where these layers have been selectively removed. The high concentration dope material for the source 112 and drain 114 may be similar to the material used for the buffer layer 104 or barrier layer 106. For example, in a system in which the buffer layer contains GaN, a GaN-based material heavily doped with silicon (Si) may be epitaxially deposited in the selectively removed region until the thickness becomes 400 Å to 700 Å. .. Molecular beam epitaxy (MBE), atomic layer epitaxial method (ALE), chemical beam epitaxial method (CBE), metalorganic vapor vapor deposition method (MOCVD), or a suitable combination thereof can be used to make the high-concentration doped material epitaxial. Can be deposited. In other embodiments, other materials, thicknesses or deposition methods are used for the high concentration doped material. One or more metals, including, for example titanium (Ti) and / or gold (Au), can be formed / deposited on the highly doped material to a thickness of 1000 Å to 1500 Å, for example using a lift-off process. In other embodiments, other materials, thicknesses and / or methods are used for the one or more metals.

In some embodiments, the source 112 and drain 114 may be formed by an injection process using an injection method that introduces impurities (eg, silicon) to provide the source 112 and drain 114 with a high concentration doped material. After injection, the source 112 and drain 114 may be annealed at high temperatures (eg 1100 ° C to 1200 ° C). In the regrowth process, the high temperature associated with the post-injection annealing can be suitably avoided.

FIG. 5 is a schematic cross-sectional view of the integrated circuit (IC) device 500 after deposition and patterning of the dielectric layer 116 according to various embodiments. In some embodiments, the dielectric layer 116 may be formed by depositing a dielectric material on the barrier layer 106. The dielectric layer 116 can include, for example, silicon nitride (SiN) or other suitable dielectric material, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) and / or atomic layer. It may be deposited using any suitable deposition process such as vapor deposition (ALD). The dielectric layer 116 may be patterned using any suitable process, such as a lithography and / or etching process, to form the gate recess opening 117 in the dielectric layer 116.

FIG. 6 is a schematic cross-sectional view of the integrated circuit (IC) device 600 after removal of the barrier layer 106 material according to various embodiments. In various embodiments, the material of the barrier layer 106 may be removed to form the gate recess opening 117 as shown. A regrowth structure (eg, the regrowth structure 110 in FIG. 7) can be subsequently formed on the barrier layer 106, and a gate (eg, the gate insulator film 118b and the gate electrode 118a in FIG. 8) can be formed on the barrier layer 106. May form a gate recess opening 117.

The material of the barrier layer 106 may be removed using any suitable process, including, for example, a dry / plasma or wet etching process (eg, a timed or selective etching process). In some embodiments, the dielectric layer 116 can act as a hardmask during the etching process of removing the material of the barrier layer 106.

In some embodiments, the material of the barrier layer 106 may be removed to obtain a thickness T that can be controlled by, for example, timed etching or selective etching as described in connection with FIG. In one embodiment, the material of the second barrier layer 108 is removed so that the lower boundary of the gate recess opening 117 is located within the first barrier layer 107. That is, the gate recess opening 117 may completely penetrate the second barrier layer 108. In some embodiments, the material of the first barrier layer 107 may be removed as shown. In some embodiments, the material of the first barrier layer 107 may be removed so that the material of the buffer layer 104 is not exposed to the gate recess opening 117. In other embodiments, the lower boundary of the gate recess opening 117 may be located at the upper boundary of the first barrier layer 107 without extending (eg, exceeding 5 Å). In other embodiments, the lower boundary of the gate recess opening 117 may be located within the second barrier layer 108 (eg, the gate recess opening 117 does not expose the material of the first barrier layer 107). ..

FIG. 7 is a schematic cross-sectional view of the integrated circuit (IC) device 700 after the regrowth structure 110 is formed according to various embodiments. The regrowth structure 110 may be formed by epitaxially depositing a group III nitride in the gate recess opening (eg, gate recess opening 117 in FIG. 6). For example, molecular beam epitaxy (MBE), atomic layer epitaxial method (ALE), chemical beam epitaxial method (CBE), metalorganic vapor vapor deposition method (MOCVD), or a suitable combination thereof deposits the regrowth structure 110. You may. In various embodiments, the deposition process may be carried out using the low temperature (LT) process described in connection with FIG. For example, in one embodiment, the regrowth structure 110 may include GaN deposited by epitaxial deposition at a temperature of 350 ° C to 500 ° C. In various embodiments, the thickness of the regrowth structure 110 may be 200 Å or less. The thickness of the regrowth structure 110 may be, for example, 25 Å to 200 Å in a direction substantially perpendicular to the surface of the buffer layer 104 below the barrier layer 106. In other embodiments, the thickness and material of the regrowth structure 110 may be other.

In some embodiments, the material deposited for the formation of the regrowth structure 110 is deposited as a capping layer 610 on the dielectric layer 116 during the deposition process used for the formation of the regrowth structure 110. May be good. In some embodiments, the dielectric layer 116 and / or the capping layer 610 may not be present in the final product of the IC device shipped to the customer, so that either or both of them may be present prior to gate formation. It may be removed.

FIG. 8 is a schematic cross-sectional view of an integrated circuit (IC) device 800 after formation of a gate (eg, gate 118 in FIG. 1) according to various embodiments. The gate may include a gate electrode 118a and, in some embodiments, a gate insulator membrane 118b.

In some embodiments, a dielectric material or an electrically insulating material may be deposited to form the gate insulation film 118b. The material of the gate dielectric film 118b is, for example, silicon nitride (SiN) or silicon oxide (SiO).₂), Aluminum oxide (Al₂O₃) And / or hafnium oxide (HfO)₂) May be configured. In other embodiments, other methods or materials may be used to form the gate dielectric film 118b. In some embodiments, the gate dielectric film 118 may not be used at all.

The gate electrode 118a may be formed by depositing a conductive material in the gate recess opening (eg, the gate recess opening 117 in FIG. 6). In the embodiment using the gate insulator film 118b, the gate electrode 118a may be deposited on the gate insulator film 118b. In the embodiment without the gate insulator film 118b, the gate electrode 118a may be deposited on the surfaces of the regrowth structure 110 and the barrier layer 106 as shown. The conductive material may be deposited by any suitable deposition process, including, for example, evaporation, atomic layer deposition (ALD) and / or chemical vapor deposition (CVD).

FIG. 9 is a flow chart showing a manufacturing method 900 of an integrated circuit device (for example, the IC device 100 or 200 of FIGS. 1 and 2) according to various embodiments. The method may be compatible with the methods and configurations described in connection with FIGS. 1-8.

Method 900 comprises in 902 forming a buffer layer (eg, buffer layer 104 in FIG. 1) on a substrate (eg, substrate 102 in FIG. 1). The step of forming the buffer layer may include a step of epitaxially depositing the buffer layer material on the substrate. In some embodiments, the buffer layer may be composed of a plurality of layers.

Method 900 may further include in 904 a step of forming a barrier layer (eg, barrier layer 106 of FIG. 1) on top of the buffer layer (eg, buffer layer 104 of FIG. 1). The step of forming the barrier layer may include a step of epitaxially depositing the barrier layer material on the buffer layer. In some embodiments, the barrier layer may be composed of a plurality of layers (eg, first barrier layer 107 and second barrier layer 108 in FIG. 2). In other embodiments, a single layer of material may be deposited to form a barrier layer.

Method 900 may further include in 906 a step of forming a source (eg, source 112 in FIG. 1) and a drain (eg, drain 114 in FIG. 1). In some embodiments, the source and drain may be connected to the barrier layer and extend through the barrier layer into the buffer layer.

Method 900 may further comprise in 908 the step of forming a regrowth structure (eg, regrowth structure 110 in FIG. 1) within the barrier layer. In some embodiments, the steps of forming the regrowth structure include removing the material of the barrier layer to form an opening (eg, the gate recess opening 117 in FIG. 6) and within the opening. It may be provided with a step of depositing the regrowth structural material. In some embodiments, the regrowth structure may be deposited in an epitaxial deposition process. In some embodiments, the step of depositing the regrowth structural material comprises depositing the regrowth structural material to a thickness of 200 Å or less.

Method 900 may further include in 910 a step of forming a gate terminal (eg, gate 118 in FIG. 1) within the barrier layer. In some embodiments, the step of forming the gate terminal comprises depositing a gate insulator film (eg, the gate insulator film 118b of FIG. 8) on the regrowth structure within the opening of the barrier layer. In some embodiments, the step of forming the gate terminal is the step of depositing the gate electrode material on the gate insulator membrane, or in the embodiment without depositing the gate insulator membrane, the regrowth structure in the opening of the barrier layer. A step of depositing a gate electrode material on the top is provided. The gate electrode may be connected to the material of the barrier layer to form a Schottky junction or a MIS junction. In various embodiments, the step of removing the material of the barrier layer and forming an opening therein may be part of the step of forming a regrowth structure within the barrier layer in 908, and 910. It may be part of a step of forming a gate terminal in the barrier layer in. The material of the barrier layer may be removed by an etching process to form an opening.

Method 900 may further include at 912 the step of forming a dielectric layer (eg, dielectric layers 116 and / or 122 in FIG. 1) on the gate. The dielectric layer may be deposited by any suitable deposition process. In various embodiments, the dielectric layer can serve as a protective layer for the IC device.

Method 900 may further include in 914 the step of forming a field plate on the dielectric layer. A field plate may be formed by depositing a conductive material on the dielectric layer using any suitable deposition method. The deposited conductive material portion can be selectively removed using a patterning process such as a lithography process and / or an etching process to form a field plate. In other embodiments, other suitable methods may be used.

The various operations are described as multiple separate operations in the order and method most useful for understanding the claimed subject matter. However, the order of description should not be construed to suggest that these operations are always order-dependent. These operations do not have to be performed in the order of presentation. The described operations may be performed in a different order from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

Embodiments of the IC devices described herein (eg, IC devices 100, 200 and 800 of FIGS. 1, 2 and 8) and devices comprising such IC devices may be incorporated into various other devices and systems. A block diagram of System Example 1000 is shown in FIG. As shown, system 1000 includes PA module 1002, which in some embodiments can be a radio frequency (RF) power amplifier (PA) module. System 1000 may include transceiver 1004 connected to power amplifier module 1002 as shown. The power amplifier module 1002 may include the IC devices described herein (eg, IC devices 100, 200 and 800 of FIGS. 1, 2 and 8).

The power amplifier module 1002 may receive an RF input signal (RFin) from the transceiver 1004. The power amplifier module 1002 may amplify the RF input signal (RFin) and output an RF output signal (RFout). The RF input signal (RFin) and RF output signal (RFout) are shown by Tx-RFin and Tx-RFout in FIG. 10, respectively, and both can be part of the transmission chain.

The amplified RF output signal (RFout) may be fed to the antenna switch module (ASM) 1006, which enables radio (OTA) transmission of the RF output signal (RFout) via the antenna structure 1008. Ru. The ASM1006 may also receive an RF signal via the antenna structure 1008 and connect the received RF signal (Rx) to the transceiver 1004 along the receive chain.

In various embodiments, the antenna structure 1008 includes, for example, a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna, or any other form of antenna suitable for OTA transmission / reception of RF signals. It may include one or more directional antennas and / or omnidirectional antennas.

System 1000 may be any system that includes power amplification. The power of an alternating current (AC) -direct current (DC) converter, a DC-DC converter, a DC-AC converter, etc., depending on the IC device (eg, IC devices 100, 200, and 800 in FIGS. Effective switch devices for power switch applications, including conditioning applications, may be provided. In various embodiments, the system 1000 may be particularly useful for high radio frequency power and power amplification at frequencies. System 1000 may be suitable for, for example, land and satellite communications, radar systems, and perhaps any one or more in a variety of industrial and medical applications. More specifically, in various embodiments, the system 1000 can be one selected from a radar device, a satellite communication device, a mobile phone, a mobile phone base station, a radio broadcast or a television amplifier system.

Although embodiments have been exemplified and described for purposes of illustration, they are provided without departing from the scope of the present disclosure by a wide range of alternative and / or equivalent embodiments or embodiments intended to achieve the same purpose. The embodiments can be replaced. This application is intended to cover any adaptations or variations to the embodiments discussed herein. Therefore, it is clear that the embodiments described herein are limited only by the claims and their equivalents.