Oxide semiconductor device

The technical field of the disclosed invention relates to a semiconductor film including an oxide semiconductor. Alternatively, the present invention relates to a semiconductor device using the semiconductor film.

The field effect transistor is one of the most widely used semiconductor devices. The materials used for the field-effect transistor vary depending on the application, but in particular, semiconductor materials containing silicon are often used.

Field-effect transistors using silicon meet the characteristics required for many applications. For example, the requirement is satisfied by using single crystal silicon for applications such as integrated circuits that require high-speed operation. Further, for large area applications such as display devices, the requirement can be satisfied by using amorphous silicon.

As described above, silicon has high versatility and can be used for various purposes, but in recent years, there has been a tendency to demand more versatility and further performance from semiconductor materials. For example, from the viewpoint of improving the performance of a large-area display device, in order to realize high-speed operation of a switching element, a semiconductor material that can easily increase the area and has a performance exceeding that of amorphous silicon is required. ..

In such a situation, a technique related to a field effect transistor (also called a FET) using an oxide semiconductor is drawing attention. For example, Patent Document 1 describes the homologous compound InMO.₃(ZnO)_mA transparent thin film field effect transistor using (M = In, Fe, Ga, or Al, m = 1 or more and less than 50) is disclosed.

Further, Patent Document 2 states that the amorphous oxide semiconductor containing In, Ga, and Zn has an electron carrier concentration of 10.¹⁸/cm³Field-effect transistors using less than or equal to are disclosed. In this document, the ratio of the number of atoms of the amorphous oxide semiconductor is In: Ga: Zn = 1: 1: m (m <6).

Further, Patent Document 3 discloses a field-effect transistor having an amorphous oxide semiconductor containing microcrystals as an active layer.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2004-103957</text></patcit><patcit num="2"><text>International Publication No. 05/088726</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2006-165529</text></patcit></p>

<p>In Patent Document 3, the composition in the crystalline state is referred to as InGaO.₃(ZnO)_mThere is a disclosure that (integer less than m = 6). Further, in Example 1 of Patent Document 3, InGaO₃(ZnO)₄Is disclosed. However, even when such an oxide semiconductor is used, the actual situation is that sufficient characteristics have not been obtained.</p><p>In view of the above problems, one of the purposes is to provide an oxide semiconductor film having a new structure suitable for use in a semiconductor device. Another object of the present invention is to provide a semiconductor device using an oxide semiconductor film having a new structure.</p>

<p>The disclosed invention provides an oxide semiconductor film having a predetermined crystal structure in the vicinity of the surface. Alternatively, a semiconductor device provided with the oxide semiconductor film is provided. The predetermined crystal structure is, for example, a crystal structure having electrical anisotropy. Alternatively, it has a crystal structure having a function of suppressing the invasion of impurities.</p><p>It is preferable that the region of the oxide semiconductor film excluding the crystal structure is mainly composed of amorphous material. The term "near the surface (near the surface)" means, for example, a region where the distance (depth) from the surface is 20 nm or less. Further, the "main" means, for example, a state in which 50% or more is occupied. The following can be mentioned as an example of the means for solving the problem.</p><p>One aspect of the disclosed invention is an amorphous region mainly composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and an In in the vicinity of the surface.₂Ga₂ZnO₇The crystal grain is an oxide semiconductor film having a crystal region containing the crystal grain of the above, and the crystal grain is oriented so that its c-axis is substantially perpendicular to the surface. The term "substantially vertical" means a state within ± 10 ° from the vertical direction.</p><p>In the above, In₂Ga₂ZnO₇The crystal grains of are the first layer containing In, the second layer not containing In, the third layer not containing In, the fourth layer containing In, and the first layer not containing In. It is preferable to include a laminated structure of 5 layers. Further, in the first layer containing In or the fourth layer containing In, it is preferable that the 5s orbit of one In has an overlap with the 5s orbit of the adjacent In.</p><p>Further, in the above amorphous region, the Zn content (atomic%) is preferably less than the In or Ga content (atomic%). Further, it is preferable that the length (magnitude) of the crystal grains in the c-axis direction is less than 5 times the length (magnitude) in the a-axis direction or the b-axis direction.</p><p>Further, another aspect of the disclosed invention is a source electrode layer that electrically connects a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, and a part of the semiconductor layer. It is a semiconductor device having the above-mentioned oxide semiconductor film as a semiconductor layer and having a drain electrode layer and a drain electrode layer.</p><p>Further, another aspect of the disclosed invention is a semiconductor layer, a gate insulating layer on the semiconductor layer, a gate electrode layer on the gate insulating layer, a source electrode layer electrically connected to a part of the semiconductor layer, and a source electrode layer. It is a semiconductor device having a drain electrode layer and applying the oxide semiconductor film as a semiconductor layer.</p><p>In the above semiconductor device, it is preferable to have an insulating layer covering the semiconductor layer. Further, it is preferable that the source electrode layer or the drain electrode layer and the semiconductor layer are electrically connected on the upper surface or the lower surface of the semiconductor layer.</p><p>In addition, in this specification etc., the wording of "above" and "below" is not limited to being directly above or directly below. For example, the expression "gate insulating layer on the gate electrode layer" does not exclude the case where another component is included between the gate electrode layer and the gate insulating layer. In addition, the words "upper" and "lower" are merely expressions used for convenience of explanation, and include those in which the upper and lower parts are interchanged unless otherwise specified.</p>

<p>In an oxide semiconductor film having a crystal structure having an electrical anisotropy in the vicinity of the surface, the electrical characteristics of the oxide semiconductor film are changed as compared with the oxide semiconductor film not having the crystal structure. For example, the conductivity in the direction parallel to the surface of the oxide semiconductor film is improved, and the insulation property in the direction perpendicular to the surface of the oxide semiconductor film is improved.</p><p>Further, in the oxide semiconductor film having a crystal structure having a function of suppressing the invasion of impurities in the vicinity of the surface, the invasion of impurities into the oxide semiconductor film is compared with the oxide semiconductor film not having the crystal structure. Is suppressed. For example, the intrusion of water, hydrogen, etc., which adversely affect the oxide semiconductor, is suppressed.</p><p>Therefore, one aspect of the disclosed invention provides an oxide semiconductor film having excellent electrical characteristics. Further, a highly reliable oxide semiconductor film is provided.</p><p>Further, another aspect of the disclosed invention provides a semiconductor device having excellent characteristics. Further, a highly reliable semiconductor device is provided.</p>

<figref num="1">It is sectional drawing which shows the structure of an oxide semiconductor film.</figref><figref num="2">In₂Ga₂ZnO₇It is a figure which shows the crystal structure of.</figref><figref num="3">It is sectional drawing which shows the manufacturing method of the oxide semiconductor film.</figref><figref num="4">It is a Bright-field-TEM image near the surface.</figref><figref num="5">It is a cross-sectional TEM image showing an electron diffraction pattern near the surface and a measurement point.</figref><figref num="6">It is a figure which compares the measured data of the electron diffraction pattern with the simulation result.</figref><figref num="7">InGaZnO₄Crystal structure and In₂Ga₂ZnO₇It is a figure which compares the crystal structure.</figref><figref num="8">This is the simulation result of the HAADF-STEM image.</figref><figref num="9">In₂Ga₂ZnO₇It is a HAADF-STEM image which concerns on the cross section of a crystal grain.</figref><figref num="10">In₂Ga₂ZnO₇It is a HAADF-STEM image which concerns on the cross section of a crystal grain.</figref><figref num="11">It is a figure which shows the crystal structure and the surface structure used for the surface energy calculation.</figref><figref num="12">It is a figure which shows the detail of the calculation condition.</figref><figref num="13">It is a figure which shows the calculation result of the surface energy.</figref><figref num="14">In₂Ga₂ZnO₇It is a figure which shows the formation mechanism and the growth mechanism of a crystal grain.</figref><figref num="15">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="16">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="17">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="18">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="19">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="20">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="21">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="22">It is sectional drawing which shows the manufacturing process of a semiconductor device.</figref><figref num="23">It is a figure which shows an example of a display device.</figref><figref num="24">It is a figure which shows the application form of the display device.</figref>

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the invention is not limited to the description of the embodiments shown below, and the form and details may be changed without departing from the spirit of the invention disclosed in the present specification and the like. In addition, the configurations according to different embodiments can be combined and implemented as appropriate. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

(Embodiment 1) In the present embodiment, the details of the oxide semiconductor film and the method for producing the oxide semiconductor film according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 14.

&lt;Structure of Oxide Semiconductor Film&gt; First, the configuration of the oxide semiconductor film will be described with reference to FIGS. 1 and 2.

FIG. 1 shows an example of a configuration in which the oxide semiconductor film 100 is provided on the surface to be formed of the base material 110. As the base material 110, any material may be used as long as it can support the oxide semiconductor film 100. Further, the oxide semiconductor film 100 is not limited to being provided on the surface to be formed of the base material 110, and may be a self-supporting film.

The oxide semiconductor film 100 has an amorphous region 120 mainly composed of an amorphous oxide semiconductor and a crystal region 140 containing crystal grains 130 near the surface (see FIG. 1 (A)). .. Further, the crystal grains 130 are oriented so that the c-axis thereof is in a direction substantially perpendicular to the surface of the oxide semiconductor film 100. Here, substantially vertical means a state within ± 10 ° from the vertical direction.

Examples of the oxide semiconductor material constituting the oxide semiconductor film 100 include In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, and Sn-Ga-. Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn There are -O-based and Zn-O-based oxide semiconductor materials.

Among them, the In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance when there is no electric field, can sufficiently reduce the off-current, and has a high field effect mobility, so that it is a semiconductor. It is suitable as a semiconductor material used in an apparatus.

InGaO is a typical example of an In-Ga-Zn-O-based oxide semiconductor material.₃(ZnO)_mSome are represented by (m&gt; 0). It should be noted that the composition according to the notation is based on the crystal structure, and is not limited to the composition as a whole of the oxide semiconductor material. Also, in the above, M is used instead of Ga, and InMO₃(ZnO)_mIt can also be written as (m&gt; 0). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co) and the like. In the In-Ga-Zn-O based oxide semiconductor material, Ga is selected as M, but in addition to the case of only Ga, Ga and Ni, Ga and Fe, etc. other than Ga mentioned above Including the case where a metal element is selected. Further, in addition to the metal element contained as M, a transition metal element or an oxide thereof may be contained as an impurity.

The amorphous region 120 is mainly composed of an amorphous oxide semiconductor. The "main" means, for example, a state in which 50% or more is occupied, and in this case, the amorphous oxide semiconductor occupies 50% or more in volume% (or weight%). .. That is, in addition to the amorphous oxide semiconductor, crystals of the oxide semiconductor and the like may be contained, but the content thereof is preferably less than 50% in volume% (or weight%). Since it can be said that the essence of the disclosed invention lies in the configuration of the crystal region 140, it is not necessary to limit the configuration of the amorphous region 120 to the above as long as the required characteristics can be ensured.

When an In-Ga-Zn-O-based oxide semiconductor material is used, the composition of the above amorphous region 120 has a Zn content (atomic%) and an In or Ga content (atomic%). It is preferable that the amount is less than. This is because such a composition facilitates the formation of crystal grains 130 having a predetermined composition in the crystal region 140.

The crystal region 140 near the surface has crystal grains 130 whose c-axis is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100 (see FIG. 1 (B)). For example, when an In-Ga-Zn-O-based oxide semiconductor material is used, the crystal region 140 is In.₂Ga₂ZnO₇The c-axis of the crystal grains is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100. The term "near the surface (near the surface)" means, for example, a region where the distance (depth) from the surface is 20 nm or less. However, this does not apply when the thickness of the oxide semiconductor film 100 increases. For example, when the thickness of the oxide semiconductor film 100 is 200 nm or more, "near the surface (near the surface)" means that the distance (depth) from the surface is 10% of the thickness of the oxide semiconductor film. Refers to the following areas.

In above₂Ga₂ZnO₇Crystals contain any of In, Ga, and Zn, and can be regarded as having a layered structure parallel to the a-axis (a-axis) and b-axis (b-axis) (see Fig. 2). .. That is, In₂Ga₂ZnO₇Crystals contain a first layer containing In, a second layer containing no In (containing Ga or Zn), a third layer containing no In (containing Ga or Zn), and In. It has a structure in which a fourth layer containing In and a fifth layer containing no In (containing Ga or Zn) are laminated in the c-axis direction.

In₂Ga₂ZnO₇Since the electrical conduction of the crystal is mainly controlled by In, the electrical characteristics of the first layer containing In and the fourth layer containing In in the direction parallel to the a-axis and the b-axis are good. This is because in the first layer containing In or the fourth layer containing In, a carrier path is formed by having a 5s orbital of one In overlap with a 5s orbital of an adjacent In. Because. On the other hand, it can be said that the insulation property is improved in the direction perpendicular to the layer (that is, the c-axis direction).

The orientation of the crystal grains having such electrical anisotropy also affects the electrical characteristics of the oxide semiconductor film 100. Specifically, for example, the electrical characteristics in the direction parallel to the surface of the oxide semiconductor film 100 are improved. This is In₂Ga₂ZnO₇The c-axis of the crystal grains is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100, and In₂Ga₂ZnO₇This is because the current flows in the direction parallel to the a-axis and the b-axis in the crystal.

The crystal region 140 may include other than the crystal grains 130. Further, the crystal structure of the crystal grains is not limited to the above, and crystal grains having other crystal structures may be included. For example, when using an In-Ga-Zn-O-based oxide semiconductor material, In₂Ga₂ZnO₇InGaZnO₄It may contain crystal grains of. Of course, In over the entire crystal region 140₂Ga₂ZnO₇It is more effective and preferable when the crystal grains of the above are present.

Further, it is preferable that the length (size) of the crystal grains in the c-axis direction is less than 5 times the length (size) in the a-axis direction or the b-axis direction, and it is less than 3 times. Even better. If the thickness of the crystal region 140 becomes too large (that is, if the crystal grains 130 become too long in the c-axis direction), the characteristics of the oxide semiconductor film 100 depend only on the crystal region 140, and the desired characteristics can be obtained. This is because it may disappear.

As described above, the oxide semiconductor film 100 can realize good electrical characteristics by having the crystal region 140 in the vicinity of the surface. In particular, the crystal region 140 is In₂Ga₂ZnO₇When the c-axis of the crystal grains is configured to include those oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100, In₂Ga₂ZnO₇Excellent electrical properties are realized by the anisotropy of the electrical properties of the crystal grains.

Further, since the crystal region 140 is more stable than the amorphous region 120, by having it near the surface of the oxide semiconductor film 100, impurities (for example, water) are taken into the amorphous region 120. It is possible to suppress this. Therefore, the reliability of the oxide semiconductor film 100 can be improved.

&lt;Method for Producing Oxide Semiconductor Film&gt; Next, the method for producing the oxide semiconductor film 100 will be described with reference to FIG.

The oxide semiconductor film 200, which is the predecessor of the oxide semiconductor film 100, is formed by using the oxide semiconductor material shown in the above section &lt;Structure of oxide semiconductor film&gt;. Further, the oxide semiconductor film 200 is formed by a sputtering method or the like under a rare gas atmosphere such as argon, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen (see FIG. 3 (A)). In the sputtering method, SiO₂By using a target containing 2% by weight or more and 10% by weight or less of_xCrystallization of the oxide semiconductor film 200 can be suppressed by including (x&gt; 0). This method is particularly effective when it is desired to obtain an amorphous oxide semiconductor film 200.

For example, metal oxide targets containing In, Ga, and Zn (In: Ga: Zn = 1: 1: 0.5 [atom%], In: Ga: Zn = 1: 1: 1 [atom%], In: Ga Using a target with a composition ratio of: Zn = 1: 1: 2 [atom%], the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC power is 0.5 kW, and the atmosphere is oxygen (oxygen). By setting the flow rate ratio to 100%), an In-Ga-Zn-O-based amorphous oxide semiconductor film can be obtained as the oxide semiconductor film 200. When a pulsed DC power source is used as the power source, powdery substances (also referred to as particles and dust) generated during film formation can be reduced, and the film thickness distribution can be made uniform. Suitable.

The thickness of the oxide semiconductor film 200 can be appropriately set according to the intended use and characteristics. For example, it may be about 20 nm to 10 μm.

The crystal region 140 is formed by heat treatment after forming the oxide semiconductor film 200 (see FIG. 3 (B)). By the heat treatment, H in the oxide semiconductor film 200₂, H, OH and the like are desorbed, so the heat treatment can also be called a dehydration treatment or a dehydrogenation treatment.

An RTA (Rapid Thermal Anneal) treatment using a high-temperature inert gas (nitrogen, noble gas, etc.) can be applied to the heat treatment. Here, the temperature of the heat treatment is preferably 500 ° C. or higher. Although there is no requirement from the essential part of the invention regarding the upper limit of the heat treatment temperature, when the base material 110 is used as the support, the upper limit of the heat treatment temperature must be within the range of the heat resistant temperature. The heat treatment time is preferably 1 minute or more and 10 minutes or less. For example, it is recommended to perform RTA processing at 650 ° C for about 3 to 6 minutes. By applying the RTA treatment as described above, the heat treatment can be performed in a short time, so that the influence of heat on the base material 110 can be reduced. That is, it is possible to raise the upper limit of the heat treatment temperature as compared with the case where the heat treatment is performed for a long time. Further, it is possible to selectively form crystal grains having a predetermined structure in the vicinity of the surface.

The above heat treatment may be performed at any timing after the oxide semiconductor film 200 is formed, but in order to promote dehydrogenation or dehydrogenation, the surface of the oxide semiconductor film 200 may be subjected to the heat treatment. It is preferable to do this before providing other components. Further, the above heat treatment is not limited to one time, and may be performed a plurality of times.

In the above heat treatment, it is desirable that hydrogen (including water) and the like are not contained in the treatment atmosphere. For example, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%, that is, the impurity concentration is 1 ppm or less) or more, preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or less) or more.

By the above heat treatment, a crystal region 140 having crystal grains 130 oriented so that the c-axis is oriented substantially perpendicular to the surface of the oxide semiconductor film, and an amorphous region mainly composed of amorphous material. An oxide semiconductor film 100 having 120 and 120 is formed (see FIG. 3 (C)).

The crystal region 140 has a function of suppressing the invasion of impurities into the film, but when a large amount of impurities are present, it cannot be said that the invasion can be completely suppressed. Therefore, it is important that the oxide semiconductor film 100 is not brought into contact with water, hydrogen, or the like as much as possible after the heat treatment. This can be achieved by not exposing to the atmosphere during the heat treatment and subsequent temperature lowering processes. For example, the heat treatment and the subsequent temperature lowering process may be performed in the same atmosphere. Of course, the atmosphere in the temperature lowering process may be different from the heat treatment atmosphere. In this case, the atmosphere of the temperature lowering process is, for example, oxygen gas, N.₂The atmosphere can be O gas, ultra-dry air (dew point is -40 ° C or less, preferably -60 ° C or less).

&lt;Growth mechanism of crystal grains&gt; Below, as an example, the growth mechanism of crystal grains in an In-Ga-Zn-O-based amorphous oxide semiconductor film will be described with reference to FIGS. 4 to 14.

First, In-Ga-Zn-O-based amorphous oxide semiconductor film near the surface of In₂Ga₂ZnO₇The c-axis orientation of the crystal grains is shown together with the results of experimental observation.

As the In-Ga-Zn-O-based amorphous oxide semiconductor film, a film formed on a glass substrate with a thickness of 50 nm by the DC sputtering method was used. Further, as the sputtering target, a target having a composition ratio of In: Ga: Zn = 1: 1: 0.5 [atom%] was used. Other film forming conditions were DC power of 0.5 kW, film formation pressure of 0.6 Pa, film formation atmosphere of oxygen (oxygen flow rate ratio 100%) atmosphere, and substrate temperature of room temperature.

In near the surface₂Ga₂ZnO₇In order to orient the crystal grains on the c-axis, RTA treatment was applied to the above-mentioned In-Ga-Zn-O-based amorphous oxide semiconductor film. The conditions of the heat treatment were a nitrogen atmosphere at atmospheric pressure, a temperature of 650 ° C, and a time of 6 minutes.

In order to observe the cross section of the sample prepared in this way, after performing mechanical polishing, flaking by the Ar ion milling method (acceleration voltage: 5 kV) or the FIB milling method (irradiation ion: Ga, acceleration voltage:: It was sliced by (treating at 5 kV after 40 kV). Gatan's PIPS was used for the Ar ion milling method, and Hitachi's NB-5000 and FB-2100 were used for the FIB milling method.

FIG. 4 shows a Bright-field-TEM image near the sample surface. The TEM image was observed using Hitachi's H-9000NAR under the condition of an acceleration voltage of 300 kV. From FIG. 4, a crystal region containing crystal grains having a width of 1 nm or more and 3 nm or less and a depth of 2 nm or more and 4 nm or less is formed near the surface of an In-Ga-Zn-O oxide semiconductor film having a thickness of 50 nm. It can be confirmed that there is.

FIG. 5 (A-1) shows a cross-sectional TEM image of the vicinity of the sample surface. Further, the electron diffraction pattern corresponding to 1 attached to the cross-sectional TEM image is shown in FIG. 5 (A-2), and the electron diffraction pattern corresponding to 2 attached to the cross-sectional TEM image is shown in FIG. 5 (A-2). The electron diffraction pattern corresponding to 3 attached to the cross-sectional TEM image shown in -3) is shown in Fig. 5 (A-4), and the electron diffraction pattern corresponding to 4 attached to the cross-sectional TEM image is shown in Fig. 5 (A-4). Fig. 5 (A-5) shows, and the electron diffraction pattern corresponding to 5 attached in the cross-sectional TEM image is shown in Fig. 5 (A-6). Each electron diffraction pattern has a clear spot with a d value of 0.29 nm or more and 0.30 nm or less. The direction of the spot corresponds to the direction of the c-axis of the crystal.

FIG. 5 (B) is a cross-sectional TEM image showing the relationship between the c-axis direction and the surface. The arrow in the figure indicates the c-axis direction of the crystal grain at that point. From FIG. 5 (B), it can be seen that the c-axis (&lt;001&gt; direction) is substantially perpendicular to the surface. It can also be seen that the direction of the c-axis reflects the flatness of the surface.

Next, in order to determine the crystal structure of the crystal grains, a detailed analysis of the electron diffraction pattern was performed. 6 (A-1) to 6 (A-3) show typical measured data of the electron diffraction pattern, and 6 (B-1) to 6 (B-3) show the measured data. Data and corresponding simulation results (In₂Ga₂ZnO₇Crystals are assumed). From the comparison between the measured data and the simulation results, the crystal structure of the crystal grains is In.₂Ga₂ZnO₇It can be confirmed that.

Figure 7 shows the homologous structure InGaO₃(ZnO)_mCrystal structure of m = 1 in (m: natural number) (InGaZnO₄) (See Figure 7 (A)) and In₂Ga₂ZnO₇The crystal structures (see Fig. 7 (B)) are compared and shown.

InGaZnO₄In the structure, there are two layers of GaO or ZnO between the layers (InO layer) composed of In and O perpendicular to the c-axis (&lt;001&gt; direction), whereas In₂Ga₂ZnO₇The structure is characterized in that a structure having one layer of GaO or ZnO and a structure having two layers appear alternately and repeatedly between the InO layers. The lattice constant in the c-axis direction is InGaZnO.₄In contrast to 2.61 nm₂Ga₂ZnO₇Then it is 2.95 nm.

Next, InGaZnO₄Crystal structure and In₂Ga₂ZnO₇The observation of HAADF (high-angle annular dark field) -STEM images in the crystal structure will be described. Figure 8 (A-1) shows InGaZnO₄The results of the crystal structure simulation, Fig. 8 (A-2) shows InGaZnO.₄It is a HAADF-STEM image of the crystal structure. Figure 8 (B-1) shows In₂Ga₂ZnO₇The result of the crystal structure simulation is shown in Fig. 8 (B-2).₂Ga₂ZnO₇It is a HAADF-STEM image of the crystal structure. Note that FIGS. 8 (A-1) and 8 (B-1) show the crystal structure seen from the (100) plane.

In the HAADF-STEM image, a contrast proportional to the square of the atomic number is obtained, so the brighter the point, the heavier the atom. That is, in the above quaternary system, bright spots represent In atoms and dark spots represent Ga atoms or Zn atoms. Moreover, since the O atom has a smaller mass than the above atom, it does not appear as an image. In this way, the HAADF-STEM image can be said to be an epoch-making observation means in that it is easy to directly image the structure at the atomic level.

In near the sample surface₂Ga₂ZnO₇HAADF-STEM images related to the cross section of the crystal grains are shown in FIGS. 9 and 10. For observation, a shotkey type field emission STEM with spherical aberration correction function (Hitachi HD-2700, spherical aberration Cs: 5 μm or less) was used. The acceleration voltage was 200 kV, and the detection angle was 40 mrad or more and 210 mrad or less. In FIGS. 9 and 10, as shown in FIG. 8, the difference in intensity between the In atom and the Ga atom or Zn atom is not clear. It is considered that this is because the crystal grains are fine and it is not possible to obtain sufficient signal strength.

A closer look at FIG. 9 shows that there are two layers containing Ga or Zn between the layers containing In (distance between layers containing In: 0.89 nm) and Ga between the layers containing In. Alternatively, it can be confirmed that there is one layer containing Zn (distance between layers containing In: 0.62 nm). Further, in FIG. 10, a more characteristic structure can be confirmed. In many regions, the outermost layer is not the layer containing In. This suggests that the outermost surface is a layer containing Ga or Zn. This is an interesting fact in understanding the formation mechanism of crystal grains.

Next, based on the above observation results, the mechanism of crystal nucleation and crystal growth near the surface of the oxide semiconductor film was confirmed by computer simulation.

In order to investigate the plane orientation of the seed crystal related to crystal growth, by first-principles calculation₂Ga₂ZnO₇(Crystal symmetry: P63 / MMC) and In₂O₃(Crystal symmetry: R-3C), Ga₂O₃The surface energies of (crystal symmetry: R-3C) and ZnO (crystal symmetry: P63MC) were determined. Here, the surface energy means the energy per unit area required for cutting out a crystal plane from a bulk crystal. That is, it can be said that the larger the surface energy, the more unstable the surface structure is and the less likely it is to become a seed crystal.

For the above calculation, CASTEP, which is a first-principles calculation software based on density functional theory, was used. Moreover, in the above calculation, the surface energy was obtained from the following equation (1).

<maths num="1"><img file="JP6503045B2_D0001.tif" /></maths>

Since Ga and Zn are adjacent to each other in the periodic table and have similar atomic radii, their placement is random. That is, Zn may be placed at the site where Ga is placed, and Ga may be placed at the site where Zn is placed. In order to handle such random arrangement, virtual crystal approximation was used in the calculation. In other words, at the site where Ga or Zn is placed, virtual atoms with Ga of 66.7% and Zn of 33.3% were placed in correspondence with the composition ratio of Ga and Zn of 2: 1. More specifically, the pseudopotentials of each atom were mixed in the above proportions and assigned to virtual atoms.

In₂Ga₂ZnO₇The crystal structure used for the surface energy calculation of the (001) plane is shown in FIG. 11 (A), and the surface structure used for the surface energy calculation is shown in FIGS. 11 (B) to 11 (D), respectively. Here, FIG. 11 (B) shows a structure in which O is the outermost surface on the (001) plane (denoted as "(001): (Ga, Zn) O"), and FIG. 11 (C) shows the (001) plane. Shows the structure in which In is on the outermost surface (denoted as "(001): In"), and FIG. 11 (D) shows the structure in which Ga or Zn is on the outermost surface on the surface (001) ("(001): Ga,". Zn ") is shown. The lattices shown in FIGS. 11 (B) to 11 (D) were taken so as to be the smallest unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) in-plane direction differs depending on the surface structure. Note that FIGS. 11 (B) to 11 (D) show the structure after structural optimization by first-principles calculation. Before structural optimization (001): Ga and Zn had Ga or Zn on the outermost surface, but due to structural optimization, O has changed to the structure on the outermost surface.

The calculation was performed by obtaining the most stable structure of the crystal including the lattice, cutting out the crystal plane, and optimizing the structure only with respect to the atomic arrangement while the lattice was fixed. The thickness of the vacuum region where no atoms exist was set to 1 nm. The details of the calculation conditions are shown in Fig. 12. The number of k points was set to 1 in consideration of the fact that there is no periodicity in the direction perpendicular to the surface. Also, In₂Ga₂ZnO₇(100) side, In₂O₃, Ga₂O₃, ZnO was calculated in the same way.

The calculation result of surface energy is shown in Fig. 13. In from Fig. 13₂Ga₂ZnO₇It can be seen that the surface energy of (001): (Ga, Zn) O is the smallest in the surface structure of. In, Ga, and Zn are metallic and become energetically unstable due to the presence of surface charge, whereas when the bond is terminated at O, the surface energy can be reduced.

From the calculation result of surface energy, it is easily understood that (001): In is difficult to be formed. This can be supported by the observation results shown in FIG.

Also, by comparing the surface energy of (001): (Ga, Zn) O with the surface energy of the (001) plane of ZnO, In₂Ga₂ZnO₇Understand the formation mechanism and growth mechanism of crystal grains. Below, In₂Ga₂ZnO₇The crystal grain formation mechanism and growth mechanism will be briefly described with reference to FIG.

The vapor pressure of ZnO is high and it easily evaporates. Therefore, when heat treatment is performed, the composition ratio of Zn becomes small and the composition ratio of Ga becomes large in the vicinity of the surface of the In-Ga-Zn-O-based amorphous oxide semiconductor film (Fig. 14 (A)). reference). Comparing the surface energy of (001): (Ga, Zn) O with the surface energy of the (001) plane of ZnO, the surface energy of (001): (Ga, Zn) O is small, and ZnO and GaO on the surface. A layer made of GaO is formed, but ZnO is small on the surface, so that a layer made of GaO is stably formed (see FIG. 14 (B)). Then, from the above layer consisting of GaO, In₂Ga₂ZnO₇Crystal grains grow (see Fig. 14 (C)). In FIG. 10, if the outermost surface is a layer containing Ga and the second layer is a layer containing In, it will be easy to understand.

In addition, In₂Ga₂ZnO₇(001): (Ga, Zn) O is In₂O₃, Ga₂O₃, Smaller than the surface energy of the main surface of ZnO. Therefore, as far as judging from the surface energy, on the surface of the oxide semiconductor film, In₂O₃, Ga₂O₃, It can be said that ZnO does not undergo phase separation.

In crystal growth, a surface having a small surface energy tends to form crystal grains more easily than a surface having a large surface energy, and the surface tends to grow easily. For this reason, In₂Ga₂ZnO₇(001): (Ga, Zn) O is In₂O₃, Ga₂O₃, ZnO, etc. are easier to crystallize. Also, In₂Ga₂ZnO₇The surface energy of (001): (Ga, Zn) O is smaller than that of (100) plane and (001): In, (001): Ga, Zn. Therefore, the outermost surface tends to be (001) :( Ga, Zn) O, and the c-axis orientation tends to occur.

From the above, by heating the surface, the c-axis oriented In near the surface of the oxide semiconductor film₂Ga₂ZnO₇It is understood that crystal grains are formed and grow. The oxide semiconductor film has excellent electrical characteristics and is suitable for semiconductor devices. Alternatively, the oxide semiconductor film has high reliability and is suitable for a semiconductor device.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 2) In the present embodiment, an example of a transistor as a semiconductor device and a method for manufacturing the transistor will be described with reference to FIGS. 15 and 16.

First, the conductive layer 302 is formed on the substrate 300 (see FIG. 15 (A)).

The substrate 300 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate is preferably a non-alkali glass substrate. For the alkali-free glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and bariumborosilicate glass are used. In addition, as the substrate 300, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon whose surface is coated with an insulating material, a metal, stainless steel, etc. A conductive substrate made of a conductor whose surface is coated with an insulating material can be used. Further, a plastic substrate can also be used provided that it can withstand the heat treatment in the manufacturing process.

The conductive layer 302 is preferably formed of a conductive material such as aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (W), and titanium (Ti). Examples of the forming method include a sputtering method, a vacuum vapor deposition method, and a CVD method. When aluminum (or copper) is used for the conductive layer 302, aluminum (or copper alone) has problems such as low heat resistance and easy corrosion, so it should be formed in combination with a heat-resistant conductive material. Is preferable.

As a heat-resistant conductive material, a metal containing an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). , Alloys containing the above-mentioned elements as components, alloys combining the above-mentioned elements, nitrides containing the above-mentioned elements as components, and the like can be used. These heat-resistant conductive materials and aluminum (or copper) may be laminated to form the conductive layer 302.

Although not shown, a base layer may be provided on the substrate 300. The underlayer has a function of preventing the diffusion of alkali metals (Li, Cs, Na, etc.), alkaline earth metals (Ca, Mg, etc.) and other impurities from the substrate 300. That is, the problem of improving the reliability of the semiconductor device can be solved by providing the base layer. The base layer may be formed in a single layer structure or a laminated structure using various insulating materials such as silicon nitride and silicon oxide. Specifically, for example, it is preferable to have a configuration in which silicon nitride and silicon oxide are laminated in order from the substrate 300 side. This is because silicon nitride has a high blocking effect on impurities. On the other hand, when silicon nitride comes into contact with a semiconductor, a defect may occur in the semiconductor element. Therefore, it is preferable to use silicon oxide as a material in contact with the semiconductor.

Next, a resist mask 304 is selectively formed on the conductive layer 302, and the conductive layer 302 is selectively etched using the resist mask 304 to form a conductive layer 306 that functions as a gate electrode (FIG. 6). See 15 (B)).

The resist mask 304 is formed by undergoing steps such as coating a resist material, exposure using a photomask, and development. A method such as a spin coating method can be applied to the application of the resist material. Further, the resist mask 304 may be selectively formed by using a droplet ejection method, a screen printing method, or the like. In this case, since steps such as exposure and development using a photomask are not required, it is possible to solve the problem of improving productivity. The resist mask 304 is removed after the conductive layer 306 is formed by etching the conductive layer 302.

The resist mask 304 may be formed by using a multi-gradation mask. Here, the multi-gradation mask means a mask capable of performing exposure with a multi-step amount of light. By using this, it is possible to form a resist mask having a plurality of (typically two types) thicknesses by one exposure and development step. Therefore, by using the multi-gradation mask, it is possible to suppress an increase in the number of steps.

For the above-mentioned etching, dry etching may be used or wet etching may be used. Further, in order to improve the covering property of the gate insulating layer or the like to be formed later and prevent step breakage, it is preferable to etch the conductive layer 306 so that the end portion has a tapered shape. For example, it is preferable to have a tapered shape such that the taper angle is 20 ° or more and less than 90 °. Here, the "tapered angle" refers to the angle formed by the side surface and the bottom surface of the layer having a tapered shape when observed from the cross-sectional direction.

Next, an insulating layer 308 that functions as a gate insulating layer is formed so as to cover the conductive layer 306 (see FIG. 15 (C)). The insulating layer 308 can be formed by using a material such as silicon oxide, silicon nitride nitride, silicon nitride, silicon nitride oxide, aluminum oxide, and tantalum oxide. Further, a film made of these materials may be laminated to form a film. It is preferable that these films are formed so that the thickness is 5 nm or more and 250 nm or less by using a sputtering method or the like. For example, as the insulating layer 308, a silicon oxide film can be formed with a thickness of 100 nm by using a sputtering method.

Further, the insulating layer 308 having a laminated structure may be formed by combining the sputtering method and the CVD method (plasma CVD method or the like). For example, the lower layer of the insulating layer 308 (the region in contact with the conductive layer 306) can be formed by the plasma CVD method, and the upper layer of the insulating layer 308 can be formed by the sputtering method. Since the plasma CVD method can easily form a film having a good step covering property, it is suitable as a method for forming a film to be formed directly above the conductive layer 306. Further, in the sputtering method, it is easier to reduce the hydrogen concentration in the film as compared with the plasma CVD method. Therefore, by providing the film by the sputtering method in the region in contact with the semiconductor layer, hydrogen in the insulating layer 308 is provided. Can be prevented from diffusing into the semiconductor layer. In particular, in an oxide semiconductor film, hydrogen has an extremely large effect on the characteristics, and it is effective to adopt such a configuration.

In the present specification and the like, the oxide nitride means that the content of oxygen (the number of atoms) is larger than that of nitrogen in its composition. For example, silicon oxide nitride means that the oxygen content is 50 atomic% or more 70. Atomic% or less, nitrogen is 0.5 atomic% or more and 15 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. Further, the nitride oxide indicates a composition having a higher nitrogen content (number of atoms) than oxygen. For example, silicon nitride oxide contains 5 atomic% or more and 30 atomic% or less of oxygen and nitrogen. 20 atomic% or more and 55 atomic% or less, silicon 25 atomic% or more and 35 atomic% or less, and hydrogen 10 atomic% or more and 25 atomic% or less. However, the above range is measured by using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). In addition, the total content ratio of the constituent elements does not exceed 100 atomic%.

Next, the semiconductor layer 310 is formed so as to cover the insulating layer 308 (see FIG. 15 (D)). In the present embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 310. For details of the oxide semiconductor film, the above-described embodiment can be referred to.

Although the case where the semiconductor layer 310 is formed by a single layer is shown in the present embodiment, the semiconductor layer 310 may have a laminated structure. For example, the semiconductor layer 310 may be formed by laminating two or more oxide semiconductor films having different compositions on the insulating layer 308. Further, the semiconductor layer 310 may be formed by laminating two or more oxide semiconductor films having different crystallinity.

Next, a resist mask 312 is selectively formed on the semiconductor layer 310, and the semiconductor layer 310 is selectively etched using the resist mask 312 to form the semiconductor layer 314 (see FIG. 16 (A)). ). Here, the resist mask 312 can be formed in the same manner as the resist mask 304. Further, the resist mask 312 is removed after the semiconductor layer 314 is formed by etching the semiconductor layer 310.

As a method of etching the semiconductor layer 310, wet etching or dry etching can be used. For example, the semiconductor layer 314 can be formed by removing unnecessary portions of the semiconductor layer 310 by wet etching using a mixed solution of acetic acid, nitric acid, and phosphoric acid. The etchant (etching liquid) that can be used for the above-mentioned wet etching is not limited to the above-mentioned one as long as it can etch the semiconductor layer 310.

When dry etching is performed, for example, it is preferable to use a gas containing chlorine or a gas containing oxygen added to the gas containing chlorine. This is because the use of a gas containing chlorine makes it easier to obtain an etching selection ratio between the conductive layer or the base layer and the semiconductor layer 310.

For dry etching, an etching apparatus using a reactive ion etching method (RIE method) or a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) can be used. it can. Further, an etching apparatus in ECCP (Enhanced Capacitively Coupled Plasma) mode, which can obtain a uniform discharge over a wider area than the ICP etching apparatus, may be used. If the etching apparatus is in ECCP mode, it is easy to handle even when a 10th generation or later substrate is used as the substrate.

Next, the conductive layer 316 is formed so as to cover the insulating layer 308 and the semiconductor layer 314 (see FIG. 16 (B)). The conductive layer 316 can be formed by the same material and method as the conductive layer 302. For example, the conductive layer 316 can be formed with a single-layer structure of a molybdenum layer or a titanium layer. Further, the conductive layer 316 may be formed in a laminated structure, and for example, a laminated structure of an aluminum layer and a titanium layer can be used. Further, a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are laminated in this order may be used. Further, a three-layer structure in which a molybdenum layer, an aluminum layer, and a molybdenum layer are laminated in order may be used. Further, as the aluminum layer used for these laminated structures, an aluminum (Al-Nd) layer containing neodymium may be used. Further, the conductive layer 316 may have a single-layer structure of an aluminum layer containing silicon.

Next, the resist mask 318 and the resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched by using the resist mask to function as one of the source electrode and the drain electrode. It forms a conductive layer 322 and a conductive layer 324 that functions as the other of the source and drain electrodes (see FIG. 16 (C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Further, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316.

As a method of etching the conductive layer 316, either wet etching or dry etching can be used.

Next, the insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, and the like (see FIG. 16 (D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed by using a material such as silicon oxide, aluminum oxide, or tantalum oxide. Further, a film made of these materials may be laminated to form a film. From the above, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16 (D)).

As shown in the present embodiment, by manufacturing the semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, water) into the oxide semiconductor film. It is possible to do. Therefore, the reliability of the semiconductor device can be improved.

Further, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device having good electrical characteristics.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 3) In the present embodiment, another example of a transistor as a semiconductor device and a method for manufacturing the transistor will be described with reference to FIGS. 17 and 18. Since the manufacturing process of the semiconductor device in the present embodiment is common to the previous embodiment in many parts, the description of the overlapping parts will be omitted below, and the differences will be described in detail. ..

First, the conductive layer 402 is formed on the substrate 400 (see FIG. 17 (A)). For the substrate 400, the conductive layer 402, and other details, the above-described embodiment (such as the explanatory portion of FIG. 4A) may be referred to. Further, a base layer may be provided on the substrate 400. The details of the underlying layer can also be taken into consideration in the previous embodiment.

Next, a resist mask 404 is selectively formed on the conductive layer 402, and the conductive layer 402 is selectively etched using the resist mask 404 to form a conductive layer 406 that functions as a gate electrode (FIG. 6). 17 (B)). For details of the resist mask 404, the conductive layer 406, etching, and the like, the above-described embodiment (such as the explanatory portion of FIG. 15B) can be referred to.

Next, an insulating layer 408 that functions as a gate insulating layer is formed so as to cover the conductive layer 406 (see FIG. 17 (C)). For the insulating layer 408 and other details, the above embodiment (explained in FIG. 15C, etc.) may be referred to.

Next, the conductive layer 410 is formed so as to cover the insulating layer 408 (see FIG. 17 (D)). The conductive layer 410 can be formed by the same material and method as the conductive layer 402. That is, for details, the above-described embodiment (explanatory portion of FIGS. 15A and 16B) may be referred to.

Next, a resist mask 412 and a resist mask 414 are selectively formed on the conductive layer 410, and the conductive layer 410 is selectively etched by using the resist mask to function as either a source electrode or a drain electrode. It forms a conductive layer 416 and a conductive layer 418 that functions as the other of the source and drain electrodes (see FIG. 18 (A)). The resist mask 412 and the resist mask 414 can be formed in the same manner as the resist mask 404. Further, as a method of etching the conductive layer 410, either wet etching or dry etching can be used. That is, for details of the resist mask and etching, it is sufficient to refer to the above-described embodiments (explanatory portions of FIGS. 15 (B) and 16 (C), etc.).

Next, the semiconductor layer 420 is formed so as to cover the insulating layer 408, the conductive layer 416, the conductive layer 418, and the like (see FIG. 18 (B)). In the present embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 420. For details of the oxide semiconductor film, the above-described embodiment can be referred to.

Next, a resist mask 422 is selectively formed on the semiconductor layer 420, and the semiconductor layer 420 is selectively etched using the resist mask 422 to form the semiconductor layer 424 (see FIG. 18 (C)). ). For details of the resist mask and etching, the above-described embodiments (explanatory portions of FIGS. 15 (B) and 16 (A), etc.) may be referred to.

Next, the insulating layer 426 is formed so as to cover the conductive layer 416, the conductive layer 418, the semiconductor layer 424, and the like (see FIG. 18 (D)). Here, the insulating layer 426 corresponds to a so-called interlayer insulating layer. The insulating layer 426 can be formed by using a material such as silicon oxide, aluminum oxide, or tantalum oxide. Further, a film made of these materials may be laminated to form a film. From the above, the transistor 450 using the oxide semiconductor film is completed (see FIG. 18 (D)).

As shown in the present embodiment, by manufacturing the semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, water) into the oxide semiconductor film. It is possible to do. Therefore, the reliability of the semiconductor device can be improved.

Further, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device having good electrical characteristics.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 4) In the present embodiment, another example of a transistor as a semiconductor device and a method for manufacturing the transistor will be described with reference to FIGS. 19 and 20. Since the manufacturing process of the semiconductor device in the present embodiment is common to the previous embodiment in many parts, the description of the overlapping parts will be omitted below, and the differences will be described in detail. ..

First, the semiconductor layer 502 is formed on the substrate 500 (see FIG. 19 (A)), the resist mask 504 is selectively formed on the semiconductor layer 502, and then the semiconductor layer 502 is selectively formed by using the resist mask 504. The semiconductor layer 506 is formed by etching the semiconductor layer 506 (see FIG. 19 (B)). In the present embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 502. For details of the oxide semiconductor film, the above-described embodiment can be referred to. In addition, the above embodiment can be taken into consideration for other details.

Next, the conductive layer 508 is formed so as to cover the semiconductor layer 506 (see FIG. 19C), and the resist mask 510 and the resist mask 512 are selectively formed on the conductive layer 508, and then the resist mask is used. The conductive layer 508 is selectively etched to form a conductive layer 514 that functions as one of the source electrode or the drain electrode and a conductive layer 516 that functions as the other of the source electrode or the drain electrode (see FIG. 19 (D)). .. For details, the previous embodiment can be taken into consideration.

Next, an insulating layer 518 that functions as a gate insulating layer is formed so as to cover the semiconductor layer 506, the conductive layer 514, and the conductive layer 516 (see FIG. 20 (A)). Then, the conductive layer 520 is formed on the insulating layer 518 (see FIG. 20B), the resist mask 522 is selectively formed on the conductive layer 520, and then the conductive layer 520 is selected using the resist mask 522. By etching, a conductive layer 524 that functions as a gate electrode is formed (see FIG. 20 (C)). For details, the previous embodiment can be taken into consideration. From the above, the transistor 550 using the oxide semiconductor film is completed (see FIG. 20 (D)).

As shown in the present embodiment, by manufacturing the semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, water) into the oxide semiconductor film. It is possible to do. Therefore, the reliability of the semiconductor device can be improved.

Further, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device having good electrical characteristics.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 5) In the present embodiment, another example of a transistor as a semiconductor device and a method for manufacturing the transistor will be described with reference to FIGS. 21 and 22. Since the manufacturing process of the semiconductor device in the present embodiment is common to the previous embodiment in many parts, the description of the overlapping parts will be omitted below, and the differences will be described in detail. ..

First, a conductive layer 602 is formed on the substrate 600 (see FIG. 21 (A)), a resist mask 604 and a resist mask 606 are selectively formed on the conductive layer 602, and then the conductive layer 602 is used using the resist mask. Is selectively etched to form a conductive layer 608 that functions as one of the source electrode or the drain electrode and a conductive layer 610 that functions as the other of the source electrode or the drain electrode (see FIG. 21 (B)). For details, the previous embodiment can be taken into consideration.

Next, the semiconductor layer 612 in contact with the conductive layer 608 and the conductive layer 610 is formed (see FIG. 21 (C)), a resist mask 614 is selectively formed on the semiconductor layer 612, and then the resist mask 614 is used. The semiconductor layer 616 is formed by selectively etching the semiconductor layer 612 (see FIG. 21 (D)). In the present embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 612. For details of the oxide semiconductor film, the above-described embodiment can be referred to. In addition, the above embodiment can be taken into consideration for other details.

Next, an insulating layer 618 that functions as a gate insulating layer is formed so as to cover the semiconductor layer 616, the conductive layer 608, and the conductive layer 610 (see FIG. 22 (A)). Then, a conductive layer 620 is formed on the insulating layer 618 (see FIG. 22 (B)), a resist mask 622 is selectively formed on the conductive layer 620, and then the conductive layer 620 is selected using the resist mask 622. By etching, a conductive layer 624 that functions as a gate electrode is formed (see FIG. 22 (C)). For details, the previous embodiment can be taken into consideration. From the above, the transistor 650 using the oxide semiconductor film is completed (see FIG. 22 (D)).

As shown in the present embodiment, by manufacturing the semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, water) into the oxide semiconductor film. It is possible to do. Therefore, the reliability of the semiconductor device can be improved.

Further, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device having good electrical characteristics.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 6) In the present embodiment, the configuration of a display device using an electrophoresis element will be described with reference to FIG. 23 as an example using the semiconductor device described in the previous embodiment. In this embodiment, an example of a display device using an electrophoresis element will be described, but the display device capable of using the semiconductor device which is one aspect of the disclosed invention is not limited thereto. The semiconductor device, which is one aspect of the disclosed invention, can be applied to a display device using various display elements such as a liquid crystal display element and an electroluminescence element.

FIG. 23 (A) shows a plan view of the pixels of the display device, and FIG. 23 (B) shows a cross-sectional view corresponding to AB in FIG. 23 (A). The display device shown in FIG. 23 is a substrate 700, a transistor 702 and a capacitive element 704 on the substrate 700, an electrophoretic element 706 on the transistor 702 and the capacitive element 704, and a translucent substrate on the electrophoretic element 706. Has 708 and. In FIG. 23 (A), the electrophoresis element 706 is omitted for the sake of simplicity.

The transistor 702 is composed of a conductive layer 710, an insulating layer 712 covering the conductive layer 710, a semiconductor layer 714 on the insulating layer 712, and a conductive layer 716 and a conductive layer 718 in contact with the semiconductor layer 714. Here, the conductive layer 710 functions as the gate electrode of the transistor, the insulating layer 712 functions as the gate insulating layer of the transistor, and the conductive layer 716 functions as the first terminal (either the source terminal or the drain terminal) of the transistor. , The conductive layer 718 functions as the second terminal (the other of the source terminal and the drain terminal) of the transistor. For details, the previous embodiment can be taken into consideration.

Further, in the above, the conductive layer 710 is electrically connected to the gate wire 720, and the conductive layer 716 is electrically connected to the source wire 722. The conductive layer 710 may be integrated with the gate wire 720, and the conductive layer 716 may be integrated with the source wire 722.

The capacitive element 704 is composed of a conductive layer 718, an insulating layer 712, and a conductive layer 724. The capacitive element 704 has a role of holding a signal input to the pixel. The above-mentioned components constituting the capacitive element 704 can be formed together with the formation of the components of the transistor.

In the above, the conductive layer 724 is electrically connected to the capacitive wiring 726. The conductive layer 718 functions as one terminal of the capacitive element, the insulating layer 712 functions as a dielectric, and the conductive layer 724 functions as the other terminal. The conductive layer 724 may be integrated with the capacitive wiring 726.

The electrophoresis element 706 is composed of a pixel electrode 728, a common electrode 730 (which may be called a counter electrode), and a layer 732 containing charged particles provided between the pixel electrode 728 and the common electrode 730. As the charged particles contained in the layer 732 containing the charged particles, titanium oxide or the like can be applied as the positively charged particles, and carbon black or the like can be applied as the negatively charged particles. Also, apply one material selected from conductors, insulators, semiconductors, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electrochromic materials, magnetic migration materials, or composite materials thereof. You can also.

In the above, the pixel electrode 728 is electrically connected to the conductive layer 718 through the openings provided in the insulating layer 734 and the insulating layer 736 that cover the transistor 702 and the capacitive element 704, and the common electrode 730 is the other electrode 730. It is electrically connected to the common electrode of the pixel.

With the above configuration, it is possible to control the electric field applied to the layer 732 containing the charged particles and control the arrangement of the charged particles in the layer 732 containing the charged particles. And this makes it possible to realize the display. The above configuration is only an example, and it is not necessary to limit the display device using the semiconductor device, which is one aspect of the disclosed invention, to the above configuration.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

(Embodiment 7) In the present embodiment, specific examples of the application modes of the display device shown in the previous embodiment will be described with reference to FIGS. 24 (A) to 24 (D).

FIG. 24A is a mobile information terminal, which includes a housing 801, a display unit 802, an operation button 803, and the like. The display device described in the previous embodiment can be applied to the display unit 802.

FIG. 24B is an example of an electronic book equipped with the display device described in the previous embodiment. The first housing 811 has a first display unit 812, the first housing 811 has an operation button 813, and the second housing 814 has a second display unit 815. The display device described in the above embodiment can be applied to the first display unit 812 and the second display unit 815. Further, the first housing 811 and the second housing 814 can be opened and closed by the support portion 816. With this configuration, it is possible to perform an operation like a paper book.

FIG. 24C shows a display device 820 for vehicle advertising. When the advertising medium is a printed matter of paper, the advertisement is exchanged manually, but by using the display device, the display of the advertisement can be changed in a short time without human intervention. In addition, a stable image can be obtained without distorting the display.

FIG. 24 (D) shows a display device 830 for outdoor advertising. A display device manufactured by using a flexible substrate is used, and by swinging the display device, the advertising effect can be enhanced.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

100 Oxide semiconductor film 110 Base material 120 Amorphous region 130 Crystal grain 140 Crystal region 200 Oxide semiconductor film 300 Substrate 302 Conductive layer 304 Resist mask 306 Conductive layer 308 Insulation layer 310 Semiconductor layer 312 Resist mask 314 Semiconductor layer 316 Conductive layer 318 Resist Mask 320 Resist Mask 322 Conductive Layer 324 Conductive Layer 326 Insulating Layer 350 Transistor 400 Substrate 402 Conductive Layer 404 Resist Mask 406 Conductive Layer 408 Insulating Layer 410 Conductive Layer 412 Resist Mask 414 Resist Mask 416 Conductive Layer 418 Conductive Layer 420 Semiconductor Layer 422 Resist mask 424 Semiconductor layer 426 Insulation layer 450 Transistor 500 Substrate 502 Semiconductor layer 504 Resist mask 506 Semiconductor layer 508 Conductive layer 510 Resist mask 512 Resist mask 514 Conductive layer 516 Conductive layer 518 Insulating layer 520 Conductive layer 522 Resist mask 524 Conductive layer 550 Transistor 600 Substrate 602 Conductive layer 604 Resist mask 606 Resist mask 608 Conductive layer 610 Conductive layer 612 Semiconductor layer 614 Resist mask 616 Semiconductor layer 618 Insulation layer 620 Conductive Layer 622 Resistor mask 624 Conductive layer 650 Transistor 700 Substrate 702 Conductor 704 Capacitive element 706 Electrophoretic element 708 Substrate 710 Conductive layer 712 Insulation layer 714 Semiconductor layer 716 Conductive layer 718 Conductive layer 720 Gate wire 722 Source wire 724 Conductive layer 726 Capacitive wiring 728 Pixel electrode 730 Common electrode 732 Layer containing charged particles 734 Insulation layer 736 Insulation layer 801 Housing 802 Display 803 Operation button 811 Housing 812 Display 813 Operation button 814 Housing 815 Display 816 Support 820 Display 830 Display