Semiconductor device, module, and electronic device
7 claims: 5 independent, 2 dependent
- 1基板上の 第1の導電体 および 第2の導電体と 、 前記第1の導電体上および前記第2の導電体上の 第1の絶縁体 と、 前記第1の絶縁体上の 第2の絶縁体 と、 前記第2の絶縁体上の、前記第1の導電膜と重なる領域を有する 酸化物半導体 と、 前記酸化物半導体上の 第3の絶縁体 と、 前記第3の絶縁体上の、前記酸化物半導体と重なる領域を有する 第3の導電体 と、 前記第3の導電体の上面と接する領域と、前記酸化物半導体の上面と接する領域と、前記第2の絶縁膜の第1の開口部を介して、前記第1の絶縁体の上面と接する領域と、を有する 第4の絶縁体 と、 前記第4の絶縁体上の 第5の絶縁体 と、 前記第4の絶縁膜の第2の開口部および前記第5の絶縁膜の第3の開口部を介して、前記酸化物半導体と接する領域を有する 第4の導電体 と、 前記第4の絶縁膜の第4の開口部および前記第5の絶縁膜の第5の開口部を介して、前記酸化物半導体と接する領域を有する 第5の導電体 と、 前記第5の絶縁膜の第6の開口部を介して、前記第4の絶縁体の上面と接する領域を有し、かつ、前記第1の絶縁体および前記第4の絶縁体を介して、前記第2の導電体を重なる領域を有する 第6の導電体と 、を 有することを特徴とする半導体装置。
- 2請求項1において、 前記第4の導電体および前記第5の導電体は、前記第3の導電体と重なる領域を有さないことを特徴とする半導体装置。
- 3請求項1または請求項2において、 前記第4の導電体および前記第5の導電体は、前記第1の導電体と重なる領域を有さないことを特徴とする半導体装置。
- 4請求項1乃至請求項3のいずれか一において、 前記酸化物半導体のチャネル幅方向において、前記第3の導電体は、前記酸化物半導体を乗り越える形状を有し、 前記第1の導電体は、前記第1の絶縁体および前記第2の絶縁体を介して、前記酸化物半導体の下面に面する形状を有することを特徴とする半導体装置。
- 5請求項1乃至請求項 4 のいずれか一において、 前記第3の絶縁体は、 前記酸化物半導体のチャネル方向において、 前記第3の導電体よりも迫り出した形状を有することを特徴とする半導体装置。
- 6請求項 5 において、 前記第3の絶縁体は、端部の断面形状が円弧となる領域を有することを特徴とする半導体装置。
- 7請求項1乃至請求項 6 のいずれか一において、 前記第3の導電体は、第1の導電層と、第2の導電層と、を有し、 前記第2の導電層は、前記第1の導電層の上面と接する領域を有し、 前記第1の導電層は、 前記酸化物半導体のチャネル方向において、 前記第2の導電層よりも迫り出した形状を有することを特徴とする半導体装置。
Independent claims7
514 paragraphs, as filed
The present invention relates to a product, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, the present invention relates to, for example, semiconductors, semiconductor devices, display devices, light emitting devices, lighting devices, power storage devices, storage devices or processors. Alternatively, the present invention relates to a method for manufacturing a semiconductor, a semiconductor device, a display device, a light emitting device, a lighting device, a power storage device, a storage device, or a processor. Alternatively, the present invention relates to a method for driving a semiconductor device, a display device, a light emitting device, a lighting device, a power storage device, a storage device, or a processor.
In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Display devices, light emitting devices, lighting devices, electro-optic devices, semiconductor circuits and electronic devices may have semiconductor devices.
Attention is being paid to a technique for constructing a transistor by using a semiconductor on a substrate having an insulating surface. The transistor is widely applied to semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor applicable to transistors.
As the silicon used for the semiconductor of the transistor, amorphous silicon, polycrystalline silicon, single crystal silicon and the like are properly used depending on the application. For example, when applied to a transistor constituting a large display device, it is preferable to use amorphous silicon for which a film forming technique for a large area substrate has been established. On the other hand, when applied to a transistor constituting a high-performance display device in which a drive circuit and a pixel circuit are formed on the same substrate, it is preferable to use polycrystalline silicon capable of producing a transistor having high field effect mobility. Is. Further, when applied to a transistor constituting an integrated circuit or the like, it is preferable to use single crystal silicon capable of producing a transistor having a higher field effect mobility. A method of forming polycrystalline silicon by heat-treating amorphous silicon at a high temperature or performing laser light treatment is known.
In recent years, oxide semiconductors have been attracting attention. Since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used as a semiconductor of a transistor constituting a large display device. Further, since the transistor using the oxide semiconductor has high field effect mobility, it is possible to realize a high-performance display device in which the drive circuit and the pixel circuit are formed on the same substrate. In addition, since it is possible to improve and use a part of the transistor production equipment using amorphous silicon, there is an advantage that capital investment can be suppressed.
By the way, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, a low power consumption CPU to which a low leakage current of a transistor using an oxide semiconductor is applied is disclosed (see Patent Document 1). As described above, when a transistor using an oxide semiconductor is applied to an integrated circuit such as a CPU, it is preferable to reduce the size of the transistor and make it highly integrated.
As semiconductor devices become more highly integrated, the effects of parasitic capacitance formed due to overlapping wiring, electrodes, etc. may not be negligible. A self-aligned top gate structure transistor using an oxide semiconductor is disclosed (see Patent Document 2). Further, Patent Document 3 discloses that a transistor having excellent electrical characteristics can be obtained even if an offset region is provided by allowing electrons to flow into a semiconductor from a conductor electrode. By using the technique disclosed in Patent Document 2 or Patent Document 3, it is possible to reduce the parasitic capacitance formed due to the overlapping of wirings, electrodes, and the like.
Further, it is disclosed that a transistor having high field effect mobility can be obtained by forming a well-type potential with an active layer made of a semiconductor (see Patent Document 4).
<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2012-257187</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2009-278115</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2011-22507</text></patcit><patcit num="4"><text>Japanese Unexamined Patent Publication No. 2012-59860</text></patcit></p>
<p>One of the issues is to provide a semiconductor device having a small parasitic capacitance. Alternatively, one of the issues is to provide a semiconductor device having low power consumption. Another issue is to provide a semiconductor device having excellent frequency characteristics. Alternatively, one of the issues is to provide a semiconductor device having a high degree of integration. Alternatively, one of the issues is to provide a durable semiconductor device. Alternatively, one of the issues is to provide a new semiconductor device.</p><p>The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the problems other than these from the description of the description, drawings, claims, etc. Is.</p>
<p>(1) One aspect of the present invention is a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a sixth conductor. A semiconductor device having a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and an oxide semiconductor. The first insulator has a region in contact with the upper surface of the first conductor and a region in contact with the upper surface of the second conductor, and the second insulator has a region in contact with the upper surface of the first insulator. The oxide semiconductor has a region in contact with the upper surface of the second insulator, the third insulator has a region in contact with the upper surface of the oxide semiconductor, and the third conductor has a contact region. The fourth insulator has a region in contact with the upper surface of the third insulator, a region in contact with the upper surface of the third insulator, a region in contact with the side surface of the third insulator, and an oxide semiconductor. The fifth insulator has a region in contact with the upper surface of the fourth insulator, and the fourth conductor has a region in contact with the upper surface and a region in contact with the upper surface of the first insulator. The fifth conductor has a region in contact with the upper surface of the oxide semiconductor, the sixth conductor has a region in contact with the upper surface of the fourth insulator, and the sixth conductor has a region in contact with the upper surface of the fourth insulator. However, the first conductor has a region in which the first conductor and the oxide semiconductor overlap each other via the first insulator and the second insulator, and the third conductor has a region where the first conductor and the oxide semiconductor overlap each other. , The third conductor and the oxide semiconductor have a region where they overlap each other through the third insulator, and the second conductor passes through the first insulator and the fourth insulator. Therefore, it is a semiconductor device having a region in which the second conductor and the sixth conductor overlap each other.</p><p>(2) Alternatively, in one aspect of the present invention, the oxide semiconductor has a first region in contact with a third insulator and a second region and a third region in contact with the fourth insulator. The second region and the third region have a region having a lower resistance than the first region, and the fourth conductor has a region in contact with the second region and has a fifth conductivity. The body is the semiconductor device according to (1), which has a region in contact with a third region.</p><p>(3) Alternatively, in one aspect of the present invention, the oxide semiconductor includes a first oxide semiconductor and a second oxide semiconductor, and the second oxide semiconductor is a first oxide. The first oxide semiconductor has a higher conductivity than the second oxide semiconductor in a region in which the fourth conductor and the oxide semiconductor overlap each other and has a region in contact with the upper surface of the semiconductor (the first oxide semiconductor has a higher conductivity than the second oxide semiconductor (). The semiconductor device according to 1) or (2).</p><p>(4) Alternatively, in one aspect of the present invention, the oxide semiconductor includes a first oxide semiconductor and a second oxide semiconductor, and the second oxide semiconductor is a first oxide. The second oxide semiconductor has a higher conductivity than the first oxide semiconductor in a region in which the fourth conductor and the oxide semiconductor overlap each other and has a region in contact with the upper surface of the semiconductor (the second oxide semiconductor has a higher conductivity than the first oxide semiconductor (). The semiconductor device according to 1) or (2).</p><p>(5) Alternatively, in one aspect of the present invention, the oxide semiconductor includes a first oxide semiconductor, a second oxide semiconductor, and a third oxide semiconductor, and has a second oxide. The semiconductor has a region in contact with the upper surface of the first oxide semiconductor, the third oxide semiconductor has a region in contact with the upper surface of the second oxide semiconductor, and the fourth conductor and the oxide have an oxide. The semiconductor device according to (1) or (2), wherein the second oxide semiconductor has higher conductivity than the first oxide semiconductor and the third oxide semiconductor in the region where the semiconductor and the semiconductor overlap each other. is there.</p><p>(6) Alternatively, one aspect of the present invention is the semiconductor device according to any one of (1) to (5), wherein the third insulator has a shape protruding more than that of the third conductor. ..</p><p>(7) Alternatively, one aspect of the present invention is the semiconductor device according to (6), wherein the third insulator has a region in which the cross-sectional shape of the end portion is an arc.</p><p>(8) Alternatively, in one aspect of the present invention, the third conductor has a first conductive layer and a second conductive layer, and the second conductive layer is a first conductive layer. The semiconductor device according to any one of (1) to (7), which has a region in contact with the upper surface and the first conductive layer has a shape protruding more than the second conductive layer.</p><p>(9) Alternatively, one aspect of the present invention is the semiconductor device according to (1) to (8), wherein the oxide semiconductor has indium and zinc.</p><p>(10) Or, one aspect of the present invention is a module having the semiconductor device according to any one of (1) to (9) and a printed circuit board.</p><p>(11) Or, one aspect of the present invention includes the semiconductor device according to any one of (1) to (9), the module according to (10), a speaker, an operation key, or a battery. It is an electronic device having.</p><p>In the semiconductor device according to one aspect of the present invention, the oxide semiconductor may be replaced with another semiconductor.</p>
<p>A transistor having a small parasitic capacitance can be provided. Alternatively, a transistor having excellent switching characteristics can be provided. Alternatively, it is possible to provide a transistor having a small current at the time of non-conduction. Alternatively, it is possible to provide a transistor having a large current at the time of conduction. Alternatively, a semiconductor device having the transistor can be provided. Alternatively, a semiconductor device having a small parasitic capacitance can be provided. Alternatively, it is possible to provide a semiconductor device having low power consumption. Alternatively, it is possible to provide a semiconductor device having excellent frequency characteristics. Alternatively, a semiconductor device having a high degree of integration can be provided. Alternatively, a durable semiconductor device can be provided. Alternatively, a new semiconductor device can be provided.</p><p>The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.</p>
<figref num="1">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="2">Top view and sectional view showing the semiconductor device which concerns on one aspect of this invention.</figref><figref num="3">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="4">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="5">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="6">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="7">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="8">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="9">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="10">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="11">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="12">The cross-sectional view which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="13">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="14">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="15">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="16">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="17">The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.</figref><figref num="18">Sectional drawing and band view of the transistor which concerns on one aspect of this invention.</figref><figref num="19">Top view and circuit diagram of the display device according to one aspect of the present invention.</figref><figref num="20">The circuit diagram of the display device which concerns on one aspect of this invention.</figref><figref num="21">The circuit diagram of the display device which concerns on one aspect of this invention.</figref><figref num="22">The circuit diagram of the display device which concerns on one aspect of this invention.</figref><figref num="23">The circuit diagram of the display device which concerns on one aspect of this invention.</figref><figref num="24">Sectional drawing of the display device which concerns on one aspect of this invention.</figref><figref num="25">The figure explaining the display module which concerns on one aspect of this invention.</figref><figref num="26">The circuit diagram of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="27">The circuit diagram of the storage device which concerns on one aspect of this invention.</figref><figref num="28">The block diagram of the RF tag which concerns on one aspect of this invention.</figref><figref num="29">The figure which shows the use example of the RF tag which concerns on one aspect of this invention.</figref><figref num="30">The block diagram which shows the CPU which concerns on one aspect of this invention.</figref><figref num="31">The circuit diagram of the storage element which concerns on one aspect of this invention.</figref><figref num="32">The figure which shows the electronic device which concerns on one aspect of this invention.</figref><figref num="33">The figure which shows the electronic device which concerns on one aspect of this invention.</figref><figref num="34">Cs-corrected high-resolution TEM image in the cross section of CAAC-OS, and schematic cross section of CAAC-OS.</figref><figref num="35">Cs-corrected high-resolution TEM image in the plane of CAAC-OS.</figref><figref num="36">The figure explaining the structural analysis by XRD of CAAC-OS and a single crystal oxide semiconductor.</figref><figref num="37">Cross-sectional TEM image and flowchart of the sample.</figref><figref num="38">The figure explaining the temperature dependence of resistivity.</figref><figref num="39">Schematic diagram, pellet and cross-sectional view of CAAC-OS illustrating the CAAC-OS film formation model.</figref><figref num="40">A schematic diagram illustrating a film formation model of nc-OS and a diagram showing pellets.</figref><figref num="41">The figure explaining the pellet.</figref><figref num="42">The figure explaining the force applied to the pellet on the surface to be formed.</figref><figref num="43">The figure explaining the movement of the pellet on the surface to be formed.</figref><figref num="44">InGaZnO<sub>4</sub>The figure explaining the crystal of.</figref><figref num="45">InGaZnO before the atoms collide<sub>4</sub>The figure explaining the structure of.</figref><figref num="46">InGaZnO after atom collision<sub>4</sub>The figure explaining the structure of.</figref><figref num="47">The figure explaining the trajectory of an atom after the atom collides.</figref><figref num="48">Cross-section HAADF-STEM images of CAAC-OS and targets.</figref><figref num="49">The figure which shows the electron diffraction pattern of CAAC-OS.</figref><figref num="50">The figure which shows the change of the crystal part by electron irradiation of In-Ga-Zn oxide.</figref>
Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be changed in various ways. Further, the present invention is not construed as being limited to the description contents of the embodiments shown below. In explaining the structure of the invention using drawings, reference numerals indicating the same thing are commonly used between different drawings. When referring to the same thing, the hatch pattern may be the same and no particular sign may be added.
In the figure, the size, the thickness of the film (layer), or the region may be exaggerated for clarity.
In addition, the voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, it is possible to paraphrase voltage as electric potential.
The ordinal numbers attached as the first and second numbers are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
Even when the term "semiconductor" is used, for example, if the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, the boundary between "semiconductor" and "insulator" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in the present specification may be paraphrased as an "insulator". Similarly, the "insulator" described herein may be paraphrased as a "semiconductor."
Further, even when the term "semiconductor" is used, for example, if the conductivity is sufficiently high, it may have characteristics as a "conductor". In addition, the boundary between "semiconductor" and "conductor" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in the present specification may be paraphrased as a "conductor". Similarly, the "conductor" described herein may be paraphrased as a "semiconductor."
Note that the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor. For example, elements with a concentration of less than 0.1 atomic% are impurities. The inclusion of impurities may cause, for example, the formation of DOS (Density of State) in a semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, there are, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of oxide semiconductors, oxygen deficiency may be formed due to the mixing of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
In the embodiment shown below, a case where the semiconductor is an oxide semiconductor will be described, but the present invention is not limited to this. For example, silicon, germanium, etc. having a polycrystalline structure or a single crystal structure may be used as the semiconductor. Alternatively, a semiconductor having strain such as strained silicon may be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphate, silicon germanium, etc., which are applicable to high electron mobility transistors (HEMTs) may be used as semiconductors. .. By using these semiconductors, a transistor suitable for high-speed operation can be obtained.
In the present specification, when it is described that A has a region of concentration B, for example, when the total concentration in the depth direction in a certain region of A is B, the concentration in the depth direction in a certain region of A is described. If the average value of is B, if the median concentration in the depth direction in a region of A is B, and if the maximum value of the concentration in the depth direction in a region of A is B, then there is A. When the minimum value of the concentration in the depth direction in the region is B, and the convergence value of the concentration in the depth direction in a certain region of A is B, the concentration in the region where a probable value of A itself can be obtained by measurement is Including the case of B.
Further, when it is described in the present specification that A has a region of size B, length B, thickness B, width B or distance B, for example, the total size and length in a certain region of A. , Thickness, width, or distance is B, and if the average value of size, length, thickness, width, or distance in a region of A is B, then the size, length in a region of A If the median value of the sum, thickness, width, or distance is B, then the maximum size, length, thickness, width, or distance in a region of A is B, then in the region of A. Measured when the minimum size, length, thickness, width, or distance is B, and the convergence value of the size, length, thickness, width, or distance in a region of A is B. Including the case where the size, length, thickness, width, or distance in the region where a probable value of the upper A itself can be obtained is B.
In the present specification, unless otherwise specified, the deposition of insulators, semiconductors, conductors, etc. is performed by a sputtering method, a chemical vapor deposition (CVD) method, or a molecular beam epitaxy (MBE:). It can be carried out by using the Molecular Beam Epitaxy) method, the Pulsed Laser Deposition (PLD) method, the Atomic Layer Deposition (ALD) method, or the like.
The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and the like. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organometallic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.
The plasma CVD method can obtain a high quality film at a relatively low temperature. Since the thermal CVD method does not use plasma, plasma damage does not occur and a film with few defects can be obtained.
In the CVD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the MCVD method and the MOCVD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the MCVD method and the MOCVD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, it is possible to shorten the time required for film formation by the amount of time required for transportation and pressure adjustment as compared with the case of forming a film using a plurality of film forming chambers. it can. Therefore, the productivity of the transistor can be increased.
The channel length is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other in a top view of a transistor, or a region in which a channel is formed. The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.
The channel width is, for example, the source and the drain facing each other in the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the region where the channel is formed. The length of the part that is being used. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.
Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). ) And may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.
Therefore, in the present specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap each other, is referred to as "enclosure channel width (enclosure channel width). SCW: Surrounded Channel Width) ". Further, in the present specification, when simply described as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image and analyzing the image. it can.
When calculating the electric field effect mobility of a transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from that calculated using the effective channel width.
In addition, when it is described in this specification that A has a shape protruding from B, it means that at least one end of A has a shape outside of at least one end of B in the top view or the cross-sectional view. In some cases. Therefore, when it is described that A has a shape protruding from B, it can be read as having a shape in which one end of A is outside the one end of B, for example, in the top view.
The <Semiconductor Device> Hereinafter, with the semiconductor device according to one embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view of a semiconductor device including a transistor 150 and a capacitive element 160.
The semiconductor device shown in FIG. 1 includes an insulator 101 on a substrate 100, a conductor 104a1 on an insulator 101, a conductor 104a2 on a conductor 104a1, a conductor 104b1 on an insulator 101, and a conductor 104b1. Insulator 104b2 above, Insulator 102a on Insulator 101, Insulator 104a1, Insulator 104a2, Insulator 104b1 and Insulator 104b2, Insulator 102b on Insulator 102a, Insulator 102b Upper semiconductor 106a, semiconductor 106b on semiconductor 106a, insulator 112 on semiconductor 106b, conductor 114a on insulator 112, conductor 114b on conductor 114a, insulator on insulator 102a, insulator On 102b, on semiconductor 106a, on semiconductor 106b, on insulator 112, on insulator 114a and on insulator 114b, insulator 118 on insulator 108, on insulator 106b, on insulator 108, Insulation of conductor 116a1 on insulator 118, conductor 116b1 on insulator 106b, insulator 108, insulator 118, conductor 116a2 on insulator 116a1, and conductor 116b2 on insulator 116b1. It has an insulator 128 on the body 118, on the conductor 116a1, on the conductor 116a2, on the conductor 116b1 and on the conductor 116b2.
The insulator 101 may have a function of suppressing impurities from being mixed into the channel forming region of the transistor 150 or the like. For example, when the conductor 104a2 and the conductor 104b2 have impurities for the semiconductor 106a such as copper or the semiconductor 106b, the insulator 101 may have a function of blocking copper or the like.
The laminate of the conductor 104a1 and the conductor 104a2 is collectively referred to as the conductor 104a. The conductor 104a may have a region that functions as a gate electrode for the transistor 150. Further, the conductor 104a may have a function of shielding the channel forming region of the transistor 150 and the like.
The laminate of the conductor 104b1 and the conductor 104b2 is collectively referred to as the conductor 104b. The conductor 104b may have a region that functions as one of the electrodes of the capacitive element 160. Further, the conductor 104b may have a function of shielding the semiconductor device from light.
The conductor 104a1 and the conductor 104b1 may be in the same layer. In that case, the process can be shortened as compared with the case where the conductor 104a1 and the conductor 104b1 are not in the same layer. Further, the conductor 104a2 and the conductor 104b2 may be in the same layer. In that case, the process can be shortened as compared with the case where the conductor 104a2 and the conductor 104b2 are not in the same layer.
The conductor 104a1 is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, ittrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing one or more of tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 104a1, it is particularly preferable to use a conductor containing titanium.
The conductor 104b1 may be used, for example, by selecting from the conductors shown in the conductor 104a1. As the conductor 104b1, it is particularly preferable to use the same type of conductor as the conductor 104a1.
The conductor 104a2 is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, ittrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing at least one tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 104a2, it is particularly preferable to use a conductor containing copper.
The conductor 104b2 may be used, for example, by selecting from the conductors shown in the conductor 104a2. As the conductor 104b2, it is particularly preferable to use the same type of conductor as the conductor 104a2.
The insulator 102a and the insulator 102b are collectively referred to as an insulator 102. The insulator 102 may have a region that functions as a gate insulator for the transistor 150. Further, the insulator 102a may have a function of suppressing impurities from being mixed into the channel forming region of the transistor 150 or the like. For example, when the conductor 104a2 or the like has impurities for the semiconductor 106a or the semiconductor 106b such as copper, the insulator 102a may have a function of blocking copper or the like. Further, the insulator 102a may have a region that functions as a dielectric of the capacitive element 160.
The insulator 102b may have an opening in a region overlapping the conductor 104b. Since the insulator 102b has an opening, the capacitance of the capacitance element 160 can be increased.
The insulator 102a is an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 102a, it is particularly preferable to use silicon nitride or silicon nitride oxide.
Insulation 102b is an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 102b, it is particularly preferable to use silicon oxide or silicon oxide nitride.
The semiconductor 106a and the semiconductor 106b are collectively referred to as a semiconductor 106. The semiconductor 106 may have a region that functions as a channel forming region of the transistor 150.
As the semiconductor 106a, silicon, germanium, or the like having a polycrystalline structure or a single crystal structure may be used. Alternatively, a semiconductor having strain such as strained silicon may be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium and the like applicable to HEMT may be used as the semiconductor 106a. Alternatively, an oxide semiconductor may be used as the semiconductor 106a. As the semiconductor 106a, it is particularly preferable to use an oxide semiconductor.
As the semiconductor 106b, silicon, germanium, or the like having a polycrystalline structure or a single crystal structure may be used. Alternatively, a semiconductor having strain such as strained silicon may be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium and the like applicable to HEMT may be used as the semiconductor 106b. Alternatively, an oxide semiconductor may be used as the semiconductor 106b. As the semiconductor 106b, it is particularly preferable to use an oxide semiconductor.
The details of the oxide semiconductor applicable to the semiconductor 106a and the semiconductor 106b will be described later.
The semiconductor 106a has a region 107a1 and a region 107b1 that do not overlap with the insulator 112, the conductor 114a, the conductor 114b, and the like. Further, the semiconductor 106b has a region 107a2 and a region 107b2 that do not overlap with the insulator 112, the conductor 114a, the conductor 114b, and the like. The region 107a1 and the region 107b1 are regions having lower resistance than the regions overlapping the insulator 112, the conductor 114a, the conductor 114b, and the like of the semiconductor 106a. Further, the region 107a2 and the region 107b2 are regions having lower resistance than the regions overlapping the insulator 112, the conductor 114a, the conductor 114b, etc. of the semiconductor 106b. A region with low resistance can also be referred to as a region with high carrier density.
When semiconductors 106a and 106b are oxide semiconductors, the carrier source may be due to hydrogen and oxygen deficiencies. Details of the carrier source of the oxide semiconductor will be described later.
Further, the area 107a1 and the area 107a2 are collectively referred to as the area 107a. Further, the area 107b1 and the area 107b2 are collectively referred to as an area 107b. Regions 107a and 107b may have regions that serve as source and drain regions for the transistor 150.
The insulator 112 may have a region that functions as a gate insulator for the transistor 150. The insulator 112 may have a shape that protrudes more than the conductor 114a. Further, the insulator 112 may have a region in which the cross-sectional shape of the end portion is an arc. When the insulator 112 has such a shape, it may be possible to suppress the shape defect of the insulator, the conductor, etc. arranged above the insulator 112.
The insulator 112 includes, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 112, it is particularly preferable to use silicon oxide or silicon oxide nitride.
When the semiconductor 106 is an oxide semiconductor, the insulator 102b and / and the insulator 112 having a region in contact with the semiconductor 106 are the energy (Evos) at the upper end of the valence band of the oxide semiconductor and the lower end of the conduction band. It is preferable to use an insulator having a low level density with energy (Ecos). For example, when the level traps electrons, it becomes a factor that fluctuates the threshold voltage of the transistor in the positive direction.
For example, nitrogen oxides in silicon oxide (NO)<sub>X</sub>Also written as. ), Nitric oxide (NO) and nitrogen dioxide (NO)<sub>2</sub>) May form a level between Evos and Ecos. Therefore, in order to obtain a transistor having stable electrical characteristics, it may be preferable to use silicon oxide as the insulator 102b and / and the insulator 112 having a small amount of nitrogen oxides. Although silicon oxide will be described below, the same applies to silicon oxide nitride. In addition, silicon oxide having a small amount of nitrogen oxides may release more ammonia than the amount of nitrogen oxides released in Thermal Desorption Spectroscopy (TDS). For example, the amount of ammonia released is 1 × 10.<sup>18</sup>Pieces / cm<sup>3</sup>Above 5 × 10<sup>19</sup>Pieces / cm<sup>3</sup>It may be as follows. The amount of ammonia released is the amount released by heat treatment when the surface temperature of the film is 50 ° C or more and 650 ° C or less, or 50 ° C or more and 550 ° C or less.
As the insulator 102b and / and the insulator 112, it is preferable to use an insulator that releases oxygen by heating.
Here, the insulator that releases oxygen by heat treatment is 1 × 10 in the surface temperature range of 100 ° C or more and 700 ° C or less or 100 ° C or more and 500 ° C or less in TDS analysis.<sup>18</sup>atoms / cm<sup>3</sup>Above, 1x10<sup>19</sup>atoms / cm<sup>3</sup>Above or 1x10<sup>20</sup>atoms / cm<sup>3</sup>The above oxygen (converted to the number of oxygen atoms) may be released.
Here, a method for measuring the amount of oxygen released using TDS analysis will be described below.
The total amount of gas released when the measurement sample is TDS-analyzed is proportional to the integral value of the ionic strength of the released gas. Then, the total amount of gas released can be calculated by comparing with the standard sample.
For example, from the TDS analysis result of a silicon substrate containing hydrogen of a predetermined density, which is a standard sample, and the TDS analysis result of the measurement sample, the amount of oxygen molecules released from the measurement sample (N).<sub>O2</sub>) Can be calculated by the formula shown below. Here, it is assumed that all the gases detected by the mass-to-charge ratio 32 obtained by the TDS analysis are derived from oxygen molecules. CH<sub>3</sub>The mass-to-charge ratio of OH is 32, but it is not considered here as it is unlikely to exist. Also, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, are not considered because their abundance ratio in nature is extremely small.
N<sub>O2</sub>= N<sub>H2</sub>/ S<sub>H2</sub>× S<sub>O2</sub>× α
N<sub>H2</sub>Is the value obtained by converting the hydrogen molecules desorbed from the standard sample by the density. S<sub>H2</sub>Is the integral value of the ionic strength when the standard sample is TDS analyzed. Here, the reference value of the standard sample is N<sub>H2</sub>/ S<sub>H2</sub>And. S<sub>O2</sub>Is the integral value of the ionic strength when the measurement sample is TDS analyzed. α is a coefficient that affects the ionic strength in TDS analysis. For details of the above formula, refer to JP-A-6-275697. The amount of oxygen released is, for example, 1 × 10 as a standard sample using the EMD-WA1000S / W thermal desorption analyzer manufactured by Electronic Science Co., Ltd.<sup>16</sup>atoms / cm<sup>2</sup>Measurement is performed using a silicon substrate containing a hydrogen atom of.
Also, in TDS analysis, some of the oxygen is detected as oxygen atoms. The ratio of oxygen molecule to oxygen atom can be calculated from the ionization rate of oxygen molecule. Since the above-mentioned α contains the ionization rate of oxygen molecules, the amount of oxygen atoms released can also be estimated by evaluating the amount of oxygen molecules released.
In addition, N<sub>O2</sub>Is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is twice the amount released of oxygen molecules.
Alternatively, the insulator that releases oxygen by heat treatment may contain radical peroxides. Specifically, the spin density due to the peroxide radical is 5 × 10.<sup>17</sup>spins / cm<sup>3</sup>That is all. Insulators containing radical peroxides may have an asymmetric signal with a g value in the vicinity of 2.01 due to electron spin resonance (ESR).
Alternatively, the insulator containing excess oxygen is silicon oxide (SiO) with excess oxygen.<sub>X</sub>It may be (X> 2)). Silicon oxide with excess oxygen (SiO)<sub>X</sub>(X> 2)) contains more than twice the number of silicon atoms as oxygen atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by Rutherford Backscattering Spectrometry (RBS).
In addition, silicon oxide is NO<sub>2</sub>With an ESR of 100K or less, the first absorption line with a g value of 2.037 or more and 2.039 or less, the second absorption line with a g value of 2.001 or more and 2.003 or less, and the third absorption line with a g value of 1.964 or more and 1.966 or less. Signals with lines may be observed. The distance between the first absorption line and the second absorption line, and the distance between the second absorption line and the third absorption line are about 5 mT in the X-band ESR measurement. Therefore, silicon oxide with low nitrogen oxides is NO.<sub>2</sub>Spin density due to 1x10<sup>18</sup>spins / cm<sup>3</sup>Less than or 1x10<sup>17</sup>spins / cm<sup>3</sup>Above 1 × 10<sup>18</sup>spins / cm<sup>3</sup>Is less than.
In addition, silicon oxide with less nitrogen oxides has a nitrogen concentration of 6 × 10 as measured by secondary ion mass spectrometry (SIMS).<sup>20</sup>atoms / cm<sup>3</sup>It is as follows.
The conductor 114a and the conductor 114b are collectively referred to as a conductor 114. The conductor 114 may have a region that functions as a gate electrode for the transistor 150. Alternatively, the conductor 114 may have a function of shielding the channel forming region of the transistor 150 and the like.
The conductor 114a may have a shape that protrudes more than the conductor 114b. Further, the conductor 114b may have a shape that is more prominent than that of the conductor 114a. Further, the conductor 114b may have a region in which the cross-sectional shape of the end portion is an arc. When the conductor 114a and the conductor 114b have such a shape, it may be possible to suppress the shape defect of the insulator, the conductor, etc. arranged above the conductor 114a and the conductor 114b.
The conductor 114a is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, ittrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing one or more of tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 114a, it is particularly preferable to use a conductor containing tantalum nitride.
The conductor 114b is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, ittrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing one or more of tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 114b, it is particularly preferable to use a conductor containing tungsten.
The insulator 108 may have a function of suppressing impurities from being mixed into the channel forming region of the transistor 150 or the like. For example, when the conductor 116a2 and the conductor 116b2 have impurities for the semiconductor 106a such as copper or the semiconductor 106b, the insulator 108 may have a function of blocking copper or the like. Further, the insulator 108 may have a region that functions as a dielectric of the capacitive element 160.
The insulator 108 has an opening that reaches the semiconductor 106. The opening is arranged so as to overlap the region 107a of the semiconductor 106. Further, the opening and another opening may be arranged so as to overlap with the region 107b of the semiconductor 106.
Insulation 108 includes, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 108, it is particularly preferable to use silicon nitride or silicon nitride oxide.
As the insulator 108, an insulator having a low level density between Evos and Ecos may be used.
The insulator 118 may have a region that functions as an interlayer insulator of the transistor 150. For example, by having the insulator 118, it is possible to reduce the parasitic capacitance between each wiring of the transistor 150 (between each conductor).
The insulator 118 has an opening at a position overlapping the opening of the insulator 108 described above. The opening is arranged so as to overlap the region 107a of the semiconductor 106. Further, the opening and another opening may be arranged so as to overlap with the region 107b of the semiconductor 106. Further, the insulator 118 may have an opening in a region overlapping with the conductor 104b. By having the opening in the region where the insulator 118 overlaps with the conductor 104b, the capacitance of the capacitance element 160 can be increased.
Insulation 118 is an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 118, it is particularly preferable to use silicon oxide or silicon oxide nitride.
The conductor 116a1 and the conductor 116a2 are collectively referred to as a conductor 116a. Further, the conductor 116b1 and the conductor 116b2 are collectively referred to as a conductor 116b. Further, the conductor 116c1 and the conductor 116c2 are collectively referred to as a conductor 116c. The conductors 116a and 116b may have regions that function as source and drain electrodes for the transistor 150. Further, the conductor 116a and the conductor 116b may have a function of shielding the channel forming region of the transistor 150 and the like. The conductor 116c may have a region that functions as the other side of the electrode of the capacitive element 160. Further, the conductor 116c may have a function of shielding the semiconductor device from light.
The conductor 116a1, the conductor 116b1, and the conductor 116c1 may be in the same layer. In that case, the process can be shortened as compared with the case where the conductor 116a1, the conductor 116b1 and the conductor 116c1 are not in the same layer. Further, the conductor 116a2, the conductor 116b2, and the conductor 116c2 may be in the same layer. In that case, the process can be shortened as compared with the case where the conductor 116a2, the conductor 116b2, and the conductor 116c2 are not in the same layer.
The conductor 116a1 is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, ittrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing at least one tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 116a1, it is particularly preferable to use a conductor containing titanium nitride, tantalum nitride or tungsten.
The conductor 116b1 may be used, for example, by selecting from the conductors shown in the conductor 116a1. As the conductor 116b1, it is particularly preferable to use the same type of conductor as the conductor 116a1. Further, the conductor 116c1 may be selected and used from, for example, the conductors shown in the conductor 116a1. As the conductor 116c1, it is particularly preferable to use the same type of conductor as the conductor 116a1 or the conductor 116b1.
The conductor 116a2 is, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin. , Tantalum and a conductor containing at least one tungsten may be used in a single layer or in a laminated manner. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. Etc. may be used. As the conductor 116a2, it is particularly preferable to use a conductor containing copper.
The conductor 116b2 may be used, for example, by selecting from the conductors shown in the conductor 116a2. As the conductor 116b2, it is particularly preferable to use the same type of conductor as the conductor 116a2. Further, the conductor 116c2 may be selected and used from, for example, the conductors shown in the conductor 116a2. As the conductor 116c2, it is particularly preferable to use the same type of conductor as the conductor 116a2 or the conductor 116b2. When a conductor containing copper is used as the conductor 116a2, the conductor 116b2 and the conductor 116c2, it may not be necessary to provide the conductor 116a1, the conductor 116b1 and the conductor 116c1. In that case, the semiconductor 106 may be in direct contact with the conductors 116a2 and 116b2, which are conductors containing copper.
The insulator 128 may have a function of suppressing impurities from being mixed into the channel forming region of the transistor 150 or the like.
Insulation 128 is an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, ittrium, zirconium, lantern, neodymium, hafnium or tantalum. It may be used in a single layer or in a laminated manner. As the insulator 128, it is particularly preferable to use silicon nitride or silicon nitride oxide.
As the substrate 100, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, and a compound semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, SOI (Silicon On) Insulator) There is a board and so on. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
Further, a flexible substrate may be used as the substrate 100. As the substrate 100, a sheet, film, foil, or the like in which fibers are woven may be used. Further, the substrate 100 may have elasticity. Further, the substrate 100 may have a property of returning to the original shape when the bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The thickness of the substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By making the substrate 100 thinner, the weight of the semiconductor device can be reduced. Further, by making the substrate 100 thinner, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate 100 due to dropping or the like. That is, it is possible to provide a durable semiconductor device.
As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. As for the substrate 100, which is a flexible substrate, the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed, which is preferable. As the substrate 100 which is a flexible substrate, for example, the coefficient of linear expansion is 1 × 10.<sup>-3</sup>/ K or less, 5 × 10<sup>-5</sup>/ K or less, or 1 × 10<sup>-5</sup>A material of / K or less may be used. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as the substrate 100, which is a flexible substrate.
As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling the transistor, and transposing it to the flexible substrate. In that case, it is advisable to provide a release layer on the substrate 100, which is a non-flexible substrate.
Here, FIG. 2 is a top view and a cross-sectional view of the transistor 150. FIG. 2A shows a top view of the transistor 150. Further, FIG. 2B is a cross-sectional view of the transistor 150 corresponding to the alternate long and short dash line A1-A2 shown in FIG. 2A. Further, FIG. 2C is a cross-sectional view of the transistor 150 corresponding to the alternate long and short dash line A3-A4 shown in FIG. 2A.
Note that FIG. 1 and the like show a cross-sectional view including an A1-A2 cross section (see FIG. 2B) corresponding to a cross-sectional view of the transistor 150 in the channel length direction. Therefore, for FIG. 2 (B), refer to the description in FIG.
From the top view shown in FIG. 2 (A), it can be seen that the transistor 150 has a small parasitic capacitance because the conductor 116a, the conductor 116b, and the conductor 114 do not have a region where they overlap each other. However, the transistor 150 may have a region in which the conductor 116a, the conductor 116b, and the conductor 114 overlap each other. Further, in FIG. 2A, the transistor 150 has a region in which the conductors 116a and 116b and the conductor 104 overlap each other, but the parasitic capacitance is small because a plurality of insulators and the like are provided between them. Become. However, the conductor 116a, the conductor 116b, and the conductor 104 do not have to have a region where they overlap each other.
From FIG. 2C, which corresponds to a cross-sectional view in the channel width direction, the conductor 114 having a region functioning as a gate electrode of the transistor 150 has a shape of passing over the semiconductor 106 via an insulator 112. Therefore, it can be seen that the electric field of the conductor 114 affects the upper surface and the side surface of the semiconductor 106. Further, the conductor 104 having a region functioning as a gate electrode of the transistor 150 has a shape facing the lower surface of the semiconductor 106 via the insulator 102. Therefore, it can be seen that the electric field of the conductor 104 affects the lower surface of the semiconductor 106.
As described above, the transistor 150 has a structure in which the upper surface, the side surface, and the lower surface of the semiconductor 106 are surrounded by an electric field by the conductor 114 and the conductor 104 that function as gate electrodes. Such a structure is referred to herein as an s-channel (surrounded channel) structure.
In a transistor having an s-channel structure, a channel may be formed in the entire semiconductor (bulk). Therefore, a transistor having an s-channel structure can pass a large current between the source and drain, and can increase the current (on-current) at the time of conduction. Further, since the transistor having the s-channel structure is greatly affected by the electric field of the gate electrode, it is possible to quickly switch between conduction and non-conduction of the transistor. Therefore, the transistor having an s-channel structure can reduce the subthreshold swing value (also referred to as S value). Further, since the S value is small, the off-current can be reduced.
<Method of manufacturing a semiconductor device> Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described.
First, the substrate 100 is prepared.
Next, the insulator 101 is formed into a film.
Next, a conductor to be the conductor 104a1 and the conductor 104b1 is formed.
Next, a conductor to be the conductor 104a2 and the conductor 104b2 is formed.
Next, the laminate of the conductors is processed by a lithography process or the like to form a conductor 104a having a conductor 104a1 and a conductor 104a2, and a conductor 104b having a conductor 104b1 and a conductor 104b2 (FIG. 3). reference.). As described above, by forming the conductor 104a and the conductor 104b through the same process, the process can be shortened. That is, the productivity of the semiconductor device can be increased.
Next, the insulator 102a is formed into a film.
Next, the insulator 132 is formed into a film (see FIG. 4). Since the insulator 132 is an insulator that becomes the insulator 102b through a later step, the description about the insulator 102b is referred to.
For silicon oxide with a small amount of nitrogen oxides, for example, use the PECVD method to set the substrate temperature to 220 ° C or higher, 280 ° C or higher, or 350 ° C or higher, and use silane and nitrous oxide as the raw material gas. Can be formed with.
Next, the protective film 113 is formed. As the protective film 113, for example, the above-mentioned conductor, the above-mentioned insulator, the above-mentioned semiconductor, or the like may be used. As the protective film 113, a film having low oxygen permeability is preferably used. As the protective film 113, for example, a film having a lower oxygen permeability than silicon oxide or silicon oxide nitride is used. As the protective film 113, a film having a lower oxygen permeability than tungsten having a columnar crystal structure is preferably used. Tantalum nitride is particularly preferably used as the protective film 113.
Next, a treatment of adding oxygen is performed from the upper surface side of the protective film 113 (see FIG. 5). Examples of the treatment for adding oxygen include plasma treatment in an atmosphere containing an oxidizing gas. The oxidizing gas includes, for example, a gas containing an oxygen atom, specifically, an oxygen gas, a nitrous oxide gas, a carbon dioxide gas, and the like. Alternatively, the process of adding oxygen includes, for example, an oxygen atom or a process of ionizing and doping a molecule containing an oxygen atom. Doping may be performed by doping the mass-separated ions or by doping the ions without mass-separation, and either of them may be used.
Since the protective film 113 has a function of blocking oxygen, oxygen can be added to the insulator 132 and / and the insulator 102a while suppressing the detachment of the added oxygen. Therefore, the amount of oxygen contained in the insulator 132 and / and the insulator 102a is larger when oxygen is added with the protective film 113 than when oxygen is added without the protective film 113. be able to. The protective film 113 may be oxidized by a treatment of adding oxygen.
The protective film 113 may have a function of blocking oxygen and may be thick enough to allow oxygen to reach the lower layer. For example, the protective film 113 may be 1 nm or more and 150 nm or less, or 5 nm or more and 100 nm or less.
When oxygen is added, the insulator 132 and / and the insulator 102a become an insulator containing excess oxygen.
Next, the protective film 113 is removed. However, when the protective film 113 is an insulator or a semiconductor, it may not be necessary to remove the protective film 113.
Next, the insulator 132 is processed by a lithography process or the like to form the insulator 102b (see FIG. 6). The insulator 102b is formed so that the region of the insulator 102a that overlaps with the conductor 104b is exposed.
Next, a semiconductor to be the semiconductor 106a is formed.
Next, a semiconductor to be the semiconductor 106b is formed.
Next, it is preferable to perform the first heat treatment. The first heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower. The first heat treatment is carried out in an atmosphere of an inert gas or an atmosphere containing 10 ppm or more, 1% or more or 10% or more of an oxidizing gas. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, after the heat treatment is performed in an inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas to supplement the desorbed oxygen. Good. By the first heat treatment, the crystallinity of the semiconductor that becomes the semiconductor 106a and the semiconductor that becomes the semiconductor 106b can be increased, and impurities such as hydrogen and water can be removed.
Next, the semiconductor 106a and the semiconductor 106b are formed by processing the laminate of the semiconductors by a lithography process or the like (see FIG. 7).
Next, an insulator to be the insulator 112 is formed.
Next, a conductor to be the conductor 114a is formed.
Next, a conductor to be the conductor 114b is formed.
Next, the laminate of the conductors is processed by a lithography process or the like. Further, by etching under the condition that the etching of the conductor in the upper layer occurs faster than the etching of the conductor in the lower layer, the conductor 114b and the conductor 114a having a shape protruding more than the conductor 114b are formed.
Next, by using the conductor 114a or the like as a mask and processing the insulator to be the insulator 112, the insulator 112 having a shape protruding from the conductor 114a is formed. At this time, etching may be performed from the upper surface of the semiconductor 106 by 0.1 nm or more and 5 nm or less.
Next, the semiconductor 106 is processed using the insulator 112, the conductor 114a, and the conductor 114b as masks (see FIG. 8).
The treatment can be performed, for example, by adding an impurity having a function of increasing the carrier density of the semiconductor 106. When the semiconductor 106 is an oxide semiconductor, one or more selected from, for example, boron, carbon, nitrogen, neon, aluminum, phosphorus, argon, manganese, arsenic, krypton, xenon and the like may be used as the impurity. As the impurity, it is particularly preferable to use argon. Impurities may be added by a doping method or the like. Further, the treatment may be performed, for example, by plasma treatment in an atmosphere containing the above-mentioned element (for example, argon or the like). The plasma treatment is preferably performed so that a self-bias is applied to the substrate 100 side, for example.
When the above-mentioned treatment is performed on the oxide semiconductor, oxygen in the oxide semiconductor is eliminated and oxygen deficiency (V) is performed.<sub>O</sub>Also written as. ) Can be formed. Oxygen deficiency with adjacent hydrogen (V)<sub>O</sub>Also written as H. ) Form a donor level in the oxide semiconductor, so that the carrier density of the region to be treated can be increased and the resistance can be reduced. V<sub>O</sub>The details of H forming the donor level will be described later.
In this way, the regions 107a1 and 107b1 which are the regions to be processed of the semiconductor 106a and the regions 107a2 and 107b2 which are the regions to be processed of the semiconductor 106b can be formed (see FIG. 9). The area 107a1 and the area 107a2 are collectively referred to as the area 107a. Further, the area 107b1 and the area 107b2 are collectively referred to as an area 107b.
Next, the insulator 138 is formed into a film. Since the insulator 138 is an insulator that becomes the insulator 108 through a later step, the description about the insulator 108 is referred to.
The insulator 138 is preferably formed by the PECVD method. For example, hydrogen can be added to the region 107a and the region 107b by forming an insulator having hydrogen, particularly silicon nitride having hydrogen (also referred to as SiNH) as the insulator 138. As a result, the hydrogen is contained in the regions 107a and 107b.<sub>O</sub>V that forms a donor level by filling<sub>O</sub>H can be formed efficiently. If the insulator 138 contains a sufficient amount of hydrogen, V in regions 107a and 107b<sub>O</sub>Hydrogen is desorbed from H and V<sub>O</sub>Even if it becomes V immediately<sub>O</sub>Can be returned to H. Therefore, the region 107a and the region 107b formed in this way can stably maintain a low resistance state. That is, when the region 107a and the region 107b are used for the source region and the drain region, the on-current of the transistor 150 can be increased.
An oxide semiconductor that has been made into a conductor in this way can be called an oxide conductor. In general, oxide semiconductors have a large energy gap and therefore have translucency with respect to visible light. On the other hand, the oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption by the donor level is small, and it has the same level of translucency as an oxide semiconductor with respect to visible light.
Here, the temperature dependence of resistivity in the oxide conductor will be described with reference to FIG. 38.
As the oxide conductor contained in the sample whose resistivity is measured, the oxide conductor (OC_SiNH) formed by contacting the oxide semiconductor with silicon nitride containing hydrogen, and argon is added to the oxide semiconductor in the doping apparatus. , And an oxide conductor (OC_Ar dope + SiNH) formed by contacting with silicon nitride containing hydrogen, or irradiating argon ions with argon plasma in a plasma processing apparatus and contacting with silicon nitride containing hydrogen. An oxide conductor (OC_Ar plasma + SiNH) formed in (OC_Ar plasma + SiNH) was prepared.
The method for preparing a sample containing an oxide conductor (OC_SiNH) is shown below. First, silicon oxide having a thickness of 400 nm is formed on a glass substrate by the PECVD method, and then oxygen ions are added to the silicon oxide using oxygen plasma to form silicon oxide that releases oxygen by heating. did. Next, in-Ga-Zn oxidation with a thickness of 100 nm was performed by a sputtering method using a sputtering target with an atomic number ratio of In: Ga: Zn = 1: 1: 1.2 on silicon oxide nitride that releases oxygen by heating. A product was formed and heat-treated in a nitrogen atmosphere at 450 ° C., and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 ° C. Next, silicon nitride having a thickness of 100 nm was formed by the PECVD method. Next, heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen at 350 ° C.
The method for preparing a sample containing an oxide conductor (OC_Ar dope + SiNH) is shown below. First, silicon oxide having a thickness of 400 nm is formed on a glass substrate by the PECVD method, and then oxygen ions are added to the silicon oxide using oxygen plasma to form silicon oxide that releases oxygen by heating. did. Next, in-Ga-Zn oxidation with a thickness of 100 nm was performed by a sputtering method using a sputtering target with an atomic number ratio of In: Ga: Zn = 5: 5: 6 on silicon oxide nitride that releases oxygen by heating. A product was formed and heat-treated in a nitrogen atmosphere at 450 ° C., and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 ° C. Next, using a doping device, the acceleration voltage is set to 10 kV for the In-Ga-Zn oxide, and the dose amount is 5 × 10.<sup>14</sup>/cm<sup>2</sup>Argon was added to form an oxygen deficiency in the In-Ga-Zn oxide. Next, silicon nitride having a thickness of 100 nm was formed by the PECVD method. Next, heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen at 350 ° C.
The method for preparing a sample containing an oxide conductor (OC_Ar plasma + SiNH) is shown below. First, silicon oxide nitriding having a thickness of 400 nm was formed on a glass substrate by the PECVD method, and then silicon oxide nitriding that releases oxygen by heating was formed by using oxygen plasma. Next, in-Ga-Zn oxidation with a thickness of 100 nm was performed by a sputtering method using a sputtering target with an atomic number ratio of In: Ga: Zn = 1: 1: 1.2 on silicon oxide nitride that releases oxygen by heating. A product was formed and heat-treated in a nitrogen atmosphere at 450 ° C., and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 ° C. Next, in the plasma processing apparatus, an oxygen deficiency was formed by generating argon plasma and causing the accelerated argon ions to collide with the In-Ga-Zn oxide. Next, silicon nitride having a thickness of 100 nm was formed by the PECVD method. Next, heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen at 350 ° C.
Next, the result of measuring the resistivity of each sample is shown in FIG. 38. Here, the resistivity was measured by the 4-terminal van-der-Pauw method. In FIG. 38, the horizontal axis represents the measured temperature and the vertical axis represents the resistivity. In addition, the measurement result of the oxide conductor (OC_SiNH) is indicated by a square mark, the measurement result of the oxide conductor (OC_Ar dope + SiNH) is indicated by a circle, and the measurement result of the oxide conductor (OC_Ar plasma + SiNH) is shown. Is indicated by a triangle mark.
Although not shown, an oxide semiconductor that does not come into contact with silicon nitride containing hydrogen has a high resistivity, and it is difficult to measure the resistivity. Therefore, it can be seen that the oxide conductor has a lower resistivity than the oxide semiconductor.
From FIG. 38, it can be seen that the oxide conductor (OC_Ar dope + SiNH) and the oxide conductor (OC_Ar plasma + SiNH) contain oxygen deficiency and hydrogen, so that the resistivity fluctuation is small. Typically, at 80K or more and 290K or less, the resistivity has a volatility of less than ± 20%. Alternatively, at 150K or more and 250K or less, the resistivity is a volatility of less than ± 10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the lower end of the conduction band and the Fermi level coincide with or substantially coincide with each other. Therefore, by using the oxide conductor as the source region and the drain region of the transistor, the oxide conductor and the conductor functioning as the source electrode and the drain electrode are in ohmic contact, and the conductor functions as the source electrode and the drain electrode. The contact resistance between the body and the oxide conductor can be reduced. Further, since the resistivity of the oxide conductor is low in temperature dependence, the fluctuation amount of the contact resistance between the conductor functioning as the source electrode and the drain electrode and the oxide conductor is small, and the transistor is highly reliable. Can be produced.
Next, an insulator to be the insulator 148 is formed. Since the insulator that becomes the insulator 148 is an insulator that becomes the insulator 118 through a later step, the description about the insulator 118 is referred to.
Next, a second heat treatment may be performed. By performing the second heat treatment, excess oxygen contained in the insulator 102 or the like moves to the semiconductor 106b via the semiconductor 106a. Since the semiconductor 106b is covered with any one of the semiconductor 106c, the insulator 112, and the insulator 108, the outward diffusion of excess oxygen is unlikely to occur. Therefore, by performing the second heat treatment at this timing, the defect (oxygen deficiency) of the semiconductor 106b can be efficiently reduced. The second heat treatment may be performed at a temperature at which excess oxygen (oxygen) in the insulator 102 diffuses to the semiconductor 106b. For example, the description about the first heat treatment may be referred to. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20 ° C or more and 150 ° C or less, preferably 40 ° C or more and 100 ° C or less. As a result, it is possible to suppress the release of excess oxygen (oxygen) from the insulator 102.
Next, the insulator 148 is formed by processing the insulator by a lithography process or the like (see FIG. 10). The insulator 148 is formed so that the region of the insulator 138 that overlaps with the conductor 104b is exposed.
Next, the laminate of the insulator 138 and the insulator 148 is processed by a lithography process or the like to form a laminate of the insulator 108 and the insulator 118 (see FIG. 11). The insulator 108 and the insulator 118 are formed so that the region 107a and the region 107b are exposed.
Next, a conductor to be the conductor 116a1, the conductor 116b1 and the conductor 116c1 is formed.
Next, a conductor to be the conductor 116a2, the conductor 116b2, and the conductor 116c2 is formed.
Next, by processing the laminate of the conductors by a lithography process or the like, the conductors 116a having the conductors 116a1 and 116a2, the conductors 116b having the conductors 116b1 and the conductors 116b2, and the conductors 116c1 and the conductors are conductive. Form a conductor 116c having a body 116c2. As described above, by forming the conductor 116a, the conductor 116b, and the conductor 116c through the same process, the process can be shortened. That is, the productivity of the semiconductor device can be increased.
Next, the insulator 128 is formed into a film (see FIG. 12).
As described above, a semiconductor device including the transistor 150 and the capacitive element 160 can be manufactured.
<Modification Example of Semiconductor Device> In FIG. 1 and the like, the semiconductor 106 of the transistor 150 has a region functioning as a channel forming region and a region 107a and a region 107b having a region functioning as a source region and a drain region. Although the structure has been described, the semiconductor device according to one aspect of the present invention is not limited to this structure. For example, as shown in FIG. 13, the structure may have a region 107c, a region 107d, a region 107e, and a region 107f inside the region 107a and the region 107b of the semiconductor 106. ..
The region 107c has a region adjacent to the region 107a. Further, the region 107c has a region that overlaps with the insulator 112 and does not overlap with the conductor 114a. Further, the region 107d has a region adjacent to the region 107b. Further, the region 107d has a region that overlaps with the insulator 112 and does not overlap with the conductor 114a. Further, the region 107e has a region adjacent to the region 107c. Further, the region 107e has a region that overlaps with the conductor 114a and does not overlap with the conductor 114b. Further, the region 107f has a region adjacent to the region 107d. Further, the region 107f has a region that overlaps with the conductor 114a and does not overlap with the conductor 114b.
The region 107c may have, for example, a region that functions as an LDD (Lightly Doped Drain) region. The LDD region has a lower carrier density and / and impurity concentration than the source region or drain region, and has a higher carrier density and / and impurity concentration than the channel formation region. Alternatively, the region 107c may have, for example, a region that functions as an offset region. The offset region has a region of carrier density and / and impurity concentration similar to that of the channel formation region.
Further, the region 107d may have, for example, a region that functions as an LDD region. Further, the region 107d may have a region that functions as an offset region, for example. Further, the region 107e may have, for example, a region that functions as an LDD region. Further, the region 107e may have a region that functions as an offset region, for example. Further, the region 107f may have, for example, a region that functions as an LDD region. Further, the region 107f may have a region that functions as an offset region, for example. In the semiconductor 106, the region where the region 107e and / and the region 107f and the conductor 114a overlap each other is referred to as an overlap region.
By having at least one of the region 107c, the region 107d, the region 107e, and the region 107f having a region functioning as an LDD region and / or a region functioning as an offset region, deterioration due to concentration of the drain electric field of the transistor is reduced. be able to. That is, it can be a highly reliable semiconductor device.
For example, when the region 107c and the region 107d have a region functioning as an LDD region and the region 107e and the region 107f have a region functioning as an offset region, deterioration due to concentration of the drain electric field of the transistor can be reduced in particular. It may be possible and preferable.
The length of each region functioning as the LDD region in the channel length direction is preferably less than 20%, less than 10%, less than 5%, or less than 2% of the distance between the source region and the drain region. .. Alternatively, the length of each of the overlap regions in the channel length direction is preferably less than 20%, less than 10%, less than 5%, or less than 2% of the distance between the source region and the drain region. Alternatively, the length of each region that functions as an offset region in the channel length direction is preferably less than 20%, less than 10%, less than 5%, or less than 2% of the distance between the source region and the drain region. ..
Further, in FIG. 1 and the like, a structure in which the semiconductor 106 having a region functioning as a channel forming region of the transistor 150 has two layers of the semiconductor 106a and the semiconductor 106b is described, but the semiconductor device according to one aspect of the present invention is described. , Not limited to this structure. For example, as shown in FIG. 14, the semiconductor 106 may have a structure having three layers of the semiconductor 106a, the semiconductor 106b, and the semiconductor 106c. In this case, the region 107a has a structure including the region 107a1, the region 107a2, and the region 107a3. Further, the region 107b has a structure having a region 107b1, a region 107b2, and a region 107b3. Further, as shown in FIG. 15, the semiconductor 106 may have a single-layer structure. In this case, the region 107a has a single layer structure. Further, the area 107b has a single layer structure.
Further, in FIG. 1 and the like, a structure having a region in which the cross-sectional shape of the end portion of the insulator 112 having a region functioning as a gate insulator of the transistor 150 is an arc is described, but it relates to one aspect of the present invention. The semiconductor device is not limited to this structure. For example, as shown in FIG. 16, a structure may have a structure in which the cross-sectional shape of the end portion of the insulator 112 does not have an arcuate region.
It is preferable that at least one of the insulator 112, the conductor 114a, and the conductor 114b of the transistor 150 according to one aspect of the present invention has a taper angle. For example, the insulator 112 has an angle θ formed by the upper surface of the semiconductor 106 and the side surface of the insulator 112.<sub>1</sub>It is preferable to have a cross section in which is less than 90 °, 30 ° or more and 85 ° or less, or 45 ° or more and 70 ° or less. Further, the conductor 114a has an angle θ formed by the upper surface of the insulator 112 and the side surface of the conductor 114a.<sub>2</sub>It is preferable to have a cross section having a cross section of less than 90 °, 10 ° or more and 85 ° or less, 15 ° or more and 85 ° or less, 30 ° or more and 85 ° or less, or 45 ° or more and 70 ° or less. Further, the conductor 114b has an angle θ formed by a straight line substantially parallel to the upper surface of the conductor 114a and a straight line substantially parallel to the side surface of the conductor 114b.<sub>3</sub>It is preferable to have a cross section in which is less than 90 °, or 30 ° or more and 85 ° or less, or 45 ° or more and 70 ° or less. Also, the angle θ<sub>1</sub>Is the angle θ<sub>2</sub>If it is smaller than that, the covering property of the layer to be formed later becomes high, which is preferable. Also, the angle θ<sub>3</sub>Is the angle θ<sub>2</sub>If it is smaller than that, the covering property of the layer to be formed later becomes high, which is preferable.
<Positional Relationship of Wiring> Hereinafter, the connection of each wiring of the semiconductor device according to one aspect of the present invention will be described.
FIG. 17A is a cross-sectional view showing an example of the connection between the wirings of the semiconductor device. In FIG. 17A, the conductor 104c which is the same layer as the conductor 104a and / and the conductor 104b and the conductor 116d which is the same layer as the conductor 116a, the conductor 116b and / and the conductor 116c and the like are shown. And show the connection part when connecting electrically. Specifically, the conductor 104c has a region in contact with the conductor 115a, which is the same layer as the conductor 114, through the openings provided in the insulator 102 and the insulator 112, and the conductor 116d has a region in contact with the conductor 115a. It suffices to have a region in contact with the conductor 115a through the openings provided in the insulator 108 and the insulator 118.
The openings provided in the insulator 102 and the insulator 112 may be formed through the same steps or may be formed through different steps. Further, the openings provided in the insulator 108 and the insulator 118 may be formed through the same steps or may be formed through different steps. By performing these steps together with the fabrication of the transistor 150 and the capacitive element 160, the productivity of the semiconductor device may be increased.
FIG. 17B is a cross-sectional view showing an example of the connection between the wirings of the semiconductor device. In FIG. 17B, the conductor 104d which is the same layer as the conductor 104a and / and the conductor 104b and the conductor 116e which is the same layer as the conductor 116a, the conductor 116b and / and the conductor 116c and the like are shown. And show the connection part when connecting electrically. Specifically, the conductor 104d may have a region in contact with the conductor 116e through the openings provided in the insulator 108 and the insulator 118.
The openings provided in the insulator 108 and the insulator 118 may be formed through the same steps or may be formed through different steps. By performing these steps together with the fabrication of the transistor 150 and the capacitive element 160, the productivity of the semiconductor device may be increased.
FIG. 17C is a cross-sectional view showing an example of the connection between the wirings of the semiconductor device. FIG. 17C shows a case where the conductor 104e, which is the same layer as the conductor 104a and / and the conductor 104b, and the conductor 115b, which is the same layer as the conductor 114, are electrically connected. Indicates the connection part. Specifically, the conductor 104e may have a region in contact with the conductor 115b through the openings provided in the insulator 102 and the insulator 112.
The openings provided in the insulator 102 and the insulator 112 may be formed through the same steps or may be formed through different steps. By performing these steps together with the fabrication of the transistor 150 and the capacitive element 160, the productivity of the semiconductor device may be increased.
FIG. 17 (D) is a cross-sectional view showing an example of the intersection between the wirings of the semiconductor device. In FIG. 17 (D), the conductor 104f which is the same layer as the conductor 104a and / and the conductor 104b and the conductor 116f which is the same layer as the conductor 116a, the conductor 116b and / and the conductor 116c and the like are shown. And indicates the overlapping region via the insulator 102, the insulator 108 and the insulator 118.
By having a plurality of layers of insulators between the wirings, it is possible to reduce the parasitic capacitance between the wirings. Therefore, since it is possible to suppress a decrease in frequency characteristics (also referred to as f characteristics) due to parasitic capacitance, it can be seen that the semiconductor device according to one aspect of the present invention has good f characteristics.
<Oxide semiconductors> The following describes oxide semiconductors applicable to semiconductors 106, semiconductors 106a, semiconductors 106b, semiconductors 106c, and the like.
The oxide semiconductor is, for example, an oxide containing indium. When the oxide semiconductor contains, for example, indium, the carrier mobility (electron mobility) becomes high. Further, the oxide semiconductor preferably contains the element M. The element M is preferably aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, there are cases where a plurality of the above-mentioned elements may be combined as the element M. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Further, the oxide semiconductor preferably contains zinc. Oxide semiconductors may be easily crystallized if they contain zinc.
However, the oxide semiconductor is not limited to the oxide semiconductor containing indium. The oxide semiconductor may be, for example, an oxide semiconductor containing zinc, zinc-containing oxide semiconductor, gallium-containing oxide semiconductor, tin-containing oxide semiconductor, etc., which does not contain indium, such as zinc tin oxide and gallium tin oxide. ..
As the oxide semiconductor, for example, an oxide having a large energy gap is used. The energy gap of the oxide semiconductor is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.
The on-current of the transistor can be increased so as to reduce the factors that hinder the movement of electrons. For example, if there is no factor that hinders the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel forming region is large.
In order to increase the on-current of the transistor, for example, the root mean square (RMS) roughness of the upper surface or the lower surface of the oxide semiconductor in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm. It may be more preferably less than 0.5 nm, more preferably less than 0.4 nm. Further, the average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. Further, the maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm may be less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. RMS roughness, Ra and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nanotechnology Co., Ltd.
If copper is mixed in the oxide semiconductor, an electron trap may be generated. The electron trap may fluctuate the threshold voltage of the transistor in the positive direction. Therefore, the lower the copper concentration on the surface or inside of the oxide semiconductor, the more preferable. For example, oxide semiconductors have a copper concentration of 1 × 10.<sup>19</sup>atoms / cm<sup>3</sup>Below, 5 × 10<sup>18</sup>atoms / cm<sup>3</sup>Below, or 1x10<sup>18</sup>atoms / cm<sup>3</sup>It is preferable to have the following regions.
<Structure of Oxide Semiconductor> The structure of the oxide semiconductor will be described below.
As used herein, the term "parallel" means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of -5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Non-single crystal oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline Oxide Semiconductor), and pseudo-amorphous oxide semiconductor (a-like OS: amorphous). like Oxide Semiconductor), amorphous oxide semiconductors, etc.
From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.
It is generally known that the definition of an amorphous structure is that it is not immobilized in a metastable state, that it is isotropic and does not have an anisotropic structure, and the like. In addition, it can be rephrased as a structure in which the coupling angle is flexible and the structure has short-range order but does not have long-range order.
On the contrary, an essentially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Also, an oxide semiconductor that is not isotropic (for example, having a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as a void) and has an unstable structure. Therefore, it can be said that the physical characteristics are close to those of an amorphous oxide semiconductor.
<CAAC-OS> First, CAAC-OS will be explained.
CAAC-OS is one of oxide semiconductors having a plurality of c-axis oriented crystal portions (also referred to as pellets).
Multiple pellets can be confirmed by observing a composite analysis image (also called a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM). .. On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.
The CAAC-OS observed by TEM will be described below. Figure 34 (A) shows a high-resolution TEM image of the cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. The Spherical Aberration Corrector function was used to observe the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be acquired by, for example, the atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.
A Cs-corrected high-resolution TEM image obtained by enlarging the region (1) of FIG. 34 (A) is shown in FIG. 34 (B). From FIG. 34 (B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface on which the CAAC-OS film is formed, and is parallel to the surface to be formed or the upper surface of CAAC-OS.
As shown in FIG. 34 (B), CAAC-OS has a characteristic atomic arrangement. FIG. 34 (C) shows the characteristic atomic arrangement with auxiliary lines. From FIGS. 34 (B) and 34 (C), it can be seen that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap generated by the inclination of the pellet and the pellet is about 0.8 nm. Therefore, pellets can also be called nanocrystals (nc: nanocrystals). CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).
Here, if the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, the structure is as if bricks or blocks were stacked (Fig. 34 (D)). reference.). The portion of the inclination observed between the pellets observed in FIG. 34 (C) corresponds to the region 5161 shown in FIG. 34 (D).
In addition, Fig. 35 (A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. Cs-corrected high-resolution TEM images obtained by enlarging the region (1), region (2), and region (3) of FIG. 35 (A) are shown in FIGS. 35 (B), 35 (C), and 35 (D), respectively. Shown. From FIGS. 35 (B), 35 (C) and 35 (D), it can be confirmed that the metal atoms of the pellet are arranged in a triangular, quadrangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different pellets.
Next, CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, InGaZnO<sub>4</sub>When the structural analysis by the out-of-plane method is performed on CAAC-OS having the above crystals, a peak may appear in the diffraction angle (2θ) near 31 ° as shown in FIG. 36 (A). This peak is InGaZnO<sub>4</sub>Since it is attributed to the (009) plane of the crystal, it can be confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface.
In the structural analysis by the out-of-plane method of CAAC-OS, in addition to the peak near 31 ° in 2θ, the peak may appear near 36 ° in 2θ. The peak with 2θ near 36 ° indicates that some crystals in CAAC-OS do not have c-axis orientation. For more preferable CAAC-OS, 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 ° in the structural analysis by the out-of-plane method.
On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction substantially perpendicular to the c-axis, a peak appears near 56 ° in 2θ. This peak is InGaZnO<sub>4</sub>It is attributed to the (110) plane of the crystal. In the case of CAAC-OS, even if 2θ is fixed near 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Fig. 36 (B) shows. No clear peaks appear as shown. On the other hand, InGaZnO<sub>4</sub>In the case of the single crystal oxide semiconductor of, when 2θ is fixed near 56 ° and φ scan is performed, as shown in Fig. 36 (C), there are 6 peaks assigned to the crystal plane equivalent to the (110) plane. Observed. Therefore, it can be confirmed from the structural analysis using XRD that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.
Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGaZnO<sub>4</sub>When an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having the above crystals in parallel with the sample surface, a diffraction pattern (also referred to as selected area diffraction pattern) as shown in FIG. 49 (A) is obtained. May appear. This diffraction pattern includes InGaZnO<sub>4</sub>Includes spots due to the (009) plane of the crystal. Therefore, it can be seen from electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 49 (B) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 49 (B), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction. The first ring in Fig. 49 (B) is InGaZnO.<sub>4</sub>It is considered that this is due to the (010) plane and the (100) plane of the crystal of. Further, it is considered that the second ring in FIG. 49 (B) is caused by the surface (110) and the like.
As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of oxide semiconductors may decrease due to the mixing of impurities and the formation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (oxygen deficiency, etc.) from the opposite perspective.
Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than the metal element constituting the oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.
When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in an oxide semiconductor may serve as a carrier trap or a carrier generation source. Further, the oxygen deficiency in the oxide semiconductor may become a carrier trap or a carrier generation source by capturing hydrogen.
CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor with a low carrier density. Specifically, the carrier density is 8 × 10.<sup>11</sup>/cm<sup>3</sup>Less than, preferably 1x10<sup>11</sup>/cm<sup>3</sup>Less than, more preferably 1x10<sup>10</sup>/cm<sup>3</sup>Less than 1x10<sup>-9</sup>/cm<sup>3</sup>It can be the above. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.
<nc-OS> Next, nc-OS will be described.
The nc-OS has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal part contained in nc-OS is often 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less in size. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, the grain boundaries may not be clearly confirmed. Nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, in the following, the crystal part of nc-OS may be referred to as a pellet.
nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method. For example, when X-rays having a diameter larger than that of pellets are used for nc-OS, the peak indicating the crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction is performed on nc-OS using an electron beam having a probe diameter larger than that of the pellet (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when nanobeam electron diffraction is performed on nc-OS using an electron beam having a probe diameter close to or smaller than the pellet size. In addition, when nanobeam electron diffraction is performed on nc-OS, a region with high brightness (ring-shaped) may be observed in a circular motion. Furthermore, a plurality of spots may be observed in the ring-shaped region.
As described above, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.
nc-OS is an oxide semiconductor with higher regularity than the amorphous oxide semiconductor. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density than CAAC-OS.
<a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
In a-like OS, voids may be observed in high-resolution TEM images. Further, in the high-resolution TEM image, it has a region where the crystal portion can be clearly confirmed and a region where the crystal portion cannot be confirmed.
The a-like OS has an unstable structure because it has voids. In the following, we show that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, so we show the structural changes due to electron irradiation.
Prepare a-like OS (denoted as sample A), nc-OS (denoted as sample B) and CAAC-OS (denoted as sample C) as samples to be subjected to electron irradiation. Both samples are In-Ga-Zn oxides.
First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, it can be seen that each sample has a crystal part.
It should be noted that the determination as to which portion is regarded as one crystal portion may be performed as follows. For example, InGaZnO<sub>4</sub>It is known that the unit cell of the crystal of is having a structure in which a total of 9 layers are layered in the c-axis direction, which has 3 layers of In-O and 6 layers of Ga-Zn-O. .. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, InGaZnO is located where the spacing between the plaids is 0.28 nm or more and 0.30 nm or less.<sub>4</sub>It can be regarded as the crystal part of. The plaid is InGaZnO.<sub>4</sub>Corresponds to the ab plane of the crystal.
FIG. 50 is an example of investigating the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 50, it can be seen that in the a-like OS (Sample A), the crystal portion becomes larger according to the cumulative irradiation amount of electrons. Specifically, as shown in (1) in Fig. 50, the crystal part (also called the initial nucleus), which had a size of about 1.2 nm at the initial stage of TEM observation, has a cumulative irradiation dose of 4.2 × 10.<sup>8</sup>e<sup>-</sup>/ nm<sup>2</sup>It can be seen that the size of the plant has grown to about 2.6 nm. On the other hand, nc-OS (Sample B) and CAAC-OS (Sample C) have a cumulative electron irradiation dose of 4.2 × 10 from the start of electron irradiation.<sup>8</sup>e<sup>-</sup>/ nm<sup>2</sup>It can be seen that there is no change in the size of the crystal part in the range up to. Specifically, as shown in (2) and (3) in FIG. 50, the size of the crystal part of nc-OS and CAAC-OS is about 1.4 nm, respectively, regardless of the cumulative irradiation amount of electrons. It can be seen that it is about 2.1 nm.
As described above, in a-like OS, the growth of the crystal part may be observed by electron irradiation. On the other hand, it can be seen that in nc-OS and CAAC-OS, almost no growth of the crystal part due to electron irradiation is observed. That is, it can be seen that a-like OS has an unstable structure as compared with nc-OS and CAAC-OS.
In addition, because it has voids, a-like OS has a structure with a lower density than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of single crystals having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.
For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], a single crystal InGaZnO having a rhombohedral structure.<sub>4</sub>Density is 6.357g / cm<sup>3</sup>Will be. Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm.<sup>3</sup>More than 5.9g / cm<sup>3</sup>Will be less than. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm.<sup>3</sup>More than 6.3g / cm<sup>3</sup>Will be less than.
In some cases, single crystals having the same composition do not exist. In that case, the density corresponding to the single crystal in the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.
As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.
<Film formation model> The CAAC-OS and nc-OS film formation models will be described below.
FIG. 39 (A) is a schematic view of a film forming chamber showing how CAAC-OS is formed by the sputtering method.
The target 230 is glued onto the backing plate. A plurality of magnets are arranged under the target 230 and the backing plate. A magnetic field is generated on the target 230 by the plurality of magnets. A sputtering method that uses the magnetic field of a magnet to increase the film formation rate is called a magnetron sputtering method.
The target 230 has a polycrystalline structure, and any of the crystal grains contains a cleavage plane. The details of the cleavage plane will be described later.
The substrate 220 is arranged so as to face the target 230, and the distance d (the distance between the target and the substrate (also referred to as the distance between TSs)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. .. Most of the film forming chamber is filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen in a proportion of 50% by volume or more), and is controlled to 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Will be done. Here, by applying a voltage above a certain level to the target 230, discharge starts and plasma is confirmed. A high-density plasma region is formed by the magnetic field on the target 230. In the high-density plasma region, ions 201 are generated by ionizing the film-forming gas. Ion 201 is, for example, a cation of oxygen (O).<sup>+</sup>) And argon cations (Ar)<sup>+</sup>) And so on.
Ion 201 is accelerated toward the target 230 by the electric field and eventually collides with the target 230. At this time, the pellets 200a and the pellets 200b, which are flat or pellet-shaped sputtered particles, are peeled off from the cleaved surface and knocked out. The structures of the pellets 200a and 200b may be distorted due to the impact of the collision of ions 201.
Pellet 200a is a flat or pellet-shaped sputtered particle having a triangular, eg equilateral, triangular plane. Further, the pellet 200b is a flat plate-like or pellet-like sputtered particle having a hexagonal surface, for example, a regular hexagonal plane. The flat or pellet-shaped sputtered particles such as pellets 200a and pellets 200b are collectively referred to as pellets 200. The flat shape of the pellet 200 is not limited to a triangle or a hexagon, and may be a combination of two or more and six or less triangles, for example. For example, it may be a quadrangle (diamond) in which two triangles (equilateral triangles) are combined.
The thickness of the pellet 200 is determined according to the type of film-forming gas and the like. The reason will be described later, but it is preferable that the thickness of the pellet 200 is uniform. Further, it is preferable that the sputtered particles are in the form of pellets having no thickness, rather than in the form of thick dice.
The pellet 200 may be negatively or positively charged on the sides by receiving an electric charge as it passes through the plasma. The pellet 200 has an oxygen atom on the side surface, and the oxygen atom may be negatively charged. For example, FIG. 41 shows an example in which the pellet 200a has a negatively charged oxygen atom on the side surface. As described above, when the side surfaces are charged with the same polarity, the charges repel each other and the flat plate shape can be maintained. When CAAC-OS is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom may be negatively charged. Alternatively, an oxygen atom bonded to an indium atom, a gallium atom or a zinc atom may be negatively charged.
As shown in FIG. 39 (A), for example, the pellet 200 flies in the plasma like a kite and flutters up to the substrate 220. Since the pellet 200 is charged, a repulsive force is generated when the region where the other pellet 200 is already deposited approaches. Here, on the upper surface of the substrate 220, a magnetic field in a direction parallel to the upper surface of the substrate 220 is generated. Further, since a potential difference is given between the substrate 220 and the target 230, a current flows from the substrate 220 toward the target 230. Therefore, the pellet 200 receives a force (Lorentz force) on the upper surface of the substrate 220 by the action of a magnetic field and an electric current (see FIG. 42). This can be understood by Fleming's left-hand rule. In order to increase the force applied to the pellet 200, the magnetic field in the direction parallel to the upper surface of the substrate 220 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more on the upper surface of the substrate 220. It is advisable to provide an area that serves as. Alternatively, on the upper surface of the substrate 220, the magnetic field in the direction parallel to the upper surface of the substrate 220 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, more preferably the magnetic field in the direction perpendicular to the upper surface of the substrate 220. It is advisable to provide an area that is 5 times or more.
Further, the substrate 220 is heated, and the resistance such as friction between the pellet 200 and the substrate 220 is small. As a result, as shown in FIG. 43 (A), the pellet 200 moves so as to glide over the upper surface of the substrate 220. The movement of the pellet 200 occurs with the flat plate surface facing the substrate 220. After that, as shown in FIG. 43 (B), when the side surfaces of the other pellets 200 that have already been deposited are reached, the side surfaces are bonded to each other. At this time, the oxygen atom on the side surface of the pellet 200 is eliminated. The desorbed oxygen atoms may fill the oxygen deficiency in CAAC-OS, resulting in CAAC-OS with a low defect level density.
Further, when the pellet 200 is heated on the substrate 220, the atoms are rearranged and the distortion of the structure caused by the collision of the ions 201 is alleviated. The strain-relieved pellet 200 becomes almost a single crystal. Since the pellets 200 become almost single crystals, even if the pellets 200 are heated after being bonded to each other, the pellets 200 themselves can hardly expand or contract. Therefore, the widening of the gap between the pellets 200 does not cause defects such as grain boundaries to form crevasses. In addition, elastic metal atoms and the like are spread in the gaps, and it is considered that the side surfaces of the misaligned pellets 200 are connected like a highway.
It is considered that pellets 200 are deposited on the substrate 220 by the above model. Therefore, unlike epitaxial growth, it can be seen that CAAC-OS can be formed even when the surface to be formed does not have a crystal structure. For example, even if the structure of the upper surface (surface to be formed) of the substrate 220 is an amorphous structure, it is possible to form a CAAC-OS film.
Further, in CAAC-OS, it can be seen that the pellets 200 are arranged along the shape not only on the flat surface but also on the upper surface of the substrate 220 which is the surface to be formed. For example, when the upper surface of the substrate 220 is flat at the atomic level, the pellet 200 is a layer having a uniform thickness, flatness, and high crystallinity because the flat plate surface, which is a plane parallel to the ab surface, is juxtaposed downward. Is formed. Then, CAAC-OS can be obtained by stacking the layers in n stages (n is a natural number) (see FIG. 39 (B)).
On the other hand, even when the upper surface of the substrate 220 has irregularities, CAAC-OS has a structure in which n layers (n is a natural number) in which pellets 200 are juxtaposed along the irregularities are stacked. Since the substrate 220 has irregularities, the CAAC-OS may be prone to gaps between the pellets 200. However, an intermolecular force acts between the pellets 200, and even if there are irregularities, the gaps between the pellets are arranged so as to be as small as possible. Therefore, it is possible to obtain CAAC-OS having high crystallinity even if it has irregularities (see FIG. 39 (C)).
Therefore, CAAC-OS does not require laser crystallization and can form a uniform film even on a glass substrate having a large area.
Since CAAC-OS is formed by such a model, it is preferable that the sputtered particles are in the form of pellets with no thickness. When the sputtered particles are in the shape of a thick dice, the surface facing the substrate 220 may not be constant, and the thickness and the orientation of the crystals may not be uniform.
With the film formation model shown above, CAAC-OS having high crystallinity can be obtained even on a surface to be formed having an amorphous structure.
CAAC-OS can also be explained by a film formation model having zinc oxide particles in addition to pellets 200.
Since the zinc oxide particles have a smaller mass than the pellet 200, they reach the substrate 220 first. On the upper surface of the substrate 220, the zinc oxide particles form a thin zinc oxide layer by preferentially growing crystals in the horizontal direction. The zinc oxide layer has c-axis orientation. The c-axis of the zinc oxide layer crystal is oriented in a direction parallel to the normal vector of the substrate 220. Since the zinc oxide layer serves as a seed layer for growing CAAC-OS, it has a function of increasing the crystallinity of CAAC-OS. The zinc oxide layer has a thickness of 0.1 nm or more and 5 nm or less, and most of them have a thickness of 1 nm or more and 3 nm or less. Since the zinc oxide layer is sufficiently thin, grain boundaries can hardly be confirmed.
Therefore, in order to form a highly crystalline CAAC-OS, it is preferable to use a target containing zinc in a proportion higher than that of the stoichiometric composition.
Similarly, nc-OS can be understood by the film formation model shown in FIG. The only difference between FIG. 40 and FIG. 39 (A) is the presence or absence of heating of the substrate 220.
Therefore, the substrate 220 is not heated, and the resistance such as friction between the pellet 200 and the substrate 220 is large. As a result, since the pellet 200 cannot move so as to glide on the upper surface of the substrate 220, nc-OS can be obtained by irregularly accumulating.
<Cleavage surface> The cleavage surface of the target described in the CAAC-OS film formation model will be described below.
First, the cleavage plane of the target will be described with reference to FIG. 44. Figure 44 shows InGaZnO<sub>4</sub>The crystal structure of is shown. In Fig. 44 (A), InGaZnO is shown in the direction parallel to the b-axis with the c-axis facing upward.<sub>4</sub>The structure when the crystal of is observed is shown. In Fig. 44 (B), InGaZnO is shown in the direction parallel to the c-axis.<sub>4</sub>The structure when the crystal of is observed is shown.
InGaZnO<sub>4</sub>The energy required for cleavage at each crystal plane of the crystal is calculated by first-principles calculation. For the calculation, a density functional theory (CASTEP) using a pseudopotential and a plane wave basis is used. An ultra-soft pseudopotential is used as the pseudopotential. GGA PBE is used for the functional. The cutoff energy is 400 eV.
The energy of the structure in the initial state is derived after performing structural optimization including cell size. Further, the energy of the structure after cleavage on each surface is derived after the structural optimization of the atomic arrangement is performed with the cell size fixed.
InGaZnO shown in Figure 44<sub>4</sub>Based on the crystal structure of, create a structure that is cleaved on any of the first, second, third, and fourth surfaces, and perform structural optimization calculations with a fixed cell size. .. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and is a crystal plane parallel to the (001) plane (or ab plane) (FIG. 44 (A). )reference.). The second plane is the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, which is parallel to the (001) plane (or ab plane) (Fig. 44 (A)). reference.). The third plane is a crystal plane parallel to the (110) plane (see FIG. 44 (B)). The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (see FIG. 44 (B)).
Under the above conditions, the energy of the structure after cleavage is calculated on each surface. Next, the cleavage energy, which is a measure of the ease of cleavage on each surface, is calculated by dividing the difference between the energy of the structure after cleavage and the energy of the structure in the initial state by the area of the cleavage surface. The energy of the structure is the energy considering the kinetic energy of the electrons and the interaction between the atoms, between the atoms and the electrons, and between the electrons with respect to the atoms and electrons contained in the structure.
As a result of the calculation, the cleavage energy of the first surface is 2.60 J / m.<sup>2</sup>, The cleavage energy of the second surface is 0.68J / m<sup>2</sup>, Cleavage energy of the third surface is 2.18J / m<sup>2</sup>, The cleavage energy of the 4th surface is 2.12J / m<sup>2</sup>It turned out to be (see the table below).
<tables num="1"><img file="JP6437331B2_D0001.tif" /></tables>
By this calculation, InGaZnO shown in FIG. 44<sub>4</sub>In the crystal structure of, the cleavage energy in the second plane is the lowest. That is, it can be seen that the surface between the Ga-Zn-O layer and the Ga-Zn-O layer is the most easily cleaved surface (cleavage surface). Therefore, in the present specification, when the term "cleavage surface" is used, it means the second surface which is the most easily cleaved surface.
InGaZnO shown in FIG. 44 (A) because it has a cleavage plane on the second surface between the Ga-Zn-O layer and the Ga-Zn-O layer.<sub>4</sub>Crystals can be separated on the plane equivalent to the two second planes. Therefore, when an ion or the like collides with the target, it is considered that the wafer-shaped unit (which we call a pellet) cleaved on the surface having the lowest cleavage energy pops out as the smallest unit. In that case, InGaZnO<sub>4</sub>Pellets consist of three layers: Ga-Zn-O layer, In-O layer and Ga-Zn-O layer.
Also, the third plane (the crystal plane between the Ga-Zn-O layer and the In-O layer, which is parallel to the (001) plane (or ab plane)) is more than the first plane (the crystal plane between the Ga-Zn-O layer and the In-O layer). Since the cleavage energy of the (110) plane (crystal plane parallel to the (110) plane) and the fourth plane (the crystal plane parallel to the (100) plane (or bc plane)) is low, the planar shape of the pellet is triangular or hexagonal. It is suggested that there are many.
Next, by classical molecular dynamics calculation, InGaZnO having a homologous structure as a target<sub>4</sub>The cleavage plane is evaluated when the target is sputtered with argon (Ar) or oxygen (O). InGaZnO used in the calculation<sub>4</sub>The cross-sectional structure of the crystal (2688 atoms) of is shown in FIG. 45 (A), and the upper surface structure is shown in FIG. 45 (B). The fixed layer shown in FIG. 45 (A) is a layer in which the arrangement of atoms is fixed so that the position does not change. The temperature control layer shown in FIG. 45 (A) is a layer having a constant temperature (300 K) at all times.
Materials Explorer 5.0 manufactured by Fujitsu Limited is used for classical molecular dynamics calculation. The initial temperature is 300K, the cell size is constant, the time step width is 0.01 femtoseconds, and the number of steps is 10 million times. In the calculation, under the conditions, 300 eV of energy is given to the atom, and InGaZnO<sub>4</sub>Atoms are incident on the cell from the direction perpendicular to the ab plane of the crystal.
FIG. 46 (A) shows InGaZnO shown in FIG. 45.<sub>4</sub>The atomic arrangement is shown 99.9 picoseconds (psec) after argon is incident on the cell having the crystal of. In addition, FIG. 46 (B) shows the atomic arrangement 99.9 picoseconds after oxygen is incident on the cell. In FIG. 46, a part of the fixed layer shown in FIG. 45 (A) is omitted.
From FIG. 46 (A), a crack is generated from the cleavage plane corresponding to the second plane shown in FIG. 44 (A) within 99.9 picoseconds after the argon is incident on the cell. Therefore, InGaZnO<sub>4</sub>It can be seen that when argon collides with the crystal of No. 1 and the uppermost surface is the second surface (0th), a large crack is generated in the second surface (2nd).
On the other hand, from FIG. 46 (B), it can be seen that cracks occur from the cleaved surface corresponding to the second surface shown in FIG. 44 (A) within 99.9 picoseconds after oxygen enters the cell. However, if oxygen collides, InGaZnO<sub>4</sub>It can be seen that a large crack occurs in the second surface (first) of the crystal of.
Therefore, InGaZnO having a homologous structure<sub>4</sub>When an atom (ion) collides from the upper surface of the target containing the crystal of InGaZnO<sub>4</sub>It can be seen that the crystals of No. 1 are cleaved along the second surface and the flat particles (pellets) are exfoliated. Further, at this time, it can be seen that the size of the pellet is smaller in the case of collision with oxygen than in the case of collision with argon.
The above calculation suggests that the exfoliated pellet contains a damaged area. Damaged areas contained in the pellet may be repaired by reacting the defects created by the damage with oxygen.
Therefore, it is investigated that the pellet size differs depending on the atom to be collided.
InGaZnO shown in FIG. 45 in FIG. 47 (A).<sub>4</sub>The locus of each atom from 0 picoseconds to 0.3 picoseconds after argon is incident on the cell having the crystal of. Therefore, FIG. 47 (A) corresponds to the period between FIGS. 45 and 46 (A).
From FIG. 47 (A), when gallium collides with gallium (Ga) in the first layer (Ga-Zn-O layer), the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer). After that, it can be seen that the zinc reaches the vicinity of the 6th layer (Ga-Zn-O layer). The argon that collides with gallium is blown out. Therefore, InGaZnO<sub>4</sub>When argon is made to collide with a target containing the crystal of No. 45 (A), it is considered that the second surface (second) in FIG. 45 (A) is cracked.
In addition, FIG. 47 (B) shows InGaZnO shown in FIG. 45.<sub>4</sub>The locus of each atom from 0 picoseconds to 0.3 picoseconds after oxygen is incident on the cell having the crystal of. Therefore, FIG. 47 (B) corresponds to the period between FIGS. 45 and 46 (A).
On the other hand, from FIG. 47 (B), when oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer), the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer). It can be seen that the zinc does not reach the 5th layer (In-O layer) after colliding with. The oxygen that collides with gallium is blown out. Therefore, InGaZnO<sub>4</sub>When oxygen is made to collide with a target containing the crystals of, it is considered that the second surface (first) in FIG. 45 (A) is cracked.
From this calculation, InGaZnO<sub>4</sub>It is suggested that the crystals of A will be exfoliated from the cleavage plane when atoms (ions) collide.
In addition, the difference in crack depth will be examined from the viewpoint of conservation law. The law of conservation of energy and the law of conservation of momentum can be expressed as Eqs. (1) and (2). Here, E is the energy of argon or oxygen before collision (300 eV), m<sub>A</sub>Is the mass of argon or oxygen, v<sub>A</sub>Is the velocity of argon or oxygen before the collision, v'<sub>A</sub>Is the velocity of argon or oxygen after collision, m<sub>Ga</sub>Is the mass of gallium, v<sub>Ga</sub>Is the velocity of gallium before collision, v'<sub>Ga</sub>Is the velocity of gallium after collision.
<maths num="1"><img file="JP6437331B2_D0002.tif" /></maths>
<maths num="2"><img file="JP6437331B2_D0003.tif" /></maths>
Assuming that the collision of argon or oxygen is an elastic collision, v<sub>A</sub>, V'<sub>A</sub>, V<sub>Ga</sub>And v'<sub>Ga</sub>The relationship of can be expressed as in Eq. (3).
<maths num="3"><img file="JP6437331B2_D0004.tif" /></maths>
From equations (1), (2) and (3), v<sub>Ga</sub>When is 0, the velocity of gallium after the collision of argon or oxygen v'<sub>Ga</sub>Can be expressed as in Eq. (4).
<maths num="4"><img file="JP6437331B2_D0005.tif" /></maths>
In equation (4), m<sub>A</sub>Substitute the mass of argon or the mass of oxygen into, and compare the velocities of gallium after each atom collides. It can be seen that when the energies of argon and oxygen before the collision are the same, the velocity of gallium is 1.24 times higher in the case of the collision of argon than in the case of the collision of oxygen. Therefore, the energy of gallium is higher in the case of collision with argon than in the case of collision with oxygen by the square of the velocity.
It can be seen that the velocity (energy) of gallium after collision is higher in the case of collision with argon than in the case of collision with oxygen. Therefore, it is considered that the crack was generated at a deeper position in the case of collision with argon than in the case of collision with oxygen.
From the above calculation, InGaZnO having a homologous structure<sub>4</sub>It can be seen that when the target containing the crystals of is sputtered, it is peeled off from the cleavage plane and pellets are formed. On the other hand, even if a region of another structure of the target having no cleavage plane is sputtered, pellets are not formed, and sputtered particles having an atomic level finer than the pellets are formed. Since the sputtered particles are smaller than the pellets, it is considered that they are exhausted via a vacuum pump connected to the sputtering apparatus. Therefore, InGaZnO having a homologous structure<sub>4</sub>When a target containing the above crystals is sputtered, it is difficult to think of a model in which particles of various sizes and shapes fly to the substrate and are deposited to form a film. The model shown in Fig. 39 (A), in which sputtered pellets are deposited to form a CAAC-OS film, makes sense.
The density of the CAAC-OS formed in this way has the same density as that of the single crystal OS. For example, InGaZnO<sub>4</sub>The density of single crystal OS with homologous structure is 6.36 g / cm.<sup>3</sup>On the other hand, the density of CAAC-OS, which has the same atomic number ratio, is 6.3 g / cm.<sup>3</sup>It will be about.
Fig. 48 shows the atomic arrangement in the cross section of the CAAC-OS In-Ga-Zn oxide (see Fig. 48 (A)) and its target (see Fig. 48 (B)) formed by the sputtering method. Shown. High-Angle Annular Dark Field Scanning Transmission Electron Microscopy (HAADF-STEM) is used to observe the atomic arrangement. In HAADF-STEM, the image intensity of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31), which have similar atomic numbers, are almost indistinguishable. Hitachi scanning transmission electron microscope HD-2700 is used for HAADF-STEM.
Comparing FIGS. 48 (A) and 48 (B), it can be seen that both CAAC-OS and the target have a homologous structure, and their atomic arrangements correspond to each other. Therefore, as shown in the film formation model shown in FIG. 39 (A), it can be seen that CAAC-OS is formed by transferring the crystal structure of the target.
<Band Diagram> The band diagram of the above-mentioned transistor in an arbitrary cross section will be described below.
FIG. 18A is a cross-sectional view of the transistor 150 according to one aspect of the present invention.
The transistor 150 shown in FIG. 18 (A) refers to the description of FIG.
Here, FIG. 18 (B) shows a band diagram in the A-A'cross section including the channel formation region of the transistor 150 shown in FIG. 18 (A). It is assumed that the semiconductor 106a has a slightly smaller energy gap than the semiconductor 106b. Further, it is assumed that the insulator 102a, the insulator 102b, and the insulator 112 have a sufficiently larger energy gap than the semiconductor 106a and the semiconductor 106b. Further, the Fermi level (denoted by Ef) of the semiconductor 106a, the semiconductor 106b, the insulator 102a, the insulator 102b and the insulator 112 is the position of each intrinsic Fermi level (denoted by Ei). Further, the work function of the conductor 104a and the conductor 114 is the same as the energy difference between the vacuum level and the Fermi level.
When the gate voltage is equal to or higher than the threshold voltage of the transistor 150, electrons preferentially flow through the semiconductor 106a due to the difference in energy at the lower end of the conduction band between the semiconductor 106a and the semiconductor 106b. That is, it can be estimated that electrons are embedded in the semiconductor 106a. The energy at the lower end of the conduction band is referred to as Ec, and the energy at the upper end of the valence band is referred to as Ev.
Therefore, in the transistor 150 according to one aspect of the present invention, the influence of interfacial scattering is reduced by embedding electrons. Therefore, the transistor 150 according to one aspect of the present invention has a small channel resistance.
Next, FIG. 18 (C) shows a band diagram in a B-B'cross section including the source region or drain region of the transistor 150 shown in FIG. 18 (A). The area 107a1, the area 107b1, the area 107a2 and the area 107b2 are in a degenerate state. Further, in the region 107b1, the Fermi level of the semiconductor 106a is set to be about the same as the energy at the lower end of the conduction band. Further, in the region 107b2, the Fermi level of the semiconductor 106b is set to be about the same as the energy at the lower end of the conduction band. The same applies to region 107a1 and region 107a2.
At this time, the conductor 116b, which functions as a source electrode or a drain electrode, and the region 107b2 are in ohmic contact because the energy barrier is sufficiently small. Further, the region 107b2 and the region 107b1 are in ohmic contact. Similarly, the conductor 116a, which functions as a source electrode or a drain electrode, and the region 107a2 are in ohmic contact because the energy barrier is sufficiently small. Further, the area 107a2 and the area 107a1 are in ohmic contact. Therefore, it can be seen that electrons are smoothly transferred between the conductors 116a and 116b and the semiconductors 106a and 106b.
As shown above, the transistor according to one aspect of the present invention is a transistor in which electrons are smoothly transferred between the source electrode and the drain electrode and the channel forming region, and the channel resistance is small. That is, it can be seen that the transistor has excellent switching characteristics.
Next, the semiconductor 106a and the semiconductor 106b, which are band diagrams, as shown in FIG. 18B, will be described.
For example, the semiconductor 106a is an oxide semiconductor composed of one or more or two or more elements other than oxygen constituting the semiconductor 106b. Since the semiconductor 106a is composed of one or more or two or more elements other than oxygen constituting the semiconductor 106b, it is difficult to form an interface level at the interface between the semiconductor 106a and the semiconductor 106b.
The semiconductor 106a and the semiconductor 106b preferably contain at least indium. When the semiconductor 106a is an In-M-Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50atomic%, M is higher than 50atomic%, and In is more preferably less than 25atomic%. , M is higher than 75 atomic%. Further, when the semiconductor 106b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably higher than 25atomic%, M is less than 75atomic%, and In is more preferably 34atomic%. High, with M less than 66 atomic%.
The semiconductor 106b uses an oxide having a higher electron affinity than the semiconductor 106a. For example, as the semiconductor 106b, an oxide having an electron affinity higher than that of the semiconductor 106a by 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less is used. The electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.
As shown in FIG. 14, when the semiconductor 106 has the semiconductor 106a, the semiconductor 106b, and the semiconductor 106c, it is possible to embed electrons in the same manner. In that case, the semiconductor 106c refers to the description of the semiconductor 106a.
The structure of the transistor shown above is an example, and a combination of these is also included in the category of one aspect of the present invention.
<Application Examples of Semiconductor Devices> Hereinafter, application examples of semiconductor devices according to one aspect of the present invention will be shown.
<Display Device> Hereinafter, a configuration example of the display device according to one aspect of the present invention will be described.
[Configuration example]
FIG. 19A shows a top view of the display device according to one aspect of the present invention. Further, FIG. 19B shows a pixel circuit when a liquid crystal element is used as a pixel of the display device according to one aspect of the present invention. Further, FIG. 19C shows a pixel circuit when an organic EL element is used as a pixel of the display device according to one aspect of the present invention.
As the transistor used for the pixel, the above-mentioned transistor can be used. Here, an example using an n-channel type transistor is shown. A transistor used for the pixel and a transistor manufactured through the same process may be used as the drive circuit. Further, as the capacitance element used for the pixel, the above-mentioned capacitance element can be used. By using the above-mentioned transistors and capacitive elements for the pixels and the drive circuit in this way, a display device having high display quality and / and high reliability can be obtained.
It should be noted that the performance of the display device may be improved by differentiating the structures of the transistor used for the pixel and the transistor used for the drive circuit. For example, a transistor having an s-channel structure may be used for the pixel, and a transistor having no s-channel structure may be used for the drive circuit. A transistor having an s-channel structure has a higher on-current and a lower off-current than a transistor having no s-channel structure, and is therefore preferable as a transistor used for pixels requiring a high on-current and / and a low off-current. In some cases. Further, a transistor having an s-channel structure may be able to reduce the occupied area when it is desired to obtain an on-current equivalent to that of a transistor having no s-channel structure. Therefore, it may be possible to increase the aperture ratio of the pixels. Specifically, the aperture ratio of the pixels may be 40% or more, preferably 50% or more, and more preferably 60% or more. Further, since the transistor having an s-channel structure has a high light-shielding property, it may be possible to suppress deterioration caused by light of the transistor used for the pixel. On the other hand, in the drive circuit, it may be preferable to use a transistor having no s-channel structure because the parasitic capacitance can be further reduced. Further, in the drive circuit, the degree of freedom in design may be higher if a transistor having no s-channel structure is used.
Further, for example, a transistor having an s-channel structure may be used for the drive circuit, and a transistor having no s-channel structure may be used for the pixels. Since a transistor having an s-channel structure has a high on-current and a low off-current, it may be preferable as a transistor used in a drive circuit in which a high on-current and / and a low off-current are required. Further, a transistor having an s-channel structure may be able to reduce the occupied area when it is desired to obtain an on-current equivalent to that of a transistor having no s-channel structure. Therefore, it may be possible to reduce the area of the drive circuit and reduce the frame of the display device. Specifically, the width of the frame may be 3 mm or less, preferably 1 mm or less, and more preferably 0.8 mm or less, respectively. On the other hand, in the pixel, a transistor having no s-channel structure may be preferable because the parasitic capacitance can be further reduced. In particular, in a light emitting device, when a pixel has a threshold value correction function, the effect may be enhanced by reducing the parasitic capacitance.
Further, for example, a transistor having an s-channel structure may be used for a part of the pixel, and a transistor having no s-channel structure may be used for another part of the pixel. Since a transistor having an s-channel structure has a high on-current and a low off-current, it may be preferable as a transistor used for a part of a pixel in which a high on-current and / and a low off-current are required. Further, a transistor having an s-channel structure may be able to reduce the occupied area when it is desired to obtain an on-current equivalent to that of a transistor having no s-channel structure. Therefore, it may be possible to increase the aperture ratio of the pixels. Specifically, the aperture ratio of the pixels may be 40% or more, preferably 50% or more, and more preferably 60% or more. Further, since the transistor having an s-channel structure has a high light-shielding property, it may be possible to suppress deterioration caused by light of the transistor used for the pixel. On the other hand, in another part of the pixel, a transistor having no s-channel structure may be preferable because the parasitic capacitance can be further reduced. In particular, in a light emitting device, when a pixel has a threshold value correction function, the effect may be enhanced by reducing the parasitic capacitance.
Further, for example, a transistor having an s-channel structure may be used as a part of the drive circuit, and a transistor having no s-channel structure may be used as another part of the drive circuit. Since a transistor having an s-channel structure has a high on-current and a low off-current, it may be preferable as a transistor used as a part of a drive circuit in which a high on-current and / and a low off-current are required. Further, a transistor having an s-channel structure may be able to reduce the occupied area when it is desired to obtain an on-current equivalent to that of a transistor having no s-channel structure. Therefore, it may be possible to reduce the area of the drive circuit and reduce the frame of the display device. Specifically, the width of the frame may be 3 mm or less, preferably 1 mm or less, and more preferably 0.8 mm or less, respectively. On the other hand, in another part of the drive circuit, a transistor having no s-channel structure may be preferable because it can reduce the parasitic capacitance.
An example of a top view of the active matrix type display device is shown in FIG. 19 (A). A pixel unit 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, and a signal line driving circuit 5004 are arranged on the substrate 5000 of the display device. The pixel unit 5001 is electrically connected to the signal line drive circuit 5004 by a plurality of signal lines, and is electrically connected to the first scan line drive circuit 5002 and the second scan line drive circuit 5003 by a plurality of scan lines. Will be done. Pixels having display elements are arranged in the regions separated by the scanning lines and the signal lines. Further, the substrate 5000 of the display device is electrically connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).
The first scan line drive circuit 5002, the second scan line drive circuit 5003, and the signal line drive circuit 5004 are formed on the same substrate 5000 as the pixel unit 5001. Therefore, the cost of manufacturing the display device can be reduced as compared with the case where the drive circuit is manufactured separately. Further, when the drive circuit is manufactured separately, the number of connections between the wirings increases. Therefore, by providing the drive circuit on the same substrate 5000, the number of connections between the wirings can be reduced, and the reliability and / and the yield can be improved.
<Liquid crystal display device> An example of the pixel circuit configuration is shown in FIG. 19 (B). Here, a pixel circuit that can be applied to pixels of a VA type liquid crystal display device is shown.
This pixel circuit can be applied to a configuration having a plurality of pixel electrodes in one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, the signal applied to each pixel electrode of the multi-domain designed pixel can be independently controlled.
The gate wiring 5012 of the transistor 5016 and the gate wiring 5013 of the transistor 5017 are separated so that different gate signals can be given. On the other hand, the source electrode or drain electrode 5014 that functions as a data line is commonly used in the transistor 5016 and the transistor 5017. As the transistor 5016 and the transistor 5017, the above-mentioned transistor 150 and the like can be appropriately used. Further, as the capacitance element 5023A and the capacitance element 5023B, the above-mentioned capacitance element 160 can be appropriately used. Thereby, it is possible to provide a liquid crystal display device having high display quality and / and high reliability.
The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012, and the gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. Given different gate signals to the gate line 5012 and the gate wiring 5013 operating pair of transistors 5016 and the transistors 5017 with different timing, it is possible to control the orientation of the liquid crystal.
Further, the capacitive wiring 5010, the gate insulator functioning as a dielectric, and the capacitive electrode electrically connected to the first pixel electrode or the second pixel electrode may form a capacitive element.
The multi-domain structure includes a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer in between, and the second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer in between. ..
The display device according to one aspect of the present invention is not limited to the pixel circuit shown in FIG. 19 (B). For example, a switch, a resistance element, a capacitive element, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel circuit shown in FIG. 19 (B).
<Light emitting device> Another example of the pixel circuit configuration is shown in FIG. 19 (C). Here, the pixel structure of a display device (also referred to as a light emitting device) using a light emitting element typified by an organic EL element is shown.
In the organic EL element, by applying a voltage to the light emitting element, electrons are injected from one of the pair of electrodes of the organic EL element into a layer containing a luminescent organic compound, and holes are injected from the other into a layer containing a luminescent organic compound, and a current flows. .. Then, when the electrons and holes are recombined, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.
FIG. 19C is a diagram showing an example of a pixel circuit. Here, an example is shown in which two n-channel transistors are used in one pixel and one capacitive element is used. As the n-channel type transistor, the above-mentioned transistor 150 or the like can be used. Further, as the capacitive element, the above-mentioned capacitive element 160 or the like can be used. Further, the pixel circuit can be driven by digital time gradation.
The configuration of the applicable pixel circuit and the operation of the pixel when the digital time gradation drive is applied will be described.
Pixel 5020 includes a switching transistor 5021, a driving transistor 5022, a light emitting element 5024, and a capacitive element 5023. In the switching transistor 5021, the gate electrode is connected to the scanning line 5026, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 5025, and the second electrode (the other of the source electrode and the drain electrode) is driven. It is connected to the gate electrode of the transistor 5022. In the drive transistor 5022, the gate electrode is connected to the power supply line 5027 via the capacitive element 5023, the first electrode is connected to the power supply line 5027, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 5024. Has been done. The second electrode of the light emitting element 5024 corresponds to the common electrode 5028. The common electrode 5028 is electrically connected to a common potential line formed on the same substrate.
As the switching transistor 5021 and the driving transistor 5022, the above-mentioned transistor 150 and the like can be used. Further, as the capacitance element 5023, the above-mentioned capacitance element 160 or the like can be used. This makes an organic EL display device with high display quality and / and high reliability.
The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027, and for example, GND, 0V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the forward threshold voltage of the light emitting element 5024, and the potential difference is applied to the light emitting element 5024 to cause a current to flow through the light emitting element 5024 to emit light. The forward voltage of the light emitting element 5024 refers to a voltage at which a desired brightness is obtained, and includes at least a forward threshold voltage.
The capacitive element 5023 may be omitted by substituting the gate capacitance of the driving transistor 5022. Regarding the gate capacitance of the drive transistor 5022, a capacitance may be formed between the channel forming region and the gate electrode.
Next, the signal input to the drive transistor 5022 will be described. Voltage input In the case of the voltage drive system, a video signal is input to the drive transistor 5022 so that the drive transistor 5022 is in two states of on and off. In order to operate the drive transistor 5022 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the gate electrode of the drive transistor 5022. Further, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 5022 to the power supply line voltage is applied to the signal line 5025.
When analog gradation driving is performed, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 5022 to the forward voltage of the light emitting element 5024 is applied to the gate electrode of the driving transistor 5022. A video signal is input so that the drive transistor 5022 operates in the saturation region, and a current is passed through the light emitting element 5024. Further, in order to operate the drive transistor 5022 in the saturation region, the potential of the power supply line 5027 is set higher than the gate potential of the drive transistor 5022. By making the video signal analog, a current corresponding to the video signal can be passed through the light emitting element 5024 to perform analog gradation drive.
The display device according to one aspect of the present invention is not limited to the pixel configuration shown in FIG. 19 (C). For example, a switch, a resistance element, a capacitive element, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit shown in FIG. 19 (C).
<Modification example 1 of light emitting device> For example, FIG. 20A is a diagram showing an example of a pixel circuit. Here, an example is shown in which three n-channel transistors are used in one pixel and one capacitive element is used.
FIG. 20A shows an example of a circuit diagram of pixel 5111. The pixel 5111 includes a transistor 5155, a transistor 5156, a transistor 5157, a capacitive element 5158, and a light emitting element 5154.
The potential of the pixel electrode of the light emitting element 5154 is controlled according to the image signal Sig input to the pixel 5111. Further, the brightness of the light emitting element 5154 is determined by the potential difference between the pixel electrode and the common electrode.
The transistor 5156 has a function of controlling the conduction state between the wiring SL and the gate of the transistor 5155. In the transistor 5155, one of the source and the drain is electrically connected to the anode of the light emitting element 5154, and the other of the source and the drain is electrically connected to the wiring VL. The transistor 5157 has a function of controlling the conduction state between the wiring ML and one of the source and drain of the transistor 5155. Of the pair of electrodes of the capacitive element 5158, one is electrically connected to the gate of the transistor 5155 and the other is electrically connected to the anode of the light emitting element 5154.
Further, the switching of the transistor 5156 is performed according to the potential of the wiring GL electrically connected to the gate of the transistor 5156. Switching of the transistor 5157 is performed according to the potential of the wiring GL electrically connected to the gate of the transistor 5157.
The above-mentioned transistor 150 or the like can be used for at least one of the transistor 5155, the transistor 5156, and the transistor 5157. Further, as the capacitance element 5158, the above-mentioned capacitance element 160 or the like can be used.
Note that, for example, the source of the transistor (or the first terminal, etc.) is electrically connected to X via (or not) Z1, and the drain of the transistor (or the second terminal, etc.) connects to Z2. Through (or not) being electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to one part of Z1 and another part of Z1. Is directly connected to X, the drain of the transistor (or the second terminal, etc.) is directly connected to one part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.
For example, "X and Y, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) are electrically connected to each other, and the X, the source of the transistor (or the first terminal, etc.) It is electrically connected in the order of (terminal, etc.), transistor drain (or second terminal, etc.), and Y. " Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (such as the second terminal). Or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. " Alternatively, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. The terminals, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. " By defining the order of connections in the circuit configuration using a representation similar to these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. Note that these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1 and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
Next, an operation example of the pixel 5111 shown in FIG. 20 (A) will be described.
FIG. 20 (B) illustrates a timing chart of the potential of the wiring GL electrically connected to the pixel 5111 shown in FIG. 20 (A) and the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 20 (B) illustrates a case where all the transistors included in the pixel 5111 shown in FIG. 20 (A) are of the n-channel type.
First, during period t1, a high level potential is applied to the wiring GL. Therefore, the transistor 5156 and the transistor 5157 are turned on. Then, the potential Vdata of the image signal Sig is given to the wiring SL, and the potential Vdata is given to the gate of the transistor 5155 via the transistor 5156.
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. The potential Vano is preferably higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 and the threshold voltage Vth of the transistor 5155 to the potential Vcat. By providing the above potential difference between the wiring VL and the wiring CL, the value of the drain current of the transistor 5155 is determined according to the potential Vdata. Then, the brightness of the light emitting element 5154 is determined by supplying the drain current to the light emitting element 5154.
Further, when the transistor 5155 is an n-channel type, in the period t1, the potential of the wiring ML is lower than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 to the potential of the wiring CL, and the potential of the wiring VL becomes It is preferably higher than the potential obtained by adding the threshold voltage Vth of the transistor 5155 to the potential of the wiring ML. With the above configuration, even if the transistor 5157 is on, the drain current of the transistor 5155 can be preferentially flowed to the wiring ML instead of the light emitting element 5154.
Next, in period t2, a low level potential is applied to the wiring GL. Therefore, the transistor 5156 and the transistor 5157 are turned off. When the transistor 5156 is turned off, the potential Vdata is held at the gate of the transistor 5155. Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. Therefore, the light emitting element 5154 emits light according to the brightness determined in the period t1.
Next, in period t3, a high level potential is applied to the wiring GL. Therefore, the transistor 5156 and the transistor 5157 are turned on. Further, the wiring SL is given a potential such that the gate voltage of the transistor 5155 becomes larger than the threshold voltage Vth. Further, the electric potential Vcat is given to the wiring CL. Then, the potential of the wiring ML becomes lower than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 to the potential of the wiring CL, and the potential of the wiring VL is the potential of the wiring ML plus the threshold voltage Vth of the transistor 5155. Is higher than the sum of the potentials. With the above configuration, the drain current of the transistor 5155 can be preferentially flowed to the wiring ML instead of the light emitting element 5154.
Then, the drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal including the value of the drain current as information. Then, in the light emitting device according to one aspect of the present invention, the value of the potential Vdata of the image signal Sig supplied to the pixel 5111 can be corrected by using the above signal.
In the light emitting device having the pixel 5111 shown in FIG. 20A, it is not necessary to perform the operation of the period t3 after the operation of the period t2. For example, in pixel 5111, the operation of the period t1 to the period t2 may be repeated a plurality of times, and then the operation of the period t3 may be performed. Further, after performing the operation for the period t3 on the pixel 5111 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 5111 in the line in which the operation is performed, so that the light emitting element 5154 is non-existent. After the light emitting state, the operation of the period t3 may be performed in the pixel 5111 in the next row.
<Modification 2 of the light emitting device> Further, for example, FIG. 21A is a diagram showing an example of a pixel circuit. Here, an example is shown in which four n-channel transistors are used in one pixel and one capacitive element is used.
FIG. 21 (A) shows an example of a circuit diagram of pixel 5211. Pixel 5211 includes a transistor 5215, a transistor 5216, a transistor 5217, a capacitive element 5218, a light emitting element 5214, and a transistor 5219.
The potential of the pixel electrode of the light emitting element 5214 is controlled according to the image signal Sig input to the pixel 5211. Further, the brightness of the light emitting element 5214 is determined by the potential difference between the pixel electrode and the common electrode.
The transistor 5219 has a function of controlling the conduction state between the wiring SL and the gate of the transistor 5215. One of the source and the drain of the transistor 5215 is connected to the anode of the light emitting element 5214. The transistor 5216 has a function of controlling the conduction state between the wiring VL and the other of the source and drain of the transistor 5215. Transistor 5217 has a function of controlling the conduction state between the wiring ML and the other of the source and drain of the transistor 5215. Of the pair of electrodes of the capacitive element 5218, one is connected to the gate of the transistor 5215 and the other is connected to the anode of the light emitting element 5214.
Further, the switching of the transistor 5219 is performed according to the potential of the wiring GLa connected to the gate of the transistor 5219. Switching of the transistor 5216 is performed according to the potential of the wiring GLb connected to the gate of the transistor 5216. Switching of the transistor 5217 is performed according to the potential of the wiring GLc connected to the gate of the transistor 5217.
The above-mentioned transistor 150 or the like can be used for at least one of the transistor 5215, the transistor 5216, the transistor 5217, and the transistor 5219. Further, as the capacitance element 5218, the above-mentioned capacitance element 160 or the like can be used.
Next, an operation example of the external correction of the pixel 5211 shown in FIG. 21 (A) will be described.
FIG. 21 (B) illustrates a timing chart of the potentials of the wiring GLa, the wiring GLb, and the wiring GLc connected to the pixel 5211 shown in FIG. 21 (A) and the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 21 (B) illustrates a case where all the transistors included in the pixel 5211 shown in FIG. 21 (A) are of the n-channel type.
First, in period t1, the wiring GLa is given a high-level potential, the wiring GLb is given a high-level potential, and the wiring GLc is given a low-level potential. Therefore, the transistor 5219 and the transistor 5216 are turned on, and the transistor 5217 is turned off. Then, the potential Vdata of the image signal Sig is given to the wiring SL, and the potential Vdata is given to the gate of the transistor 5215 via the transistor 5219.
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. The potential Vano is preferably higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5214 to the potential Vcat. The potential Vano of the wiring VL is given to the other of the source and drain of the transistor 5215 via the transistor 5216. Therefore, the value of the drain current of the transistor 5215 is determined according to the potential Vdata. Then, the brightness of the light emitting element 5214 is determined by supplying the drain current to the light emitting element 5214.
Next, in period t2, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, and the wiring GLc is given a low-level potential. Therefore, the transistor 5216 is turned on, and the transistor 5219 and the transistor 5217 are turned off. When the transistor 5219 is turned off, the potential Vdata is held at the gate of the transistor 5215. Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. Therefore, the light emitting element 5214 maintains the brightness defined in the period t1.
Next, in period t3, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, and the wiring GLc is given a high-level potential. Therefore, the transistor 5217 is turned on, and the transistor 5219 and the transistor 5216 are turned off. Further, the electric potential Vcat is given to the wiring CL. Then, the potential Vano is given to the wiring ML, and it is connected to the monitor circuit.
By the above operation, the drain current of the transistor 5215 is supplied to the wiring ML via the transistor 5217. Moreover, the drain current is also supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal including the value of the drain current as information. Then, in the light emitting device according to one aspect of the present invention, the value of the potential Vdata of the image signal Sig supplied to the pixel 5211 can be corrected by using the above signal.
In the light emitting device having the pixel 5211 shown in FIG. 21 (A), it is not necessary to perform the operation of the period t3 after the operation of the period t2. For example, in the light emitting device, the operation of the period t1 to the period t2 may be repeated a plurality of times, and then the operation of the period t3 may be performed. Further, after performing the operation for the period t3 on the pixel 5211 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 5211 in the line in which the operation is performed, so that the light emitting element 5214 is non-existent. After the light emitting state, the operation of the period t3 may be performed in the pixel 5211 in the next row.
<Modification 3 of the light emitting device> Further, for example, FIG. 22A is a diagram showing an example of a pixel circuit. Here, an example is shown in which five n-channel transistors are used in one pixel and one capacitive element is used.
FIG. 22 (A) shows an example of a circuit diagram of pixel 5311. The pixel 5311 shown in FIG. 22A includes a transistor 5315, a transistor 5316, a transistor 5317, a capacitive element 5318, a light emitting element 5314, a transistor 5319, and a transistor 5320.
The transistor 5320 has a function of controlling the conduction state between the wiring RL and the anode of the light emitting element 5314. The transistor 5319 has a function of controlling the conduction state between the wiring SL and the gate of the transistor 5315. One of the source and the drain of the transistor 5315 is connected to the anode of the light emitting element 5314. The transistor 5316 has a function of controlling the conduction state between the wiring VL and the other of the source and drain of the transistor 5315. Transistor 5317 has a function of controlling the conduction state between the wiring ML and the other of the source and drain of the transistor 5315. Of the pair of electrodes of the capacitive element 5318, one is connected to the gate of the transistor 5315 and the other is connected to the anode of the light emitting element 5314.
Further, the switching of the transistor 5319 is performed according to the potential of the wiring GLa connected to the gate of the transistor 5319. Switching of transistor 5316 is performed according to the potential of the wiring GLb connected to the gate of transistor 5316. Switching of transistor 5317 is performed according to the potential of the wiring GLc connected to the gate of transistor 5317. Switching of transistor 5320 is performed according to the potential of the wiring GLd connected to the gate of transistor 5320.
The above-mentioned transistor 150 or the like can be used for at least one of the transistor 5315, the transistor 5316, the transistor 5317, the transistor 5319, and the transistor 5320. Further, as the capacitance element 5318, the above-mentioned capacitance element 160 or the like can be used.
Next, an operation example of the external correction of the pixel 5311 shown in FIG. 22 (A) will be described.
FIG. 22 (B) shows a timing chart of the potentials of the wiring GLa, wiring GLb, wiring GLc, and wiring GLd connected to the pixel 5311 shown in FIG. 22 (A) and the potential of the image signal Sig supplied to the wiring SL. Illustrate. The timing chart shown in FIG. 22 (B) illustrates a case where all the transistors included in the pixel 5311 shown in FIG. 22 (A) are of the n-channel type.
First, in period t1, the wiring GLa is given a high level potential, the wiring GLb is given a high level potential, the wiring GLc is given a low level potential, and the wiring GLd is given a high level potential. Therefore, the transistor 5319, the transistor 5316, and the transistor 5320 are turned on, and the transistor 5317 is turned off. Further, the potential Vdata of the image signal Sig is given to the wiring SL, and the potential Vdata is given to the gate of the transistor 5315 via the transistor 5319. Therefore, the value of the drain current of the transistor 5315 is determined according to the potential Vdata. Then, since the potential Vano is given to the wiring VL and the potential V1 is given to the wiring RL, the drain current flows between the wiring VL and the wiring RL via the transistor 5316 and the transistor 5320.
The potential Vano is preferably higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5314 to the potential Vcat. The potential Vano of the wiring VL is given to the other of the source and drain of the transistor 5315 via the transistor 5316. Further, the potential V1 given to the wiring RL is given to one of the source and the drain of the transistor 5315 via the transistor 5320. The potential Vcat is given to the wiring CL.
The potential V1 is preferably sufficiently lower than the potential V0 minus the threshold voltage Vth of the transistor 5315. In the period t1, the potential V1 can be made sufficiently lower than the potential obtained by subtracting the threshold voltage Vthe of the light emitting element 5314 from the potential Vcat, so that the light emitting element 5314 does not emit light.
Next, in period t2, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a low-level potential. .. Therefore, the transistor 5316 is turned on, and the transistor 5319, the transistor 5317, and the transistor 5320 are turned off. When the transistor 5319 is turned off, the potential Vdata is held at the gate of the transistor 5315.
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. Therefore, the drain current of the transistor 5315 whose value is determined in the period t1 is supplied to the light emitting element 5314 when the transistor 5320 is turned off. Then, by supplying the drain current to the light emitting element 5314, the brightness of the light emitting element 5314 is determined, and the brightness is maintained in the period t2.
Next, in period t3, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, the wiring GLc is given a high-level potential, and the wiring GLd is given a low-level potential. .. Therefore, the transistor 5317 is turned on, and the transistor 5319, the transistor 5316, and the transistor 5320 are turned off. Further, the electric potential Vcat is given to the wiring CL. Then, the potential Vano is given to the wiring ML, and it is connected to the monitor circuit.
By the above operation, the drain current of the transistor 5315 is supplied to the wiring ML via the transistor 5317. Moreover, the drain current is also supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal including the value of the drain current as information. Then, in the light emitting device according to one aspect of the present invention, the value of the potential Vdata of the image signal Sig supplied to the pixel 5311 can be corrected by using the above signal.
In the light emitting device having the pixel 5311 shown in FIG. 22 (A), it is not necessary to perform the operation of the period t3 after the operation of the period t2. For example, in the light emitting device, the operation of the period t1 to the period t2 may be repeated a plurality of times, and then the operation of the period t3 may be performed. Further, after performing the operation for the period t3 on the pixel 5311 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 5311 in the line in which the operation is performed, so that the light emitting element 5314 is not generated. After the light emitting state, the operation of the period t3 may be performed in the pixel 5311 in the next row.
Further, in the pixel 5311 shown in FIG. 22 (A), even if the resistance value between the anode and the cathode of the light emitting element 5314 varies among the pixels due to deterioration of the light emitting element 5314, when the potential Vdata is given to the gate of the transistor 5315. In addition, the potential of the source of the transistor 5315 can be set to a predetermined potential V1. Therefore, it is possible to prevent variations in the brightness of the light emitting element 5314 between the pixels.
<Modification example 4 of light emitting device> Further, for example, FIG. 23 (A) is a diagram showing an example of a pixel circuit. Here, an example is shown in which six n-channel transistors are used in one pixel and one capacitive element is used.
FIG. 23 (A) shows an example of a circuit diagram of pixel 5411. The pixel 5411 includes a transistor 5415, a transistor 5416, a transistor 5417, a capacitive element 5418, a light emitting element 5414, a transistor 5440, a transistor 5441, and a transistor 5442.
The potential of the pixel electrode of the light emitting element 5414 is controlled according to the image signal Sig input to the pixel 5411. Further, the brightness of the light emitting element 5414 is determined by the potential difference between the pixel electrode and the common electrode.
The transistor 5440 has a function of controlling the conduction state between the wiring SL and one of the pair of electrodes of the capacitive element 5418. The other of the pair of electrodes of the capacitive element 5418 is connected to one of the source and drain of transistor 5415. The transistor 5416 has a function of controlling the conduction state between the wiring VL1 and the gate of the transistor 5415. The transistor 5441 has a function of controlling the conduction state between one of the pair of electrodes of the capacitive element 5418 and the gate of the transistor 5415. The transistor 5442 has a function of controlling the conduction state between one of the source and drain of the transistor 5415 and the anode of the light emitting element 5414. Transistor 5417 has a function of controlling the conduction state between one of the source and drain of transistor 5415 and the wiring ML.
Further, in FIG. 23 (A), the other of the source and drain of the transistor 5415 is connected to the wiring VL.
Further, on or off selection in the transistor 5440 is performed according to the potential of the wiring GLa connected to the gate of the transistor 5440. The selection of on or off in the transistor 5416 is made according to the potential of the wiring GLa connected to the gate of the transistor 5416. The selection of on or off in transistor 5441 is made according to the potential of the wiring GLb connected to the gate of transistor 5441. The selection of on or off in transistor 5442 is made according to the potential of the wiring GLb connected to the gate of transistor 5442. The selection of on or off in transistor 5417 is made according to the potential of the wiring GLc connected to the gate of transistor 5417.
FIG. 23 (B) illustrates a timing chart of the potentials of the wiring GLa, the wiring GLb, and the wiring GLc connected to the pixel 5411 shown in FIG. 23 (A) and the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 23 (B) illustrates a case where all the transistors included in the pixel 5411 shown in FIG. 23 (A) are of the n-channel type.
First, in period t1, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, and the wiring GLc is given a high-level potential. Therefore, the transistor 5441, the transistor 5442 and the transistor 5417 are turned on, and the transistor 5440 and the transistor 5416 are turned off. When transistor 5442 and transistor 5417 are turned on, the potential V0 of the wiring ML is given to one of the source and drain of transistor 5415 and the other of the pair of electrodes of the capacitive element 5418 (shown as node A). ..
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. The potential Vano is preferably higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential V0. Further, the potential V0 is preferably lower than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential Vcat. By setting the potential V0 to the above value, it is possible to prevent the current from flowing through the light emitting element 5414 during the period t1.
Next, by applying a low-level potential to the wiring GLb, the transistor 5441 and the transistor 5442 are turned off, and the node A is held at the potential V0.
Next, in period t2, the wiring GLa is given a high-level potential, the wiring GLb is given a low-level potential, and the wiring GLc is given a low-level potential. Therefore, the transistor 5440 and the transistor 5416 are turned on, and the transistor 5441, the transistor 5442 and the transistor 5417 are turned off.
When shifting from the period t1 to the period t2, it is preferable to switch the potential given to the wiring GLa from the low level to the high level and then switch the potential given to the wiring GLc from the high level to the low level. By performing such an operation, it is possible to prevent the potential fluctuation of the node A due to the switching of the potential given to the wiring GLa.
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL. Then, the potential Vdata of the image signal Sig is given to the wiring SL, and the potential V1 is given to the wiring VL1. The potential V1 is preferably higher than the potential obtained by adding the threshold voltage Vth of the transistor 5415 to the potential Vcat and lower than the potential obtained by adding the threshold voltage Vth of the transistor 5415 to the potential Vano.
In the pixel configuration shown in FIG. 23 (A), even if the potential V1 is higher than the value obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential Vcat, as long as the transistor 5442 is off, the light emitting element 5414 Does not emit light. Therefore, it is possible to widen the range of values that can be set as the potential V0, and it is also possible to widen the range of values that can be taken as V1-V0. Therefore, since the degree of freedom in setting the value of V1-V0 increases, it is accurate even when the time required to acquire the threshold voltage of the transistor 5415 is shortened or when the acquisition period of the threshold voltage is limited. The threshold voltage of the transistor 5415 can be acquired.
By the above operation, a potential V1 higher than the potential obtained by adding the threshold voltage to the potential of the node A is input to the gate of the transistor 5415 (shown as the node B), and the transistor 5415 is turned on. Therefore, the electric charge of the capacitive element 5418 is emitted through the transistor 5415, and the potential of the node A, which has a potential of V0, begins to rise. Finally, when the potential of the node A converges to V1-Vth and the gate voltage of the transistor 5415 converges to the threshold voltage Vth, the transistor 5415 is turned off.
Further, the potential Vdata of the image signal Sig given to the wiring SL is given to one of the pair of electrodes of the capacitive element 5418 (shown as node C) via the transistor 5440.
Next, in period t3, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, and the wiring GLc is given a low-level potential. Therefore, the transistor 5441 and the transistor 5442 are turned on, and the transistor 5440, the transistor 5416 and the transistor 5417 are turned off.
When transitioning from the period t2 to the period t3, it is preferable that the potential given to the wiring GLa is switched from the high level to the low level, and then the potential given to the wiring GLb is switched from the low level to the high level. With the above configuration, it is possible to prevent the fluctuation of the potential at the node A due to the switching of the potential given to the wiring GLa.
Further, the potential Vano is given to the wiring VL, and the potential Vcat is given to the wiring CL.
Since the potential Vdata is given to the node B by the above operation, the gate voltage of the transistor 5415 becomes Vdata-V1 + Vth. Therefore, the gate voltage of the transistor 5415 can be set to a value in which the threshold voltage Vth is added. With the above configuration, it is possible to suppress variations in the threshold voltage Vth of the transistor 5415. Therefore, it is possible to suppress variations in the current value supplied to the light emitting element 5414, and it is possible to reduce uneven brightness of the light emitting device.
By increasing the fluctuation of the potential given to the wiring GLb, it is possible to prevent the variation of the threshold voltage of the transistor 5442 from affecting the current value supplied to the light emitting element 5414. That is, the high-level potential given to the wiring GLb is sufficiently larger than the threshold voltage of the transistor 5442, and the low-level potential given to the wiring GLb is made sufficiently smaller than the threshold voltage of the transistor 5442. It is possible to reliably switch the 5442 on and off, and prevent the variation in the threshold voltage of the transistor 5442 from affecting the current value of the light emitting element 5414.
Next, in period t4, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, and the wiring GLc is given a high-level potential. Therefore, the transistor 5417 is turned on, and the transistor 5416, the transistor 5440, the transistor 5441, and the transistor 5442 are turned off.
Further, the potential Vano is given to the wiring VL, and the wiring ML is connected to the monitor circuit.
By the above operation, the drain current Id of the transistor 5415 flows to the wiring ML through the transistor 5417 instead of the light emitting element 5414. The monitor circuit uses the drain current Id flowing through the wiring ML to generate a signal including the value of the drain current Id as information. This drain current Id has a size that depends on the mobility of the transistor 5415, the size of the transistor 5415 (channel length, channel width), and the like. Then, in the light emitting device according to one aspect of the present invention, the value of the potential Vdata of the image signal Sig supplied to the pixel 5411 can be corrected by using the above signal. That is, the influence of the variation in the mobility of the transistor 5415 can be reduced.
In the light emitting device having the pixel 5411 shown in FIG. 23 (A), it is not necessary to perform the operation of the period t4 after the operation of the period t3. For example, in the light emitting device, the operation of the period t1 to the period t3 may be repeated a plurality of times, and then the operation of the period t4 may be performed. Further, after the operation of the period t4 is performed on the pixel 5411 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 5411 in the line in which the operation is performed, so that the light emitting element 5414 is non-emitted. After the state is set, the operation of the period t4 may be performed in the pixel 5411 in the next line.
In the light emitting device having the pixel 5411 shown in FIG. 23 (A), the other of the source and drain of the transistor 5415 and the gate of the transistor 5415 are electrically separated, so that the potentials of the respective potentials should be controlled individually. Can be done. Therefore, in the period t2, the other potentials of the source and drain of the transistor 5415 can be set to a value higher than the potential obtained by adding the threshold voltage Vth to the potential of the gate of the transistor 5415. Therefore, when the transistor 5415 is normalized, that is, when the threshold voltage Vth has a negative value, the capacitive element in the transistor 5415 until the source potential is higher than the gate potential V1. Charges can be stored in the 5418. Therefore, in the light emitting device according to one aspect of the present invention, even if the transistor 5415 is a normalion, the threshold voltage Vth can be acquired in the period t2, and the acquired threshold voltage Vth can be obtained in the period t3. The gate voltage can be set accordingly.
Therefore, in the light emitting device according to one aspect of the present invention, even if the transistor 5415 becomes a normalion, display unevenness can be reduced and high image quality display can be performed.
Not only the characteristics of the transistor 5415 but also the characteristics of the light emitting element 5414 may be monitored. At this time, it is preferable to prevent current from flowing through the transistor 5415 by controlling the potential of the potential Vdata of the image signal Sig. As a result, the current of the light emitting element 5414 can be taken out. As a result, it is possible to acquire the state of deterioration and variation of the current characteristics of the light emitting element 5414.
For example, in the present specification and the like, the display element, the display device which is a device having a display element, the light emitting element, and the light emitting device which is a device having a light emitting element use various forms or have various elements. Can be done. Display elements, display devices, light emitting elements or light emitting devices include, for example, EL elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.). , Transistor (transistor that emits light according to current), electron emitting element, liquid crystal element, electronic ink, electrophoresis element, grating light valve (GLV), plasma display panel (PDP), MEMS (micro electromechanical system) Display element using, digital micromirror device (DMD), DMS (digital micro shutter), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowet It has at least one such as a ting element, a piezoelectric ceramic display, and a display element using carbon nanotubes. In addition to these, a display medium whose contrast, brightness, reflectance, transmittance, and the like are changed by an electric or magnetic action may be provided. An example of a display device using an EL element is an EL display. As an example of a display device using an electron emitting element, a field emission display (FED) or an SED flat display (SED:) Surface-conduction Electron-emitter Display) and so on. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using electronic ink or an electrophoresis element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.
In addition, in order to display the display device in full color by using white light (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.), a colored layer (also referred to as a color filter) may be used. Good. As the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be appropriately combined and used. By using the colored layer, the color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% in a bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from an element having each emission color. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.
<Pixel Structure of Light Emitting Device> An example of the pixel structure of the light emitting device according to one aspect of the present invention will be described below.
In FIG. 24 (A), a plurality of transistors 500 (also referred to as FETs) are formed on the substrate 502, and each transistor 500 includes each light emitting element (504R, 504G, 504B,) included in the pixels of the light emitting device. It is electrically connected to 504W). Specifically, each transistor 500 is electrically connected to the conductor 506 of the light emitting element. Each light emitting element is composed of a conductor 506, a conductor 507, a light emitting layer 510, and a conductor 512. It is not necessary to have the light emitting element 504W among the light emitting elements. Note that FIG. 24 (B) is an enlarged cross-sectional view of the region 520 in FIG. 24 (A).
Further, colored layers (514R, 514G, 514B, 514W) are arranged on each light emitting element. Although FIG. 24A shows a structure in which the colored layer is provided on the substrate 516, the structure is not limited to this structure. For example, the colored layer may be provided on the substrate 502. Further, a sealing film 518 is arranged between the substrate 502 and the substrate 516. As the sealing film 518, for example, a glass frit or the like, a curable resin such as a two-component mixed resin that cures at room temperature, a photocurable resin, a thermosetting resin, or the like can be used.
Further, a partition wall 508 is provided between the adjacent light emitting elements so as to cover the ends of the conductor 506 and the conductor 507. Further, a spacer 509 is provided on the partition wall 508. The conductor 506 has a region that functions as a reflecting electrode and a region that functions as an anode of a light emitting element. Further, the conductor 507 has a region that contributes to adjusting the optical path length of each light emitting element. Further, a light emitting layer 510 is formed on the conductor 507, and a conductor 512 is formed on the light emitting layer 510. Further, the conductor 512 has a region that functions as a semi-transmissive / semi-reflective electrode and a region that functions as a cathode of a light emitting element. Further, the spacer 509 is arranged between the light emitting element and the colored layer.
Further, the light emitting layer 510 may be common to each light emitting element. However, the light emitting layer 510 may be different for each light emitting element. Each light emitting element has a micro optical resonator (also referred to as a microcavity) structure in which light emitted from the light emitting layer 510 is resonated by the conductor 506 and the conductor 512, and has the same light emitting layer 510. It is possible to narrow the line and extract light of different wavelengths. Specifically, each light emitting element adjusts the thickness of the conductor 507 provided below the light emitting layer 510 to make the spectrum obtained from the light emitting layer 510 a desired light emitting spectrum, and emits light having high color purity. Can be obtained. Therefore, by adopting the configuration shown in FIG. 24 (A), for example, the step of painting separately becomes unnecessary, and it may be easy to realize high definition. However, the light emitting device according to one aspect of the present invention may be manufactured by separately coating the light emitting layer on each light emitting element.
Further, in the light emitting device shown in FIG. 24 (A), light of different wavelengths narrowed by the microcavity structure is further narrowed by passing through a colored layer, and only a desired emission spectrum is emitted. It is a configuration. Therefore, by combining the microcavity structure and the colored layer, it is possible to obtain light emission with even higher color purity. Specifically, in the light emitting element 504R, the optical path length of the light emitting element is adjusted so as to obtain red light emission, and red light is emitted in the direction of the arrow through the colored layer 514R. Further, in the light emitting element 504G, the optical path length of the light emitting element is adjusted so as to obtain green light emission, and green light is emitted in the direction of the arrow through the colored layer 514G. Further, in the light emitting element 504B, the optical path length of the light emitting element is adjusted so as to obtain blue light emission, and blue light is emitted in the direction of the arrow through the colored layer 514B. Further, in the light emitting element 504W, the optical path length of the light emitting element is adjusted so as to obtain white light emission, and white light is emitted in the direction of the arrow through the colored layer 514W.
The method of adjusting the optical path length of each light emitting element is not limited to this. For example, in each light emitting element, the thickness of the light emitting layer 510 may be adjusted to adjust the optical path length.
Further, the colored layer (514R, 514G, 514B) may have a function of transmitting light in a specific wavelength band, for example, a red (R) colored layer that transmits light in a red wavelength band. , A green (G) colored layer that transmits light in the green wavelength band, a blue (B) colored layer that transmits light in the blue wavelength band, and the like can be used. Further, as the colored layer 514W, for example, an acrylic resin material or the like that does not contain a pigment or the like may be used. Further, it is not necessary to have the colored layer 514W. The colored layer can be formed into a desired shape by a printing method, an inkjet method, a method using a photolithography process, or the like.
As the conductor 506, for example, a metal having a high reflectance (the reflectance of visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less) can be used. As the conductor 506, aluminum, silver, or an alloy containing these metal materials (for example, an alloy of silver, palladium, and copper) can be used as a single layer or laminated.
Further, the conductor 507 can be formed by using, for example, a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, or those metal oxides containing silicon or tungsten can be used. By providing the conductor 507, it is possible to suppress the formation of an insulator formed between the light emitting layer 510 formed later and the conductor 506, which is preferable. Further, a conductive metal oxide used as the conductor 507 may be formed in the lower layer of the conductor 506.
The conductor 512 is formed of a conductive material having reflectivity and a conductive material having translucency, and has a visible light reflectance of 20% or more and 80% or less, preferably 40% or more and 70% or less. Is preferable. As the conductor 512, for example, silver, magnesium, or an alloy containing these metal materials is formed thinly (for example, 1 nm or more and 10 nm or less), and then a conductive metal oxide that can be used for the conductor 507. Should be formed.
In the configuration described above, the light emitting device has a structure that extracts light from the substrate 516 side (top emission structure), but has a structure that extracts light to the substrate 501 side on which the transistor 500 is formed (bottom emission structure), or It may be a light emitting device having a structure (dual emission structure) that extracts light to both the substrate 501 and the substrate 516. In the case of the bottom emission structure, for example, the colored layer (514R, 514G, 514B, 514W) may be formed below the conductor 506. A translucent substrate may be used as the substrate on the side that emits light, and a translucent substrate and a light-shielding substrate may be used as the substrate on the side that does not emit light.
<Module> In the following, a display module to which the semiconductor device according to one aspect of the present invention is applied will be described with reference to FIG.
The display module 8000 shown in FIG. 25 has a touch panel 8004 connected to the FPC 8003, a cell 8006 connected to the FPC 8005, a backlight unit 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. Has 8011. In some cases, the backlight unit 8007, battery 8011, touch panel 8004, etc. are not provided.
The semiconductor device according to one aspect of the present invention can be used, for example, in cell 8006.
The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the cell 8006.
The touch panel 8004 can be used by superimposing a resistive film type or capacitance type touch panel on the cell 8006. It is also possible to give the facing substrate (sealing substrate) of the cell 8006 a touch panel function. Alternatively, an optical sensor may be provided in each pixel of the cell 8006 to form an optical touch panel. Alternatively, it is also possible to provide a touch sensor electrode in each pixel of the cell 8006 to form a capacitive touch panel.
The backlight unit 8007 has a light source 8008. A light source 8008 may be provided at the end of the backlight unit 8007, and a light diffusing plate may be used.
The frame 8009 may have a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010, in addition to the protective function of the cell 8006. Further, the frame 8009 may have a function as a heat radiating plate.
The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply using a separately provided battery 8011. When using a commercial power source, it is not necessary to have the battery 8011.
Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.
<Circuit> Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device of one aspect of the present invention will be described.
The circuit diagram shown in FIG. 26 (A) shows the configuration of a so-called CMOS inverter in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their respective gates are connected. As the transistor 2200 and the transistor 2100, the above-mentioned transistor 150 may be used.
The circuit diagram shown in FIG. 26B shows a configuration in which the sources and drains of the transistors 2100 and 2200 are connected. With such a configuration, it can function as a so-called CMOS analog switch.
FIG. 27 shows an example of a semiconductor device (storage device) using a transistor according to one aspect of the present invention, which can retain the stored contents even in a situation where power is not supplied and has no limit on the number of times of writing.
The semiconductor device shown in FIG. 27 (A) includes a transistor 3200 using the first semiconductor, a transistor 3300 using the second semiconductor, and a capacitive element 3400. As the transistor 3300, the above-mentioned transistor 150 can be used.
The transistor 3300 is, for example, a transistor using an oxide semiconductor. Due to the small off-current of the transistor 3300, it is possible to retain the stored contents in a specific node of the semiconductor device for a long period of time. That is, since the refresh operation is not required or the frequency of the refresh operation can be extremely reduced, the semiconductor device has low power consumption.
In FIG. 27 (A), the first wire 3001 is electrically connected to the source of the transistor 3200 and the second wire 3002 is electrically connected to the drain of the transistor 3200. Further, the third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. Then, the gate of the transistor 3200 and the source and drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitive element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitive element 3400. Has been done. As the capacitance element 3400, the above-mentioned capacitance element 160 can be used.
The semiconductor device shown in FIG. 27 (A) has a characteristic that the potential of the gate of the transistor 3200 can be held, so that information can be written, held, and read as shown below.
Writing and retaining information will be described. First, the potential of the fourth wiring 3004 is set to the potential at which the transistor 3300 is in the conductive state, and the transistor 3300 is brought into the conductive state. As a result, the potential of the third wiring 3003 is given to the gate of the transistor 3200 and the node FG which is electrically connected to one of the electrodes of the capacitive element 3400. That is, a predetermined charge is given (write) to the gate of the transistor 3200. Here, it is assumed that either of the charges giving two different potential levels (hereinafter referred to as low level charge and high level charge) is given. After that, the electric charge is held (retained) in the node FG by setting the potential of the fourth wiring 3004 to the potential at which the transistor 3300 is in the non-conducting state and making the transistor 3300 in the non-conducting state.
Since the off-current of transistor 3300 is extremely small, the charge of node FG is retained for a long period of time.
Next, reading information will be described. When a predetermined potential (constant potential) is applied to the first wiring 3001 and an appropriate potential (reading potential) is applied to the fifth wiring 3005, the second wiring 3002 is charged with the electric charge held by the node FG. Take an electric potential according to the amount. This is because, assuming that the transistor 3200 is an n-channel type, the apparent threshold voltage V when the gate of the transistor 3200 is given a high level charge.<sub>th_H</sub>Is the apparent threshold voltage V when the gate of transistor 3200 is given a low level charge.<sub>th_L</sub>Because it will be lower. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to bring the transistor 3200 into a "conducting state". Therefore, the potential of the fifth wiring 3005 is V.<sub>th_H</sub>And V<sub>th_L</sub>Potential V between<sub>0</sub>By doing so, the charge given to the node FG can be discriminated. For example, in writing, if the node FG is given a high level charge, the potential of the fifth wire 3005 is V.<sub>0</sub>(> V<sub>th_H</sub>), The transistor 3200 is in the "conducting state". On the other hand, when the node FG is given a low level charge, the potential of the fifth wiring 3005 is V.<sub>0</sub>(<V<sub>th_L</sub>), The transistor 3200 remains in the "non-conducting state". Therefore, by discriminating the potential of the second wiring 3002, the information held in the node FG can be read out.
When the memory cells are arranged in an array, the information of the desired memory cells must be read at the time of reading. In order not to read the information of other memory cells, the potential that makes the transistor 3200 "non-conducting" regardless of the charge given to the node FG, that is, V<sub>th_H</sub>A lower potential may be given to the fifth wire 3005. Alternatively, the potential at which the transistor 3200 becomes "conducting" regardless of the charge given to the node FG, that is, V<sub>th_L</sub>A higher potential may be given to the fifth wire 3005.
The semiconductor device shown in FIG. 27 (B) differs from the semiconductor device shown in FIG. 27 (A) in that it does not have the transistor 3200. In this case as well, information can be written and held by the same operation as that of the semiconductor device shown in FIG. 27 (A).
The reading of information in the semiconductor device shown in FIG. 27 (B) will be described. When the transistor 3300 becomes conductive, the floating third wiring 3003 and the capacitance element 3400 conduct with each other, and the electric charge is redistributed between the third wiring 3003 and the capacitance element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 takes a different value depending on the potential of one of the electrodes of the capacitance element 3400 (or the electric charge accumulated in the capacitance element 3400).
For example, the potential of one of the electrodes of the capacitance element 3400 is V, the capacitance of the capacitance element 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of one of the electrodes of the capacitive element 3400 takes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 when the potential V1 is held The potential (= (CB × VB0 + C × V1) / (CB + C)) is the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + C × V0) / ( It can be seen that it is higher than CB + C)).
Then, the information can be read out by comparing the potential of the third wiring 3003 with a predetermined potential.
In this case, a transistor to which the first semiconductor is applied is used for the drive circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked and arranged on the drive circuit as the transistor 3300. do it.
The semiconductor device shown above can retain the stored contents for a long period of time by applying a transistor using an oxide semiconductor and having an extremely small off-current. That is, since the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely reduced, a semiconductor device having low power consumption can be realized. Further, even when there is no power supply (however, the potential is preferably fixed), it is possible to retain the stored contents for a long period of time.
Further, since the semiconductor device does not require a high voltage for writing information, deterioration of the element is unlikely to occur. For example, unlike a conventional non-volatile memory, electrons are not injected into the floating gate or extracted from the floating gate, so that problems such as deterioration of the insulator do not occur. That is, the semiconductor device according to one aspect of the present invention is a semiconductor device in which the number of rewritable times, which is a problem in the conventional non-volatile memory, is not limited, and the reliability is dramatically improved. Further, since information is written depending on the conductive state and non-conducting state of the transistor, high-speed operation is possible.
<RF Tag> In the following, the RF tag including the above-mentioned transistor or storage device will be described with reference to FIG. 28.
The RF tag according to one aspect of the present invention has a storage circuit inside, stores information in the storage circuit, and exchanges information with the outside by using non-contact means, for example, wireless communication. Due to these characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading individual information of the article or the like. High reliability is required for use in these applications.
The configuration of the RF tag will be described with reference to FIG. FIG. 28 is a block diagram showing a configuration example of the RF tag.
As shown in FIG. 28, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader / writer, etc.). Further, the RF tag 800 has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. As the semiconductor of the transistor which exhibits the rectifying action included in the demodulation circuit 807, for example, an oxide semiconductor capable of sufficiently suppressing the reverse current may be used. As a result, it is possible to suppress a decrease in the rectifying action due to the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RF tag 800 can be used in any of the methods.
Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal at the antenna 804, for example, half-wave double pressure rectification, and the rectified signal is smoothed by the capacitive element in the subsequent stage. This is a circuit for generating an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so that power exceeding a certain power is not input to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.
The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 by utilizing a stable rise in the power supply voltage.
The demodulation circuit 807 is a circuit for generating a demodulated signal by demodulating the input AC signal by detecting the envelope. Further, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.
The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The storage circuit 810 is a circuit that holds the input information, and has a row decoder, a column decoder, a storage area, and the like. Further, ROM811 is a circuit for storing a unique number (ID) and the like and outputting according to processing.
It should be noted that each of the above-mentioned circuits can be appropriately discarded.
Here, the above-mentioned storage device can be used for the storage circuit 810. The storage device according to one aspect of the present invention is suitable for RF tags because it can retain information even when the power supply is cut off. Further, the storage device according to one aspect of the present invention does not cause a difference in the maximum communication distance between reading and writing data because the power (voltage) required for writing data is lower than that of the conventional non-volatile memory. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.
Further, since the storage device according to one aspect of the present invention can be used as a non-volatile memory, it can also be applied to ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data to the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign the unique number only to the non-defective product to be shipped, instead of assigning the unique number to all the RF tags produced. The unique numbers of the products after shipment do not become discontinuous, and customer management corresponding to the products after shipment becomes easy.
<Example of Use of RF Tag> Hereinafter, an example of use of the RF tag according to one aspect of the present invention will be described with reference to FIG. 29. RF tags have a wide range of uses, such as banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see Fig. 29 (A)), packaging containers (wrapping paper). , Bottles, etc., see Fig. 29 (C)), recording media (DVD, video tape, etc., see Fig. 29 (B)), vehicles (bicycles, etc., see Fig. 29 (D)), personal belongings (bags, etc.) , Eyeglasses, etc.), foods, plants, animals, human bodies, clothing, daily necessities, medical products containing chemicals and drugs, or electronic devices (LCD display devices, EL display devices, television devices, or mobile phones) It can be used by providing it on an article such as, or a tag attached to each article (see FIGS. 29 (E) and 29 (F)).
The RF tag 4000 according to one aspect of the present invention is fixed to an article by being attached to or embedded in a surface. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF tag 4000 according to one aspect of the present invention realizes small size, thinness, and light weight, the design of the article itself is not impaired even after being fixed to the article. Further, an authentication function can be added to banknotes, coins, securities, bearer bonds, certificates, etc. by the RF tag 4000 according to one aspect of the present invention, and if this authentication function is utilized, counterfeiting can be performed. Can be prevented. Further, by attaching the RF tag 4000 according to one aspect of the present invention to packaging containers, recording media, personal belongings, foods, clothing, daily necessities, electronic devices, etc., the efficiency of systems such as inspection systems can be improved. Can be planned. Further, even for vehicles, by attaching the RF tag 4000 according to one aspect of the present invention, it is possible to enhance the security against theft and the like.
As described above, the RF tag according to one aspect of the present invention can be used for each of the above-mentioned uses.
<CPU> In the following, a CPU including a semiconductor device such as the above-mentioned transistor and the above-mentioned storage device will be described.
FIG. 30 is a block diagram showing a configuration of an example of a CPU using the above-mentioned transistor as a part.
The CPU shown in FIG. 30 is an ALU1191 (ALU: Arithmetic logic unit, arithmetic unit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, and bus interface 1198 on the board 1190. (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (ROM) I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in FIG. 30 is only an example showing the simplified configuration, and the actual CPU has a wide variety of configurations depending on its use. For example, the configuration including the CPU or the arithmetic circuit shown in FIG. 30 may be one core, and a plurality of the cores may be included so that each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.
Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU1191. In addition, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits based on their priority and mask state during CPU program execution. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.
The timing controller 1195 also generates signals that control the timing of operations of the ALU1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generator that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above-mentioned various circuits.
In the CPU shown in FIG. 30, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-mentioned transistor 150, capacitive element 160, and the like can be used.
In the CPU shown in FIG. 30, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from ALU1191. That is, in the memory cell of the register 1196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When data retention by flip-flop is selected, the power supply voltage is supplied to the memory cells in register 1196. When data retention in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.
FIG. 31 is an example of a circuit diagram of a storage element 1200 that can be used as a register 1196. The storage element 1200 has a selection function of a circuit 1201 in which stored data is volatilized when the power is cut off, a circuit 1202 in which the stored data is not volatilized when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, and a capacitance element 1207. It has a circuit 1220 and has. Circuit 1202 includes capacitive elements 1208, transistors 1209, and transistors 1210. The storage element 1200 may further include other elements such as a diode, a resistance element, and an inductor, if necessary.
Here, the above-mentioned storage device can be used for the circuit 1202. When the supply of the power supply voltage to the storage element 1200 is stopped, GND (0V) or the potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of transistor 1209 is grounded via a load such as a resistor.
Switch 1203 is configured with a monoconductive (eg, n-channel) transistor 1213, and switch 1204 is configured with a conductive (eg, p-channel) transistor 1214 that is the opposite of the monoconductive. An example of this is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. The control signal RD input to is selected to conduct or not conduct between the first terminal and the second terminal (that is, the conducting or non-conducting state of the transistor 1213). The first terminal of switch 1204 corresponds to one of the source and drain of transistor 1214, the second terminal of switch 1204 corresponds to the other of the source and drain of transistor 1214, and switch 1204 is input to the gate of transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction or non-conduction state of the transistor 1214).
One of the source and drain of transistor 1209 is electrically connected to one of the pair of electrodes of capacitive element 1208 and the gate of transistor 1210. Here, the connection part is node M2. One of the source and drain of transistor 1210 is electrically connected to a wire that can supply a low power potential (eg GND line), and the other is the first terminal of switch 1203 (source and drain of transistor 1213). One) is electrically connected. The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wire that can supply the power potential VDD. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and the capacitance element 1207. One of the pair of electrodes is electrically connected. Here, let the connection part be node M1. The other of the pair of electrodes of the capacitive element 1207 can be configured to receive a constant potential. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitive element 1207 is electrically connected to a wiring (eg, GND wire) capable of supplying a low power potential. The other of the pair of electrodes of the capacitive element 1208 can be configured to receive a constant potential. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitive element 1208 is electrically connected to a wire (eg, GND wire) capable of supplying a low power potential.
The capacitive element 1207 and the capacitive element 1208 can be omitted by positively utilizing the parasitic capacitance of the transistor and the wiring.
The control signal WE is input to the gate of transistor 1209. The switch 1203 and switch 1204 are selected from the conductive state and the non-conducting state between the first terminal and the second terminal by the control signal RD different from the control signal WE, and the first terminal and the second terminal of one switch are selected. When the terminals of the switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conducting state.
A signal corresponding to the data held in the circuit 1201 is input to the other of the source and drain of the transistor 1209. FIG. 31 shows an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logic value is inverted by the logic element 1206, and is input to the circuit 1201 via the circuit 1220. ..
Note that FIG. 31 shows an example in which the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is input to the circuit 1201 via the logic element 1206 and the circuit 1220. Not limited to. The signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) may be input to circuit 1201 without inverting the logic value. For example, if there is a node in circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, from the second terminal of switch 1203 (the other of the source and drain of transistor 1213). The output signal can be input to the node.
Further, in FIG. 31, among the transistors used in the storage element 1200, the transistors other than the transistor 1209 can be a transistor in which a channel is formed on a film made of a semiconductor other than an oxide semiconductor or a substrate 1190. For example, it can be a transistor in which a channel is formed on silicon or a silicon substrate. Further, all the transistors used in the storage element 1200 may be transistors whose channels are formed of oxide semiconductors. Alternatively, the storage element 1200 may include a transistor whose channel is formed of an oxide semiconductor in addition to the transistor 1209, and the remaining transistor has a channel formed on a layer or substrate 1190 made of a semiconductor other than the oxide semiconductor. It can also be a transistor to be used.
For the circuit 1201 in FIG. 31, for example, a flip-flop circuit can be used. Further, as the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.
In the semiconductor device according to one aspect of the present invention, the data stored in the circuit 1201 can be held by the capacitive element 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the storage element 1200.
Further, the off-current of a transistor in which a channel is formed in an oxide semiconductor is extremely small. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor is significantly smaller than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held by the capacitive element 1208 is maintained for a long period of time even when the power supply voltage is not supplied to the storage element 1200. In this way, the storage element 1200 can retain the stored contents (data) even when the supply of the power supply voltage is stopped.
Further, since the storage element is characterized in that the precharge operation is performed by providing the switch 1203 and the switch 1204, the time until the circuit 1201 re-holds the original data after the power supply voltage supply is restarted is shortened. be able to.
Further, in the circuit 1202, the signal held by the capacitive element 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the storage element 1200 is resumed, the signal held by the capacitive element 1208 is converted into the state of the transistor 1210 (conducting state or non-conducting state) and read out from the circuit 1202. Can be done. Therefore, even if the potential corresponding to the signal held by the capacitive element 1208 fluctuates to some extent, the original signal can be accurately read out.
By using such a storage element 1200 for a storage device such as a register or a cache memory of a processor, it is possible to prevent data loss in the storage device due to a stop supply of power supply voltage. Further, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply is stopped in a short time. Therefore, the power consumption can be suppressed because the power supply can be stopped even for a short time in the entire processor or one or a plurality of logic circuits constituting the processor.
The storage element 1200 has been described as an example of using the storage element 1200 for a CPU, but the storage element 1200 can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), and RF-ID (Radio Frequency Identification). Is.
<Electronic device> The semiconductor device according to one aspect of the present invention reproduces a recording medium such as a display device, a personal computer, and an image reproduction device (typically, a DVD: Digital Versatile Disc) including a recording medium, and reproduces the image. It can be used for a device having a display capable of displaying). In addition, as electronic devices that can use the semiconductor device according to one aspect of the present invention, mobile phones, game machines including portable types, mobile data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, and goggles. Type display (head mount display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic cash deposit / payment machine (ATM), vending machine, etc. Be done. A specific example of these electronic devices is shown in FIG.
FIG. 32 (A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, an operation key 907, a stylus 908, and the like. The portable game machine shown in FIG. 32 (A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this.
FIG. 32B is a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. is there. The image in the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915. Further, a display device having a function as a position input device may be used for at least one of the first display unit 913 and the second display unit 914. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, which is also called a photo sensor, in the pixel portion of the display device.
FIG. 32 (C) is a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like.
FIG. 32 (D) is an electric refrigerator / freezer, which has a housing 931, a refrigerator door 932, a freezer door 933, and the like.
FIG. 32 (E) is a video camera, which has a first housing 941, a second housing 942, a display unit 943, an operation key 944, a lens 945, a connection unit 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. is there. The image on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 on the connection unit 946.
FIG. 32 (F) is an ordinary automobile, which has a vehicle body 951, wheels 952, dashboard 953, lights 954, and the like.
<Electronic device having a curved surface in the display area or the light emitting area> Hereinafter, an electronic device having a curved surface in the display area or the light emitting area, which is an example of the electronic device according to one aspect of the present invention, will be described with reference to FIG. 33. .. Here, as an example of an electronic device, an information device, particularly a portable information device (portable device) will be described. Examples of portable information devices include mobile phones (phablets, smartphones (smartphones)), tablet terminals (slate PCs), and the like.
FIG. 33 (A-1) is a perspective view illustrating the outer shape of the portable device 1300A. FIG. 33 (A-2) is a top view of the mobile device 1300A. FIG. 33 (A-3) is a diagram illustrating a usage state of the portable device 1300A.
33 (B-1) and 33 (B-2) are perspective views illustrating the outer shape of the portable device 1300B.
33 (C-1) and 33 (C-2) are perspective views illustrating the outer shape of the portable device 1300C.
<Mobile device> The mobile device 1300A has one or more functions selected from functions such as telephone, e-mail creation and viewing, notebook or information viewing.
The portable device 1300A is provided with display units along a plurality of surfaces of the housing. For example, the display unit may be provided by arranging the flexible display device along the inside of the housing. As a result, character information, image information, and the like can be displayed in the first area 1311 and / and the second area 1312.
For example, an image to be used for the three operations can be displayed in the first region 1311 (see FIG. 33 (A-1)). In addition, character information and the like can be displayed in the second area 1312 as shown by the broken line rectangle in the figure (see FIG. 33 (A-2)).
When the second area 1312 is placed on the upper part of the mobile device 1300A, the characters and image information displayed in the second area 1312 of the mobile device 1300A can be displayed while the mobile device 1300A is stored in the chest pocket of the clothes. , The user can easily confirm (see Fig. 33 (A-3)). For example, the telephone number or name of the caller of the incoming call can be observed from above the mobile device 1300A.
The portable device 1300A may have an input device or the like between the display device and the housing, in or on the display device. As the input device, for example, a touch sensor, an optical sensor, an ultrasonic sensor, or the like may be used. When the input device is placed between the display device and the housing or on the housing, a touch panel such as a matrix switch method, a resistance film method, an ultrasonic surface acoustic wave method, an infrared method, an electromagnetic induction method, or a capacitance method is used. It may be used. When the input device is arranged in the display device, an in-cell type sensor, an on-cell type sensor, or the like may be used.
The portable device 1300A can be provided with a vibration sensor or the like and a storage device that stores a program that shifts to a mode of rejecting an incoming call based on the vibration detected by the vibration sensor or the like. As a result, the user can shift to the mode of rejecting the incoming call by tapping the mobile device 1300A from the top of the clothes to give vibration.
The portable device 1300B has a display unit having a first region 1311 and a second region 1312, and a housing 1310 that supports the display unit.
The housing 1310 includes a plurality of bent portions, and the longest bent portion included in the housing 1310 is sandwiched between the first region 1311 and the second region 1312.
The mobile device 1300B can be used with the second region 1312 along the longest bend facing sideways.
The portable device 1300C has a display unit having a first region 1311 and a second region 1312, and a housing 1310 that supports the display unit.
The housing 1310 includes a plurality of bent portions, and the second longest bent portion included in the housing 1310 is sandwiched between the first region 1311 and the second region 1312.
The portable device 1300C can be used with the second area 1312 facing upwards.
The contents described in the embodiment can be applied, combined, or replaced with respect to a part thereof and another part thereof. Further, the content described in the embodiment is a content described by using various figures or a content described by using a sentence described in the specification.
Further, by appropriately combining a part of a certain figure, another part of the figure, and a part of another figure, more figures can be formed.
In addition, it is possible to construct an aspect of the invention that stipulates that the contents not specified in the figures and sentences are excluded. Alternatively, if a numerical range indicated by an upper limit value and a lower limit value is described for a certain value, the range can be narrowed arbitrarily or by excluding one point in the range. It is possible to specify one aspect of the invention excluding parts. These can, for example, specify that the prior art does not fall within the technical scope of one aspect of the invention.
As a specific example, it is assumed that a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it is possible to define as an invention that the circuit does not have a sixth transistor. Alternatively, it is possible to specify that the circuit does not have a capacitive element. Further, the invention can be configured by defining that the circuit does not have a sixth transistor such as having a particular connection structure. Alternatively, the invention can be constructed by defining that the circuit does not have a capacitive element having a specific connection structure. For example, it is possible to specify the invention that the gate does not have a sixth transistor connected to the gate of the third transistor. Alternatively, for example, it is possible to define the invention that the first electrode does not have a capacitive element connected to the gate of the third transistor.
As another specific example, it is assumed that a certain value is described as, for example, "a certain voltage is preferably 3V or more and 10V or less". In that case, it is possible to specify one aspect of the invention, for example, except when a certain voltage is -2V or more and 1V or less. Alternatively, one aspect of the invention can be specified, for example, except when a certain voltage is 13 V or more. It is also possible to specify the invention that the voltage is 5 V or more and 8 V or less, for example. In addition, for example, it is possible to specify the invention that the voltage is approximately 9V. It should be noted that, for example, the invention can be specified except when the voltage is 3 V or more and 10 V or less, but 9 V or less. Even if a certain value is described as "preferably in a certain range", the certain value is not limited to those descriptions. That is, even if it is described as "preferable", it is not limited to those descriptions.
As another specific example, it is assumed that a certain value is described as, for example, "a certain voltage is preferably 10V". In that case, it is possible to specify one aspect of the invention, for example, except when a certain voltage is -2V or more and 1V or less. Alternatively, one aspect of the invention can be specified, for example, except when a certain voltage is 13 V or more.
As another specific example, it is assumed that the property of a substance is described as, for example, "a film is an insulating film". In that case, it is possible to specify one aspect of the invention, for example, except when the insulating film is an organic insulating film. Alternatively, it is possible to specify, for example, one aspect of the invention, except when the insulating film is an inorganic insulating film. Alternatively, it is possible to specify, for example, one aspect of the invention, except when the film is a conductive film. Alternatively, it is possible to specify, for example, one aspect of the invention, except when the film is a semiconductor film.
As another specific example, it is assumed that a certain laminated structure is described as, for example, "a certain film is provided between the A film and the B film". In that case, it is possible to specify the invention, for example, except when the film is a laminated film having four or more layers. Alternatively, for example, it is possible to specify the invention except when a conductive film is provided between the A film and the film.
In the present specification and the like, those skilled in the art may be skilled in the art without specifying the connection destinations of all the terminals of active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistance elements, etc.). For example, it may be possible to construct one aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. When the content in which the connection destination is specified is described in the present specification or the like, it can be determined that one aspect of the invention in which the connection destination is not specified is described in the present specification or the like. There is. In particular, when a plurality of locations are assumed as the connection destinations of the terminals, the connection destinations of the terminals need not be limited to specific locations. Therefore, one aspect of the invention can be configured by specifying the connection destination of only some terminals of active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistance elements, etc.). In some cases.
In the present specification and the like, a person skilled in the art may be able to specify the invention if at least the connection destination is specified for a certain circuit. Alternatively, a person skilled in the art may be able to specify the invention by at least specifying the function of a certain circuit. That is, it can be said that one aspect of the invention is clear if the function is specified. Then, it may be possible to determine that one aspect of the invention whose function has been specified is described in the present specification or the like. Therefore, for a certain circuit, if the connection destination is specified without specifying the function, it is disclosed as one aspect of the invention, and one aspect of the invention can be configured. Alternatively, for a certain circuit, if the function is specified without specifying the connection destination, it is disclosed as one aspect of the invention, and one aspect of the invention can be configured.
In the present specification and the like, it is possible to construct one aspect of the invention by taking out a part of the figure or sentence described in the item of the embodiment. Therefore, when a figure or sentence describing a certain part is described, the content obtained by taking out the figure or sentence of the part is also disclosed as one aspect of the invention, and constitutes one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistance elements, etc.), conductors, insulators, semiconductors, organic substances, inorganic substances, parts, devices, operating methods, manufacturing methods, etc. are described. In the figure or sentence given, it is possible to take out a part thereof to construct one aspect of the invention. For example, from a circuit diagram composed of N (N is a natural number) circuit elements (transistors, capacitive elements, etc.), M (M is a natural number and M <N) circuit elements (transistors, capacitive elements, etc.) Etc.) can be extracted to construct one aspect of the invention. As another example, one aspect of the invention is constructed by extracting M (M is a natural number and M <N) layers from a cross-sectional view having N (N is a natural number) layers. It is possible to do. As yet another example, one aspect of the invention is constructed by extracting M elements (M is a natural number and M <N) from a flowchart composed of N elements (N is a natural number). It is possible to do. As yet another example, some elements are arbitrarily extracted from the sentence "A has B, C, D, E or F", and "A has B and E." Inventions such as "has", "A has E and F", "A has C, E and F", or "A has B, C, D and E". It is possible to construct one aspect.
In the present specification and the like, when at least one specific example is described in the figure or sentence described in the embodiment, it is easily understood by those skilled in the art to derive a superordinate concept of the specific example. To. Therefore, when at least one specific example is described in the figure or sentence described in the embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention, and constitutes one aspect of the invention. It is possible to do. And it can be said that one aspect of the invention is clear.
In addition, in this specification and the like, at least the contents described in the figure are disclosed as one aspect of the invention, and it is possible to constitute one aspect of the invention. Therefore, if a certain content is described in the figure, the content is disclosed as one aspect of the invention even if it is not described by using a sentence, and can constitute one aspect of the invention. It is possible. Similarly, a figure obtained by taking out a part of the figure is also disclosed as one aspect of the invention, and it is possible to construct one aspect of the invention. And it can be said that one aspect of the invention is clear.
<p>In this example, the cross-sectional shape of the semiconductor device according to one aspect of the present invention was evaluated by a cross-sectional TEM image.</p><p>In the following, a method for preparing a sample will be described with reference to FIG. 37. In addition, FIG. 37 (A), FIG. 37 (B), FIG. 37 (C) and FIG. 37 (D) show a cross-sectional TEM image of the sample. Further, FIG. 37 (E) shows a flowchart of a sample preparation method.</p><p>First, a glass substrate was prepared. Next, silicon nitride having a thickness of 100 nm was formed on the glass substrate by the PECVD method. Next, silicon oxide having a thickness of 400 nm was formed on the silicon nitride by the PECVD method. Next, an oxide semiconductor (also referred to as OS) having a thickness of 50 nm was formed on the silicon oxide by a sputtering method. Next, silicon oxide (also referred to as SiON) having a thickness of 100 nm was formed on the oxide semiconductor by the PECVD method. Next, tantalum nitride having a thickness of 30 nm was formed on the silicon oxide by a sputtering method. Next, tungsten having a thickness of 150 nm was formed on the tantalum nitride by a sputtering method.</p><p>The oxide semiconductor was formed using a target with In: Ga: Zn = 5: 5: 6 [atomic number ratio].</p><p>Next, a resist mask was formed on the tungsten (see step S101 in FIG. 37 (E)). A cross-sectional TEM image of the sample extracted here is shown in FIG. 37 (A).</p><p>Next, a part of tungsten and tantalum nitride was etched using a resist mask (see step S102 in FIG. 37 (E)). A cross-sectional TEM image of the sample extracted here is shown in FIG. 37 (B).</p><p>The etching was performed in three stages. First, as the first step, 160 sccm chlorine gas, 320 sccm sulfur hexafluoride gas and 80 sccm oxygen gas are used, the pressure is 0.6 Pa, 250 W (13.56 MHz) is applied to the sample side, and the coil facing the sample. Tungsten was etched by applying 9000 W (13.56 MHz) to the mold electrode. At this time, the time was adjusted so that the tungsten was not completely etched and the tantalum nitride was not exposed.</p><p>Next, as the second step, 320 sccm chlorine gas, 160 sccm sulfur hexafluoride gas and 240 sccm oxygen gas are used, the pressure is set to 0.6 Pa, 1000 W (13.56 MHz) is applied to the sample side, and the sample faces the sample. The remaining tungsten was etched by applying 9000 W (13.56 MHz) to the coil type electrode. Since the second step is a condition in which the etching rate of tantalum nitride is slower than the etching rate of tungsten, it is possible to reduce the variation in the etching amount in the sample surface by having the second step.</p><p>Next, as the third step, tantalum nitride is formed by using 540 sccm of chlorine gas and 540 sccm of sulfur hexafluoride gas, setting the pressure to 3.0 Pa, and applying 3000 W (13.56 MHz) to the coil type electrode facing the sample. Etched. In the third step, since the etching rate of silicon oxide nitride is slower than the etching rate of tantalum nitride, it is possible to reduce the variation in the etching amount in the sample surface. The three-step etching was performed with the temperature of the sample side electrode set to 80 ° C.</p><p>As described above, a part of tungsten and tantalum nitride was etched.</p><p>Next, a resist mask and tungsten and tantalum nitride were used as masks, and a part of silicon oxide was etched and processed so that the ends of tungsten and tantalum nitride had a taper angle (step 37 (E)). See S103.). A cross-sectional TEM image of the sample extracted here is shown in FIG. 37 (C).</p><p>The etching conditions are 240 sccm of carbon tetrafluoride gas and 160 sccm of oxygen gas, with a pressure of 0.8 Pa, 1000 W (13.56 MHz) applied to the sample side, and 7000 W (7000 W) to the coil type electrode facing the sample. The silicon oxide nitride was etched by applying 13.56 MHz). Since this condition is a condition in which the etching rate of the oxide semiconductor is slower than the etching rate of silicon oxide nitride, it is possible to reduce the variation in the etching amount in the sample surface. The etching was performed with the temperature of the electrode on the sample side set to 10 ° C.</p><p>From FIG. 37 (C), the taper angle between the upper surface of tantalum nitride and the side surface of tungsten was about 40 °. The taper angle between the upper surface of silicon oxide and the side surface of tantalum nitride was about 31 °. The taper angle between the upper surface of the oxide semiconductor and the side surface of silicon oxide was about 84 °.</p><p>The cross-sectional shape shown in FIG. 37 (C) corresponds to the cross-sectional shape shown in FIG. Specifically, the silicon oxide nitride shown in FIG. 37 (C) corresponds to the insulator 112 shown in FIG. Further, the tantalum nitride shown in FIG. 37 (C) corresponds to the conductor 114a shown in FIG. Further, the tungsten shown in FIG. 37 (C) corresponds to the conductor 114b shown in FIG.</p><p>For the sample shown in Fig. 37 (C), use 240 sccm of carbon tetrafluoride gas and 160 sccm of oxygen gas for another 60 seconds, set the pressure to 0.8 Pa, apply 1000 W (13.56 MHz) to the sample side, and use the sample. Silicon oxide was etched by applying 7000W (13.56MHz) to the facing coil type electrodes. Since this condition is a condition in which the etching rate of the oxide semiconductor is slower than the etching rate of silicon oxide nitride, it is possible to reduce the variation in the etching amount in the sample surface. The etching was performed with the temperature of the electrode on the sample side set to 10 ° C.</p><p>Due to the relationship between the etching rates of silicon oxide, tantalum nitride, and tungsten, the end of silicon oxide has an arc shape and the tantalum nitride has a shape protruding from tungsten (step 37 (E)). See S104.).</p><p>After that, a cross-sectional TEM image of a sample in which silicon nitride having a thickness of 100 nm and silicon oxide having a thickness of 300 nm is formed is shown in FIG. 37 (D).</p><p>From FIG. 37 (D), the taper angle between the upper surface of tantalum nitride and the side surface of tungsten was about 82 °. The taper angle between the upper surface of silicon oxide and the side surface of tantalum nitride was about 23 °. The taper angle between the upper surface of the oxide semiconductor and the side surface of silicon oxide was about 55 °.</p>
100 Substrate 101 Insulator 102 Insulator 102a Insulator 102b Insulator 104 Conductor 104a Conductor 104a1 Conductor 104a2 Conductor 104b Conductor 104b1 Conductor 104b2 Conductor 104c Conductor 104d Conductor 104e Conductor 104f Conductor 106 Semiconductor 106a Semiconductor 106b Semiconductor 106c Semiconductor 107a Region 107a1 Region 107a2 Region 107a3 Region 107b Region 107b1 Region 107b2 Region 107b3 Region 107c Region 107d Region 107e Region 107f Region 108 Insulator 112 Insulator 113 Protective film 114 Conductor 114a Conductor 114b Conductor 115a Conductor 115b Conductor 116a Conductor 116a1 Conductor 116a2 Conductor 116b Conductor 116b1 Conductor 116b2 Conductor 116c Conductor 116c1 Conductor 116c2 Conductor 116d Conductor 116e Conductor 116f Conductor 118 Insulator 128 Insulator 132 Insulator 138 Insulator 148 Insulator 150 Transistor 160 Capacitive element 200 Pellet 200a Pellet 200b Pellet 201 Ion 220 Substrate 230 Target 500 Transistor 501 Board 502 Board 504B Light emitting element 504G Light emitting element 504R Light emitting element 504W Light emitting element 506 Conductor 507 Conductor 508 Partition 509 Spacer 510 Light emitting layer 512 Conductor 514B Colored layer 514G Colored layer 514R Colored layer 514W Colored layer 516 518 Encapsulating film 520 Area 800 RF tag 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM901 Housing 902 Housing 903 Display 904 Display 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display 914 Display 915 Connection 916 Operation key 921 Housing 922 Display 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerating room door 933 Freezer door 941 Housing 942 Housing 943 Display 944 Operation key 945 Lens 946 Connection 951 Body 952 Wheels 953 Dashboard 954 Write 1189 ROM Interface 1190 Board 1191 ALU1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM1200 Storage element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 1300A Portable device 1300B Portable device 1300C Portable device 1310 Housing 1311 Region 1312 Region 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitive element 4000 RF tag 5000 Board 5001 Pixel part 5002 Scan line drive circuit 5003 Scan line drive circuit 5004 Signal line drive Circuit 5010 Capacitive wiring 5012 Gate wiring 5013 Gate wiring 5014 Source electrode or drain electrode 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 Pixel 5021 Switching transistor 5022 Driving transistor 5023 Capacitive element 5023A Capacitive element 5023B Capacitive element 5024 Light emitting element 5025 Signal line 5026 Scan line 5027 Power line 5028 Common electrode 5100 Pellet 5111 Pixel 5120 Substrate 5154 Light emitting element 5155 Transistor 5156 Transistor 5157 Transistor 5158 Capacitive element 5161 Area 5211 pixel 5214 Light emitting element 5215 Transistor 5216 Transistor 5217 Transistor 5218 Capacitive element 5219 Transistor 5311 Pixel 5314 Transistor 5316 Transistor 5317 Transistor 5318 Capacitive element 5319 Transistor 5320 Transistor 5411 Pixel 5414 Light emitting element 5415 Transistor 5416 Transistor 5417 Transistor 5418 Capacitive element 5440 Transistor 5441 Transistor 5442 Transistor 8000 Display module 8001 Top cover 8002 Bottom cover 8003 FPC8004 Touch panel 8005 FPC8006 Cell 8007 Backlight unit 8007 Light source 8009 Frame 8010 Printed board 8011 Battery
55 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38 Sheet 39 Sheet 40 Sheet 41 Sheet 42 Sheet 43 Sheet 44 Sheet 45 Sheet 46 Sheet 47 Sheet 48 Sheet 49 Sheet 50 Sheet 51 Sheet 52 Sheet 53 Sheet 54 Sheet 55
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP2003308027A | Cites | Japan |
| JP2003297749A | Cites | Japan |
| JP2012019206A | Cites | Japan |
| JP2012151461A | Cites | Japan |
| JP2011077517A | Cites | Japan |
| JP2013247270A | Cites | Japan |
| JP2002083805A | Cites | Japan |
30 members in 4 offices
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 2014020542 | Japan | – | |
| 2014020542 | Japan | A | |
| 2014050588 | Japan | – | |
| 2014050588 | Japan | A |
Members30
| Document | Office | Kind | |
|---|---|---|---|
| US2015221775A1 | United States of America | A1 | |
| KR20150092707A | Republic of Korea | A | |
| TW201535673A | Taiwan Province of China | A | |
| JP2015188064A | Japan | A | |
| US9705002B2 | United States of America | B2 | |
| US2017271520A1 | United States of America | A1 | |
| US10096721B2 | United States of America | B2 | |
| JP6437331B2This record | Japan | B2 | |
| JP2019041122A | Japan | A | |
| TWI665778B | Taiwan Province of China | B | |
| JP6700368B2 | Japan | B2 | |
| JP2020145443A | Japan | A | |
| KR102307729B1 | Republic of Korea | B1 | |
| KR20210119934A | Republic of Korea | A | |
| JP6982655B2 | Japan | B2 | |
| JP2022033792A | Japan | A | |
| KR102381183B1 | Republic of Korea | B1 | |
| KR20220042342A | Republic of Korea | A | |
| JP7274553B2 | Japan | B2 | |
| JP2023104930A | Japan | A | |
| KR102584384B1 | Republic of Korea | B1 | |
| KR20230141710A | Republic of Korea | A | |
| KR102646595B1 | Republic of Korea | B1 | |
| KR20240035977A | Republic of Korea | A | |
| JP7478882B2 | Japan | B2 | |
| JP2024097799A | Japan | A | |
| JP7678913B2 | Japan | B2 | |
| KR102827949B1 | Republic of Korea | B1 | |
| KR20250105346A | Republic of Korea | A | |
| JP2025118763A | Japan | A |
12 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Report on retrievalJAPANESE INTERMEDIATE CODE: A971007A977 | A977 | |
| Decision of grant or rejection writtenTRDD | TRDD | |
| Request for written amendment filedJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Written request for application examinationJAPANESE INTERMEDIATE CODE: A621A621 | A621 |
Numbers
- Publication
- 6437331
- Application
- 21220
Titles2
- Japanese
- 半導体装置
- English
- Semiconductor device
Classification
- CPC, 8
- H10D86/60
- H10D30/6755
- H10D86/423
- H10D86/481
- H10D30/6734
- H10D30/6757
- H10K59/1213
- H10D30/673
- IPC, 8
- H01L29 786
- H01L21 336
- H01L21 8242
- H01L27 108
- H01L51 50
- H05B33 14
- G02F1 1368
- H10B12 00
