Semiconductor device

0001The present invention relates to a semiconductor device and a method for manufacturing the same.

0002In the present specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In general, electro-optic devices, semiconductor circuits, electronic devices, etc. are all semiconductor devices.

0003Semiconductor devices using silicon are miniaturized according to the scaling law of transistors, etc. As a result, high integration has progressed, and power consumption has been reduced and performance has been improved.

0004However, in recent years, the limit of the scaling law has become a problem. For example, Chan-hae By reducing the length, so-called short-channel effects such as the punch-through phenomenon become apparent. Came.

0005It is also known that a narrow channel effect occurs when the channel width becomes smaller.

0006Miniaturized transistors have a threshold due to the effects of short-channel effect and narrow-channel effect. It becomes difficult to control the value voltage, and the characteristics tend to vary. So the short channel effect And a design rule that considers the fluctuation of the threshold voltage due to the narrow channel effect has been proposed. (See Patent Document 1).

0007In addition to this, in order to reduce the short channel effect that occurs when the transistor is miniaturized, Various methods have been studied (see Patent Document 2).

<p num="0008"><patcit num="1"><text>JP-A-4-134832</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2006-100842</text></patcit></p>

<p num="0009">However, the prior art is a major factor in the deterioration of the electrical characteristics of transistors due to miniaturization. The main aim is to reduce the effects of a short-channel effect, which is essentially a short-channel effect. No transistors have been proposed.</p><p num="0010">Therefore, in one aspect of the present invention, even if the channel length is small, the short channel effect does not substantially occur. One of the problems is to provide a transistor capable of obtaining switching characteristics.</p><p num="0011">Another issue is to provide a semiconductor device with a high degree of integration to which the transistor is applied. To do.</p>

<p num="0012">A transistor using an oxide semiconductor film with a channel length of 5 nm or more and less than 60 nm. And the channel width shall be 5 nm or more and less than 200 nm.</p><p num="0013">At this time, the channel width is 0.5 times or more and 10 times or less the channel length.</p><p num="0014">The oxide semiconductor film preferably contains at least In.</p><p num="0015">Alternatively, the oxide semiconductor film preferably contains at least In, Ga and Zn.</p><p num="0016">The inventors have found that the short-channel effect produced by transistors using silicon is an oxide semiconductor film. It was found that the transistor using the above may not occur substantially. This is really amazing It should be. Therefore, the miniaturization of transistors according to the conventional scaling law is completely different. It can be said that it became necessary to establish different laws of miniaturization.</p><p num="0017">The punch-through phenomenon, which is one of the short-channel effects that occur in transistors using silicon, is , DIBL (Drain Induced Barrier Lower) as one of the causes ing) is known.</p><p num="0018">In the following, the band generated near the junction between the oxide semiconductor film and the source electrode and drain electrode Focusing on the bending width of, DIBL, as seen in transistors using silicon, is oxidized. It is shown that it is unlikely to occur in a transistor using a physical semiconductor film.</p><p num="0019">Figure 21 shows the band structure between the source and drain of a transistor using n-type silicon. Fig. 21 (A) shows a schematic diagram of the band structure in the long channel, and Fig. 21 (B) shows the short channel. A schematic diagram of the band structure in the band structure is shown for each. Here, the gate voltage (V)_g) Is zero A case (off state) will be described.</p><p num="0020">From Fig. 21, the drain voltage (V)_d) Is zero, but the band bends near the pn junction interface You can see that it is sharp (solid line). This is n⁺Fermi level of region and p region are equal As a result of exchanging carriers in this way, a depletion layer with donor and acceptor ions Is formed and an electric field is generated.</p><p num="0021">Here V_dWhen is applied, n on the drain side⁺The band of the area is eV_dAs well as going down The depletion layer spreads from the drain side (dashed line). At this time, in the case of a long channel, V_dIs a saw It does not affect the side. On the other hand, in the case of short channel, V_dSpreads from the drain side The depletion layer extends to the source side, resulting in a decrease in the potential in the p region (lowering the bank). The conclusion As a result, the current becomes easier to flow, and the threshold voltage shifts in the negative direction.</p><p num="0022">Therefore, if the channel length of a transistor using n-type silicon is reduced, it will be on the drain side. The width of the depletion layer that spreads out, that is, the bending width of the band is V_dIt turns out that it increases with. Below Is a saw of a transistor using silicon and a transistor using an oxide semiconductor film. The bending width of the band near the junction (pn junction interface) between the drain and the channel, Each is derived analytically.</p><p num="0023">FIG. 22 shows the band structure on the source side of the transistor using n-type silicon. Figure 22 For reference, first, the band song on the source side in the p region of the transistor using n-type silicon Width L_s^SiTo ask. L_s^SiIs equal to the width of the depletion layer with acceptor ions. φ (y) is the potential at the distance y from the pn junction interface, and the origin is the true level E in the p region._i_pL^SiIt is said. eφ_F^SiIs E_ipL^SiAnd Fermi level E_F^SiDue to the difference with eφ_F^Si= E_ipL^Si-E_F^SiIs defined as. Here, e is an elementary charge. Bending of the band The width reflects the spatial change of φ (y). Equation (1) is Poisson's equation.</p><p num="0024"><maths num="1"><img id="000002" he="12" wi="71" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0025">ε^SiIs the permittivity and ρ is the charge density. When focusing on the depletion layer in the p region, ρ has a negative charge Only one acceptor ion needs to be considered, and the formula (2) is obtained.</p><p num="0026"><maths num="2"><img id="000003" he="10" wi="71" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0027">Where N_A^SiIs the acceptor density. Substitute formula (2) into formula (1) and formula ( Formula (4) can be obtained by solving under the boundary conditions shown in 3).</p><p num="0028"><maths num="3"><img id="000004" he="12" wi="70" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0029"><maths num="4"><img id="000005" he="13" wi="83" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0030">Here, from the boundary condition shown in equation (5), L_s^SiCan be obtained as in the formula (6).</p><p num="0031"><maths num="5"><img id="000006" he="14" wi="86" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0032"><maths num="6"><img id="000007" he="15" wi="77" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0033">Meanwhile, V_dBand bending width L on the drain side at the time of application_d^SiIs L_s^SiTotal similar to the case of It can be calculated as mathematical formula (7).</p><p num="0034"><maths num="7"><img id="000008" he="14" wi="84" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0035">From equation (7), for transistors using silicon, V_dBy L_d^SiWill increase, That is, V_dIt can be seen that the depletion layer spreads from the drain side. The above uses silicon DIBL in the transistor.</p><p num="0036">Next, FIG. 23 shows a battery between the source and drain of the transistor using the oxide semiconductor film. The structure is shown. Oxide semiconductor of a transistor using an oxide semiconductor film with reference to FIG. Band bend width L on the source side in the area_s^OSAnd the band bend width L on the drain side_d^OSTo ask. Work function of metal used for source and drain φ_mAnd oxide semiconductor electrons Affinity χ^OSIs equal to (φ_m= χ^OS), The metal-oxide semiconductor is ohmi It is assumed that they are in contact with each other. φ (y) is the distance y from the metal-oxide semiconductor junction interface on the source side. The potential at, and the origin is the intrinsic level E of the oxide semiconductor region._iL^OSIt is said. eφ_F^OSIs E_iL^OSAnd the Fermi level E on the source side_F^OSBy the difference of eφ_F^OS= E_iL^OS-E_F^OSIs defined as. In this case, the bending width of the band in the oxide semiconductor region is a large number of carriers. Electron density n^OSSince it is considered to arise from (y), the charge density ρ is given by equation (8).</p><p num="0037"><maths num="8"><img id="000009" he="12" wi="86" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0038">Where k is the Boltzmann constant and T is the absolute temperature. n₀^OSIs the bulk area of oxide semiconductors Intrinsic carrier density n, the electron density in the region_i^OSIt is expressed by the mathematical formula (9) using.</p><p num="0039"><maths num="9"><img id="000010" he="14" wi="85" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0040">Therefore, φ (y) can be obtained from the Poisson's equation shown in the equation (10).</p><p num="0041"><maths num="10"><img id="000011" he="14" wi="88" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0042">When this is solved under the boundary conditions shown in equation (11), equation (12) is obtained.</p><p num="0043"><maths num="11"><img id="000012" he="13" wi="83" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0044"><maths num="12"><img id="000013" he="15" wi="84" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0045">Therefore, the mathematical formula (14) can be obtained from the boundary condition shown by the mathematical formula (13).</p><p num="0046"><maths num="13"><img id="000014" he="14" wi="100" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0047"><maths num="14"><img id="000015" he="15" wi="95" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0048">Where E_g^OS/ 2 + eφ_F^OS&gt;&gt; 2kT, so formula (14) is formula (15) Can be approximated as.</p><p num="0049"><maths num="15"><img id="000016" he="16" wi="106" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0050">Meanwhile, V_dL at the time of application_d^OSIs eφ in formula (13)_F^OSEφ_F^OS+ eV_dPlace in You can find it if you change it. Again, E_g^OS/ 2 + eφ_F^OS+ eV_d&gt;&gt; 2kT, so number Equation (16).</p><p num="0051"><maths num="16"><img id="000017" he="15" wi="79" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths></p><p num="0052">From the above, in the case of a transistor using an oxide semiconductor film, L_d^OSIs V_dDoes not depend on You can see that. Therefore, DIBL does not occur in transistors using oxide semiconductor films. Eh.</p><p num="0053">In addition, the punch-through phenomenon that occurs in transistors using silicon is due to the electric field of the gate. It may also occur because the depletion layer does not extend deep into the channel region. is this, Minority carrier density contained in silicon is 1 × 10¹¹Pieces / cm³This is because it is high. That is, the accumulation of a small number of carriers makes the penetration of the electric field at the gate shallower, completing the transistor. It cannot be turned off completely, and the off-current increases.</p><p num="0054">On the other hand, according to the vigorous research of the inventors, the minority carrier density contained in the oxide semiconductor film has been determined. 1x10^-9Pieces / cm³It has become clear that it can be made extremely small. That is, half an oxide In a transistor using a conductor film, accumulation of a small number of carriers hardly occurs, and the electricity of the gate Since the penetration of the field is deep and the transistor can be easily turned off completely, the off current can be reduced. This In a transistor using an oxide semiconductor film, the depletion layer is widened due to the electric field of the gate. Will be extremely large.</p><p num="0055">As mentioned above, the short-channel effect commonly known for transistors using silicon is: It can be said that there is virtually no transistor using an oxide semiconductor film.</p><p num="0056">Therefore, a transistor using an oxide semiconductor film can be switched even when the channel length is small. It can be said that it is easy to obtain ching characteristics.</p><p num="0057">In addition, when miniaturizing a transistor using silicon, the channel length is reduced and the channel length is reduced. The flannel width was also generally reduced.</p><p num="0058">However, in a transistor using an oxide semiconductor film, as the channel length decreases, When the channel width was reduced, the threshold voltage sometimes shifted in the negative direction. .. This is also one of the findings of the vigorous research of the inventors.</p><p num="0059">Therefore, in order to obtain switching characteristics with a transistor using an oxide semiconductor film, When the channel length is small, it is important to make the channel width sufficiently large. Or It can be said that it is important to miniaturize the ratio of the channel width to the channel length while keeping it constant. ..</p><p num="0060">Note that the oxide semiconductor film generates electrons, which are carriers, due to oxygen deficiency. Should.</p><p num="0061">When electrons are generated in the oxide semiconductor film, the transistor is on even if the gate voltage is zero. It tends to be the so-called normally-on electrical characteristics. Therefore, the acid of the oxide semiconductor film It is preferable to reduce elementary defects.</p><p num="0062">For example, it is supplied from the outside of the oxide semiconductor film in order to reduce oxygen deficiency of the oxide semiconductor film. Oxygen may be used. As a method of supplying oxygen from the outside, specifically, iondo Oxidation treatment such as ping treatment, ion implantation treatment, and plasma treatment may be performed. Or An excess oxygen-containing layer may be provided, from which oxygen may be supplied to the oxide semiconductor film.</p><p num="0063">Even if such a method is used, the transistor using the oxide semiconductor film is miniaturized. As a result, the proportion of oxygen deficiency that occurs in the oxide semiconductor film is higher than that of oxygen supplied from the outside. May become. One of the causes is the table for the volume of the oxide semiconductor film with miniaturization. The area is increasing. From this point of view, when the channel length is reduced, the cha It can be said that it is important to increase the flannel width.</p><p num="0064">However, if the channel width is made extremely large, the transistor will be miniaturized. The original purpose cannot be achieved. Therefore, the ratio of channel length to channel width is currently You will choose from a practical range. From this point of view, the channel length can be reduced without restrictions. Attempting was not realistic because the channel width could not be increased above a certain level. there is a possibility.</p><p num="0065">Therefore, it is important to effectively utilize oxygen supplied from the outside of the oxide semiconductor film. Example For example, by providing a layer with low oxygen permeability on a transistor using an oxide semiconductor film, an acid can be used. The outward diffusion of the element is suppressed, and oxygen can be effectively utilized. Therefore, the channel length is small. Even when the channel width is less than a certain size, switching characteristics can be obtained. Can be done.</p><p num="0066">Further, as the transistor using the oxide semiconductor film is miniaturized, the side surface of the oxide semiconductor film is increased. Parasitic channels may be formed in. This is also due to the vigorous research of the inventors. This is one of the things that came to me.</p><p num="0067">The effects of parasitic channels can be significant on short-channel transistors, as they can be significant. It is easily mistaken for the short-channel effect, but it is not exactly.</p><p num="0068">Parasitic channels often have a lower threshold voltage than the original channel of the transistor. I. Therefore, when the influence of the parasitic channel becomes large, it is as if the threshold value of the transistor is increased. It looks as if the pressure has shifted in the negative direction. This is because carriers are on the sides of the oxide semiconductor film. This is because it is easy to generate. Therefore, with respect to the side surface of the oxide semiconductor film, with respect to other surfaces. It is important to supply more oxygen from the outside than the above.</p><p num="0069">For example, a structure in which a layer having low oxygen permeability is provided on the side surface of an oxide semiconductor film to prevent oxygen deficiency from occurring. It is good to say. Further, an oxide semiconductor film is laminated with a layer having low oxygen permeability to form an excess oxygen-containing layer. It is recommended to install it on the side of. At this time, the excess oxygen-containing layer is provided in contact with the side surface of the oxide semiconductor film. Is preferable.</p><p num="0070">In addition to oxygen deficiency, the oxide semiconductor film also generates electrons, which are carriers, by hydrogen. Is known to be. Therefore, it is preferable to reduce hydrogen in the oxide semiconductor film as well.</p><p num="0071">Minority carrier density is extremely low, and carrier generation sources such as oxygen deficiency and hydrogen are reduced. The off-current of a transistor using an oxide semiconductor film can be made extremely small.</p><p num="0072">In addition, the transistor using the oxide semiconductor film is a conventional transistor using silicon or the like. Can be used in combination with data. For example, transistors and compounds using silicon Transistors using semiconductors are on compared to transistors using oxide semiconductor films. It is easy to improve the characteristics. Therefore, silicon was used for the transistor for which the on characteristic is required. Low off-current is required by using transistors and transistors using compound semiconductors. A transistor using an oxide semiconductor film may be applied to the transistor. Oxide Since the semiconductor film can be formed by a thin film forming method such as a sputtering method, the other half One of the features is that there are few restrictions when using it in combination with a conductor material.</p><p num="0073">In addition, the transistor using silicon has good electricity by hydrogen-terminating the silicon surface. The characteristics can be obtained. Therefore, it serves as a hydrogen supply source for transistors using silicon. It is preferable to provide a hydrogen-containing layer. However, as mentioned above, an oxide semiconductor film is used. Hydrogen is a carrier generation source for the transistors that have been used, and is a factor that deteriorates electrical characteristics. is there.</p><p num="0074">Therefore, a transistor using silicon and a transistor using an oxide semiconductor film are assembled. When used together, a hydrogen-containing layer is provided on the transistor side using silicon to provide hydrogen permeability. It is preferable to provide a low layer on the transistor side using the oxide semiconductor film.</p>

<p num="0075">By using an oxide semiconductor film, even if the channel length is small, a substantially short channel effect is obtained. Can be provided, and a transistor capable of obtaining switching characteristics can be provided.</p><p num="0076">Further, it is possible to provide a semiconductor device having a high degree of integration to which the transistor is applied.</p>

0077<figref num="1">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="2">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="3">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="4">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="5">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="6">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="7">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="8">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="9">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="10">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="11">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="12">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="13">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="14">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="15">Top view and sectional view showing an example of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="16">The cross-sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention.</figref><figref num="17">A circuit diagram showing an example of a semiconductor storage device according to one aspect of the present invention, a diagram showing electrical characteristics, and a sectional view.</figref><figref num="18">A circuit diagram showing an example of a semiconductor storage device according to one aspect of the present invention, a diagram showing electrical characteristics, and a sectional view.</figref><figref num="19">A block diagram showing a specific example of a CPU according to one aspect of the present invention and a circuit diagram thereof.</figref><figref num="20">The perspective view which shows an example of the electronic device which concerns on one aspect of this invention.</figref><figref num="21">Band diagram between source and drain of transistor using n-type silicon.</figref><figref num="22">Band diagram of the source side of a transistor using n-type silicon.</figref><figref num="23">Band diagram between the source and drain of a transistor using an oxide semiconductor film.</figref>

0078Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is based on the following theory. It is easy for a person skilled in the art to be able to change the form and details in various ways without being limited to the obvious. Understood. Further, the present invention is construed as being limited to the description of the embodiments shown below. is not it. In explaining the structure of the invention using the drawings, the reference numerals indicating the same thing are different. It is also used in common among the drawings. In addition, when pointing to the same thing, the hatch pattern is the same However, there are cases where no particular sign is attached.

0079Hereinafter, the present invention will be described, but the terms used in the present specification will be briefly described. First, Regarding the source and drain of the Langista, one of them is referred to as a drain in this specification. Sometimes the other is the source. That is, they are not distinguished by the high or low potential. Therefore, the book In the specification, the part referred to as the source can be read as the drain.

0080In addition, the voltage is a certain potential and a reference potential (for example, ground potential (GND) or source potential). In many cases, it indicates the potential difference with. Therefore, it is possible to paraphrase voltage as electric potential. ..

0081In the present specification, even when it is expressed as "electrically connected", it is a real circuit. In some cases, there is no physical connection and the wiring is just extended.

0082The ordinal numbers attached as the first and second numbers are used for convenience, and are in process order or stacking order. Does not indicate. In addition, a unique name as a matter for specifying the invention in the present specification. It does not indicate a name.

0083The channel length refers to the distance between the source and drain of the transistor. channel The smaller the length, the smaller the on-resistance, and the transistor can operate at high speed. Also, The channel width refers to the opposite length of the source and drain of the transistor. Large channel width The smaller the on-resistance, the smaller the on-resistance, and the more the transistor can operate at high speed.

0084(Embodiment 1) In the present embodiment, the transistor according to one aspect of the present invention will be described.

0085FIG. 1A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 1 (A) A cross-sectional view corresponding to the chain lines A1-A2 is shown in FIG. 1 (B). In addition, the alternate long and short dash line shown in Fig. 1 (A) A cross-sectional view corresponding to A3-A4 is shown in FIG. 1 (C). For ease of explanation, Fig. 1 ( In A), the underlying insulating film 102 and the like are omitted.

0086FIG. 1 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. Area to do. At least a part of the two sides of the oxide semiconductor film 106 is a gate electrode. Superimpose with 104.

0087The transistor shown in Fig. 1 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0088The transistor shown in FIG. 1 (A) has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0089FIG. 1B shows the underlying insulating film 102 provided on the substrate 100 and the underlying insulating film 102. The oxide semiconductor film 106 and the gate insulating film 1 provided on the oxide semiconductor film 106 12 and a game located on the gate insulating film 112 and superimposed on the oxide semiconductor film 106. It is a cross-sectional structure of a transistor having an electrode 104.

0090In addition, in FIG. 1 (B), the oxidation provided on the oxide semiconductor film 106 and the gate electrode 104. An interlayer insulating film 118 having an opening reaching the semiconductor film 106 and an opening of the interlayer insulating film 118. The wiring 136 provided in contact with the oxide semiconductor film 106 via the portion is shown.

0091As the material of the oxide semiconductor film 106, for example, an In-M-Zn-O-based material may be used. This Here, the metal element M is an element having a higher binding energy with oxygen than In and Zn. Ma Or, it is an element that has the function of suppressing the desorption of oxygen from In-M-Zn-O materials. is there. The formation of oxygen deficiency in the oxide semiconductor film is suppressed to some extent by the action of the metal element M. To. Therefore, fluctuations in the electrical characteristics of the transistor due to oxygen deficiency can be reduced. , A highly reliable transistor can be obtained.

0092Specifically, the metal element M is Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga. , Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, D It may be y, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, preferably Al. , Ti, Ga, Y, Zr, Ce or Hf. The metal element M is one of the above-mentioned elements. Or you can select two or more types. Also, Si or Ge may be used instead of the metal element M. I don't know.

0093However, the oxide semiconductor film 10 is solely affected by the action of the metal element M contained in the oxide semiconductor film 106. The formation of oxygen deficiency in 6 cannot be completely suppressed. Therefore, the underlying insulating film 102 and It is important to supply oxygen from at least one of the gate insulating film 112.

0094In addition, the hydrogen concentration in the oxide semiconductor film 106 is set to 2 × 10.²⁰atoms / cm³Below, good 5 × 10¹⁹atoms / cm³Below, more preferably 1 × 10¹⁹atom s / cm³It is as follows. This is because the hydrogen contained in the oxide semiconductor film 106 is unintended. This is because it may generate a rear. The generated carriers are the electrical characteristics of the transistor. It becomes a factor that fluctuates.

0095The oxide semiconductor film 106 is single crystal, polycrystalline (also referred to as polycrystal) or amorphous. Which state to take.

0096Preferably, the oxide semiconductor film 106 is CAAC-OS (C Axis Aligned). Crystalline Oxi de Semiconductor) Membrane.

0097The CAAC-OS membrane is neither completely single crystal nor completely amorphous. CAAC-OS membrane Is an oxide semiconductor film having a crystal-amorphous mixed phase structure having a crystal portion in an amorphous phase. In addition, this The crystal part is often sized to fit inside a cube with a side of less than 100 nm. Also, Transmission Electron Microscope (TEM) In the observation image by scope), the boundary between the amorphous part and the crystalline part contained in the CAAC-OS film Is not clear. In addition, by TEM, grain boundaries (grain boundaries) are formed on the CAAC-OS film. Also called. ) Cannot be confirmed. Therefore, the CAAC-OS film has a carry due to grain boundaries. A. The decrease in mobility is suppressed.

0098The crystal part contained in the CAAC-OS film has the c-axis on the surface to be formed or the upper surface of the CAAC-OS film. Triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane and aligned in the vertical direction The metal atoms are layered or the metal atoms and oxygen atoms are layered when viewed from the direction perpendicular to the c-axis. Are arranged. The orientations of the a-axis and b-axis are different between different crystal parts. May be good. In the present specification, when simply described as vertical, the range of 85 ° or more and 95 ° or less is also included. It will be rare.

0099In the CAAC-OS film, the distribution of crystal portions does not have to be uniform. For example, CAA When crystal growth is performed from the upper surface side of the oxide semiconductor film 106 in the process of forming the C-OS film. , The proportion of the crystal part may be higher on the upper surface side than on the surface to be formed side. Also, CAA By adding impurities to the C-OS film, the crystal part becomes amorphous in the impurity-added region. It may become.

0100The c-axis of the crystal part contained in the CAAC-OS film is the normal vector of the surface to be formed of the CAAC-OS film. The shape of the CAAC-OS film (to be formed) because it is aligned in the direction parallel to the normal vector of the top surface. Depending on the cross-sectional shape of the surface or the cross-sectional shape of the upper surface), they may face in different directions. Na Oh, the direction of the c-axis of the crystal part is the normal vector of the surface to be formed when the CAAC-OS film is formed. The direction is parallel to the normal vector of the top surface. The crystal part can be formed by forming a film. Is formed by performing a crystallization treatment such as a heat treatment after the film formation.

0101Transistors using CAAC-OS film have fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Is small. Therefore, the transistor has high reliability.

0102The oxide semiconductor film 106 has a region 106a and a region 106b. Area 106 a functions as a channel area, and area 106b serves as a source area and a drain area. It works. Therefore, region 106b may be referred to as a conductor rather than a semiconductor. for that reason For convenience, even when the oxide semiconductor film 106 is shown, the region 106b is excluded and the region 106 Sometimes it points only to a.

0103The region 106b is a region having a lower resistance than the region 106a. Region 106b is half an oxide This is a region containing impurities that have the effect of lowering the resistance of the conductor film. Lowers the resistance of oxide semiconductor films Impurities that have an effect are, for example, helium, boron, nitrogen, fluorine, neon, and aluminium. Mu, phosphorus, argon, arsenic, krypton, indium, tin, antimony and xenon Can be mentioned.

0104The band gap of the region 106a in the oxide semiconductor film 106 is 2.8eV to 3.2e. About V, minority carrier density is 10^-9Pieces / cm³Very few, many carriers A only comes from the source of the transistor.

0105The oxide semiconductor film 106 has a larger bandgap of about 1 to 2 eV than that of silicon. So Therefore, the transistor using the oxide semiconductor film 106 is less likely to undergo collision ionization. Avalanche breakdown is unlikely to occur. That is, the transistor is a hot carry. It can be said that deterioration is unlikely to occur.

0106Further, the region 106a has a low impurity concentration and a small oxygen deficiency. Therefore, the transition The star is when the oxide semiconductor film 106 is thick (for example, 15 nm or more and less than 100 nm). ) But the electric field of the gate electrode 104 can completely deplete the region 106a. Therefore, the transistor shifts the threshold voltage in the negative direction due to the punch-through phenomenon. Does not occur and, for example, when the channel length is 3 μm, the off-voltage power per 1 μm of channel width Flow 10 at room temperature^-21Less than A, or 10^-24Can be less than A.

0107Oxide semiconductor films with less oxygen deficiency are electron spin resonance (ESR: Electron Sp). in Resonance), an oxide semiconductor that does not have a signal due to oxygen deficiency It is a membrane. Specifically, the spin density due to oxygen deficiency is 5 × 10.¹⁶spins / c m³Less than an oxide semiconductor film. If the oxide semiconductor film has oxygen deficiency, ESR A signal with symmetry appears in the vicinity of g value 1.93.

0108The underlying insulating film 102 preferably has sufficient flatness. Specifically, the average surface roughness (R) a) is 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. .. By setting Ra to be less than or equal to the above value, an oxide semiconductor film 106 having a high degree of crystallinity can be provided. Can be done. In addition, the unevenness at the interface between the underlying insulating film 102 and the oxide semiconductor film 106 is small. Therefore, the influence of interfacial scattering can be reduced. Ra is JIS B 0601: 2 Apply the arithmetic mean roughness defined in 001 (ISO4287: 1997) to curved surfaces It is expanded to three dimensions so that it can be done, and "the absolute value of the deviation from the reference plane to the designated plane is averaged. It can be expressed by "value" and is defined by mathematical formula (17).

0109<maths num="17"><img id="000018" he="14" wi="83" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0110Here, the designated surface is a surface to be measured for roughness, and the coordinates (x).₁, y₁, f (x₁, y₁)), (x₁, y₂, f (x₁, y₂)), (x₂, y₁, f (x₂, y₁)), (x₂, y₂, f (x₂, y₂)) Make a quadrilateral area represented by 4 points, and set the designated surface to the xy plane. The area of the projected rectangle is S₀, Z the height of the reference plane (average height of the designated plane)₀And. Ra Is evaluated by Atomic Force Microscope (AFM) It is worthy.

0111The underlying insulating film 102 is preferably an insulating film containing excess oxygen.

0112The insulating film containing excess oxygen is TDS (Thermal Desorption Spec). troscopy: Oxygen released by temperature desorption gas spectroscopy) Converted to oxygen atoms 1x10¹⁸atoms / cm³Above, 1x10¹⁹atoms / cm³Above or 1 × Ten²⁰atoms / cm³The above is the insulating film.

0113Here, a method for measuring the amount of oxygen released using TDS analysis will be described below.

0114The total amount of gas released during TDS analysis is proportional to the integral value of the ionic strength of the released gas. So Then, by comparing this integral value with the standard sample, the total amount of gas released can be calculated.

0115For example, TDS analysis results of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and From the TDS analysis results of the insulating film, the amount of oxygen molecules released from the insulating film (N)_O2) Is the formula (18) Can be obtained at. Here, all of the gases detected by the mass number 32 obtained by TDS analysis It is assumed that they are derived from oxygen molecules. Another CH as one with a mass number of 32₃There is OH, but it exists It is not considered here as it is unlikely to be done. Also, the mass number, which is an isotope of oxygen atom Oxygen molecules containing 17 oxygen atoms and 18 mass number oxygen atoms are also found in nature. Not considered because the abundance ratio is extremely small.

0116<maths num="18"><img id="000019" he="14" wi="88" file="JP6286009B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0117N_H2Is the value obtained by converting the hydrogen molecules desorbed from the standard sample by the density. S_H2Is a standard trial It is the integral value of the ionic strength when the material is analyzed by TDS. Here, the reference value of the standard sample is N_H2/ S_H2And. S_O2Is the integral value of the ionic strength when the insulating film is TDS analyzed. To. α is a coefficient that affects the ionic strength in TDS analysis. In the details of formula (18) For reference, refer to JP-A-6-275697. The amount of oxygen released from the insulating film is , Standard sample using EMD-WA1000S / W thermal desorption analyzer manufactured by Electronic Science Co., Ltd. As 1x10¹⁶atoms / cm²Measured using a silicon wafer containing hydrogen atoms Ta.

0118Also, in TDS analysis, some of the oxygen is detected as oxygen atoms. Oxygen molecule and oxygen source The ratio of offspring can be calculated from the ionization rate of oxygen molecules. The above α is the oxygen content. Since it contains the ionization rate of the child, the amount of oxygen atom released can be determined by evaluating the amount of oxygen molecule released. Even so, it can be estimated.

0119In addition, N_O2Is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the oxygen molecule. It is twice the amount released.

0120Alternatively, the insulating film containing excess oxygen may be an insulating film containing radical peroxides. concrete Has a spin density of 5 × 10 due to radical peroxides.¹⁷spins / cm³More than It is an insulating film. In addition, the insulating film containing radical peroxide has a g value of around 2.01 in ESR. It is an insulating film having an asymmetric signal.

0121Alternatively, the insulating film containing excess oxygen is silicon oxide (SiO) containing excess oxygen._X(X&gt; 2)) There may be. Silicon oxide with excess oxygen (SiO)_X(X&gt; 2)) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume. Silicon source per unit volume The number of children and the number of oxygen atoms are values measured by the Rutherford backscattering method.

0122The underlying insulating film 102 includes aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, One or more of materials containing lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide It may be selected above and used in a single layer or in a laminated manner. Also, in addition to the single layer or lamination described above , Silicon nitride oxide and silicon nitride may be laminated.

0123Silicon oxynitride shows a higher oxygen content than nitrogen in its composition. In addition, silicon nitride shows a content of nitrogen higher than oxygen in its composition. ..

0124Further, the gate insulating film 112 is preferably an insulating film containing excess oxygen.

0125The gate insulating film 112 includes aluminum oxide, magnesium oxide, silicon oxide, and nitriding silicon oxide. Recon, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, oxidation Contains zirconium, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide One or more materials may be selected and used in a single layer or in a laminated manner.

0126Excess oxygen contained in at least one of the underlying insulating film 102 and the gate insulating film 112 , Oxygen contained beyond the stoichiometric composition of the material. Therefore, excess oxygen causes heat and other factors. It has the property of releasing energy when given. Excess oxygen is excess for stoichiometric composition Because it is contained in, even if it is lost by releasing it, it may deteriorate the film quality. Absent.

0127For example, the oxygen deficiency of the oxide semiconductor film 106 can be removed from the underlying insulating film 102 and the gate insulating film 11. It can be reduced by oxygen supplied from any of 2. That is, the oxide semiconductor film Negative shift of transistor threshold voltage by reducing 106 oxygen deficiency Can be suppressed. For that purpose, at least the base insulating film and the gate insulating film are used. An insulating film containing excess oxygen may be used instead.

0128The oxide semiconductor film 106 is sandwiched between the underlying insulating film 102 and the gate insulating film 112 and heated. By performing the treatment, the oxygen released from the underlying insulating film 102 is efficiently released from the oxide semiconductor film 1 Can be supplied to 06. In addition, the heat treatment is performed at a temperature of 250 ° C or higher and 550 ° C or lower. In addition to supplying oxygen to the oxide semiconductor film 106, the oxide semiconductor film 106, below The hydrogen concentration of the ground insulating film 102 and the gate insulating film 112 can be reduced.

0129However, due to the heat treatment, either the underlying insulating film 102 or the gate insulating film 112 is formed. The excess oxygen contained may be lost. Reduce fluctuations in the electrical characteristics of transistors From the viewpoint of this, either the underlying insulating film 102 or the gate insulating film 112 is used even after the heat treatment. Preferably contains excess oxygen.

0130The substrate 100 is not significantly limited, but at least has heat resistance sufficient to withstand the subsequent heat treatment. Must be done. For example, glass substrate, ceramic substrate, quartz substrate, sapphire substrate Etc. may be used as the substrate 100. Also, single crystal half such as silicon and silicon carbide Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI ( Silicon On Insulator) It is also possible to apply a substrate, etc. A semiconductor element provided on these substrates may be used as the substrate 100.

0131In addition, as the substrate 100, the 5th generation (1000 mm x 1200 mm or 1300 mm x 1500mm), 6th generation (1500mm x 1800mm), 7th generation (1870mm x) 2200mm), 8th generation (2200mm x 2500mm), 9th generation (2400mm x 2400mm) For large glass substrates such as 2800 mm) and 10th generation (2880 mm x 3130 mm) If so, due to the shrinkage of the substrate 100 caused by heat treatment in the manufacturing process of the semiconductor device. Therefore, fine processing may become difficult. Therefore, a large glass substrate as described above is used as a substrate. When used as 100, it is preferable to use one having a small shrinkage due to heat treatment. Example For example, the substrate 100 is 400 ° C, preferably 450 ° C, and more preferably 500 ° C. The amount of shrinkage after heat treatment at temperature for 1 hour is 10 ppm or less, preferably 5 ppm or less. More preferably, a large glass substrate having a concentration of 3 ppm or less may be used.

0132Further, a flexible substrate may be used as the substrate 100. In addition, a tran on a flexible substrate As a method of providing a gista, after making a transistor on a non-flexible substrate, a transistor is provided. There is also a method of peeling off the gista and transposing it onto the substrate 100, which is a flexible substrate. In that case, A release layer may be provided between the non-flexible substrate and the transistor.

0133The gate electrode 104 includes Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, and T. Elemental substances, nitrides, oxides or alloys containing one or more of a and W, either in a single layer or in a laminate You can use it.

0134The interlayer insulating film 118 includes aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, Silicon Oxidation, Silicon Nitride, Silicon Nitride, Germanium Oxide, Oxidation Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more of the materials containing tantalum oxide may be selected and used in a single layer or in a laminated manner.

0135The interlayer insulating film 118 preferably has a low relative permittivity and a sufficient thickness. example For example, using a silicon oxide film with a relative permittivity of about 3.8, 200 nm or more and 1000 nm or more. It may be provided with the thickness below. The upper surface of the interlayer insulating film 118 is slightly fixed due to the influence of atmospheric components and the like. It has an electric charge, and the threshold voltage of the transistor may fluctuate due to its influence. That Therefore, the interlayer insulating film 118 has a ratio within a range in which the influence of the electric charge generated on the upper surface is sufficiently small. It is preferably the dielectric constant and the thickness. Polyimide on the interlayer insulating film 118 for the same reason By forming a resin film such as silicon resin, acrylic resin, epoxy resin, silicone resin, etc. The influence of the electric charge generated on the upper surface of the interlayer insulating film 118 may be reduced.

0136Wiring 136 includes Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and Elementary substances, nitrides, oxides or alloys containing one or more watts can be used in single layers or in layers. Just do it.

0137In addition, for a transistor having a structure different from that shown in FIG. 1, use FIG. explain.

0138FIG. 2A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 2 (A) A cross-sectional view corresponding to the chain lines B1-B2 is shown in FIG. 2 (B). In addition, the alternate long and short dash line shown in Fig. 2 (A) A cross-sectional view corresponding to B3-B4 is shown in FIG. 2 (C). For ease of explanation, Fig. 2 ( In A), the underlying insulating film 102 and the like are omitted.

0139Figure 2 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. Area to do. At least a part of the two sides of the oxide semiconductor film 106 is a gate electrode. Superimpose with 104.

0140The transistor shown in Fig. 2 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0141The transistor shown in FIG. 2 (A) has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0142FIG. 2B shows the underlying insulating film 102 provided on the substrate 100 and the underlying insulating film 102. The oxide semiconductor film 106 and the gate insulating film 1 provided on the oxide semiconductor film 106 12 and a game located on the gate insulating film 112 and superimposed on the oxide semiconductor film 106. On the electrode 104, the underlying insulating film 102, the oxide semiconductor film 106, and the gate electrode 104. It has a barrier film 108 having an opening that reaches the oxide semiconductor film 106, which is provided. It is a cross-sectional structure of a transistor.

0143In addition, in FIG. 2 (B), the oxidation provided on the oxide semiconductor film 106 and the gate electrode 104. An interlayer insulating film 118 having an opening reaching the semiconductor film 106 and an opening of the interlayer insulating film 118. The wiring 136 provided in contact with the oxide semiconductor film 106 via the portion is shown.

0144The transistors shown in FIG. 2 include an underlying insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 provided on 104 and having an opening reaching the oxide semiconductor film 106 It differs from the transistor shown in FIG. 1 only in that it has. Therefore, for other configurations, The description of FIG. 1 can be referred to.

0145The barrier film 108 is an insulating film having low oxygen permeability. Specifically, 350 ° C, 1 hour addition It is an insulating film having the property of not allowing oxygen to permeate by heat treatment.

0146The barrier film 108 is composed of aluminum oxide, aluminum nitride, magnesium oxide, and an oxide gel. Manium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, clam oxide Select one or more of the materials containing funium and tantalum pentoxide for single layer or laminated I just need to be there. Preferably, an aluminum oxide film is used.

0147The transistors shown in FIG. 2 include an underlying insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 provided on 104 and having an opening reaching the oxide semiconductor film 106 Excess oxygen contained in either the underlying insulating film 102 or the gate insulating film 112 It is possible to suppress the outward diffusion of. Therefore, the underlying insulating film 102 and the gate insulating film 11 The excess oxygen contained in any of 2 can be efficiently supplied to the oxide semiconductor film 106. Wear. That is, the threshold voltage of the transistor is more negative than that of the transistor shown in FIG. The shift in the direction can be suppressed.

0148In addition, a transistor having a structure different from that shown in FIGS. 1 and 2 is shown in FIG. This will be explained using 3.

0149FIG. 3A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 3 (A) A cross-sectional view corresponding to the chain lines C1-C2 is shown in FIG. 3 (B). In addition, the alternate long and short dash line shown in Fig. 3 (A) A cross-sectional view corresponding to C3-C4 is shown in FIG. 3 (C). For ease of explanation, Fig. 3 ( In A), the underlying insulating film 102 and the like are omitted.

0150FIG. 3 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. Area to do. At least a part of the two sides of the oxide semiconductor film 106 is a gate electrode. Superimpose with 104.

0151The transistor shown in Fig. 3 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0152In addition, the transistor shown in FIG. 3 (A) has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0153FIG. 3B shows the underlying insulating film 102 provided on the substrate 100 and the underlying insulating film 102. The oxide semiconductor film 106 and the first layer 132 provided on the oxide semiconductor film 106 On the gate insulating film 132, including a and the second layer 132b, and on the gate insulating film 132, A transistor having a gate electrode 104 provided on top of the oxide semiconductor film 106. It is a cross-sectional structure of. The first layer 132a is an oxide semiconductor film more than the second layer 132b. It is provided on the 106 side.

0154In addition, in FIG. 3 (B), the oxidation provided on the oxide semiconductor film 106 and the gate electrode 104. An interlayer insulating film 118 having an opening reaching the semiconductor film 106 and an opening of the interlayer insulating film 118. The wiring 136 provided in contact with the oxide semiconductor film 106 via the portion is shown.

0155The transistor shown in FIG. 3 replaces the gate insulating film 112 with the first layer 132a and the second layer. It differs from the transistor shown in FIG. 1 only in that it has a gate insulating film 132 including the layer 132b of the above. To. Therefore, for other configurations, the description of FIG. 1 can be referred to.

0156Here, the first layer 132a is an insulating film containing excess oxygen.

0157The first layer 132a is composed of aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, Silicon Oxidation, Silicon Nitride, Silicon Nitride, Germanium Oxide, Oxidation Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more of the materials containing tantalum oxide may be selected and used in a single layer or in a laminated manner.

0158The second layer 132b is an insulating film having low oxygen permeability. Specifically, 350 ° C, 1 It is an insulating film having the property of not allowing oxygen to permeate due to heat treatment for a long time.

0159The second layer 132b contains aluminum oxide, aluminum nitride, magnesium oxide, and metal oxide. Lumanium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxidation Select one or more of the materials containing hafnium and tantalum pentoxide, either in a single layer or in a laminate You can use it. Preferably, an aluminum oxide film is used.

0160As shown in FIG. 3C, the oxide semiconductor film 10 is located in the region overlapping the gate electrode 104. A first layer 132a is provided in contact with the side surface of 6. Therefore, it overlaps with the gate electrode 104. Oxygen is supplied from the first layer 132a to the side surface of the oxide semiconductor film 106 in the region. be able to. In addition, a second layer 132b is provided so as to cover the first layer 132a. Therefore, oxygen can be efficiently supplied from the first layer 132a.

0161Parasitic channels are formed on the side surface of the oxide semiconductor film due to the nature of the side surface of the oxide semiconductor film. May be made. Parasitic channels have a higher threshold than the original channel of the transistor The voltage is often low. Therefore, when the influence of parasitic channels becomes large, it is as if it were a tran. It looks as if the threshold voltage of the gista has shifted in the negative direction. This is an oxide semiconductor film This is because carriers are easily generated. Therefore, with respect to the side surface of the oxide semiconductor film It is important to supply more oxygen from the outside than to other surfaces.

0162The effects of parasitic channels can be significant on short-channel transistors, as they can be significant. For miniaturized transistors, it is effective to adopt the structure shown in Fig. 3. To.

0163The transistor shown in FIG. 3 has an oxide semiconductor film 1 in a region overlapping with the gate electrode 104. Parasitic channels are unlikely to form on the sides of 06. That is, it is better than the transistor shown in Fig. 1. In addition, it is possible to suppress the negative shift of the threshold voltage of the transistor.

0164Further, a transistor having a structure different from that shown in FIGS. 1 to 3 is shown in FIG. Will be described with reference to.

0165FIG. 4A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 4 (A) A cross-sectional view corresponding to the chain lines D1-D2 is shown in FIG. 4 (B). In addition, the alternate long and short dash line shown in Fig. 4 (A) A cross-sectional view corresponding to D3-D4 is shown in FIG. 4 (C). For ease of explanation, Fig. 4 ( In A), the underlying insulating film 102 and the like are omitted.

0166FIG. 4 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. Area to do. At least a part of the two sides of the oxide semiconductor film 106 is a gate electrode. Superimpose with 104.

0167The transistor shown in Fig. 4 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0168The transistor shown in FIG. 4 (A) has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0169FIG. 4B shows the underlying insulating film 102 provided on the substrate 100 and the underlying insulating film 102. The oxide semiconductor film 106 and the first layer 132 provided on the oxide semiconductor film 106 On the gate insulating film 132, including a and the second layer 132b, and on the gate insulating film 132, A gate electrode 104 provided on top of the oxide semiconductor film 106, an underlying insulating film 102, and an acid. Reaching the oxide semiconductor film 106 provided on the compound semiconductor film 106 and the gate electrode 104 It is a cross-sectional structure of a transistor having a barrier film 108 having an opening to be formed. In addition, it should be noted The first layer 132a is provided on the oxide semiconductor film 106 side of the second layer 132b.

0170In addition, in FIG. 4 (B), the oxidation provided on the oxide semiconductor film 106 and the gate electrode 104. An interlayer insulating film 118 having an opening reaching the semiconductor film 106 and an opening of the interlayer insulating film 118. The wiring 136 provided in contact with the oxide semiconductor film 106 via the portion is shown.

0171The transistors shown in FIG. 4 include an underlying insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 provided on 104 and having an opening reaching the oxide semiconductor film 106 It is similar to the transistor shown in FIG. 2 in that it has. In addition, the transistor shown in Fig. 4 is Gate insulating including a first layer 132a and a second layer 132b instead of the insulating film 112 It is similar to the transistor shown in FIG. 3 in that it has a film 132. Therefore, the tran shown in FIG. For the configuration of the gista, the description of FIGS. 1 to 3 can be referred to.

0172The transistors shown in FIG. 4 include an underlying insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 provided on 104 and having an opening reaching the oxide semiconductor film 106 To have excess oxygen contained in either the underlying insulating film 102 or the first layer 132a External diffusion can be suppressed. Therefore, of the underlying insulating film 102 and the first layer 132a Excess oxygen contained in any of them can be efficiently supplied to the oxide semiconductor film 106. .. That is, it is possible to suppress the shift of the threshold voltage of the transistor in the negative direction.

0173Further, as shown in FIG. 4 (C), the oxide semiconductor in the region overlapping with the gate electrode 104. The first layer 132a is provided in contact with the side surface of the film 106. Therefore, it overlaps with the gate electrode 104. Oxygen is supplied from the first layer 132a to the side surface of the oxide semiconductor film 106 in the area to be folded. Can be paid. Further, a second layer 132b is provided so as to cover the first layer 132a. As a result, oxygen can be efficiently supplied from the first layer 132a.

0174Therefore, the transistor shown in FIG. 4 has an oxide in the region where it overlaps with the gate electrode 104. Parasitic channels are unlikely to be formed on the side surface of the semiconductor film 106. That is, the threshold value of the transistor It is possible to suppress the shift of the voltage in the negative direction.

0175As shown above, even when the channel length is small (5 nm or more and less than 60 nm), it is substantially short. As a transistor that does not have a channel effect, it has a large channel width (5 nm or more and 200 n). (Less than m), we propose a transistor using an oxide semiconductor film.

0176In addition, a tiger using an oxide semiconductor film in which the channel width is a constant ratio to the channel length. Propose an engineer.

0177In addition, the threshold voltage shifts in the negative direction due to oxygen deficiency of the oxide semiconductor film 106, and parasitism. We propose a transistor in which the negative shift of the threshold voltage due to the channel is suppressed.

0178From the above, it is possible to provide a transistor that can obtain switching characteristics even if it is miniaturized. Wear.

0179The manufacturing method of the transistor shown in FIG. 4 is shown below with reference to FIGS. 5 and 6. In addition, the figure For the method of manufacturing the transistor shown in FIGS. 1 to 3, the method of manufacturing the transistor shown in FIG. 4 The law may be adopted as appropriate. For ease of explanation, here is a cross-sectional view corresponding to FIG. 4 (B). Show only.

0180First, the substrate 100 is prepared.

0181Next, the underlying insulating film 102 is formed on the substrate 100 (see FIG. 5 (A)). Underlayer insulating film 1 02 is selected from the materials shown as the underlying insulating film 102, and is subjected to the sputtering method and chemical vapor deposition. Long (CVD: Chemical Vapor Deposition) method, molecular beam epitaxy Kissy (MBE: Molecular Beam Epitaxy) method, atomic layer deposition (A) LD: Atomic Layer Deposition) or pulsed laser deposition (LD) The film may be formed using the PLD: Pulsed Laser Deposition) method. ..

0182Here, the underlying insulating film 102 may be dehydrated or dehydrogenated. Dehydration and dehydrogenation The theory can be performed, for example, by heat treatment. Heat treatment temperature is 250 ° C or higher 6 It may be performed at 50 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower. The atmosphere of the heat treatment is Inert gas atmosphere, atmosphere containing 10ppm or more, 1% or more or 10% or more of oxidizing gas Perform with qi or decompression. Alternatively, the heat treatment atmosphere is an inert gas atmosphere. After that, 10ppm or more, 1% or more or 1 of oxidizing gas is added to supplement the desorbed oxygen. The heat treatment may be performed in an atmosphere containing 0% or more. Or, as dehydration and dehydrogenation treatment Plasma treatment, UV treatment or chemical treatment may be performed.

0183Next, oxygen may be added to the underlying insulating film 102 from the upper surface side. Addition of oxygen is Io It may be carried out by the injection method or the ion doping method. In that case, the acceleration voltage is 5kV or more. The upper 100kV or less. In addition, the amount of oxygen added is 1 x 10¹⁴ions / cm²Above 1 × Ten¹⁶ions / cm²It is as follows. Further, it is different from the underlying insulating film 102 from the upper surface side. Oxygen may be added under the following conditions.

0184Alternatively, oxygen can be added by applying a bias voltage to the substrate side in a plasma containing oxygen. You may go. In that case, the bias voltage shall be 10V or more and less than 1kV. Also, bias The voltage application time is 10s or more and 1000s or less, preferably 10s or more and 200s or less. More preferably, it may be 10 s or more and 60 s or less. The higher the bias voltage, the more the bias The longer the voltage is applied, the more oxygen can be added, but at the same time the film etches. You can't ignore it.

0185By adding oxygen, the underlying insulating film 102 can be made into an insulating film containing excess oxygen. However, the method for forming the insulating film containing excess oxygen is not limited to the above-mentioned method. For example, of oxygen Perform in a high-ratio atmosphere and at a substrate temperature of room temperature (about 25 ° C) or higher and 150 ° C or lower. An insulating film containing excess oxygen can also be formed by the putting method. In particular , The ratio of oxidizing gas such as oxygen in the film formation gas is 20% or more, preferably 50% or more. It is preferably 80% or more. The method of forming the insulating film containing excess oxygen is appropriately assembled. Can be matched.

0186The underlying insulating film 102 containing excess oxygen may be formed as described above. However, the real thing The form of application is not limited to the case where the underlying insulating film 102 contains excess oxygen.

0187Since the underlying insulating film 102 preferably has sufficient flatness, the underlying insulating film 102 is compared with the underlying insulating film 102. , Flattening treatment may be performed. As a flattening process, chemical mechanical polishing (CMP: Chemi) Use cal Mechanical Polishing) or dry etching method I just need to be there. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less. The underlying insulating film 102 is provided so as to be 0.1 nm or less, more preferably 0.1 nm or less.

0188Next, an oxide semiconductor film is formed. The oxide semiconductor film is shown as the oxide semiconductor film 106. Select from the selected materials and use the sputtering method, CVD method, MBE method, ALD method or PLD method. It may be used to form a film. The oxide semiconductor film is preferably formed by a sputtering method. To. At this time, the oxidizing gas such as oxygen is 5% or more, preferably 10% or more, more preferably. Uses a film-forming gas containing 20% or more, more preferably 50% or more. As the film forming gas, Use a gas with a low impurity concentration such as hydrogen.

0189After forming the oxide semiconductor film, the first heat treatment may be performed. The temperature of the first heat treatment is 2 It may be performed at 50 ° C or more and 650 ° C or less, preferably 300 ° C or more and 500 ° C or less. First addition The atmosphere of the heat treatment is an inert gas atmosphere, an oxidizing gas of 10 ppm or more, 1% or more, or Perform in an atmosphere containing 10% or more or in a reduced pressure state. Or, the atmosphere of the first heat treatment is not good After heat treatment in an active gas atmosphere, 10 ppm of oxidizing gas is added to supplement the desorbed oxygen. As mentioned above, the heat treatment may be performed in an atmosphere containing 1% or more or 10% or more. First heat treatment Therefore, impurities such as hydrogen and water can be removed from the oxide semiconductor film.

0190Next, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107 (Fig. 5 (B). )reference. ).

0191Next, the first layer 133a is formed. The first layer 133a is shown as the first layer 132a Select from the selected materials and use the sputtering method, CVD method, MBE method, ALD method or PLD method. It may be used to form a film.

0192Here, the first layer 133a may be dehydrated or dehydrogenated. Dehydration and dehydrogenation The theory can be performed, for example, by heat treatment. Heat treatment temperature is 250 ° C or higher 6 It may be performed at 50 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower. The atmosphere of the heat treatment is Inert gas atmosphere, atmosphere containing 10ppm or more, 1% or more or 10% or more of oxidizing gas Perform with qi or decompression. Alternatively, the heat treatment atmosphere is an inert gas atmosphere. After that, 10ppm or more, 1% or more or 1 of oxidizing gas is added to supplement the desorbed oxygen. The heat treatment may be performed in an atmosphere containing 0% or more. Or, as dehydration and dehydrogenation treatment Plasma treatment, UV treatment or chemical treatment may be performed.

0193Next, oxygen may be added to the first layer 133a from the upper surface side. Addition of oxygen is Io It may be carried out by the injection method or the ion doping method. In that case, the acceleration voltage is 5kV or more. The upper 100kV or less. In addition, the amount of oxygen added is 1 x 10¹⁴ions / cm²Above 1 × Ten¹⁶ions / cm²It is as follows. Further, it is different from the first layer 133a from the upper surface side. Oxygen may be added under the following conditions.

0194Alternatively, oxygen can be added by applying a bias voltage to the substrate side in a plasma containing oxygen. You may go. In that case, the bias voltage shall be 10V or more and less than 1kV. Also, bias The voltage application time is 10s or more and 1000s or less, preferably 10s or more and 200s or less. More preferably, it may be 10 s or more and 60 s or less.

0195By adding oxygen, the first layer 133a can be made into an insulating film containing excess oxygen. .. However, the method for forming the insulating film containing excess oxygen is not limited to the above-mentioned method. For example, oxygen Sputtering performed in an atmosphere with a high proportion of, and at a substrate temperature of room temperature or higher and 150 ° C or lower. An insulating film containing excess oxygen can also be formed by the method. Specifically, the proportion of oxygen It may be 20% or more, preferably 50% or more, and more preferably 80% or more. Over The methods for forming the insulating film containing excess oxygen can be appropriately combined.

0196As described above, the first layer 133a containing excess oxygen may be formed. However, the real thing The form of application is not limited to the case where the first layer 133a contains excess oxygen.

0197Next, the second layer 133b is formed. The second layer 133b is shown as the second layer 132b. Select from the selected materials and use the sputtering method, CVD method, MBE method, ALD method or PLD method. It may be used to form a film.

0198Next, the conductive film 105 is formed (see FIG. 5C). The conductive film 105 is a gate electrode 10. Select from the materials shown as 4, sputtering method, CVD method, MBE method, ALD method or May be formed by using the PLD method.

0199Next, the conductive film 105 is processed to form the gate electrode 104.

0200Next, use the gate electrode 104 as a mask, or use a mask for processing the gate electrode 104. The second layer 133b and the first layer 133a are processed using the second layer 132b and the second layer. A gate insulating film 132 including the layer 132a of 1 is formed (see FIG. 6 (A)).

0201Next, impurities are added to the oxide semiconductor film 107 using the gate electrode 104 as a mask. .. Impurities include helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, and a. Selected from Lugon, Arsenic, Krypton, Indium, Tin, Antimony and Xenon Only one or more may be added. The method of adding impurities is the ion implantation method and the ion doping method. Just do it. At that time, the acceleration voltage is set to 5 kV or more and 100 kV or less. Also, the addition of impurities The amount is 1 x 10¹⁴ions / cm²Above 1 × 10¹⁶ions / cm²It is as follows. So After that, heat treatment may be performed.

0202The oxide semiconductor film 107 is partially formed by adding (and heat-treating) the above-mentioned impurities. Reduces resistance. Here, the region where the resistance is reduced is the region 106b, and the region where the resistance is not reduced is the region 106b. The region 106a is used, and the oxide semiconductor film 106 is used in total.

0203In the present embodiment, after the gate insulating film 132 is formed, the oxide semiconductor film 107 is not formed. The method of adding a pure product is described, but the method is not limited to this. For example, the gate electrode After forming 104, the oxide semiconductor is passed through the second layer 133b and the first layer 133a. Impurities may be added to the membrane 107. Via the second layer 133b and the first layer 133a By doing so, it is possible to prevent damage to the oxide semiconductor film 107.

0204Next, the barrier film 108 is formed (see FIG. 6 (B)). The barrier film 108 is the barrier film 1 Select from the materials shown as 08, including sputtering method, CVD method, MBE method, ALD method. Alternatively, the film may be formed using the PLD method.

0205After the barrier film 108 is formed, a second heat treatment is performed. By the second heat treatment, the base Oxygen can be released from the insulating film 102 and / and the gate insulating film 132. Release The emitted oxygen is supplied to the oxide semiconductor film 106, and oxygen deficiency can be reduced. In addition, the influence of parasitic channels can be reduced. The second heat treatment is the first heat treatment It may be performed under the same conditions as.

0206The second heat treatment may be performed at any time after the barrier film 108 is formed. Also, It is not necessary to perform the second heat treatment.

0207As described above, the transistor shown in FIG. 4 can be manufactured.

0208In the transistor shown in FIG. 4, the oxide semiconductor film 106 has few oxygen deficiencies and is a parasitic channel. The effect is small, and switching characteristics can be obtained even if the size is reduced.

0209Next, an interlayer insulating film 118 is formed on the barrier film 108. The interlayer insulating film 118 is provided with interlayer insulation. Select from the materials shown as film 118, sputtering method, CVD method, MBE method, ALD The film may be formed by the method or the PLD method.

0210Next, openings are provided in the interlayer insulating film 118 and the barrier film 108, and the oxide semiconductor film 106 is formed. Be exposed.

0211Next, a conductive film to be the wiring 136 is formed. The conductive film to be the wiring 136 is the wiring 136. Select from the materials shown in the above, sputtering method, CVD method, MBE method, ALD method or PL The film may be formed using the D method.

0212Next, the conductive film to be the wiring 136 is processed to form the wiring 136 (see FIG. 6 (C)). ..

0213According to the present embodiment, a transistor capable of obtaining switching characteristics even when miniaturized is provided. be able to. Further, to provide a semiconductor device having a high degree of integration using the transistor. Can be done.

0214In addition, this embodiment can be used in combination with other embodiments as appropriate.

0215(Embodiment 2) In the present embodiment, a transistor having a structure different from that of the first embodiment will be described.

0216FIG. 7A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 7 (A) A cross-sectional view corresponding to the chain lines E1-E2 is shown in FIG. 7 (B). In addition, the alternate long and short dash line shown in Fig. 7 (A) A cross-sectional view corresponding to E3-E4 is shown in FIG. 7 (C). For ease of explanation, Fig. 7 ( In A), the underlying insulating film 202 and the like are omitted.

0217FIG. 7 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 204 in the oxide semiconductor film 206. Area to do. At least two sides of the oxide semiconductor film 206 are gate electrodes 204. Superimpose with.

0218The transistor shown in Fig. 7 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0219The transistor shown in FIG. 7 (A) has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0220FIG. 7B shows the underlying insulating film 202 provided on the substrate 200 and the underlying insulating film 202. A pair of the oxide semiconductor film 206 provided on the same plane as the oxide semiconductor film 206. Electrode 216, gate insulating film 212 provided on oxide semiconductor film 206, and gate termination A gate electrode 204 located on the edge film 212 and superposed on the oxide semiconductor film 206, It is a cross-sectional structure of a transistor having.

0221Note that FIG. 7B shows the oxide semiconductor film 206, the pair of electrodes 216, and the gate electrode 204. An interlayer insulating film 218 having an opening reaching a pair of electrodes 216 and interlayer insulation provided in The wiring 236 provided in contact with the pair of electrodes 216 through the opening of the film 218 is shown.

0222The material of the substrate 200 may be selected from the same materials as those of the substrate 100.

0223The underlying insulating film 202 may be selected from the same materials as the underlying insulating film 102.

0224The gate electrode 204 may be used by selecting from the same materials as the gate electrode 104.

0225The gate insulating film 212 may be selected and used from the same materials as the gate insulating film 112. Na The gate insulating film 212 may be provided as a layer structure similar to that of the gate insulating film 132.

0226The oxide semiconductor film 206 may be selected and used from the same materials as the oxide semiconductor film 106. ..

0227The interlayer insulating film 218 may be selected from the same materials as the interlayer insulating film 118.

0228The wiring 236 may be used by selecting from the same materials as the wiring 136.

0229The pair of electrodes 216 are Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T. Elemental substances, nitrides, oxides or alloys containing one or more of a and W, either in a single layer or in a laminate You can use it.

0230Although not shown, the underlying insulating film 202, the pair of electrodes 216, the oxide semiconductor film 206, and the game A barrier film may be provided on the electrode 204. Is the barrier film the same material as the barrier film 108? It may be selected and used, and has the same function as the barrier film 108.

0231Therefore, the transistor shown in FIG. 7 is different from the transistor shown in FIGS. 1 to 4 in oxide semiconductivity. It differs only in the shape of the body membrane 206 and in having a pair of electrodes 216. Therefore, that For the configuration, the description of FIGS. 1 to 4 can be referred to.

0232The transistor shown in FIG. 7 is the transistor shown in FIG. 1 of the oxide semiconductor film 106. The structure has a pair of electrodes 216 instead of the region 106b. Therefore, in the first embodiment The resistance of the source and drain can be reduced as compared with the shown transistor. That Therefore, it is possible to provide a transistor having high on-characteristics even if it is miniaturized.

0233The method for manufacturing the transistor shown in FIG. 7 is shown below with reference to FIG. To facilitate the explanation Therefore, only the cross-sectional view corresponding to FIG. 7 (B) is shown here.

0234First, the substrate 200 is prepared.

0235Next, the underlying insulating film 202 is formed on the substrate 200. The underlying insulating film 202 is the underlying insulating film 1 It may be formed using the same materials and methods as in 02.

0236Next, a conductive film to be a pair of electrodes 216 is formed. The conductive film that becomes the pair of electrodes 216 is one. Select from the materials shown as paired electrodes 216, sputtering method, CVD method, MBE method, The film may be formed using the ALD method or the PLD method.

0237Next, a conductive film to be a pair of electrodes 216 is processed to have an opening for exposing the underlying insulating film 202. The conductive film 217 is formed.

0238Next, the oxide semiconductor film 207 is formed (see FIG. 8 (A)). Oxide semiconductor film 207 , The film may be formed using the material and method shown as the oxide semiconductor film 106.

0239After forming the oxide semiconductor film 207, the first heat treatment may be performed. The first heat treatment is actually See Form 1 of the application.

0240Next, the oxide semiconductor film 207 and the conductive film 217 are flattened. Flattening The reason is that CMP processing may be used. By the flattening treatment, the opening of the conductive film 217 Only an oxide semiconductor film is provided.

0241Next, an oxide semiconductor film provided only in the opening of the conductive film 217 and the conductive film 217 are added. It is processed and formed into an island shape to form an oxide semiconductor film 206 and a pair of electrodes 216 (Fig. 8 (B). )reference. ).

0242Next, the gate insulating film 212 and the gate electrode 204 on the gate insulating film 212 are formed. (See Figure 8 (C).). The gate insulating film 212 is the gate insulating film 112 or the gate insulating film. It may be formed using the same materials and methods as in 132. The gate electrode 204 is a gate electrode. It may be formed using the same materials and methods as pole 104.

0243Next, a barrier film may be formed. The barrier film is made of the same material and method as the barrier film 108. The film may be formed using.

0244As described above, the transistor shown in FIG. 7 can be manufactured.

0245In the transistor shown in FIG. 7, the oxide semiconductor film 206 has few oxygen deficiencies and is a parasitic channel. The effect is small, and switching characteristics can be obtained even if the size is reduced. Also, a pair of electrodes 2 By having 16, it is possible to make a transistor with excellent on-characteristics even if it is miniaturized. Wear.

0246Next, the interlayer insulating film 218 is formed. The interlayer insulating film 218 is made of the same material as the interlayer insulating film 118. The film may be formed using a material and a method.

0247Next, an opening is provided in the interlayer insulating film 218 to expose the pair of electrodes 216.

0248Next, the wiring 236 is formed. Wiring 236 uses the same materials and methods as Wiring 136. (See Fig. 8 (D)).

0249According to this embodiment, switching characteristics can be obtained even if the size is reduced, and the on characteristics are excellent. Langista can be provided. In addition, a semi-conduct with a high degree of integration using the transistor Body equipment can be provided.

0250In addition, this embodiment can be used in combination with other embodiments as appropriate.

0251(Embodiment 3) In the present embodiment, the transistor has a structure different from that of the first and second embodiments. I will explain.

0252FIG. 9A is a top view of the transistor according to one aspect of the present invention. One point shown in Fig. 9 (A) A cross-sectional view corresponding to the chain lines F1-F2 is shown in FIG. 9 (B). In addition, the alternate long and short dash line shown in Fig. 9 (A) A cross-sectional view corresponding to F3-F4 is shown in FIG. 9 (C). For ease of explanation, Fig. 9 ( In A), the underlying insulating film 302 and the like are omitted.

0253FIG. 9 (A) shows the channel length (L) and channel width (W) of the transistor. In addition, it should be noted The channel region of the transistor overlaps with the gate electrode 304 in the oxide semiconductor film 306. Area to do. At least two sides of the oxide semiconductor film 306 are gate electrodes 304. Superimpose with.

0254The transistor shown in Fig. 9 (A) has a channel length of 5 nm or more and less than 60 nm and a channel. The width is 5 nm or more and less than 200 nm.

0255The transistor shown in FIG. 9A has a channel width of 0.5 times or more the channel length. It is less than 10 times the top.

0256FIG. 9B shows the underlying insulating film 302 provided on the substrate 300 and the underlying insulating film 302. With the oxide semiconductor film 306 having the first region 306a and the second region 306b , On the gate insulating film 312 provided on the oxide semiconductor film 306 and on the gate insulating film 312 Yes, the gate electrode 304 provided on top of the oxide semiconductor film 306 and the gate electrode 30 4 In contact with the insulating film 320 provided on the gate electrode 304 and the side surface of the insulating film 320. An oxide semiconductor film 3 provided on the provided side wall insulating film 310 and the oxide semiconductor film 306. A pair of electrodes 316 provided in contact with the second region 306b of 06 and the side wall insulating film 310. An interlayer insulating film 31 provided on the pair of electrodes 316 and having the same height as the insulating film 320 on the upper surface. It is sectional drawing of the transistor which has 8 and.

0257In addition, in FIG. 9B, the interlayer insulating film provided on the interlayer insulating film 318 and the insulating film 320 is shown. Reaching 328 and a pair of electrodes 316 provided on the interlayer insulating film 318 and the interlayer insulating film 328 The wiring 336 provided in contact with the pair of electrodes 316 is shown through the opening.

0258In FIG. 9B, the gate electrode 304 and the insulating film 320 have the same top surface shape. Also, The gate insulating film 312 has the same upper surface shape as the gate electrode 304 and the side wall insulating film 310. To.

0259The first region 306a of the oxide semiconductor film 306 is a transistor channel region. Works. The second region 306b of the oxide semiconductor film 306 is a transistor saw. Functions as a space and drain area.

0260In the transistor shown in FIG. 9, a pair of electrodes 316 sandwich the side wall insulating film 310 and the gate electrode 3 It is installed near 04. Therefore, reduce the resistance of the source and drain. It is possible to improve the on-characteristics of the transistor.

0261The material of the substrate 300 may be selected from the same materials as those of the substrate 100.

0262The underlying insulating film 302 may be selected from the same materials as the underlying insulating film 102.

0263The gate electrode 304 may be used by selecting from the same materials as the gate electrode 104.

0264The gate insulating film 312 may be selected from the same materials as the gate insulating film 112. Na The gate insulating film 312 may be provided as a layer structure similar to that of the gate insulating film 132.

0265The oxide semiconductor film 306 may be selected and used from the same materials as the oxide semiconductor film 106. ..

0266The side wall insulating film 310 includes aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, Silicon Oxidation, Silicon Nitride, Silicon Nitride, Germanium Oxide, Oxidation Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more of the materials containing tantalum oxide may be selected and used.

0267The insulating film 320 includes aluminum oxide, aluminum nitride, magnesium oxide, and silico oxide. , Silicon Oxidation, Silicon Nitride, Silicon Nitride, Germanium Oxidation, Itt oxide Thorium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxidation One or more of the materials containing tantalum may be selected and used.

0268The pair of electrodes 316 may be selected and used from the same materials as the pair of electrodes 216.

0269The interlayer insulating film 318 may be selected from the same materials as the interlayer insulating film 218.

0270The interlayer insulating film 328 may be selected from the same materials as the interlayer insulating film 218.

0271The wiring 336 may be used by selecting from the same materials as the wiring 136.

0272Although not shown, the underlying insulating film 302, the pair of electrodes 316, the oxide semiconductor film 306, and the insulating film 3 A barrier film may be provided on the 20 and the gate electrode 304. The barrier film is the barrier film 108 It may be selected from the same materials as the above and used, and has the same function as the barrier film 108.

0273The method for manufacturing the transistor shown in FIG. 9 is shown below with reference to FIGS. 10 to 12. Explanation For the sake of simplicity, only the cross-sectional view corresponding to FIG. 9B is shown here.

0274First, the substrate 300 is prepared.

0275Next, the underlying insulating film 302 is formed. The underlying insulating film 302 is the same material as the underlying insulating film 102. The film may be formed using a material and a method.

0276Next, the oxide semiconductor film 307 is formed. The oxide semiconductor film 307 is the oxide semiconductor film 10 It may be formed using the same materials and methods as in 7.

0277Next, the gate insulating film 313 is formed. The gate insulating film 313 is the gate insulating film 112 or May be formed using the same material and method as the gate insulating film 132.

0278Next, the conductive film 305 is formed. The conductive film 305 is shown as a material to be the gate electrode 304. Select from the selected materials, sputtering method, CVD method, MBE method, ALD method or PLD method The film may be formed using.

0279Next, the insulating film 321 is formed (see FIG. 10 (A)). The insulating film 321 is an insulating film 320. Select from the materials shown as, sputtering method, CVD method, MBE method, ALD method or The film may be formed using the PLD method.

0280Next, the insulating film 321 and the conductive film 305 are processed, and the insulating film 322 and the gate electrode 304 are processed. (See Fig. 10 (B)). The insulating film 322 and the gate electrode 304 have the same upper surface. The shape.

0281Next, using the insulating film 322 and the gate electrode 304 as masks, the oxide semiconductor film 307 is impure. Add things. Specifically, as impurities, helium, boron, nitrogen, fluorine, neon, Aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony One or more selected from xenon may be added. The method is the ion implantation method, The ion doping method may be used. The ion implantation method is preferably used. At that time, acceleration power The pressure shall be 5 kV or more and 100 kV or less. In addition, the amount of impurities added is 1 x 10¹⁴ions / cm²Above 1 × 10¹⁶ions / cm²It is as follows. After that, heat treatment may be performed. ..

0282The region to which the impurities are added has a low resistance and becomes a second region 306b. Also, the addition of impurities The region not added is the first region 306a. As described above, the first region 306a And an oxide semiconductor film 306 having a second region 306b is formed (see FIG. 10 (C)). .. ).

0283Next, an insulating film to be the side wall insulating film 310 is formed. The insulating film that becomes the side wall insulating film 310 is on the side. Select from the materials shown as wall insulating film 310, sputtering method, CVD method, MBE method, The film may be formed using the ALD method or the PLD method. Next, an insulating film to be the side wall insulating film 310 By performing an etching process with high anisotropy, the insulating film 322 and the gate electrode 3 A side wall insulating film 310 in contact with the side surface of 04 can be formed.

0284The side wall insulating film 310 is formed, and the gate insulating film 313 is combined with the side wall insulating film 310. The gate electrode 304 is processed as a mask to form the gate insulating film 312 (see Fig. 11 (A)). Teru. ).

0285Next, a conductive film 317 is formed (see FIG. 11 (B)). The conductive film 317 is a pair of electrodes 3 Select from the materials shown as 16 to the sputtering method, CVD method, MBE method, ALD method. Alternatively, the film may be formed using the PLD method.

0286After the conductive film 317 is formed, a second heat treatment is performed. By the second heat treatment, the ground is removed Oxygen can be released from the peripheral film 302 and / and the gate insulating film 312. release The generated oxygen is supplied to the oxide semiconductor film 306, and oxygen deficiency can be reduced. No. The heat treatment of 2 may be performed under the same conditions as the second heat treatment shown in the first embodiment.

0287Further, the second heat treatment is not limited to immediately after the formation of the conductive film 317, but forms the conductive film 317. After that, it may be performed at any time.

0288Next, an interlayer insulating film 319 is formed (see FIG. 11 (C)). The interlayer insulating film 319 is an interlayer. Select from the materials shown as the insulating film 318, sputtering method, CVD method, MBE method, A The film may be formed by using the LD method or the PLD method.

0289Next, flattening treatment (CMP treatment, dry etching treatment, etc.) is performed from the interlayer insulating film 319. Perform to form a pair of electrodes 316, interlayer insulating film 318, sidewall insulating film 310 and insulating film 320. (See Figure 12 (A)).

0290By flattening the interlayer insulating film 319 from above, the insulating film 322 (gate) of the conductive film 317 Only the region overlapping with the electrode 304) can be removed. At that time, the insulating film 322 Is also exposed to the flattening treatment, resulting in a thin insulating film 320.

0291By forming a pair of electrodes 316 using such a method, the pair of electrodes 316 can be formed. It can be provided near the gate electrode 304 with the side wall insulating film 310 interposed therebetween.

0292As described above, the transistor shown in FIG. 9 can be manufactured.

0293In the transistor shown in FIG. 9, the oxide semiconductor film 306 has less oxygen deficiency and is a parasitic channel. The effect is small, and switching characteristics can be obtained even if the size is reduced. Also, a pair of electrodes 3 By having 16, it is possible to make a transistor with excellent on-characteristics even if it is miniaturized. Wear.

0294Next, an interlayer insulating film 328 is formed (see FIG. 12B). The interlayer insulating film 328 is an interlayer. Select from the materials shown as the insulating film 328, sputtering method, CVD method, MBE method, A The film may be formed by using the LD method or the PLD method.

0295Next, the interlayer insulating film 328 and the interlayer insulating film 318 are processed to expose the pair of electrodes 316. Form an opening.

0296Next, the wiring 336 is formed (see FIG. 12 (C)). Wiring 336 is the same as wiring 136 It may be formed using the materials and methods of.

0297According to this embodiment, switching characteristics can be obtained even if the size is reduced, and the on characteristics are excellent. Langista can be provided. In addition, a semi-conduct with a high degree of integration using the transistor Body equipment can be provided.

0298In addition, this embodiment can be used in combination with other embodiments as appropriate.

0299(Embodiment 4) In the present embodiment, the transistor has a structure different from that of the first to third embodiments. I will explain.

0300FIG. 13A is a top view of the transistor according to one aspect of the present invention. Shown in Fig. 13 (A) A cross-sectional view corresponding to the alternate long and short dash line G1-G2 is shown in FIG. 13 (B). In addition, it is shown in FIG. 13 (A). A cross-sectional view corresponding to the alternate long and short dash line G3-G4 is shown in FIG. 13 (C). In addition, it made the explanation easy. Therefore, in FIG. 13 (A), the underlying insulating film 402 and the like are omitted.

0301FIG. 13 (A) shows the channel length (L) and channel width (W) of the transistor. It should be noted that , The channel region of the transistor overlaps with the gate electrode 404 in the oxide semiconductor film 406. This is the area to be folded. At least two sides of the oxide semiconductor film 406 are gate electrodes 40. Superimpose with 4.

0302The transistor shown in Fig. 13 (A) has a channel length of 5 nm or more and less than 60 nm, and a channel. The width is 5 nm or more and less than 200 nm.

0303The transistor shown in FIG. 13 (A) has a channel width 0.5 times that of the channel length. More than 10 times or less.

0304FIG. 13B shows the underlying insulating film 402 provided on the substrate 400 and the underlying insulating film 402. Oxide semiconductor film 406 having a thickness of 1 to 5 times the provided channel width and oxidation The gate insulating film 412 provided on the semiconductor film 406 and the gate insulating film 412. A transistor having a gate electrode 404 provided on top of the oxide semiconductor film 406. It is a cross-sectional structure of.

0305In addition, in FIG. 13 (B), the acid provided on the oxide semiconductor film 406 and the gate electrode 404 Opening of the interlayer insulating film 418 having an opening reaching the compound semiconductor film 406 and the interlayer insulating film 418 The wiring 436 provided in contact with the oxide semiconductor film 406 via the mouth portion is shown.

0306FIG. 13 is a so-called fin type transistor. The fin type transistor is a channel The thick region allows the carrier conduction path to be large, even if the channel width is small. It can be a transistor with excellent on-characteristics.

0307In the case of a fin-type transistor using silicon, the channel region is thick. Therefore, it is difficult to completely turn off the transistor because the depletion layer due to the electric field of the gate does not spread completely. The challenge is what is wrong. On the other hand, fin-type transistors using an oxide semiconductor film have a chi Even if the channel region is thick, the depletion layer due to the electric field of the gate spreads sufficiently, and the transistor can be turned on. You can do it.

0308The material of the substrate 400 may be selected from the same materials as those of the substrate 100.

0309The underlying insulating film 402 may be selected from the same materials as the underlying insulating film 102.

0310The gate electrode 404 may be used by selecting from the same materials as the gate electrode 104.

0311The gate insulating film 412 may be selected and used from the same materials as the gate insulating film 112. Na The gate insulating film 412 may be provided as a layer structure similar to that of the gate insulating film 132.

0312The oxide semiconductor film 406 may be selected and used from the same materials as the oxide semiconductor film 106. .. The thickness of the oxide semiconductor film 406 shall be 100 nm or more and less than 2 μm.

0313The interlayer insulating film 418 may be selected from the same materials as the interlayer insulating film 118.

0314The wiring 436 may be used by selecting from the same materials as the wiring 136.

0315Although not shown, it is mounted on the underlying insulating film 402, the oxide semiconductor film 406, and the gate electrode 404. A rear film may be provided. If the barrier film is selected from the same materials as the barrier film 108, It often has the same function as the barrier film 108.

0316The manufacturing method of the transistor shown in FIG. 13 is shown below with reference to FIG. Make the explanation easier Therefore, only the cross-sectional view corresponding to FIG. 13 (B) is shown here.

0317First, the substrate 400 is prepared.

0318Next, the underlying insulating film 402 is formed on the substrate 400. The underlying insulating film 402 is the underlying insulating film 1 It may be formed using the same materials and methods as in 02.

0319Next, an oxide semiconductor film is formed (see FIG. 14 (A)). Oxide semiconductor film is half oxide It may be formed by using the same material and method as the conductor film 107.

0320Next, the gate insulating film 412 and the gate electrode 404 on the gate insulating film 412 are formed ( See Figure 14 (B). ). The gate insulating film 412 is a gate insulating film 112 or a gate insulating film. It may be formed using the same materials and methods as in 132. The gate electrode 404 is a gate electric It may be formed using the same materials and methods as pole 104.

0321Next, using the gate electrode 404 as a mask, impurities are added to the oxide semiconductor film 407. Gutai As impurities, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus , Argon, Arsenic, Krypton, Indium, Tin, Antimony and Xenon It is sufficient to add one or more of the above. The methods are ion implantation method and ion doping method. You can do it with. The ion implantation method is preferably used. At that time, the acceleration voltage is 5kV or more and 10 It should be 0 kV or less. In addition, the amount of impurities added is 1 x 10¹⁴ions / cm²Above 1 × 10¹⁶ions / cm²It is as follows. After that, heat treatment may be performed.

0322Next, a barrier film may be formed. The barrier film is made of the same material and method as the barrier film 108. The film may be formed using.

0323As described above, the transistor shown in FIG. 13 can be manufactured.

0324In the transistor shown in FIG. 13, the oxide semiconductor film 406 has few oxygen deficiencies and is a parasitic channel. The influence of the above is small, and switching characteristics can be obtained even if the size is reduced. Also, oxide semiconducting Even if the body membrane 406 is miniaturized by having a thickness of 1 to 5 times the channel width. It can be a transistor with excellent on-characteristics.

0325Next, the interlayer insulating film 418 is formed. The interlayer insulating film 418 is the same material as the interlayer insulating film 118. It may be formed by using a material and a method.

0326Next, an opening is provided in the interlayer insulating film 418 to expose the oxide semiconductor film 406.

0327Next, the wiring 436 is formed. Wiring 436 uses the same materials and methods as Wiring 136. (See Fig. 14 (C)).

0328According to this embodiment, switching characteristics can be obtained even if the size is reduced, and the on characteristics are excellent. Langista can be provided. In addition, a semi-conduct with a high degree of integration using the transistor Body equipment can be provided.

0329In addition, this embodiment can be used in combination with other embodiments as appropriate.

0330(Embodiment 5) In the present embodiment, the transistor has a structure different from that of the first to fourth embodiments. I will explain.

0331FIG. 15A is a top view of the transistor according to one aspect of the present invention. Shown in Fig. 15 (A) A cross-sectional view corresponding to the alternate long and short dash line H1-H2 is shown in FIG. 15 (B). In addition, it is shown in FIG. 15 (A). A cross-sectional view corresponding to the alternate long and short dash line H3-H4 is shown in FIG. 15 (C). In addition, it made the explanation easy. Therefore, in FIG. 15 (A), the underlying insulating film 502 and the like are omitted.

0332FIG. 15 (A) shows the channel length (L) and channel width (W) of the transistor. It should be noted that , The channel region of the transistor is sandwiched between a pair of electrodes 516 in the oxide semiconductor film 506. It is an area to be covered. At least two sides of the oxide semiconductor film 506 are gate electrodes 50. Superimpose with 4.

0333The transistor shown in Fig. 15 (A) has a channel length of 5 nm or more and less than 60 nm, and a channel. The width is 5 nm or more and less than 200 nm.

0334The transistor shown in FIG. 15A has a channel width 0.5 times that of the channel length. More than 10 times or less.

0335FIG. 15B shows the underlying insulating film 502 provided on the substrate 500 and the underlying insulating film 502. The gate electrode 504 provided and the gate insulating film 512 provided on the gate electrode 504 , An oxide semiconductor film 5 provided so as to be superimposed on the gate electrode 504 via the gate insulating film 512. 06, a pair of electrodes 516 provided on the oxide semiconductor film 506, and a pair of electrodes 516 It is sectional drawing of the transistor which has the interlayer insulating film 518 provided in.

0336The material of the substrate 500 may be selected from the same materials as those of the substrate 100.

0337In the underlying insulating film 502, impurities caused by the substrate 500 do not affect the oxide semiconductor film 506. It is provided so that it can be used. However, if the substrate 500 does not contain impurities, the underlying insulating film It is not necessary to provide 502. Alternatively, the gate insulating film 512 suppresses the diffusion of impurities. If it can be controlled, the underlying insulating film 502 may not be provided.

0338The underlying insulating film 502 includes aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, One or more of materials containing lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide It may be selected above and used in a single layer or in a laminated manner. Also, in addition to the single layer or lamination described above , Silicon nitride oxide and silicon nitride may be laminated.

0339The gate electrode 504 may be used by selecting from the same materials as the gate electrode 104.

0340The gate insulating film 512 is made of the same material as the gate insulating film 112 or the gate insulating film 132. It may be selected and used.

0341The oxide semiconductor film 506 may be selected and used from the same materials as the oxide semiconductor film 106. ..

0342The pair of electrodes 516 may be selected and used from the same materials as the pair of electrodes 216.

0343The interlayer insulating film 518 includes aluminum oxide, aluminum nitride, magnesium oxide, and aluminum oxide. Recon, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, One or more of materials containing lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide It may be selected above and used in a single layer or in a laminated manner. Also, in addition to the single layer or lamination described above , Silicon nitride oxide and silicon nitride may be laminated.

0344The interlayer insulating film 518 preferably has a low relative permittivity and a sufficient thickness. example For example, using a silicon oxide film with a relative permittivity of about 3.8, 200 nm or more and 1000 nm or more. It may be provided with the thickness below. The upper surface of the interlayer insulating film 518 is slightly fixed due to the influence of atmospheric components and the like. It has an electric charge, and the threshold voltage of the transistor may fluctuate due to its influence. That Therefore, the interlayer insulating film 518 has a ratio within a range in which the influence of the electric charge generated on the upper surface is sufficiently small. It is preferably the dielectric constant and the thickness. Polyimide on the interlayer insulating film 518 for the same reason By forming a resin film such as silicon resin, acrylic resin, epoxy resin, silicone resin, etc. The influence of the electric charge generated on the upper surface of the interlayer insulating film 518 may be reduced.

0345The method of manufacturing the transistor shown in FIG. 15 will be described below with reference to FIG. Easy to explain Here, only the cross-sectional view corresponding to FIG. 15 (B) is shown.

0346First, the substrate 500 is prepared.

0347Next, a base insulating film 502 is formed on the substrate 500. The underlying insulating film 502 is the underlying insulating film 5 Select from the materials shown as 02, including sputtering method, CVD method, MBE method, and ALD method. Alternatively, the film may be formed using the PLD method.

0348Next, the gate electrode 504 is formed. The gate electrode 504 is made of the same material as the gate electrode 104. It may be formed by using a material and a method.

0349Next, the gate insulating film 512 is formed (see FIG. 16 (A)). The gate insulating film 512 is Formed using the same materials and methods as the gate insulating film 112 or the gate insulating film 132. Just do it.

0350Next, the oxide semiconductor film 506 is formed (see FIG. 16 (B)). Oxide semiconductor film 506 May be formed using the same materials and methods as the oxide semiconductor film 107.

0351Next, a conductive film to be a pair of electrodes 516 is formed. The conductive film that becomes the pair of electrodes 516 is one. Select from the materials shown as paired electrodes 516, sputtering method, CVD method, MBE method, The film may be formed using the ALD method or the PLD method.

0352Next, the conductive film to be the pair of electrodes 516 is processed to form the pair of electrodes 516. In addition, it should be noted Part of the processing of the conductive film that becomes the pair of electrodes 516 is an electron beam lithography system (EB (Electr)). on Beam) Also called an exposure machine. ) Is preferably used. The EB exposure machine is extremely fine Since it can be processed, it is suitable for manufacturing a miniaturized transistor.

0353Next, an interlayer insulating film 518 is formed (see FIG. 16C). The interlayer insulating film 518 is an interlayer. Select from the materials shown as the insulating film 518, sputtering method, CVD method, MBE method, A The film may be formed by using the LD method or the PLD method.

0354As described above, the transistor shown in FIG. 15 can be manufactured.

0355In the transistor shown in FIG. 15, the oxide semiconductor film 506 has less oxygen deficiency and is a parasitic channel. The influence of the above is small, and switching characteristics can be obtained even if the size is reduced. Also, a pair of electrodes By having 516, it is possible to make a transistor with excellent on-characteristics even if it is miniaturized. it can.

0356According to this embodiment, switching characteristics can be obtained even if the size is reduced, and the on characteristics are excellent. Langista can be provided. In addition, a semi-conduct with a high degree of integration using the transistor Body equipment can be provided.

0357In addition, this embodiment can be used in combination with other embodiments as appropriate.

0358(Embodiment 6) In the present embodiment, the transistor shown in any one of the first to fifth embodiments is used. An example of manufacturing a semiconductor storage device will be described.

0359As a typical example of a volatile semiconductor storage device, a transistor constituting a storage element is selected. DRAM (Dynamic Ra) that stores information by accumulating electric charge in the capacitor In memory using circuits such as ndom Access Memory) and flip-flops SRAM (Static Random Access Memory) that holds the contents is there.

0360A typical example of a non-volatile semiconductor storage device is between a transistor gate and a channel region. Has a floating gate, and stores by holding an electric charge in the floating gate There is a flash memory to do.

0361Embodiment 1 to Embodiment 5 on a part of the transistors included in the semiconductor storage device described above. The transistor shown in any of the above can be applied.

0362First, a semiconductor to which the transistor shown in any one of the first to fifth embodiments is applied. FIG. 17 shows a specific example of the memory cells constituting the storage device.

0363The memory cells are bit line BL, word line WL, sense amplifier SAmp, and transition. It has a T Tr and a capacitor C (see FIG. 17 (A)).

0364The time change of the voltage held in the capacitor C is due to the off current of the transistor Tr. It is known that it gradually decreases as shown in 7 (B). Initially charged from V0 to V1 The charged voltage decreases to VA, which is the limit point for reading data1 over time. .. Let this period be the retention period T_1. That is, in the case of a binary memory cell, during the retention period T_1 Need to be refreshed.

0365Here, the transistor shown in any one of the first to fifth embodiments of the transistor Tr When the transistor is applied, the transistor can have extremely low off current, so it can be retained. The period T_1 can be lengthened. That is, it is possible to reduce the frequency of refreshment. Therefore, the power consumption can be reduced. For example, the off current is 1x10^-21A 1 × 10^-25When a memory cell is composed of transistor Tr which is A, no power is supplied. It will be possible to retain data for days to decades.

0366Further, the transistor Tr is the transistor shown in any one of the first to fifth embodiments. When is applied, the area of the memory cell can be reduced because the transistor is miniaturized. To. Therefore, the degree of integration of the semiconductor storage device can be increased.

0367FIG. 17C is an example of the cross-sectional structure of the memory cell. In addition, in FIG. 17 (C), the tran The transistor shown in Fig. 4 is applied to the Gista Tr. Therefore, the transistor Tr Of the respective configurations, those not described below will be referred to the description of the first embodiment and the like.

0368Here, the capacitor C is on the underlying insulating film 102, and the region 106b of the transistor Tr. It was formed of the same layer and the same material as the electrode 116 and the gate insulating film 132 provided in contact with the electrode 116. By an electrode (capacitive electrode) formed of the same layer and the same material as the insulating layer and the gate electrode 104 It is composed of. In FIG. 17C, the electrode 116 is embedded in the underlying insulating film 102. The shape is not limited to this. The electrode 116 is on the underlying insulating film 102 and Any shape can be used as long as it is provided in contact with the region 106b of the transistor Tr. I don't know.

0369Electrodes 116 include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and Elementary substances, nitrides, oxides or alloys containing one or more watts can be used in single layers or in layers. Just do it.

0370Further, the word line WL is electrically connected to the gate electrode 104. Also, the bit line BL is , Electrically connected to wiring 136.

0371In the memory cell shown in FIG. 17 (C), the transistor Tr and the capacitor C are in the same layer and Since it is composed of electrodes and insulating film made of the same material, the number of steps can be reduced and raw Productivity can be increased. However, the transistor Tr and the capacitor C are on the same layer and It does not have to be composed of electrodes and an insulating film made of the same material. For example, The area of the memory cell is further reduced by superimposing the Langista Tr and the capacitor C. It doesn't matter if you cut it.

0372As described above, according to one aspect of the present invention, a semiconductor storage device having a high degree of integration and low power consumption You can get a place.

0373Next, the semiconductor description to which the transistor shown in any one of the first to fifth embodiments is applied. An example different from that of FIG. 17 will be described with reference to FIG. 18 with respect to the memory cells constituting the memory device.

0374FIG. 18A is a circuit diagram of a memory cell. The memory cells are transistor Tr_1 and Word line WL_1 that electrically connects to the gate of transistor Tr_1 and transistor T Source line SL_1 that electrically connects to the source of r_1, transistor Tr_2, and tiger Source line SL_2 that electrically connects to the source of engineer Tr_2, and transistor Tr_ Drain line DL_2 that electrically connects to the drain of 2, capacitor C, and capacitor C The capacitance line CL that electrically connects to one end of the capacitor C, the other end of the capacitor C, and the transistor Tr_1 It has a drain and a node N that electrically connects to the gate of transistor Tr_2. ..

0375The semiconductor storage device shown in the present embodiment has a transistor T according to the potential of the node N. This utilizes the fact that the apparent threshold voltage of r_2 fluctuates. For example, Figure 18 (B) is the voltage V of the capacitance line CL_CLAnd the drain current I flowing through the transistor Tr_2_d_ It is a figure explaining the relationship with 2.

0376The potential of the node N can be adjusted via the transistor Tr_1. For example Let the potential of the source line SL_1 be VDD. At this time, the potential of the word line WL_1 is changed. By setting the potential to be equal to or higher than the potential obtained by adding VDD to the threshold voltage Vth of the star Tr_1, the node N The potential can be set to HIGH. In addition, the potential of the word line WL_1 is changed to the transistor Tr. By setting the threshold voltage Vth or less of _1, the potential of node N can be set to LOW. To.

0377Therefore, V indicated by N = LOW_CL-I_d_2 curve and V indicated by N = HIGH_CL-I_dYou can get any of the _2 curves. That is, when N = LOW, V_CL= 0V At I_dSince _2 is small, the data is 0. Also, at N = HIGH, V_CLTo = 0V I_dSince _2 is large, it becomes data 1. In this way, you can store the data Wear.

0378Here, the transistor shown in any one of the first to fifth embodiments is connected to the transistor Tr_1. When a gista is applied, the transistor can reduce the off-current extremely, so that The charge stored in node N is unintentionally between the source and drain of transistor Tr_1. It can be suppressed from leaking to. Therefore, data can be retained for a long period of time. To. Also, since a high voltage is not required when writing, it is erased compared to flash memory etc. The power consumption is low and the operating speed can be increased.

0379Further, the transistor Tr_1 has a transition shown in any one of the first to fifth embodiments. When the star is applied, the transistor is miniaturized, so that the area of the memory cell is reduced. it can. Therefore, the degree of integration of the semiconductor storage device can be increased.

0380FIG. 18C is an example of the cross-sectional structure of the memory cell. In Fig. 18 (C), the tran The transistor shown in Fig. 4 is applied to Gista Tr_1. Therefore, the transistor T For each configuration of r_1 that is not explained below, refer to the explanation of the first embodiment and the like. Illuminate.

0381In this embodiment, a transistor using silicon as the transistor Tr_2 Will be described when is applied. However, the transistor Tr_2 is used in the first to second embodiments. The transistor shown in any of the fifth embodiments may be applied.

0382The transistor using silicon is the transistor shown in the first to fifth embodiments. Compared with this, it has the advantage that the on-characteristics can be easily enhanced. Therefore, a low off-current required tran It can be said that it is more suitable for transistor Tr_2, which requires higher on-characteristics than Gista Tr_1. ..

0383Here, the transistor Tr_2 is formed by the base insulating film 152 provided on the substrate 150 and the base. Silicon film 156 including region 156a and region 156b provided on the insulating film 152 And the gate insulating film 162 provided on the silicon film 156 and the gate insulating film 162. The gate electrode 154 provided on top of the silicon film 156 and the gate insulating film 162 It also has a side wall insulating film 160 provided in contact with the side wall of the gate electrode 154.

0384An interlayer insulating film 158 is provided on the transistor Tr_2, and an interlayer insulating film 158 is provided. Is provided with a hydrogen-containing layer 168.

0385The material of the substrate 150 may be selected from the same materials as those of the substrate 100.

0386The base insulating film 152 may be selected from the same materials as the base insulating film 102.

0387If a silicon film such as a single crystal silicon film or a polycrystalline silicon film is used for the silicon film 156, Good.

0388The area 156a functions as a channel area. In addition, area 156b is the source area. And functions as a drain area.

0389In this embodiment, the silicon film is used for the channel region, the source region, and the drain region. However, if the substrate 150 is a semiconductor substrate such as a silicon wafer, it will be charged inside the semiconductor substrate. A flannel region, a source region, and a drain region may be provided.

0390The gate insulating film 162 may be selected and used from the same materials as the gate insulating film 112.

0391The gate electrode 154 may be used by selecting from the same materials as the gate electrode 104.

0392The side wall insulating film 160 may be selected from the same materials as the side wall insulating film 310.

0393The interlayer insulating film 158 may be selected from the same materials as the interlayer insulating film 118. In addition, it should be noted Polyimide resin, acrylic resin, epoxy resin, silicone resin on the interlayer insulating film 158 Any resin film may be formed.

0394The hydrogen-containing layer 168 is subjected to secondary ion mass spectrometry (SIMS: Secondary Ion M). 1 × 10 hydrogen with ass Spectrometry)²¹atoms / cm³Including the above It is an insulating film.

0395As the hydrogen-containing layer 168, for example, a silicon nitride film or a silicon nitride film may be used.

0396Since the transistor Tr_2 is a transistor using silicon, the silicon film 156 The electrical characteristics can be improved by hydrogen-terminating the surface of the. Therefore, it contains hydrogen It is preferable that hydrogen is supplied from layer 168. However, in this embodiment, the hydrogen-containing layer 168 Is not limited to the structure provided with. For example, a transistor without the hydrogen-containing layer 168 Hydrogen may be supplied to Tr_2.

0397Further, although not shown, a layer having low hydrogen permeability between the hydrogen-containing layer 168 and the underlying insulating film 102. May be provided. Transistor Tr_1 is a transistor using an oxide semiconductor film. To. Hydrogen can be a source of carrier generation in oxide semiconductor membranes, so hydrogen is extremely mixed. It is preferable to reduce the force. Therefore, when the hydrogen-containing layer 168 is provided, hydrogen permeation It is preferable to suppress the diffusion of hydrogen into the transistor Tr_1 with a low-quality layer.

0398Specifically, in the layer with low hydrogen permeability, hydrogen is released by heat treatment at 350 ° C for 1 hour. It is an insulating film that does not permeate.

0399Further, the capacitor C is on the underlying insulating film 102, and the region 106 of the transistor Tr_1 It is formed of the same layer and material as the electrode 166 and the gate insulating film 132 provided in contact with b. For the insulating layer and the electrode (capacitive electrode) formed of the same layer and material as the gate electrode 104 Therefore, it is configured. The electrode 166 includes an underlying insulating film 102, a hydrogen-containing layer 168, and interlayer insulation. It contacts the gate electrode 154 of the transistor Tr_2 through the opening provided in the membrane 158. To. In FIG. 18C, the electrode 166 is embedded in the underlying insulating film 102. However, it is not limited to this. Electrode 166 is on the underlying insulating film 102 and is a transistor. Provided in contact with region 106b of Tr_1 and gate electrode 154 of transistor Tr_2 Any shape may be used as long as it is used.

0400Electrodes 166 include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and Elementary substances, nitrides, oxides or alloys containing one or more watts can be used in single layers or in layers. Just do it.

0401Further, the word line WL_1 is electrically connected to the gate electrode 104. Also, the source line S L_1 is electrically connected to the wiring 136. In addition, the capacitance line CL is electrically connected to the capacitance electrode. Be connected.

0402In the memory cell shown in FIG. 18C, the transistor Tr_1 and the capacitor C are in the same layer. Moreover, since it is composed of electrodes and an insulating film made of the same material, the number of steps can be reduced. , Productivity can be increased. However, the transistor Tr_1 and the capacitor C are the same. It does not have to be composed of one layer and an electrode and an insulating film made of the same material. Example For example, by superimposing the transistor Tr and the capacitor C, the area of the memory cell can be increased. It may be made smaller.

0403As described above, according to one aspect of the present invention, a semiconductor storage device having a high degree of integration and low power consumption You can get a place.

0404This embodiment can be used in combination with other embodiments as appropriate.

0405(Embodiment 7) The transistor shown in any one of the first to fifth embodiments or the sixth embodiment. CPU (Central Process i) using at least a part of the semiconductor storage device ng Unit) can be configured.

0406FIG. 19A is a block diagram showing a specific configuration of the CPU. C shown in Fig. 19 (A) The PU is an arithmetic logic unit (ALU) on the board 1190. unit) 1191, ALU controller 1192, instruction decoder 11 93, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface (Bus I / F) 1 198, rewritable ROM 1199, and ROM interface (ROM I / F) has 1189. The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, etc. Is used. ROM1199 and ROM interface 1189 are provided on separate chips. May be good. Of course, the CPU shown in Fig. 19 (A) is an example showing a simplified configuration. Actual CPUs have a wide variety of configurations depending on their use.

0407Instructions input to the CPU via bus interface 1198 are instructions. After input to decoder 1193 and decoded, ALU controller 1192, inter Rapto controller 1194, register controller 1197, timing controller Entered in 1195.

0408ALU controller 1192, interrupt controller 1194, register controller La 1197 and timing controller 1195 have various controls based on the decoded instructions. Do the god. Specifically, the ALU controller 1192 controls the operation of the ALU1191. Generate a signal for In addition, the interrupt controller 1194 is a CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are given priority or masked. Judge from the state and process. The register controller 1197 is an address of register 1196. Generates a register and reads or writes register 1196 according to the CPU status.

0409The timing controller 1195 is ALU1191 and ALU controller 119. 2, instruction decoder 1193, interrupt controller 1194, and Generates a signal that controls the timing of operation of register controller 1197. For example The iming controller 1195 has an internal clock signal based on the reference clock signal CLK1. Equipped with an internal clock generator that generates CLK2, the clock signal CLK2 can be generated from the above types. Supply to the circuit.

0410In the CPU shown in FIG. 19 (A), a storage element is provided in the register 1196. cash register As the storage element of the star 1196, the semiconductor storage device shown in the sixth embodiment can be used. ..

0411In the CPU shown in FIG. 19 (A), the register controller 1197 is ALU1191. The holding operation in the register 1196 is performed according to the instruction from. That is, register 1196 Holds data by flip-flop or capacitor in the storage element of Data is retained by. If the data is held by flip-flops, check The power supply voltage is supplied to the storage element in the Gista 1196. Day by capacitor If the data is retained, the data is rewritten to the capacitor and register 1196 It is possible to stop the supply of the power supply voltage to the storage element inside.

0412Regarding the power stop, as shown in Fig. 19 (B) or Fig. 19 (C), the storage element group and the electric power A switching element is installed between the nodes given the source potential VDD or the power potential VSS. It can be done by kicking. Below is a description of the circuits in Figures 19 (B) and 19 (C). I do.

0413In FIGS. 19B and 19C, a switch that controls the supply of the power potential to the storage element. A configuration in which the transistor shown in any one of the first to fifth embodiments is used for the device. An example is shown.

0414The storage device shown in FIG. 19B has a plurality of switching elements 1141 and storage elements 1142. It has a memory element group 1143. Specifically, for each storage element 1142 , The semiconductor storage device shown in the sixth embodiment can be used. Memory element group 1143 has Each storage element 1142 has a high level via a switching element 1141. The power supply potential VDD is supplied. Furthermore, each memory of the memory element group 1143 The element 1142 is given the potential of the signal IN and the potential of the low-level power supply potential VSS. There is.

0415In FIG. 19 (B), the transition element 1141 has an extremely small off-current. A star is used, and the transistor is switched by the signal SigA given to the gate. Thatching is controlled.

0416In FIG. 19B, the switching element 1141 has only one transistor. Although the result is shown, the present invention is not limited to this, and a plurality of transistors may be provided. switch When the switching element 1141 has a plurality of transistors that function as switching elements. In that case, the plurality of transistors may be connected in parallel or in series. Alternatively, series and parallel may be combined and connected.

0417Further, in FIG. 19C, each storage element 1142 included in the storage element group 1143 is shown in FIG. The low-level power supply potential VSS is supplied via the switching element 1141. An example of a memory device is shown. Due to the switching element 1141, the storage element group 1143 has the same. By controlling the supply of low-level power potential VSS to each storage element 1142 Wear.

0418Between the storage element group and the node to which the power potential VDD or power potential VSS is given. When a hatching element is provided to temporarily stop the operation of the CPU and stop the supply of power supply voltage It is possible to retain the data even if the data is stored, and the power consumption can be reduced. example For example, a user of a personal computer can input information to an input device such as a keyboard. CPU operation can be stopped even while it is stopped, thereby reducing power consumption. Can be

0419Here, the CPU was taken as an example, but DSP (Digital Signal P) rocessor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Array).

0420This embodiment can be implemented in combination with the above embodiment as appropriate.

0421(Embodiment 8) In the present embodiment, an electron to which at least one of the first to seventh embodiments is applied. An example of the device will be described.

0422FIG. 20A shows a portable information terminal. The portable information terminal shown in FIG. 20 (A) has a housing 93. 00, button 9301, microphone 9302, display 9303, speaker 9 It is equipped with a 304 and a camera 9305, and has a function as a portable telephone. Of the present invention One form can be applied to an arithmetic unit, a wireless circuit or a storage circuit inside the main body.

0423FIG. 20B is a display. The display shown in Fig. 20 (B) is the housing 931. 0 and a display unit 9311 are provided. One form of the present invention is an arithmetic unit inside the main body, nothing. It can be applied to line circuits or storage circuits.

0424FIG. 20 (C) is a digital still camera. Digital still turtle shown in Fig. 20 (C) La has a housing 9320, a button 9321, a microphone 9322, and a display 9323. And. One embodiment of the present invention is an arithmetic unit, wireless circuit or storage circuit inside the main body. Can be applied to.

0425FIG. 20 (D) is a mobile information terminal that can be folded in half. Can be folded in half as shown in Fig. 20 (D) The mobile information terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, and a fastener 9633. , Has an operation switch 9638. One form of the present invention is an arithmetic unit inside the main body, wireless. It can be applied to circuits or storage circuits.

0426In addition, the display unit 9631a and / and the display unit 9631b touch part or all of them. It can be a flannel, and you can enter data by touching the displayed operation keys. it can.

0427By using the semiconductor device according to one aspect of the present invention, the performance of the electronic device is improved and the power consumption is reduced. You can do it.

0428This embodiment can be used in combination with other embodiments as appropriate.

0429100 boards 102 Underlayer insulating film 104 Gate electrode 105 Conductive 106 Oxide semiconductor film 106a area 106b area 107 Oxide semiconductor film 108 Barrier membrane 112 Gate insulating film 116 Electrodes 118 Interlayer insulating film 132 Gate insulating film 136 Wiring 150 board 152 Underlayer insulating film 154 Gate electrode 156 Silicon film 156a area 156b area 158 Interlayer insulating film 160 Side wall insulating film 162 Gate insulating film 166 Electrodes 168 Hydrogen-containing layer 200 board 202 Underlayer insulating film 204 Gate electrode 206 Oxide semiconductor film 207 Oxide semiconductor film 212 Gate insulating film 216 Pair of electrodes 217 Conductive 218 Interlayer insulating film 236 Wiring 300 board 302 Underlayer insulating film 304 Gate electrode 305 Conductive 306 Oxide semiconductor film 306a area 306b area 307 Oxide semiconductor film 310 Side wall insulating film 312 Gate insulating film 313 Gate insulating film 316 Pair of electrodes 317 Conductive 318 Interlayer insulating film 319 Interlayer insulating film 320 insulating film 321 Insulation film 322 Insulation film 328 interlayer insulating film 336 wiring 400 board 402 Base insulating film 404 gate electrode 406 Oxide semiconductor film 407 Oxide semiconductor film 412 Gate insulating film 418 Interlayer insulating film 436 Wiring 500 board 502 Underlayer insulating film 504 Gate electrode 506 Oxide semiconductor film 512 gate insulating film 516 Pair of electrodes 518 Interlayer insulating film 1141 switching element 1142 storage element 1143 Memory element group 1189 ROM interface 1190 board 1191 ALU 1192 ALU controller 1193 Instruction decoder 1194 interrupt controller 1195 Timing controller 1196 register 1197 register controller 1198 bus interface 1199 ROM 9300 housing 9301 button 9302 microphone 9303 Display 9304 speaker 9305 camera 9310 housing 9311 Display 9320 chassis 9321 button 9322 microphone 9323 Display 9630 chassis 9631a Display 9631b Display 9633 Fasteners 9638 Operation switch