Semiconductor device and method for fabricating the same

0001The present invention uses a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface. The present invention relates to a semiconductor device provided with an active circuit and a method for manufacturing the same. In particular, the present invention has an image display area. An electro-optical device represented by a liquid crystal display device in which the device and its drive circuit are provided on the same substrate, and an electro-optical device. It can be suitably used for electronic devices equipped with an electro-optical device. The semiconductor device in the present specification. Refers to all devices that function by utilizing semiconductor characteristics, and the above-mentioned electro-optical devices and their devices. The category includes electronic devices equipped with the electro-optical device of.

0002TFT in which a semiconductor layer is formed of a crystalline silicon film (hereinafter referred to as crystalline silicon TFT) Has high field-effect mobility and can form various functional circuits. Crystalline Siri The active matrix type liquid crystal display device using the computer TFT displays the image display area and the image display. The drive circuit for doing this is formed on the same substrate. N-channel type T in the image display area Pixel TFT formed by FT and holding capacity are provided, and the drive circuit is basically a CMOS circuit. Shift register circuit, level shifter circuit, buffer circuit, sampling formed as It is composed of circuits and the like.

0003However, the operating conditions are not the same between the pixel TFT and the drive circuit TFT, so the TFT is used. The required characteristics are not a little different. For example, a pixel TFT can be used as a switch element. It is capable and is driven by applying a voltage to the liquid crystal. The liquid crystal is driven by alternating current Therefore, a method called frame inversion drive is often adopted. Power consumption in this method The characteristic required for the pixel TFT to keep it low is the off-current value (when the TFT is off). The drain current that flows) should be sufficiently low. On the other hand, the buffer circuit of the control circuit is expensive. Since the drive voltage is applied, it is necessary to increase the withstand voltage so that it will not break even if a high voltage is applied. There is. Also, in order to increase the current drive capability, the on-current value (the current that flows when the TFT is on-operation) It is necessary to secure sufficient rain current).

0004Low-concentration drain (LDD: Lightly) as a TFT structure to reduce the off-current value Doped Drain) structure is known. This structure has channel formation regions and high concentrations of impurities Impurity elements are added at a low concentration between the source region or drain region formed by adding elements. The added area is provided, and this area is called the LDD area. Also, hot ca As a means to prevent deterioration of the on-current value due to the rear, the LDD region is passed through the gate insulating film. So-called GOLD (Gate-drain Overlapped LDD), which is placed on top of the gate electrode. The structure is known. With such a structure, the high electric field near the drain is relaxed. It is known to be effective in preventing hot carrier injection and preventing deterioration phenomena.

0005On the other hand, in order to increase the value of the active matrix type liquid crystal display device as a product, the screen There is a demand for larger size and higher definition. However, for larger screens and higher definition Since the number of scanning lines (gate wiring) increases and the length also increases, the resistance of the gate wiring can be reduced. More needed. That is, as the number of scanning lines increases, the charging time to the liquid crystal becomes shorter, and the gate It is necessary to reduce the wiring time constant (resistance x capacitance) and respond at high speed. For example, the gate When the specific resistance of the material forming the wiring is 100 μΩcm, the screen size is 6 inch class. Although it is almost the limit, in the case of 3 μΩ cm, it is possible to display up to 27 inch class equivalent. There is.

<p num="0006"> However, the pixel TFT of the pixel matrix circuit and the shift register circuit and buffer times The required characteristics are not always the same as those of TFTs of control circuits such as roads. For example , Large reverse bias on the gate in pixel TFT (negative voltage in n-channel TFT) Is applied, but the TFT of the control circuit basically does not operate in the reverse bias state. Well Also, regarding the operating speed, the pixel TFT may be 1/100 or less of the TFT of the control circuit.</p><p num="0007"> In addition, the GOLD structure is highly effective in preventing deterioration of the on-current value, but on the other hand, it is a normal LDD. There was a problem that the off-current value became larger than that of the structure. Therefore, it is applied to pixel TFT It was not a preferable structure. On the contrary, the normal LDD structure has the effect of suppressing the off-current value. High, but is it less effective in relaxing the electric field near the drain and preventing deterioration due to hot carrier injection? It was. In this way, a plurality of devices having different operating conditions such as an active matrix type liquid crystal display device. In a semiconductor device having an integrated circuit of, all TFTs must be formed with the same structure. It was not preferable. Such problems are especially present in crystalline silicon TFTs. The higher the characteristics and the higher the performance required for the active matrix liquid crystal display device. It has become apparent.</p><p num="0008"> As a wiring material to realize a large-screen active matrix type liquid crystal display device It is possible to use luminium (Al) or copper (Cu), but the corrosion resistance and heat resistance are poor. There was a drawback such as. Therefore, it is not possible to form the gate electrode of the TFT with such a material. Not always preferable and it is not easy to introduce such materials into the manufacturing process of TFTs. won. Of course, the wiring can be made of other conductive materials, but aluminum (A). There is no material with lower resistance than l) and copper (Cu), and it is impossible to make a large screen display device. It was.</p>

<p num="0009"> In order to solve the above problems, the configuration of the present invention includes a pixel TFT provided in the display area and the table. In a semiconductor device having the TFT of the drive circuit provided around the indicated area on the same substrate. The pixel TFT and the TFT of the drive circuit have a gate electrode formed of a first conductive layer. However, the gate electrode is in electrical contact with the gate wiring formed by the second conductive layer at the connection portion. The connection portion is a channel forming region of the pixel TFT and the TFT of the drive circuit. It is characterized by being provided on the outside.</p><p num="0010"> Further, the configuration of another invention is provided in the pixel TFT provided in the display area and around the display area. In a semiconductor device having the TFT of the drive circuit on the same substrate, the pixel TFT and the said The TFT of the drive circuit has a gate electrode formed of a first conductive layer, and the gate electrode is , The gate wiring formed by the second conductive layer, the pixel TFT and the TFT of the drive circuit The pixel TFT has electrical contact at a connection portion provided outside the channel forming region of the pixel TFT. The LDD region is arranged so as not to overlap the gate electrode of the pixel TFT, and the drive circuit of the drive circuit. The LDD region of the first n-channel TFT is the gate electrode of the first n-channel TFT. Arranged so as to overlap, the LDD region of the second n-channel TFT of the drive circuit is the first. It is arranged so that at least a part of it overlaps with the gate electrode of the n-channel TFT of 1. It is characterized by.</p><p num="0011"> In the configuration of the present invention, the first conductive layer is made of tantalum, tungsten, titanium, or the like. A conductive layer (A) containing at least one selected from molybdenum and nitrogen, and the conductive layer (A). Formed on top and selected from tantalum, tungsten, titanium, molybdenum at least one A conductive layer (B) containing a seed as a main component and a region in which the conductive layer (B) does not contact the conductive layer (A). Made with at least one selected from tantalum, tungsten, titanium, molybdenum and nitrogen It has a conductive layer (C) containing elements, and the second conductive layer is at least aluminum or Is composed of a conductive layer (D) containing copper as the main component, and tantalum, tungsten, titanium, and molybdenum. It has a conductive layer (E) containing at least one selected as a main component, and a conductive layer (C) at the connection portion. ) And the conductive layer (D) are in contact with each other. The conductive layer (B) is an additive element. The oxygen concentration in the conductive layer (B) is 30 ppm or less. Is desirable.</p><p num="0012"> In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention is an image provided in a display area. A semi-conducting device having a raw TFT and a TFT of a drive circuit provided around the display area on the same substrate. In the method of manufacturing the body device, the gate electrodes of the pixel TFT and the TFT of the drive circuit are The process of forming the first conductive layer and the gate wiring connected to the gate electrode are connected to the second conductive layer. The gate electrode and the gate wiring are the pixel TFT and the gate wiring. It is characterized by connecting with a connection part provided outside the channel formation region with the TFT of the drive circuit. It is said.</p><p num="0013"> Further, the method for manufacturing the semiconductor device of the present invention includes a pixel TFT provided in the display area and the display area. In a semiconductor device having the TFT of the drive circuit provided around the above on the same substrate, the above-mentioned drive 2 × 10 on the semiconductor layer of the first and second n-channel TFTs that form the dynamic circuit¹⁶~5× 10¹⁹atoms / cm³First step of selectively adding an impurity element that imparts n-type in the concentration range of And the gate electrode of the pixel TFT and the TFT of the drive circuit is formed by the first conductive layer. 3 × 10 on the semiconductor layer of the p-channel TFT that forms the drive circuit in step 2²⁰~3 ×10²¹atoms / cm³Third method of selectively adding an impurity element that imparts p-type in the concentration range of The semiconductor layers of the first and second n-channel TFTs forming the drive circuit, and the above. 1x10 on the semiconductor layer of the pixel TFT²⁰~1×10²¹atoms / cm³N-type is given in the concentration range of The fourth step of selectively adding the impurity element to be used, and the gate to the semiconductor layer of the pixel TFT. 1x10 with electrodes as mask¹⁶~5×10¹⁸atoms / cm³N-type is not given in the concentration range of The fifth step of selectively adding pure elements, and the pixel TFT and the TFT of the drive circuit It has a sixth step of forming the gate wiring with the second conductive layer, the gate electrode and the gate. The wiring is provided outside the channel formation region between the pixel TFT and the TFT of the drive circuit. It is characterized by connecting with a connected part.</p><p num="0014"> In the method for manufacturing a semiconductor device of the present invention, the first conductive layer is tantalum or tongue. Conductive layer (A) containing at least one selected from stainless steel, titanium, molybdenum and nitrogen The step of forming and tantalum, tungsten, titanium, molyb formed on the conductive layer (A) A step of forming a conductive layer (B) containing at least one selected from den as a main component, and the conductivity. A layer (B) is formed in a region not in contact with the conductive layer (A), and tantalum, tungsten, titanium, etc. The process of forming a conductive layer (C) containing at least one selected from molybdenum and nitrogen The second conductive layer is formed from, at least, a conductor containing at least aluminum or copper as a main component. The process of forming the electric layer (D) and selected from tantalum, tungsten, titanium and molybdenum The connection is formed from the step of forming a conductive layer (E) containing at least one of the main components. It is characterized in that the conductive layer (C) and the conductive layer (D) are connected at the portion. The conductive layer (A) is , Tantalum, Tungsten, Chita in a mixed atmosphere of argon and nitrogen or ammonia Sputtering using a target whose main component is at least one selected from molybdenum and molybdenum It can be formed by the method, and the conductive layer (C) has a nitrogen atmosphere with an oxygen concentration of 1 ppm or less. It is desirable that the conductive layer (B) is formed by heat treatment. The conductive layer (C) is oxygen-rich. The conductive layer (B) may be formed by heat treatment in a nitrogen plasma atmosphere having a degree of 1 ppm or less.</p>

<p num="0015"> By using the present invention, a semiconductor device in which a plurality of functional circuits are formed on the same substrate (here). Then, specifically, in the electro-optical device), the appropriate properties according to the specifications required by the functional circuit. Noh TFTs can be placed, and their operating characteristics and reliability can be greatly improved. Can be done. In particular, the LDD region of the n-channel TFT of the pixel matrix circuit is n.^--At the concentration of Moreover, by forming it as Loff only, the off-current value can be significantly reduced, and the pixel matrix can be reduced. It can contribute to the reduction of power consumption of the circuit. In addition, the n-channel TFT of the control circuit LDD area n^-By forming only Lov at the concentration of Moreover, deterioration due to hot carriers can be prevented, and deterioration of the on-current value can be reduced. Further, a semiconductor device having such an electro-optical device as a display medium (here, specifically, electricity). The operating performance and reliability of the slave device) can also be improved.</p><p num="0016"> Furthermore, the gate electrodes of the pixel TFT and the TFT of the drive circuit are formed of a highly heat-resistant conductive material. The gate wiring to be connected to the gate electrode is made of a low resistance material such as aluminum (Al). By doing so, the above-mentioned good TFT characteristics are realized, and 4 in using such TFT. It is possible to realize a display device with a large screen larger than Chiclas.</p>

0017<figref num="1">The cross-sectional view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="2">The cross-sectional view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="3">The cross-sectional view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="4">The cross-sectional view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="5">Sectional view of pixel TFT, holding capacity, TFT of drive circuit.</figref><figref num="6">The top view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="7">The top view which shows the manufacturing process of the pixel TFT, the holding capacity, and the TFT of a drive circuit.</figref><figref num="8">The top view which shows the manufacturing process of the TFT of a drive circuit.</figref><figref num="9">The top view which shows the manufacturing process of a pixel TFT.</figref><figref num="10">Top view showing input / output terminals and wiring circuit arrangement of a liquid crystal display device.</figref><figref num="11">The cross-sectional view which shows the structure of the liquid crystal display device.</figref><figref num="12">The perspective view which shows the structure of the liquid crystal display device.</figref><figref num="13">Top view showing pixels in the display area</figref><figref num="14">Circuit block diagram of liquid crystal display device</figref><figref num="15">The figure which shows the positional relationship between a gate electrode and an LDD region.</figref><figref num="16">The figure which shows the connection of a gate electrode and a gate wiring.</figref><figref num="17">The figure which shows an example of the semiconductor device.</figref><figref num="18">Top view and cross-sectional view showing the structure of the EL display device.</figref><figref num="19">Sectional drawing of the pixel part of an EL display device.</figref><figref num="20">Top view and circuit diagram of the pixel part of the EL display device.</figref><figref num="21">An example of a circuit diagram of the pixel part of an EL display device.</figref><figref num="22">Cross-sectional TEM photograph of the superposition of the gate electrode and the gate wiring.</figref><figref num="23">Cross-sectional TEM photograph near the interface between the gate electrode (Ta) and the gate wiring (Al-Nd).</figref><figref num="24">A graph showing the results of a bias-heat stress test, which is the VG-ID characteristic of TFT.</figref><figref num="25">The graph which shows the rise time (A) and fall time (B) of the signal waveform at the input part and the end part of a gate wiring.</figref><figref num="26">The graph which shows the result of having calculated the influence of the contact resistance of a gate electrode and a gate wiring by a simulation.</figref>

0018[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. 1 to 5. Here, the pixel TFT in the display area and Process for manufacturing the TFT of the drive circuit provided around the display area on the same substrate It will be explained in detail according to. However, for the sake of simplicity, the control circuit has a shift register. Form a sampling circuit with a CMOS circuit, which is a basic circuit such as a circuit or buffer circuit. An n-channel TFT will be illustrated.

0019In FIG. 1 (A), a low-alkali glass substrate or a quartz substrate may be used for the substrate 101. it can. In this example, a low alkaline glass substrate was used. In this case, 1 than the glass strain point It may be heat-treated in advance at a temperature as low as 0 to 20 ° C. TFT of this board 101 On the surface forming the silicon oxide film, nitriding to prevent the diffusion of impurities from the substrate 101. A base film 102 such as a silicon film or a silicon oxide nitriding film is formed. For example, plasma SiH by CVD method₄, NH₃, N₂Silicon oxynitride film made from O at 100 nm, same Like SiH₄, N₂A silicon oxynitride film made from O is laminated to a thickness of 200 nm. To.

0020Next, a half with an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm). The conductor film 103a is formed by a known method such as a plasma CVD method or a sputtering method. This implementation In the example, an amorphous silicon film was formed to a thickness of 55 nm by the plasma CVD method. Amorphous structure Examples of the semiconductor film having the above include an amorphous semiconductor film and a microcrystalline semiconductor film. A compound semiconductor film having an amorphous structure such as a rumanium film may be applied. Also, the base film Since 102 and the amorphous silicon film 103a can be formed by the same film forming method, both Persons may be continuously formed. After forming the base film, it is possible to prevent contamination of the surface by not exposing it to the atmosphere once. Therefore, it is possible to reduce variations in the characteristics of the manufactured TFT and fluctuations in the threshold voltage. .. (Fig. 1 (A))

0021Then, using a known crystallization technique, the amorphous silicon film 103a to the crystalline silicon film is used. Form 103b. For example, apply the laser crystallization method or thermal crystallization method (solid phase growth method). However, here, the catalyst source is according to the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. A crystalline silicon film 103b was formed by a crystallization method using an element. Prior to the crystallization process Although it depends on the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed at 400 to 500 ° C for about 1 hour. It is desirable to reduce the hydrogen content to 5 atom% or less before crystallization. Amorphous silicon When the film is crystallized, the atoms are rearranged and densified, so that a crystalline silicon film is produced. The thickness of is about 1 to 15% of the initial thickness of the amorphous silicon film (55 nm in this example). Diminished. (Fig. 1 (B))

0022Then, the crystalline silicon film 103b is divided into islands to form the island-shaped semiconductor layers 104 to 107. Form. Then, by plasma CVD method or sputtering method, the thickness is 50 to 100 nm. A mask layer 108 made of a silicon oxide film is formed. (Fig. 1 (C))

0023Then, a resist mask 109 is provided, and an island-shaped semiconductor layer 10 forming an n-channel TFT is formed. 1 × 10 for the purpose of controlling the threshold voltage over the entire surface of 5 to 107¹⁶~5×10¹⁷atoms / cm³About Boron (B) was added as an impurity element that imparts p-type at a concentration of degree. Addition of boron (B) The addition may be carried out by the ion doping method, or is added at the same time when the amorphous silicon film is formed. You can also keep it. The addition of boron (B) here is not always necessary, but boron (B) ) Is added to the semiconductor layers 110 to 112, and the threshold voltage of the n-channel TFT is within a predetermined range. It was preferred to form to fit inside. (Fig. 1 (D))

0024Impurities that impart n-type to form the LDD region of the n-channel TFT of the drive circuit Elements are selectively added to the island-shaped semiconductor layers 110 and 111. Therefore, resist in advance Masks 113-116 were formed. Impurity elements that impart n-type include phosphorus (P) and arsenic. Element (As) may be used, and here Phosphorus (PH) is added in order to add phosphorus (P).₃) The ion doping method using the above was applied. Phosphorus (P) in the formed impurity regions 117 and 118 Concentration is 2 x 10¹⁶~5×10¹⁹atoms / cm³It should be in the range of. In this specification, here The concentration of the impurity element that imparts the n-type contained in the formed impurity regions 117 to 119 is (n).^-). Further, the impurity region 119 forms a holding capacitance of the pixel matrix circuit. Phosphorus (P) was added to this region at the same concentration. (Fig. 2 (A))

0025Next, the mask layer 108 is removed with hydrofluoric acid or the like, and FIGS. 1 (D) and 2 (A) are shown. The step of activating the impurity element added in step 1 is performed. Activation is 500-6 in a nitrogen atmosphere It can be performed by heat treatment at 00 ° C for 1 to 4 hours or by laser activation. Also, Both may be used in combination. In this example, the method of laser activation is used and KrF excitement is used. A linear beam is formed using Shimalaser light (wavelength 248 nm), and the oscillation frequency is 5 to 50. Hz, energy density 100 ~ 500mJ / cm²As a linear beam overlap split The entire surface of the substrate on which the island-shaped semiconductor layer was formed was treated by scanning with a ratio of 80 to 98%. still, There are no restrictions on the laser light irradiation conditions, and the practitioner may make a proper decision.

0026Then, the gate insulating film 120 is subjected to 10 to 15 by plasma CVD method or sputtering method. It is formed of an insulating film containing silicon with a thickness of 0 nm. For example, oxidative nitriding with a thickness of 120 nm Form a silicon film. The gate insulating film is a single layer or laminated insulating film containing other silicon. It may be used as a structure. (Fig. 2 (B))

0027Next, a first conductive layer is formed to form the gate electrode. This first conductive layer is a single layer Although it may be formed with, a laminated structure such as two layers or three layers may be used if necessary. Book In the embodiment, the conductive layer (A) 121 made of a conductive nitride metal film and the conductive layer made of a metal film (B) 122 was laminated. Conductive layer (B) 122 is tantalum (Ta), titanium (Ti) , Molybdenum (Mo), Tungsten (W) Elements selected from, alloys containing the elements as the main components, or alloys combining the elements It may be formed of a film (typically a Mo-W alloy film or a Mo-Ta alloy film), and the conductive layer (A) 1 21 is tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, Formed from molybdenum nitride (MoN). In addition, the conductive layer (A) 121 can be used as an alternative material. Ngusten silicide, titanium silicide, and molybdenum silicide may be applied. Guidance The electric layer (B) should reduce the concentration of impurities contained in the electric layer (B) in order to reduce the resistance, especially the oxygen concentration. The degree should be 30ppm or less. For example, tungsten (W) has an oxygen concentration. By setting the value to 30 ppm or less, a resistivity value of 20 μΩcm or less could be realized.

0028The conductive layer (A) 121 is set to 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) ) 122 may be 200 to 400 nm (preferably 250 to 350 nm). This implementation In the example, the conductive layer (A) 121 is provided with a tantalum nitride film having a thickness of 30 nm, and the conductive layer (B) 122 is provided with a tantalum nitride film. A 350 nm Ta film was used for each, and all of them were formed by a sputtering method. By this sputtering method In film formation, when an appropriate amount of Xe or Kr is added to Ar of the sputtering gas, the inside of the film to be formed Partial stress can be relaxed and peeling of the film can be prevented. Although not shown, the conductive layer (A) 1 A phosphorus (P) -doped silicon film with a thickness of about 2 to 20 nm is formed under 21. That is valid. This improves the adhesion of the conductive film formed on it and prevents oxidation. At the same time, the alkali metal element contained in the conductive layer (A) or the conductive layer (B) in a trace amount is a game. It can be prevented from diffusing into the insulating film 120. (Fig. 2 (C))

0029Next, resist masks 123 to 127 are formed, and the conductive layer (A) 121 and the conductive layer (B) 1 are formed. 22 is etched together to form gate electrodes 128 to 131 and capacitive wiring 132. The gate electrodes 128 to 131 and the capacitive wiring 132 are provided with a conductive layer (A). 128a to 132a composed of and 128b to 132b composed of the conductive layer (B) are integrated. Is formed. At this time, the gate electrodes 129 and 130 formed in the drive circuit are impurity regions. It is formed so as to overlap a part of 117 and 118 via the gate insulating film 120. (Figure 2( D))

0030Next, the source region and drain region of the p-channel TFT of the drive circuit are formed. Therefore, a step of adding an impurity element that imparts p-type is performed. Here, the gate electrode 128 As a mask, an impurity region is formed in a self-aligned manner. At this time, the n-channel TFT is formed. The formed region is covered with a resist mask 133. And diborane (B₂H₆) The impurity region 134 was formed by the ion doping method. Boron (B) concentration in this region is 3 × Ten²⁰~3×10²¹atoms / cm³To be. In the present specification, the defects formed here The concentration of the impurity element that imparts the p-type contained in the pure substance region 134 is (p).⁺). (Fig. 3 ( A))

0031Next, in an n-channel TFT, it does not function as a source area or a drain area. A pure region was formed. Non-formation of resist masks 135-137 and imparting n-type Pure elements were added to form impurity regions 138-142. This is Phosphine (PH₃) Is performed by the ion doping method, and the phosphorus (P) concentration in this region is 1 × 10.²⁰~1×10²¹atoms / cm³And said. In the present specification, it is contained in the impurity regions 138 to 142 formed here. The concentration of the impurity element that imparts the n-type to be mixed (n)⁺). (Fig. 3 (B))

0032Phosphorus (P) or boron (B) already added in the previous step to the impurity regions 138 to 142 ) Is included, but phosphorus (P) is added at a sufficiently high concentration compared to that, so prework It is not necessary to consider the effect of phosphorus (P) or boron (B) added in the above. Also, impurities The concentration of phosphorus (P) added to region 138 is shown in Fig. 3 (A). Since the concentration of boron (B) added in is 1/2 to 1/3, p-type conductivity is ensured and TFT is used. It had no effect on the characteristics of.

0033Then, the n-type for forming the LDD region of the n-channel type TFT of the pixel matrix circuit. The step of adding impurities was performed. Here, the gate electrode 131 is used as a mask for self-adjustment. Impurity elements that together give n-type were added by the ion doping method. Concentration of phosphorus (P) to be added Degree is 1 x 10¹⁶~5×10¹⁸atoms / cm³2 (A) and 3 (A) and 3 (B) By adding at a concentration lower than the concentration of the impurity element added in), the impurity region 1 is substantially achieved. Only 43 and 144 are formed. In the present specification, it is included in these impurity regions 143 and 144. The concentration of the impurity element that gives the n-type is (n)^--). (Fig. 3 (C))

0034Then activate the impurity elements that impart the n-type or p-type added at the respective concentrations. Therefore, a heat treatment step is performed. This process is performed by Furnace anneal method, Laser annealing method, etc. Alternatively, it can be performed by the rapid thermal annealing method (RTA method). Furness here The activation step was carried out by the annealing method. The heat treatment has an oxygen concentration of 1 ppm or less, preferably 0.1. Performed at 400-800 ° C, typically 500-600 ° C in a nitrogen atmosphere below ppm In this example, the heat treatment was performed at 550 ° C for 4 hours. In addition, a quartz substrate is attached to the substrate 101. When using a heat-resistant material such as, heat treatment at 800 ° C for 1 hour is also acceptable. In addition, the activation of the impurity element and the impurity region and channel formation region to which the impurity element was added We were able to form a good bond.

0035In this heat treatment, the metal film 12 forming the gate electrodes 128 to 131 and the capacitance wiring 132 8b to 132b have a thickness of 5 to 80 nm from the surface and a conductive layer (C) 128c to 132c is formed. Made. For example, when the conductive layer (B) 128b to 132b is tungsten (W), it is nitrogenous. Tungsten oxide (WN) is formed, and in the case of tantalum (Ta), tantalum nitride (TaN) ) Can be formed. Further, the conductive layer (C) 128c to 132c is nitrogen or anne. Same even if the gate electrodes 128 to 131 are exposed to a plasma atmosphere containing nitrogen using monia or the like. Can be formed like this. In addition, 300-4 in an atmosphere containing 3-100% hydrogen A heat treatment was performed at 50 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. This work The process is the process of terminating the dangling bond of the semiconductor layer with thermally excited hydrogen. Another means of hydrogenation is plasma hydrogenation (using plasma-excited hydrogen). You may go.

0036A field in which an island-shaped semiconductor layer is formed from an amorphous silicon film by a crystallization method using a catalytic element. In this case, a small amount of catalytic element remained in the island-shaped semiconductor layer. Of course, even in such a state, TFT It can be completed, but at least removes residual catalytic elements from the channel formation region. It was better to leave. Phosphorus (P) is one of the means to remove this catalytic element. There was a means to utilize the tattering action. The concentration of phosphorus (P) required for gettering is shown in Fig. 3. Impurity region (n) formed in (B)⁺), And the heat of the activation process performed here By treatment, catalyst from the channel formation region of n-channel TFT and p-channel TFT I was able to getter the elements. (Fig. 3 (D))

0037FIGS. 6 (A) and 7 (A) are top views of the TFT in the steps up to this point, and are AA. The'cross section and C-C'cross section correspond to A-A'and C-C' in FIG. 3 (D). Also, B The -B'cross section and the D-D'cross section correspond to the cross sections of FIGS. 8 (A) and 9 (A). Figure The top view of 6 and 7 omits the gate insulating film, but at least the islands in the process up to this point. Gate electrodes 128 to 131 and capacitive wiring 132 are shown in the figure on the semiconductor layers 104 to 107. It is formed like a sea urchin.

0038After the activation and hydrogenation steps are completed, a second conductive film to be used as the gate wiring is formed. This second conductive film is mainly composed of aluminum (Al) and copper (Cu), which are low resistance materials. Conductive layer (D), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum It is preferable to form it with a conductive layer (E) made of (Mo). In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is used as a conductive layer. It was set to (D) 145, and a titanium (Ti) film was formed as a conductive layer (E) 146. Conductive layer (D ) 145 may be 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer. (E) 146 may be formed at 50 to 200 (preferably 100 to 150 nm). (Figure 4 (A))

0039Then, in order to form the gate wiring connected to the gate electrode, the conductive layer (E) 146 and the conductive layer (E) 146 are conducted. Etching the layer (D) 145 to separate the gate wiring 147, 148 and the capacitance wiring 149. Formed. Etching process is SiCl first₄And Cl₂And BCl₃Dora using a mixed gas with B. Remove from the surface of the conductive layer (E) to the middle of the conductive layer (D) by the etching method, and then phosphoric acid. By removing the conductive layer (D) by wet etching with the etching solution of the system, the lower part It was possible to form the gate wiring while maintaining the selective workability with the ground.

00406 (B) and 7 (B) show the top view of this state, A-A'cross section and C-C' cross section. Corresponds to A-A'and C-C' in Fig. 4 (B). Also, B-B'cross section and DD' The cross sections correspond to B-B'and D-D'in FIGS. 8 (B) and 9 (B). Figure 6 (B) And in FIG. 7 (B), a part of the gate wirings 147 and 148 is the gate electrodes 128 and 1. It overlaps with a part of 29 and 131 and is in electrical contact. This is the B-B'cross section and D- It is clear from the cross-sectional structural drawings of FIGS. 8 (B) and 9 (B) corresponding to the D'cross section, and the first derivation The conductive layer (C) forming the electric layer and the conductive layer (D) forming the second conductive layer are in electrical contact with each other. ing.

0041The first interlayer insulating film 150 has a thickness of 500 to 1500 nm and is a silicon oxide film or nitrogen oxide. The source region, which is formed of a siliconized silicon film and then formed on each island-shaped semiconductor layer. Form a contact hole that reaches the drain area, and the source wiring 151 to 154 and the drain Form in-wiring 155 to 158. Although not shown, in this embodiment, this electrode is referred to as Ti. Sputtering method for 100 nm film, 300 nm aluminum film containing Ti, 150 nm Ti film It was a laminated film with a three-layer structure that was continuously formed in.

0042Next, as the passivation film 159, a silicon nitride film, a silicon oxide film, or nitrogen is used. A silicon oxide film is formed with a thickness of 50 to 500 nm (typically 100 to 300 nm). To. When the hydrogenation treatment was carried out in this state, favorable results were obtained for improving the characteristics of the TFT. For example, heat treatment at 300 to 450 ° C for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. It is good to do the reason, or the same effect was obtained by using the plasma hydrogenation method. In addition, this At this position, a contact hole for connecting the pixel electrode and the drain wiring will be formed later. Therefore, an opening may be formed in the passivation film 159. (Fig. 4 (C))

0043Fig. 6 (C) and Fig. 7 (C) show the top view of this state, A-A'cross section and C-C' cutoff. The planes correspond to A-A'and C-C' in FIG. 4 (C). Also, B-B'cross section and D- The D'cross section corresponds to B-B'and D-D' in FIGS. 8 (C) and 9 (C). Figure 6 ( Although the first interlayer insulating film is omitted in C) and FIG. 7 (C), the island-shaped semiconductor layers 104 and 105 are shown. , 107 Source Wiring 151, 152, 1 in Unshown Source and Drain Regions 54 and drain wiring 155, 156, 158 are contacts formed in the first interlayer insulating film. It is connected through a hole.

0044After that, a second interlayer insulating film 160 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. To do. Organic resins include polyimide, acrylic, polyamide, polyimide amide, BC B (benzocyclobutene) or the like can be used. Here, after coating on the substrate, thermal polymerization It was formed by firing at 300 ° C. using a type of polyimide. And the second interlayer insulation A contact hole is formed in the film 160 to reach the drain wiring 158, and the pixel electrodes 161, 1 Form 62. If the pixel electrode is a transmissive liquid crystal display device, a transparent conductive film can be used. A metal film may be used in the case of a reflective liquid crystal display device. Transparent type in this embodiment Indium tin oxide (ITO) film to a thickness of 100 nm to make it a liquid crystal display device It was formed by a sputtering method. (Fig. 5)

0045In this way, the substrate having the TFT of the drive circuit and the pixel TFT of the display area is completed on the same substrate. I was able to make it. The drive circuit is a p-channel type TFT201, the first n-channel type T FT202, second n-channel type TFT203, pixel TFT204 in display area, holding capacity Quantity 205 formed. In the present specification, for convenience, such a substrate is referred to as an active matrix substrate. Call.

0046In the p-channel type TFT 201 of the drive circuit, the channel formation region 2 is formed in the island-shaped semiconductor layer 104. It has 06, source areas 207a and 207b, and drain areas 208a and 208b. In the first n-channel type TFT 202, the channel forming region 209, in the island-shaped semiconductor layer 105, LDD region 210 that overlaps with the gate electrode 129 (hereinafter, such an LDD region is referred to as Lov. ), It has a source area 211 and a drain area 212. Channel length of this Lov region The orientation length was 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. Second n channel In the le-type TFT 203, the island-shaped semiconductor layer 106 has a channel formation region 213 and an LDD region 21. It has 4,215, source area 216, and drain area 217. This LDD area is L The LDD region that does not overlap the ov region and the gate electrode 130 (hereinafter, such an LDD region is referred to as Lof. (Indicated as f) is formed, and the length of this Loff region in the channel length direction is 0.3 to 2.0 μm. It is preferably 0.5 to 1.5 μm. The pixel TFT 204 has an island-shaped semiconductor layer 107. Channel forming regions 218, 219, Loff regions 220-223, source or drain regions It has 224 to 226. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm. , Preferably 1.5 to 2.5 μm. In addition, capacitance wiring 132, 149 and gate failure An insulating film made of the same material as the peripheral film and connected to the drain region 226 of the pixel TFT204, n A retention capacity 205 is formed from the semiconductor layer 227 to which an impurity element that imparts a mold is added. There is. In Fig. 5, the pixel TFT204 has a double gate structure, but a single gate structure is also available. It is good, and a multi-gate structure in which a plurality of gate electrodes are provided may be used.

0047As described above, the present invention configures each circuit according to the specifications required by the pixel TFT and the drive circuit. By optimizing the structure of the TFT, it is possible to improve the operating performance and reliability of semiconductor devices. can do. Furthermore, by forming the gate electrode with a conductive material having heat resistance, Easy activation of LDD region, source region and drain region, gate wiring low resistance material By forming with, the wiring resistance can be sufficiently reduced. Therefore, the display area (screen size) is It can be applied to display devices of 4 inch class or larger.

0048[Embodiment 2] FIG. 16 is a diagram showing another embodiment of the gate electrode and the gate wiring. Gate electrode in FIG. And the gate wiring are formed in the same manner as in the process shown in the first embodiment, and the island-shaped semiconductor layer. It is formed above the 901 and the gate insulating film 902.

0049In FIG. 16 (A), the conductive layer (A) 903 is nitrogen-containing in the first conductive layer used as the gate electrode. Tantalum Nitride (TaN), Tungsten Nitride (WN), Titanium Nitride (TiN) Membrane, Mori Nitride Formed in butene (MoN). Conductive layer (B) 904 is tantalum (Ta), titanium (Ti) , Molybdenum (Mo), Tungsten (W), or the main component of the element Or an alloy film in which the above elements are combined, and on the surface thereof in the same manner as in the first embodiment. To form the conductive layer (C) 905. Conductive layer (A) 903 is 10 to 50 nm (preferably) 20 to 30 nm), and the conductive layer (B) 904 is 200 to 400 nm (preferably 250 to 250 nm). 350nm). The second conductive layer used for the gate wiring is aluminum, which is a low resistance material. A conductive layer (D) mainly composed of aluminum (Al) and copper (Cu), and titanium (Ti) and ta It is laminated with a conductive layer (E) formed of enthal (Ta) or the like. Aluminum (Al) Copper (Cu) diffuses easily by stress migration and electromigration Therefore, the silicon nitride film 908 with a thickness of 50 to 150 nm is applied so as to cover the second conductive layer. It is necessary to form.

0050FIG. 16B shows a gate electrode and a gate wiring manufactured in the same manner as in the first embodiment, and shows a gate. A phosphorus (P) -doped silicon film 909 is formed under the electrodes. The phosphorus (P) -doped silicon film 909 is a trace amount of alkali metal contained in the gate electrode. It has the effect of preventing elements from diffusing into the gate insulating film, and is intended to ensure the reliability of the TFT. It is useful.

0051FIG. 16 (C) shows a silico in which phosphorus (P) is doped in the first conductive layer forming the gate electrode. This is an example formed by the film 910. Phosphorus (P) -doped silicon film is another conductive metal material Although it is a high resistance material compared to the material, the second conductive layer forming the gate wiring is aluminum ( By forming with Al) or copper (Cu), it can be applied to large-area liquid crystal display devices. Wear. Here, the gate wiring is Ti film 911 100 nm, aluminum containing Ti ( Al) The film 912 has a three-layer structure formed at 300 nm and the Ti film 913 at 150 nm. Prevent direct contact between the minium (Al) film and the phosphorus (P) -doped silicon film As a result, heat resistance can be provided.

0052[Embodiment 3] FIG. 15 is a diagram for explaining the structure of the TFT of the present invention, and is a channel formation region of the semiconductor layer. It has a region, an LDD region, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The positional relationship between the gate electrode and the LDD region is explained in the TFT.

0053In FIG. 15 (A), channel formation region 209, LDD region 210, drain region 2 A semiconductor layer having 12 and a gate insulating film 120 and a gate electrode 129 on the semiconductor layer were provided. The configuration is shown. The LDD region 210 is connected to the gate electrode 129 via the gate insulating film 120. It is a Lov provided so as to overlap. Lov slows down the high electric field generated near the drain It has a summing effect, can prevent deterioration due to hot carriers, and shifts the control circuit. Suitable for use in n-channel TFTs such as star circuits, level shifter circuits, and buffer circuits. ing.

0054In FIG. 15 (B), the channel formation region 213, the LDD region 215a, 215b, and the do A semiconductor layer having a rain region 217, a gate insulating film 120 and a gate electrode on the semiconductor layer. Shows the configuration in which 130 is provided. The LDD region 215a passes through the gate insulating film 120. It is provided so as to overlap with the gate electrode 130. In addition, the LDD region 215b is an Loff provided so as not to overlap with the gate electrode 130. ing. Loff has the effect of reducing the off-current value, so a configuration with Lov and Loff is provided. By doing so, it is possible to prevent deterioration due to hot carriers and at the same time reduce the off-current value. , Suitable for use in n-channel TFTs of control circuit sampling circuits.

0055FIG. 15 (C) shows the channel formation region 219, the LDD region 223, and the drain in the semiconductor layer. Area 226 is provided. The LDD region 223 does not overlap with the gate electrode 131. It is the Loff provided in the pixel T, which makes it possible to effectively reduce the off current value. Suitable for use in FT. Not giving n type in LDD area 223 of pixel TFT The concentration of pure elements is 1/2 to 1/1 of the concentration of LDD regions 210 and 215 of the drive circuit. It is desirable to set it to 0.

0056[Embodiment 4] In the present embodiment, the active matrix type liquid crystal display device is used from the active matrix substrate. The process of making the table will be described. As shown in FIG. 11, the state of FIG. 5 produced in the first embodiment. An alignment film 601 is formed on the active matrix substrate. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. Opposing board on the opposite side A light-shielding film 603, a transparent conductive film 604, and an alignment film 605 were formed on the 602. Alignment film After forming, the liquid crystal molecules are subjected to a rubbing treatment to orient with a certain pretilt angle. I did. Then, the pixel matrix circuit and the active mat in which the CMOS circuit is formed Sealing material and spacers (both shown) are applied to the Rix substrate and the facing substrate by a known cell assembly process. Do not stick them together. After that, liquid crystal material 606 is injected between both substrates and completely sealed with a sealant (not shown). did. A known liquid crystal material may be used as the liquid crystal material. In this way, the act shown in FIG. The ive matrix type liquid crystal display device was completed.

0057Next, the configuration of this active matrix type liquid crystal display device is shown in the perspective view of FIG. 12 and FIG. 13 This will be described with reference to the top view of. Note that FIGS. 12 and 13 are cross-sectional structural views of FIGS. 1 to 5 and 11. A common code is used for association. In addition, the cross-sectional structure along E-E'shown in FIG. 13 The structure corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.

0058In FIG. 12, the active matrix substrate is a display formed on the glass substrate 101. It is composed of a region 306, a scanning signal drive circuit 304, and an image signal drive circuit 305. display Pixel TFT204 is provided in the area, and the drive circuit provided in the periphery is basically a CMOS circuit. It is configured as. The scanning signal drive circuit 304 and the image signal drive circuit 305 are respectively. The gate wiring 148 and the source wiring 154 are connected to the pixel TFT 204. Also, FPC The 731 is connected to the external input / output terminal 734, and the input wirings 302 and 303 drive the respective drives. Connected to the road.

0059FIG. 13 is a top view showing substantially one pixel of the display area 306. The gate wiring 148 is shown in the figure. It intersects the semiconductor layer 107 below it through a gate insulating film (not shown). Illustrated Although not, the semiconductor layer has a source region, a drain region, and n.^--Loff area consisting of area is shaped It is made. In addition, 163 is the contact part between the source wiring 154 and the source area 224, 164 is the contact part between the drain wiring 158 and the drain area 226, and 165 is the drain. It is a contact portion between the wiring 158 and the pixel electrode 161. Retention capacity 205 is pixel TFT20 Capacitive wiring 1 via the semiconductor layer 227 extending from the drain region 226 of 4 and the gate insulating film 1 It is formed in the area where 32 and 149 overlap.

0060The active matrix type liquid crystal display device of this embodiment has the structure described in the first embodiment. Although it was explained in light of the above, it can be freely combined with the configuration of the second embodiment to be an active mat. A lix-type liquid crystal display device can be manufactured.

0061[Embodiment 5] FIG. 10 is a diagram showing an example of the arrangement of the input / output terminals, the display area, and the drive circuit of the liquid crystal display device. .. In the display area 306, m gate wires and n source wires intersect in a matrix. To. For example, if the pixel density is VGA, there are 480 gate wires and 640 source wires. Formed, in the case of XGA, 768 gate wires and 1024 source wires are formed To. The screen size of the display area is 340 mm in diagonal length for the 13-inch class. , In the case of 18 inch class, it will be 460 mm. To realize such a liquid crystal display device Needs to form the gate wiring with a low resistance material as shown in Embodiment 1 and Embodiment 2. There is.

0062A scanning signal drive circuit 304 and an image signal drive circuit 305 are provided around the display area 306. It has been. The length of the gate wiring of these drive circuits also increases with the increase in the screen size of the display area. Since it is inevitably long, it is shown in the first and second embodiments in order to realize a large screen. It is preferably formed of such a low resistance material.

0063Further, in the present invention, the input wirings 302 and 303 connecting the input terminal 301 to each drive circuit Can be made of the same material as the gate wiring, which can contribute to lowering the wiring resistance. Wear.

0064[Embodiment 6] FIG. 14 shows the circuit configuration of the active matrix board shown in the first embodiment or the second embodiment. It is an example and is a figure which shows the circuit structure of the direct-view type display device. Active matrix of this example The circuit board is an image signal drive circuit 1001, a scanning signal drive circuit (A) 1007, and a scanning signal drive. It has a dynamic circuit (B) 1011, a precharge circuit 1012, and a display area 1006. still , The driving circuit described in this specification is an image signal driving circuit 1001, a scanning signal driving time. It is a general term including road (A) 1007.

0065The image signal drive circuit 1001 includes a shift register circuit 1002 and a level shifter circuit 100. 3. Equipped with buffer circuit 1004 and sampling circuit 1005. The scanning signal drive circuit (A) 1007 includes a shift register circuit 1008 and a level shifter. It is equipped with circuit 1009 and buffer circuit 1010. Scan signal drive circuit (B) 1011 It has a similar configuration.

0066The drive voltage of the shift register circuits 1002 and 1008 is 5 to 16V (typically 10V). The n-channel TFT of the CMOS circuit forming this circuit is shown in 202 in FIG. Structure is suitable. Also, level shifter circuits 1003, 1009 and buffer circuit 100 The drive voltage of 4 and 1010 is as high as 14 to 16V, but like the shift register circuit, the figure A CMOS circuit containing 5 n-channel TFT202s is suitable. In these circuits , If the gate is formed with a multi-gate structure, the withstand voltage will increase and the reliability of the circuit will be improved. It is valid.

0067The sampling circuit 1005 has a drive voltage of 14 to 16V, but the polarities are alternately inverted. Since it is driven and the off-current value needs to be reduced, the n-channel TFT20 shown in Fig. 5 is used. CMOS circuits including 3 are suitable. In Figure 5, only n-channel TFTs are displayed. Although not, in the actual sampling circuit, it is also formed by combining p-channel TFTs. To. At this time, the structure shown by 201 in the figure is sufficient for the p-channel TFT.

0068In addition, the pixel TFT204 has a drive voltage of 14 to 16V, which means that it can be used from the viewpoint of low power consumption. It is required to further reduce the off-current value than the pumping circuit, and the pixel TFT204 A structure having an LDD (Loff) region provided so as not to overlap with the gate electrode. It is desirable to make it.

0069The configuration of this embodiment is based on producing a TFT according to the process shown in the first embodiment. Can be easily realized. In this embodiment, only the display area and the configuration of the drive circuit are shown. However, according to the process of the first embodiment, there are other signal division circuits, frequency division circuits, and D / A. Signals from converters, γ correction circuits, operational amplifier circuits, memory circuits, arithmetic processing circuits, etc. It is possible to form a processing circuit or a logic circuit on the same substrate. Thus, the book The invention is a semiconductor device including a display area and its drive circuit on the same substrate, for example, a signal drive circuit. And a semiconductor device having a display area can be realized.

0070[Embodiment 7] The active matrix substrate and the liquid crystal display device produced by carrying out the present invention have various electric power. It can be used in an electro-optical device. Then, such an electro-optical device is assembled as a display medium. The present invention can be applied to all embedded electronic devices. As an electronic device, personal Computers, digital cameras, camcorders, personal digital assistants (mobile computers) , Mobile phones, e-books, etc.), navigation systems, etc. An example of them Is shown in FIG.

0071Figure 17 (A) shows a personal computer, which includes a microprocessor and memory. Main unit 2001, image input unit 2002, display device 2003, keyboard 2004 Made. The present invention can form a display device 2003 or other signal processing circuit.

0072FIG. 17B shows a video camera, which is the main body 2101, display device 2102, and audio input unit 2. It consists of 103, an operation switch 2104, a battery 2105, and an image receiving unit 2106. Book The invention can be applied to display devices 2102 and other signal control circuits.

0073FIG. 17 (C) shows a mobile information terminal, which is a main body 2201, an image input unit 2202, and an image receiving unit 22. It consists of 03, operation switch 2204, and display device 2205. The present invention is a display device 220 It can be applied to 5 and other signal control circuits.

0074FIG. 17 (D) shows a pre-recording medium (hereinafter referred to as a recording medium) on which the program is recorded. -Yar, main unit 2401, display device 2402, speaker section 2403, recording medium 24 It consists of 04 and operation switch 2405. The recording medium is DVD (Digital Versati). Playing music programs and displaying images using le Disc) or compact discs (CD) , Video games (or video games) and information display via the Internet Can be done. The present invention can be suitably used for a display device 2402 and other signal control circuits. it can.

0075Figure 17 (E) shows a digital camera, which is the main body 2501, the display device 2502, and the eyepiece 25. It consists of 03, operation switch 2504, and image receiving unit (not shown). The present invention is a display device 2 It can be applied to 502 and other signal control circuits.

0076As described above, the scope of application of the present invention is extremely wide, and it is applied to electronic devices in all fields. It is possible. What kind of combination of the electronic devices of this example is in Examples 1 to 6? It can also be realized by using a configuration consisting of.

0077[Embodiment 8] In the present embodiment, the same active matrix substrate as in the first embodiment is used for electroluminescence. Self-luminous display panel using essence (EL: Electro Luminescence) material (hereinafter, E) An example of manufacturing (referred to as L display device) will be described. Figure 18 (A) shows the EL display panel. The top view of is shown. In FIG. 18 (A), 10 is the substrate, 11 is the pixel part, and 12 is the source side drive. The driving circuit, 13 is the gate side drive circuit, and each drive circuit is F via wiring 14 to 16. It reaches PC17 and is connected to an external device.

0078A cross-sectional view corresponding to the A-A'line of FIG. 18 (A) is shown in FIG. 18 (B). At least at this time The facing plate 80 is provided above the pixel portion, preferably above the drive circuit and the pixel portion. Opposing plate 8 0 is the sealing material 19 and the active mat where the self-luminous layer using TFT and EL material is formed. It is attached to the Rix substrate. A filler (not shown) is mixed in the sealant 19. With this filler, two substrates are bonded together with an almost uniform interval. Further, the outside of the sealing material 19 and the upper surface and the periphery of the FPC 17 are sealed with the sealing agent 81. To do. The sealant 81 is made of silicone resin, epoxy resin, phenol resin, butyl rubber, etc. Use material.

0079In this way, the active matrix substrate 10 and the opposing substrate 80 are attached by the sealant 19. When they are put together, a space is formed between them. The space is filled with filler 83. The filler 83 also has the effect of adhering the facing plate 80. Filler 83 is PVC (Polyvinyl chloride) Nyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) EVA (ethylene vinyl acetate) or the like can be used. In addition, the self-luminous layer is water Since it is vulnerable to moisture and easily deteriorates, the inside of this filler 83 is dried with barium oxide or the like. It is desirable to mix a dry agent because it can maintain the hygroscopic effect. In addition, nitriding on the self-luminous layer A passivation film 82 formed of a recon film, a silicon oxide nitride film, or the like is formed, and a filler is formed. It has a structure that prevents corrosion due to alkaline elements contained in 83.

0080The facing plate 80 includes a glass plate, an aluminum plate, a stainless steel plate, and FRP (Fiberglass-Reinf). orced Plastics) board, PVF (polyvinyl fluoride) film, Mylar film ( DuPont brand name), polyester film, acrylic film or acrylic board, etc. Can be used. In addition, PVC film and Mylarf are made of tens of μm aluminum foil. Moisture resistance can also be improved by using a sheet with a structure sandwiched between ilms. In this way, E The L element is in a sealed state and is shielded from the outside air.

0081Further, in FIG. 18B, the TFT for the drive circuit (however, this) is placed on the substrate 10 and the base film 21. Here, a CMOS circuit that combines an n-channel TFT and a p-channel TFT is illustrated. There is. ) 22 and TFT23 for pixel part (However, here, TF that controls the current to the EL element Only T is shown. ) Is formed. Of these TFTs, especially the n-channel TF T has a decrease in on-current due to hot carrier effect, Vth shift and bias stress. An LDD region having the configuration shown in this embodiment is provided in order to prevent deterioration of characteristics due to the above.

0082For example, as TFT22 for a drive circuit, the p-channel type TFT201 and ncha shown in FIG. A flannel type TFT 202 may be used. In addition, the TFT of the pixel part depends on the drive voltage, If it is 10V or more, the first n-channel type TFT204 shown in Fig. 5 or a similar structure A p-channel type TFT having the above may be used. The first n-channel TFT202 is a dray The structure is provided with an LDD that overlaps with the gate electrode on the side of the gate, but the drive voltage is 1. If it is 0V or less, the deterioration of TFT due to the hot carrier effect can be almost ignored. There is no need to provide it.

0083To make an EL display device from the active matrix board in the state shown in Fig. 1, source wiring , An interlayer insulating film (flattening film) 26 made of a resin material is formed on the drain wiring, and pixels are formed on the interlayer insulating film (flattening film) 26. A pixel electrode 27 made of a transparent conductive film that is electrically connected to the drain of the TFT 23 for a part is formed. .. The transparent conductive film is a compound of indium oxide and tin oxide (called ITO) or oxidation. A compound of indium and zinc oxide can be used. Then, the pixel electrode 27 is formed. Then, the insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

0084Next, the self-luminous layer 29 is formed. The self-luminous layer 29 is a known EL material (hole injection layer, hole transfer). A laminated structure or a single layer by freely combining a sending layer, a light emitting layer, an electron transporting layer or an electron injecting layer) It may be a structure. A known technique may be used to determine the structure. Also, EL material There are low-molecular-weight materials and high-molecular-weight (polymer-based) materials. When using low molecular weight materials The vapor deposition method is used, but when a polymer-based material is used, the spin coating method, printing method or injection method is used. It is possible to use a simple method such as the Kujet method.

0085The self-luminous layer is a vapor deposition method using a shadow mask, an inkjet method, or a dispenser. Formed by law. In any case, a light emitting layer capable of emitting light having a different wavelength for each pixel (red emission) By forming the light layer, the green light emitting layer, and the blue light emitting layer), color display becomes possible. Other Also, a method that combines a color conversion layer (CCM) and a color filter, a white light emitting layer and color There is a method in which filters are combined, but any method may be used. Of course, monochromatic emission It can also be an EL display device.

0086After forming the self-luminous layer 29, the cathode 30 is formed on the self-luminous layer 29. Of the cathode 30 and the self-luminous layer 29 It is desirable to eliminate water and oxygen existing at the interface as much as possible. Therefore, it emits light in a vacuum. The layer 29 and the cathode 30 are formed continuously, or the self-luminous layer 29 is formed in an inert atmosphere to solve the atmosphere. It is necessary to devise such as forming the cathode 30 in a vacuum without releasing it. Multi in this embodiment By using a chamber type (cluster tool type) film forming device, the above-mentioned film formation can be performed. Make it possible.

0087In this embodiment, the cathode 30 is a LiF (lithium fluoride) film and Al (aluminium fluoride). M) Use a laminated structure of membranes. Specifically, 1 nm thick LiF (huh) is deposited on the self-luminous layer 29. A lithium chemical) film is formed, and a 300 nm-thick aluminum film is formed on the film. Of course, known The MgAg electrode, which is the cathode material of the above, may be used. And the cathode 30 is in the region indicated by 31 It is connected to the wiring 16. Wiring 16 supplies power to the cathode 30 to provide a predetermined voltage. It is a wire and is connected to the FPC 17 via an anisotropic conductive paste material 32. FPC17 A resin layer 80 is further formed on the resin layer 80 to increase the adhesive strength of this portion.

0088Intersection to electrically connect the cathode 30 and the wiring 16 in the region shown in 31 It is necessary to form contact holes in the peripheral film 26 and the insulating film 28. These are interlayer insulating films At the time of etching of 26 (when forming contact holes for pixel electrodes) And the insulating film 28 may be formed at the time of etching (when the opening is formed before the self-luminous layer is formed). .. Also, when etching the insulating film 28, even if the interlayer insulating film 26 is etched all at once. good. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the contact ho The shape of the wheel can be made good.

0089Further, the wiring 16 has a gap between the sealing material 19 and the substrate 10 (however, it is closed by the sealing agent 81). To. ) To be electrically connected to FPC17. In addition, wiring 16 is explained here. However, the other wires 14 and 15 also pass under the sealant 18 and send electricity to FPC17. Be connected in an airy manner.

0090Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 19, a top surface structure is shown in FIG. 20 (A), and a circuit diagram. Is shown in FIG. 20 (B). In FIG. 19 (A), the switchon provided on the substrate 2401. The TFT 2402 for operation is formed with the same structure as the pixel TFT 204 of FIG. 5 of the first embodiment. Dub By adopting a lugate structure, two TFTs are substantially connected in series, and the gate electrode and the gate electrode are used. To reduce the off-current value by forming an LDD with offset regions that do not overlap. There is an advantage that it can be done. Although the double gate structure is used in this embodiment, it is triple. A gate structure or a multi-gate structure having more gates may be used.

0091For the current control TFT2403, the first n-channel type TFT202 shown in FIG. 5 is used. To form. This TFT structure is an LD that overlaps with the gate electrode only on the drain side. The structure is provided with D, which reduces the parasitic capacitance and series resistance between the gate and drain to reduce the current. It has a structure that enhances the driving ability. From another point of view, structure is very important. Have a taste. Because the current control TFT is an element for controlling the amount of current flowing through the EL element. Even for devices that carry a large amount of current and have a high risk of deterioration due to heat or hot carriers. is there. Therefore, the current control TFT should be provided with an LDD region that partially overlaps the gate electrode. It is possible to prevent the deterioration of the TFT and improve the stability of operation. At this time, for switching The drain wire 35 of the TFT 2402 is connected to the gate electrode 37 of the TFT for current control by wiring 36. Is electrically connected to. The wiring indicated by 38 is the switching TFT240. It is a gate wire that electrically connects the gate electrodes 39a and 39b of 2.

0092Further, in this embodiment, the current control TFT2403 is illustrated with a single gate structure. , A multi-gate structure in which multiple TFTs are connected in series may be used. In addition, multiple TFTs Can be connected in parallel to substantially divide the channel formation region into multiple parts, and heat can be radiated with high efficiency. The structure may be such that. Such a structure is effective as a countermeasure against deterioration due to heat.

0093Further, as shown in FIG. 20 (A), it becomes the gate electrode 37 of the current control TFT 2403. The wiring is the area indicated by 2404, and the drain wire 40 and the insulating film of the current control TFT 2403. Overlap through. At this time, a capacitor is formed in the region indicated by 2404. this Capacitor 2404 is for holding the voltage applied to the gate of TFT 2403 for current control. Functions as a capacitor. The drain line 40 is in contact with the current supply line (power supply line) 2501. It continues, and a constant voltage is constantly applied.

0094First passive on top of TFT 2402 for switching and TFT 2403 for current control An ion film 41 is provided, and a flattening film 42 made of a resin insulating film is formed on the film. Flattening It is very important to flatten the step by TFT using the film 42. Formed later Since the self-luminous layer is very thin, the presence of a step may cause light emission failure. Therefore, the self-luminous layer is flattened before forming the pixel electrodes so that the self-luminous layer can be formed on a flat surface as much as possible. It is desirable to keep it.

0095Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film, which controls current. It is electrically connected to the drain of TFT2403. Aluminum as the pixel electrode 43 Use a low resistance conductive film such as an alloy film, a copper alloy film or a silver alloy film, or a laminated film thereof. Is preferable. Of course, a laminated structure with another conductive film may be used. Also, an insulating film (preferably a tree) Light emission in grooves (corresponding to pixels) formed by banks 44a and 44b formed of fat) Layer 44 is formed. Although only one pixel is shown here, R (red) and G (green) , B (blue) light emitting layers corresponding to each color may be made separately. As an organic EL material for the light emitting layer A π-conjugated polymer-based material is used. As a typical polymer-based material, polyparapheni Lembinirene (PPV) -based, polyvinyl carbazole (PVK) -based, polyfluorene-based Which can be mentioned. There are various types of PPV-based organic EL materials, for example, " H. Shenk, H.Becker, O.Gelsen, E.Kluge, W.Kreuder, and H.Spreitzer, Polymers for Ligh t Emitting Diodes , Euro Display, Proceedings, 1999, p.33-37 and JP-A-10-925 A material as described in Japanese Patent Application Laid-Open No. 76 may be used.

0096As a specific light emitting layer, cyanopolyphenylene vinylene is used as the light emitting layer that emits red light. Polyphenylene vinylene for the light emitting layer that emits green light, and polyphenylene for the light emitting layer that emits blue light Nilenbinylene or polyalkylphenylene may be used. Film thickness is 30 ~ 150nm (Preferably 40 to 100 nm). However, the above example should be used as a light emitting layer. It is an example of an organic EL material that can be produced, and there is no need to limit it to this. Light emitting layer, electricity Self-luminous layer (light emission and carrier for it) by freely combining a cargo transport layer or a charge injection layer It suffices to form a layer) for carrying out the movement of. For example, in this example, a polymer-based material is used. Although an example of using it as a light emitting layer is shown, a low molecular weight organic EL material may be used. Also, charge transfer It is also possible to use an inorganic material such as silicon carbide as the sending layer or the charge injection layer. These organic Known materials can be used as the EL material and the inorganic material.

0097In this example, PEDOT (polythiophene) or PAni (polya) is placed on the light emitting layer 45. It is a self-luminous layer having a laminated structure provided with a hole injection layer 46 made of nirin). And hole injection An anode 47 made of a transparent conductive film is provided on the entry layer 46. In the case of this embodiment, the light emitting layer 45 Since the light generated in is emitted toward the upper surface side (toward the upper side of the TFT), the anode is Must be translucent. As a transparent conductive film, a compound of indium oxide and tin oxide A compound of indium oxide and zinc oxide can be used, but a light emitting layer having low heat resistance or positive Since it is formed after the pore injection layer is formed, it is preferable that the film can be formed at the lowest possible temperature.

0098The self-luminous element 2405 is completed when the anode 47 is formed. The EL here Element 2405 is formed by a pixel electrode (cathode) 43, a light emitting layer 45, a hole injection layer 46, and an anode 47. Refers to the capacitor made. As shown in FIG. 20 (A), the pixel electrode 43 is approximately the area of the pixel. Since they match, the entire pixel functions as an EL element. Therefore, the utilization efficiency of light emission is very high, and a bright image can be displayed.

0099By the way, in this embodiment, a second passivation film 48 is further provided on the anode 47. There is. As the second passivation film 48, a silicon nitride film or a silicon oxide film is preferable. .. The purpose is to block the outside from the EL element, and the deterioration of the organic EL material due to oxidation. It has both the meaning of preventing the problem and the meaning of suppressing the degassing from the organic EL material. This will The reliability of the EL display device is improved.

0100As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. A switching TFT with a sufficiently low off-current value and a strong current for hot carrier injection It has a control TFT. Therefore, it has high reliability and can display a good image. L display panel is obtained.

0101FIG. 19B shows an example in which the structure of the self-luminous layer is inverted. TFT2601 for current control is shown in the figure. It is formed with the same structure as the p-channel type TFT201 of 5. See Embodiment 1 for fabrication process Just do it. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically Uses a conductive film made of a compound of indium oxide and zinc oxide. Of course, with indium oxide A conductive film made of a compound with tin oxide may be used.

0102Then, after the banks 51a and 51b made of the insulating film are formed, polyvinyl is applied by solution coating. A light emitting layer 52 made of carbazole is formed. On top of that is potassium acetylacetone The electron injection layer 53 made of (denoted as acacK) and the cathode 54 made of aluminum alloy It is formed. In this case, the cathode 54 also functions as a passivation film. In this way EL Element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is indicated by an arrow. It is radiated toward the substrate on which the TFT is formed. Structure like this example In this case, the current control TFT2601 is preferably formed by a p-channel type TFT.

0103The EL display device shown in this embodiment as described above serves as a display unit for the electronic device of the seventh embodiment. Can be used.

0104[Embodiment 9] In this embodiment, an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 20 (B) is used as an example. This is shown in FIG. In this embodiment, 2701 is a switching TFT 270. 2 source wiring, 2703 is the gate wiring of TFT2702 for switching, 2704 is the electric Flow control TFT, 2705 is a capacitor, 2706, 2708 is a current supply line, 2707 is Use as an EL element.

0105FIG. 21 (A) shows an example in which the current supply line 2706 is shared between the two pixels. Immediately The special feature is that the two pixels are formed so as to be line-symmetrical with respect to the current supply line 2706. There is a sign. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined. Can be refined.

0106In addition, FIG. 21 (B) shows the case where the current supply line 2708 is provided in parallel with the gate wiring 2703. Is an example of. In Fig. 21 (B), if the current supply line 2708 and the gate wiring 2703 overlap. The structure is provided so that there is no wiring, but if the wiring is formed in different layers, it is insulated. It can also be provided so as to overlap with each other via a membrane. In this case, power supply line 2708 and gate arrangement Since the occupied area can be shared with the line 2703, the pixel part can be further improved in definition. Can be done.

0107Further, in FIG. 21 (C), the current supply line 2708 is gated in the same manner as in the structure of FIG. 21 (B). It is provided parallel to the 2703, and the two pixels are line-symmetrical with respect to the current supply line 2708. It is characterized in that it is formed in this way. Also, connect the current supply line 2708 to the gate wiring 2703. It is also effective to provide it so that it overlaps one of them. In this case, reduce the number of power supply lines Therefore, the pixel portion can be further improved in definition. Fig. 21 (A), Fig. 21 ( In B), the capacitor 2 is used to hold the voltage applied to the gate of the current control TFT 2704. Although the structure is such that the 705 is provided, the capacitor 2705 can be omitted.

0108The n-channel type T of the present invention as shown in FIG. 19 (A) as a current control TFT 2403. Since FT is used, the gate electrode (L provided so as to overlap with the gate electrode) is provided via the gate insulating film. It has a DD area. Parasites commonly referred to as gate capacitance in this overlapping region Although the amount is formed, in this embodiment, this parasitic capacitance is positively used as a substitute for the capacitor 2404. It is characterized in that it is used as a target. The capacitance of this parasitic capacitance is the above gate electrode and LDD area. Since the area changes with the overlapping area, the LDD area included in the overlapping area It depends on the length. Similarly, the structures shown in FIGS. 21 (A), (B), and (C) are also controlled. It is possible to omit the denter 2705.

0109The circuit configuration of the EL display device shown in the present embodiment is based on the TFT configuration shown in the first embodiment. It may be selected to form the circuit shown in FIG. Further, as a display unit of the electronic device of the seventh embodiment. It is possible to use the EL display panel of this embodiment.

<p num="0110"> As shown in the first embodiment, the gate electrode and the gate wiring of the TFT are provided outside the island-shaped semiconductor layer. They are in contact with each other without passing through a contact hole. In such a structure Tables 1 and 2 show the results of evaluating the resistance between the gate electrode and the gate wiring. Table 1 shows the gate electrodes And the sheet resistance value of the material forming the gate wiring is shown.</p><p num="0111"><tables num="1"><img id="000002" he="44" wi="150" file="JP6022016B2_D0001.tif" img-format="tif" img-content="drawing" /></tables></p><p num="0112"> Table 2 shows the contact chain to evaluate the contact resistance between the gate electrode and the gate wiring. (Number of contacts 100 to 200) is formed, and from the measured value, per contact part The result of finding the contact resistance is shown. The area of each contact is 4 μm x 10 μm. Was 6 μm × 10 μm.</p><p num="0113"><tables num="2"><img id="000003" he="44" wi="150" file="JP6022016B2_D0001.tif" img-format="tif" img-content="drawing" /></tables></p><p num="0114"> Two types of gate electrodes were prepared: a film in which a TaN film and a Ta film were laminated, and a W film. Gate wiring Formed with Al. However, 1% by weight of Nd is added to this Al (hereinafter, Al-Nd). Notated as a membrane). From the values shown in Table 2, the area of the overlap between the gate electrode and the gate wiring is 40μ. Assuming m2, it is about 200Ω for a film in which a TaN film and a Ta film are laminated, and about 0.1Ω for a W film. became.</p><p num="0115"> FIG. 22 shows a superposition of an Al-Nd film and a gate electrode formed by laminating a TaN film and a Ta film. The bottom was observed with a transmission electron microscope (TEM). Show the fruit. Fig. 23 is an enlarged observation of the interface between the Ta film and the Al-Nd film, which is shown in the figure. Energy Dispersion X (EDX) at points * 1 to * 4 -The composition was examined by ray Spectroscopy). As a result, * 1 is Al and * 4 is Ta. Although it was confirmed that, Al and oxygen were detected in * 2, and Ta and oxygen were detected in * 3, respectively. It was found that a layer containing an oxide was formed. The cause of this is the gate electrode After forming the Ta film, a heat treatment step is performed to activate the impurity elements. Therefore, it is considered that this is because the surface of the Ta film is oxidized. In addition, it forms an Al-Nd film Then, it is considered that the oxygen on the surface of the Ta film oxidizes the Al-Nd film. This The increase in contact resistance was a result that was particularly noticeable when Ta was used.</p><p num="0116"> However, when examining the effect of contact resistance on the signal waveform by simulation, It was confirmed that about 200Ω does not have much effect. Figures 26 (A) and (B) are The change of the rising waveform and the falling waveform depending on the resistance value is shown. Equivalent circuit used in the calculation Is inserted in the figure. Here, R2 corresponding to the contact resistance is set from 1Ω to 1MΩ. It was calculated by changing it, but it was confirmed that there was almost no effect of contact resistance up to about 10 kΩ. We were able to.</p><p num="0117"> In addition, an energization test is conducted as a reliability test of the contact part to investigate changes in contact resistance. It was. Prepare a test sample with a contact area of 40 μm2 and 200 contacts, 1 A 1 mA current was applied for 1 hour in an atmosphere of 80 ° C. About the above two types of gate electrode materials Upon examination, almost no change in contact resistance was observed. </p>

<p num="0118"> The reliability of the manufactured TFT is adjusted by the bias-heat stress test (hereinafter referred to as BT test). It was solid. The size of the TFT is 8 μm in channel length and 8 μm in channel width. The test condition is n cha Hold for 1 hour at 150 ° C with gate voltage + 20V and drain voltage 0V for flannel type TFT. I had it. Figures 24 (A) and 24 (B) show the connection between the n-channel TFT and the p-channel TFT, respectively. Although it shows results, in any case, almost no deterioration due to bias stress is observed.</p>

<p num="0119"> The effect of signal delay due to the difference in the material of the gate wiring was evaluated. Figure 25 shows the input and end The signal waveforms are shown, Fig. 25 (A) shows the rising waveform, and Fig. 25 (B) shows. Shows a falling waveform. The distance between the input part and the end part is 83 mm. In Figure 25 The characteristic described as J2 is expressed as J4 by laminating the TaN film and Ta film to form the gate wiring. The sample was a sample in which the gate wiring was formed with an Al-Nd film. The width of the gate wiring is It is 10 μm. In the former sample, the rise and fall times of the input and end parts In contrast to the large difference in the latter sample, the difference is very small. Table 3 The result of summarizing the delay time is shown in. The delay time of the J2 sample is about 10 of the J4 sample. It is doubled, and as is clear from the sheet resistance values shown in Table 1, the resistance of the wiring material has an effect. It can be judged that there is.</p><p num="0120"><tables num="3"><img id="000004" he="43" wi="131" file="JP6022016B2_D0001.tif" img-format="tif" img-content="drawing" /></tables></p><p num="0121"> From this result, when the screen size is 4 inches or more, the gate electric power is used as in the present invention. It was shown that the gate wiring connecting to the poles should be made of low resistance material.</p>

0122101 board 102 Base film 103b Crystalline semiconductor layer 104-107 island-shaped semiconductor layer 128 ~ 131 Gate electrode, 132 Capacitive wiring 128a ~ 132a Conductive layer (A) 128b ~ 132b Conductive layer (B) 128c ~ 132c Conductive layer (C) 147, 148 Gate wiring, 149 Capacitive wiring 147a ~ 149a Conductive layer (D) 147b ~ 149b Conductive layer (E) 150 First interlayer insulating film 151 ~ 154 Source wiring 155 ~ 158 Drain electrode 159 Passivation membrane 160 Second interlayer insulating film 161, 162 pixel electrodes