Apparatuses and methods for combining error coding and modulation schemes

The present disclosure relates generally to semiconductor memory devices and methods, and more specifically to devices and methods for combining error coding schemes and modulation schemes.

Memory devices are typically provided as internal semiconductor integrated circuits within a computer or other electronic device. Among other things, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Resistive Random Access Memory (eg, RRAM®), and Flash. There are many different types of memory, including memory.

Memory devices are used as volatile and non-volatile data storage for a wide range of electronic applications. Flash memory, which is just one type of memory, typically includes a large array of memory cells, enabling high memory density, high reliability, and low power consumption. Non-volatile memory shall be used in portable music players such as personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, mobile phones, MP3 players, movie players, and other electronic devices. Can be done.

<figref num="1">FIG. 3 is a block diagram of a device in the form of a computing system, including at least one memory system, according to some embodiments of the present disclosure.</figref><figref num="2">FIG. 6 is a functional block diagram showing a combination of signal set extension and low density parity check (LDPC) code according to some embodiments of the present disclosure.</figref><figref num="3">It is a figure which shows the trellis generated according to some embodiments of this disclosure.</figref>

Methods and devices for combining error coding schemes and modulation schemes are provided. One example method is to encode data using linear error correction code, modulate the encoded data, write the modulated data to memory, and the Viterbi algorithm and linear error. It may include decoding the written data using a correction code decoder.

Bose, Chaudhuri, and Hocquenghem (BCH) codes can be used to correct a certain number of errors in the flash data. Low density parity check (LDPC) codes can outperform these BCH codes. For example, the LDPC code can be decrypted by soft data (eg, reliability information).

As the storage density increases, the signal-to-noise ratio (SNR) associated with the read operation can decrease, for example, leading to the need for stronger error correction code to prevent read errors. .. One approach to increasing signal-to-noise ratio includes, for example, extension of the signal set by trellis coded modulation (TCM). For example, extending the signal set may include converting binary data to multi-level data.

The embodiments of the present disclosure may provide an increase in SNR by combining LDPC and TCM. The embodiment can also increase the SNR gain by effectively using the soft data generated by the decoder in conjunction with the soft data generated by the Viterbi component.

In the following detailed description of the present disclosure, references are made to the accompanying drawings that form part of the present disclosure, and how one or more embodiments of the present disclosure are implemented in the accompanying drawings. The illustration shows whether or not it can be done. These embodiments are described in sufficient detail to allow one of ordinary skill in the art to implement the embodiments of the present disclosure, and other embodiments may be utilized, and the present disclosure. It is understood that process, electrical, and / or structural changes can be made without departing from scope. As used herein, the indicator "N" indicates that one or more of the particular features so designed may be included with respect to one or more embodiments of the present disclosure. ..

The figures herein follow a numbering convention in which one or more first digits correspond to drawing numbers and the remaining digits identify elements or components in the drawing. Similar elements or components between different figures can be identified by the use of similar digits. As will be appreciated, the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated to provide some further embodiments of the present disclosure. Moreover, the proportions and relative scales of the elements provided in the figures are intended to indicate the various embodiments of the present disclosure and are not used in a restrictive sense.

FIG. 1 is a block diagram of a device in the form of a computing system 100 including at least one memory system 104, according to some embodiments of the present disclosure. As used herein, the memory system 104, controller 108, or memory device 110 can also be considered separately as "apparatus". The memory system 104 is, for example, a solid state drive (SSD) and provides a host (eg, physical) interface 106, a controller 108 (eg, a processor and / or other control circuit element), and a storage volume for the memory system 104. May include several memory devices 110-1, ..., 110-N (eg, solid-state memory devices such as NAND flash devices). In another embodiment, the memory system 104 may simply be a single memory device.

As shown in FIG. 1, controller 108 is coupled to host interface 106 and memory devices 110-1, ..., 110-N via multiple channels to transfer data between memory system 104 and host 102. Can be used to transfer. Interface 106 can be in the form of a standard interface. For example, when the memory system 104 is used for data storage in the computing system 100, the interface 106, among other connectors and interfaces, is a serial advanced technology attachment (SATA), peripheral. Peripheral component interconnect It can be express) (PCIe) or universal serial bus (USB). However, in general, the interface 106 may provide an interface for passing controls, addresses, data, and other signals between the memory system 104 and the host 102 having compatible receptors for the interface 106.

The host 102 can be a host system such as a personal laptop computer, desktop computer, digital camera, mobile phone, or memory card reader, among various other types of hosts. Host 102 includes a system motherboard and / or backplane and may include several memory access devices (eg, some processors). The host 102 can also be a memory controller, such as when the memory system 104 is a memory device (eg, having an on-die controller).

Controller 108 communicates with some memory devices 110-1, ..., 110-N (in some embodiments, it can be several memory arrays on a single die) and other operations. In, you can control data read, write, and erase operations. In some embodiments, the controller 108 may be on the same or different dies as any or all of the memory devices 110 of some memory devices 110.

Although not specifically shown, in some embodiments, the controller 108 may include a discrete memory channel controller for each channel that couples the controller 108 to memory devices 110-1, ..., 110-N. Controller 108 may, for example, control access to some memory devices 110-1, ..., 110-N and / or host 102 and memory devices 110-1, ..., 110-N. It may include several components in the form of hardware and / or firmware (eg, one or more integrated circuits) and / or software to facilitate data transfer to and from.

As shown in FIG. 1, the controller 108 includes an error coding component 107 (eg, an encoder such as an error correction code (ECC) engine) and a modulation component 109 (eg, for use in TCM). Can include. Each of the error coding component 107 and the modulation component 109 can be a discrete component such as an application specific integrated circuit (ASIC), or the component does not necessarily have a discrete physical form away from the rest of the controller 108. It can reflect the functionality provided by the circuit elements in controller 108 that it does not have. Although not shown as components within controller 108 in FIG. 1, error coding component 107 and modulation component 109, respectively, may be outside of controller 108, or some components located within controller 108 and controller 108. It may have several components located outside of.

The error coding component 107 encodes the data received from the host 102 (eg, user data) and stores it in memory such as memory devices 110-1, ..., 110-N (eg, written). ) Can be configured. For example, user data can be encoded using a linear error correcting code, such as an LDPC code, as described in more detail herein.

The encoded data may have a code rate corresponding to the encoded data. Code rate refers to the percentage of encoded data that is non-redundant. In some embodiments of the present disclosure, the binary encoded data can be converted into a multi-level signal (eg, a 3-level signal). For example, an extension of the signal set from 2 to 3 can be used, which can increase the Euclidean distance between the pairs of the closest signal sequences within the 3-level domain, without code rate loss.

In some embodiments, the controller 108 uses a linear error correction code encoder to encode the binary data, uses a modulation scheme to convert the binary data to multi-level data, and writes the multi-level data to memory. , The data may be read from memory, the read data may be decoded using the Vitabi algorithm, and the linear error correction code decoder may be configured to decode the hard and soft data generated by the Vitabi algorithm. Binary data is encoded using LDPC code and the modulation scheme used to convert the binary data can include TCM. The Viterbi algorithm is a soft-output Viterbi algorithm. The linear error correction code decoder may include an LDPC decoder, including algorithm) (SOVA). In some embodiments, the controller 108 may be configured to iteratively exchange soft data between the SOVA and the LDPC decoder. SOVA can differ from the typical Viterbi algorithm in that it uses a modified path metric that takes into account the former (former) probability of the input symbol and produces a soft output that indicates the reliability of the decision. Further functionality associated with controller 108 is described in more detail herein.

Some memory devices 110-1, ..., 110-N may include several arrays of memory cells (eg, non-volatile memory cells). The array can be, for example, a flash array with a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. Memory cells can be grouped into blocks containing, for example, some physical pages. Some blocks may be contained in a plane of a memory cell and the array may contain several planes. As an example, a memory device can be configured to store 8 KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device. ..

During operation, the data may be written to and / or read from memory (eg, memory devices 110-1, ..., 110-N of system 104), for example as pages of data. Therefore, a page of data can be referred to as the data transfer size of the memory system. Data can be transferred from / to a host (eg, host 102) within a data segment called a sector (eg, host sector). Therefore, the sector of data can be referred to as the host's data transfer size.

A page of data can contain user data (eg, a data payload containing several sectors of data) as well as some bytes of metadata corresponding to the user data, but the size of the page of data is often that of the user data. Can only refer to the number of bytes. As an example, a page of data with a page size of 4KB will have 4KB of user data (eg 8 sectors assuming a sector size of 512B) and some bytes of metadata corresponding to the user data (eg 32B, 54B). , 224B, etc.) can be included. The metadata includes completeness data such as error data (eg, error detection and / or correction code data) and / or address data (eg, logical address data), among other metadata corresponding to user data. obtain.

FIG. 2 is a functional block diagram 220 related to combining a signal set extension (eg, TCM) with an LDPC code according to some embodiments of the present disclosure. LDPC codes provide increased error correction capability compared to algebraic error correction codes (eg, BCH codes) and can be decrypted as well, for example, along with soft data.

In some embodiments, the combination of the LDPC code and the signal set extension may result in an SNR gain compared to the SNR achieved using the LDPC code alone or the signal set extension alone. For example, a binary LDPC code for a single level cell at a given rate without signal set expansion can increase the SNR by about 7 times with a given code rate loss. Similarly, a non-LDPC code at the same or similar given rate with signal set expansion can increase the SNR by a factor of 9 with the same or similar given code rate loss. However, in some embodiments, a binary LDPC code at the same or similar given rate that has undergone a signal set extension (eg, from level 2 to level 3) has the same or similar code rate loss. The SNR can be increased by about 18 times in the state.

Figure 2 shows the host data 211-1 (eg, binary host data) H received by the linear error correction code encoder 214 (eg, LDPC encoder)._kIs shown. The host data 212-1 is encoded by the LDPC encoder 214 and the encoded data U._k216-1 will be provided to Precoder 218. Precoder 218 performs a precoding operation on the encoded data 216-1.

As an example, a precoded operation is a binary encoded data (eg, U)._k216-1) precoded data (eg V_k) Can be a (1 / (1xorD)) operation. Precoded data V output by precoder 218_kIs received by operator 224. Operator 224 is a binary precoded data V by the (1 + D) operation._kThe multi-level data 226 (eg X_k) Can be converted. Therefore, the signal set is extended from a binary domain (eg, 2 levels) to a multi-level domain (eg, 3 levels). As an example, U_kX that can be 3 levels equivalent to data 216-1_kData 226 can be written to memory (eg, flash memory).

In the example operation, D can accommodate a delay of one unit. For example, in one operation yn = xn + x (n-1), the current sample xn is added to the previous sample x (n-1). This can be represented by the expression (1 + D). "1" represents the current sample (xn) and D represents the delay of one unit (eg x (n-1)).

In the example shown in Figure 2, the combination of the (1 / (1xorD)) predecessor operation and the (1 + D) operation is used in connection with the TCM to extend the signal set (eg, multi-level data of binary data). Convert to). Signal set expansion can, for example, increase the Euclidean distance between pairs of closest signal sequences in a three-level domain. In some embodiments, signal set expansion can be achieved without the code rate loss associated with LDPC. During signal set expansion (eg, TCM), a multi-level trellis can be generated that can include several states (eg, 3 level trellis in 2 states), the example of which is discussed in more detail with respect to FIG. ..

Multi-level data X_kSignal noise associated with n_k(For example, X_k+ n_k) Can be read from memory 210 and decrypted by the Viterbi component 234. In some embodiments, the Viterbi component 234 also produces soft data (eg, log likelihood ratio (LLR)) corresponding to the read data 232, as shown in FIG. It can be a SOVA capable (eg, a two-state SOVA). The soft data generated by the Viterbi component 234 may include LDPC code bits, along with reliability metrics corresponding to the LDPC code bits. The LLR can be used to compare the fit of two models (eg, "0" and "1") in a code sequence. For example, if the probability that a bit is "0" is 0.7 and the probability that a bit is "1" is 0.3, then LLR is equivalent to the logarithm (0.7 / 0.3).

Decrypted hard data and soft data U_kIs output from the Viterbi component 234 and can be further decoded using the LDPC decoder 236. The resulting decrypted host data H_k212-1 may be provided to the requesting entity (eg, a host such as host 102 shown in FIG. 1). In some embodiments, the decoded host data 212-2 contains, for example, an increased SNR gain compared to past LDPC approaches.

In some embodiments, repetitive soft data exchange between the Viterbi component 234 and the LDPC decoder 236 is U._kIt can be introduced to further refine the soft data related to 216-2. For example, the LDPC decoder 236 may also generate soft data (eg, LLR). For example, the LDPC decoder 236 has host data H._kIt outputs soft data with 212-2, which may be sent to the Viterbi component 234 for further decoding and then returned to the LDPC decoder 236 (eg, in an iterative process). In some embodiments, this iterative process can continue until the noise associated with data 216-2 is reduced, for example, to the desired threshold level.

FIG. 3 shows a trellis 330 that can be produced according to one embodiment of several embodiments of the present disclosure. As an example, the trellis 330 can be generated through operations performed by components such as components 218 and 224 shown in FIG. The trellis 330 is a two-state (eg, state 1 and state 0) Viterbi trellis that can be used in a TCM modulation scheme, also called trellis modulation. TCM can result in increased transmission efficiency compared to other modulation schemes.

In the example shown in FIG. 3, the LDPC encoder 314 can be used to encode the data (eg, host data 212-1). The encoded data can undergo a TCM so that the signal set extends (eg, from a binary domain to a three-level domain). For example, as described in connection with FIG. 2, the combination of (1 / (1xorD)) and (1 + D) operations is performed on the data output from 314, which includes signal expansion and trellis 330, etc. Can result in the production of trellis. As a result, the square Euclidean distance between the two closest three-level signal sequences in the two-state trellis 330 can be twice the distance of the uncoded three-level signal sequence. In some embodiments, the level of the trellis 330 may include a voltage value of about 4-3 volts.

The trellis 330 is "state 0" (eg, states 338-1, 338-2, and 338-3) and "state 1" (eg, states 342-1, 344-2,). And 2 states including 342-3). Each line between the states shown in FIG. 3 indicates a sequence path, and each path is represented by a bit (eg, LDPC encoder output bit) and a corresponding 3-level signal. For example, paths 344-1 and 344-2 indicate bit "0" with a corresponding three-level signal of "0". Similarly, for example, paths 384-1 and 384-2 represent corresponding three-level signals of bits "0" and "2", while paths 346-1 ... 346-4 are of "1". Indicates bit "1" with the corresponding 3-level signal.

A three-level label sequence on the edge of the path formed by state sequence 0-0-0 is given by 0-0 (eg, paths 344-1 and 344-2), while state sequence 0-1- A three-level label sequence on the edge of the path formed by 0 can be given by 1-1 (eg, paths 346-1 and 346.2). In these examples, the squared Euclidean distance between the two paths is equal to 2. For example, (1-0)²+(1-0)²= 2. The other path pair will always have a longer distance between the two paths.

The trellis 330 may include a level of trellis that has a particular relationship with at least one other level of trellis. For example, the binary user data U in Figure 2._k216 is a three-level data X based on the (1 / (1xorD)) operation performed by the precoder 218 in FIG. 2 and the (1 + D) operation performed by the operator 224 in FIG._kCan be related to 226. The relationships achieved by these operations are noise robustness (eg, SNR gain) compared to unextended signal sets (eg, 2-level, 3-level, or 4-level data) that correspond to levels that are independent of each other. Can bring.

In Figure 3, the values for routes 344-1, 344-2, 346-1, 346.2, 346-3, 346-4, 348-1, and 348-2 are U._k/ X_kRepresents U_kIs binary data such as data 216-1 shown in Fig. 2, and X_kIs modulated data (eg, 3-level data) such as data 226 shown in FIG. For example, as discussed further herein, path 344-1 is a U of 0._kValue, X of 2_kIt has a value and is displayed as 0/2. These routes correspond to the possible routes taken by the sequence of levels, and this information is utilized by the Viterbi component (eg, component 234 shown in Figure 2) as the multi-level data passes through the trellis 330. It can identify the route used by multi-level data and result in an increase in the performance of the Viterbi component compared to a component that has no route information at all.

As an example, the binary user data U received by a precoder such as the precoder 218 shown in FIG._k= Consider {100101011 ...}. U_kPrecoded data V by performing a specific operation (eg, (1 / (1xorD)) operation on)_kCan be determined. For example, V_k= xor (U_k, V_k-1) Is V_k= {111001101 ...}.

V_kUsing the (1 + D) operation with respect to 3 level data X_kCan result in the generation of. For example, X_kX so that = {122101211 ...}_k= V_k+ V_k-1Is. Therefore, during levels 0, 1, and 2 of the trellis 330, especially U_kAnd X_k(Here, U_kIf = 1, X_kThere is a certain relationship with (= 1). This relationship can result in an increase in SNR gain compared to memory cells that have independent levels.

In the above example, an even number of 1 is U at a particular point in the sequence._k0 U when passing in sequence_kThe value is X, as in the case of routes 344-1 and 344-2._kGenerate = 0. This can be referred to as state 0 (eg, states 338-1, 338-2, and 338-3). An odd number of 1 is U at a particular point in the sequence_k0 U when passing in sequence_kThe value is X, as in the case of routes 344-1 and 344-2._kGenerate = 2. This can be referred to as state 1 (eg, states 342-1, 342-2, and 342-3).

Data output from the TCM (eg, multi-level data) can be written to memory (eg, flash memory) 310 and sent to SOVA for decryption as shown in 232 of FIG. In some embodiments, the SNR gain is achieved by recovering binary LDPC code bits from soft data read from memory (eg, memory 310) using a Viterbi algorithm with respect to the trellis (eg, trellis 330). Can be done. The soft data is the three-level signal discussed with respect to Figure 3 (eg, X)._k) Approximation can be included.

Although a particular embodiment has been shown and described herein, one of ordinary skill in the art will recognize that any arrangement configuration planned to achieve the same result may be replaced with the particular embodiment shown. There will be. The present disclosure is intended to include adaptive or modified forms of the various embodiments of the present disclosure. It is understood that the above description is given in an exemplary manner rather than in a restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will become apparent to those skilled in the art upon examination of the above description. The scope of the various embodiments of the present disclosure includes other uses in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the claims, along with the full scope of the equivalents to which the claims are entitled.

In the above detailed description, the various features are combined together in a single embodiment to streamline the disclosure. This method of the present disclosure is not construed as reflecting the intent that the disclosed embodiments of the present disclosure must use more features than those expressly stated in each claim. Rather, the subject matter of the present invention resides in less than all features of the disclosed single embodiment, as reflected in the appended claims. Therefore, the appended claims are incorporated into the detailed description, with each claim being independent as a separate embodiment.