Semiconductor device
5 claims: 5 independent, 0 dependent
- 1ゲート電極と、 前記ゲート電極上の、ゲート絶縁膜と、 前記ゲート絶縁膜上の、酸化物半導体層と、 前記酸化物半導体層のチャネル形成領域と重なる、ハロゲン元素を有する第1の絶縁層と、 前記酸化物半導体層と電気的に接続された、ソース電極と、 前記酸化物半導体層と電気的に接続された、ドレイン電極と、 前記ソース電極上、及び前記ドレイン電極上の、第2の絶縁層と、を有し、 前記酸化物半導体層は、Inと、Gaと、Znと、を含み、 前記酸化物半導体層と、前記ソース電極との間に、第1のn型領域を有し、 前記酸化物半導体層と、前記ドレイン電極との間に、第2のn型領域を有し、 前記第1のn型領域は、酸化チタンを含み、 前記第2のn型領域は、酸化チタンを含み、 前記第1のn型領域のキャリア濃度は、前記酸化物半導体層のキャリア濃度より高く、 前記第2のn型領域のキャリア濃度は、前記酸化物半導体層のキャリア濃度より高く、 前記酸化物半導体層は、前記第1のn型領域を介して、前記ソース電極と電気的に接続され、 前記酸化物半導体層は、前記第2のn型領域を介して、前記ドレイン電極と電気的に接続され、 前記ソース電極の上方からみたとき、前記第1のn型領域は、前記ソース電極と重なる第3の領域と、前記ソース電極と重ならない第4の領域とを有し、 前記第4の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接し、 前記ドレイン電極の上方からみたとき、前記第2のn型領域は、前記ドレイン電極と重なる第5の領域と、前記ドレイン電極と重ならない第6の領域とを有し、 前記第6の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接していることを特徴とする半導体装置。
- 2ゲート電極と、 前記ゲート電極上の、ゲート絶縁膜と、 前記ゲート絶縁膜上の、酸化物半導体層と、 前記酸化物半導体層のチャネル形成領域と重なる、ハロゲン元素を有する第1の絶縁層と、 前記酸化物半導体層と電気的に接続された、ソース電極と、 前記酸化物半導体層と電気的に接続された、ドレイン電極と、 前記ソース電極上、及び前記ドレイン電極上の、第2の絶縁層と、を有し、 前記酸化物半導体層は、Inと、Gaと、Znと、を含み、 前記酸化物半導体層と、前記ソース電極との間に、ソース領域を有し、 前記酸化物半導体層と、前記ドレイン電極との間に、ドレイン領域を有し、 前記ソース領域は、酸化チタンを含み、 前記ドレイン領域は、酸化チタンを含み、 前記ソース電極の上方からみたとき、前記ソース領域は、前記ソース電極と重なる第3の領域と、前記ソース電極と重ならない第4の領域とを有し、 前記第4の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接し、 前記ドレイン電極の上方からみたとき、前記ドレイン領域は、前記ドレイン電極と重なる第5の領域と、前記ドレイン電極と重ならない第6の領域とを有し、 前記第6の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接していることを特徴とする半導体装置。
- 3ゲート電極と、 前記ゲート電極上の、ゲート絶縁膜と、 前記ゲート絶縁膜上の、酸化物半導体層と、 前記酸化物半導体層のチャネル形成領域と重なる、ハロゲン元素を有する第1の絶縁層と、 前記酸化物半導体層と電気的に接続された、ソース電極と、 前記酸化物半導体層と電気的に接続された、ドレイン電極と、 前記ソース電極上、及び前記ドレイン電極上の、第2の絶縁層と、を有し、 前記酸化物半導体層は、Inと、Gaと、Znと、を含み、 前記酸化物半導体層と、前記ソース電極との間に、前記酸化物半導体層と前記ソース電極との接触抵抗を低減させる第1の領域を有し、 前記酸化物半導体層と、前記ドレイン電極との間に、前記酸化物半導体層と前記ドレイン電極との接触抵抗を低減させる第2の領域を有し、 前記第1の領域は、酸化チタンを含み、 前記第2の領域は、酸化チタンを含み、 前記ソース電極の上方からみたとき、前記第1の領域は、前記ソース電極と重なる第3の領域と、前記ソース電極と重ならない第4の領域とを有し、 前記第4の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接し、 前記ドレイン電極の上方からみたとき、前記第2の領域は、前記ドレイン電極と重なる第5の領域と、前記ドレイン電極と重ならない第6の領域とを有し、 前記第6の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接していることを特徴とする半導体装置。
- 4ゲート電極と、 前記ゲート電極上の、ゲート絶縁膜と、 前記ゲート絶縁膜上の、酸化物半導体層と、 前記酸化物半導体層のチャネル形成領域と重なる、ハロゲン元素を有する第1の絶縁層と、 前記酸化物半導体層と電気的に接続された、ソース電極と、 前記酸化物半導体層と電気的に接続された、ドレイン電極と、 前記ソース電極上、及び前記ドレイン電極上の、第2の絶縁層と、を有し、 前記酸化物半導体層は、Inと、Gaと、Znと、を含み、 前記酸化物半導体層と、前記ソース電極との間に、第1の酸化チタンを有し、 前記酸化物半導体層と、前記ドレイン電極との間に、第2の酸化チタンを有し、 前記ソース電極の上方からみたとき、前記第1の酸化チタンは、前記ソース電極と重なる第3の領域と、前記ソース電極と重ならない第4の領域とを有し、 前記第4の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接し、 前記ドレイン電極の上方からみたとき、前記第2の酸化チタンは、前記ドレイン電極と重なる第5の領域と、前記ドレイン電極と重ならない第6の領域とを有し、 前記第6の領域は、前記チャネル形成領域上で、前記第2の絶縁層と接していることを特徴とする半導体装置。
- 5請求項1乃至請求4のいずれか一において、 前 記第1の絶縁層が有するハロゲン元素は、SIMSを用いた分析により得られる濃度ピークが1×10 15 cm -3 以上1×10 20 cm -3 以下の範囲内にあることを特徴とする半導体装置。
Independent claims5
299 paragraphs, as filed
0001One aspect of the present invention is a thin film transistor using an oxide semiconductor film in the channel formation region (hereinafter referred to as thin film transistor). The present invention relates to a semiconductor device having a circuit composed of (referred to as TFT) and a method for manufacturing the same. example For example, an electro-optical device typified by a liquid crystal display panel or a light emitting display device having an organic light emitting element. Regarding electronic devices installed as products.
0002In the present specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In general, electro-optic devices, semiconductor circuits and electronic devices are all semiconductor devices.
0003In recent years, each display pixel arranged in a matrix is composed of a thin film transistor (TFT). Active matrix type display device (liquid crystal display device or light emission display device) provided with a hatching element And electrophoretic display devices) are being actively developed. Active matrix type display device , A switching element is provided for each pixel (or 1 dot), making it a simple matrix method. This is advantageous because it can be driven at a low voltage when the pixel density increases.
0004In addition, a thin film transistor (TFT) is created using an oxide semiconductor film in the channel formation region. Attention is being paid to technologies that are manufactured and applied to electronic devices and optical devices. For example, oxide semiconduct TFT using ZnO as body membrane and InGaO<sub>3</sub>(ZnO)<sub>m</sub>TFT using Is done. A TFT formed using these oxide semiconductor films is formed on a translucent substrate. However, the technologies used for switching elements of image display devices are described in Patent Document 1, Patent Document 2, etc. It is disclosed.
<p num="0005"><patcit num="1"><text>JP-A-2007-123861</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2007-96055</text></patcit></p>
<p num="0006">For thin film transistors that use an oxide semiconductor film for the channel formation region, the operating speed is high. The manufacturing process is required to be relatively simple and sufficiently reliable.</p><p num="0007">When forming a thin film transistor, the source electrode and drain electrode are metal materials with low resistance. Use the fee. In particular, when manufacturing a display device that displays a large area, the signal due to the resistance of the wiring The delay problem becomes noticeable. Therefore, as a material for wiring and electrodes, gold with a low electrical resistance value It is desirable to use genus materials. On the other hand, a source electrode made of a metal material with a low electrical resistance value and If the thin film transistor structure is such that the drain electrode and the oxide semiconductor film are in direct contact with each other, Tact resistance may increase. The cause of high contact resistance is the source electrode and the The factor is that a Schottky junction is formed on the contact surface between the rain electrode and the oxide semiconductor film. It is considered to be one.</p><p num="0008">In addition, there is a capacitance in the part where the source electrode and drain electrode are in direct contact with the oxide semiconductor film. Formed, the frequency characteristic (called f characteristic) becomes low, and the high-speed operation of the thin film transistor There is a risk of hindering.</p><p num="0009">One aspect of the present invention is a thin film using an oxide semiconductor film containing indium, gallium, and zinc. In a transistor, the contact resistance between the source electrode and drain electrode and the oxide semiconductor layer One of the problems is to provide a thin film transistor and a method for producing the same.</p><p num="0010">In addition, a thin film transistor using an oxide semiconductor film containing indium, gallium, and zinc. One of the issues is to improve the operating characteristics and reliability of the.</p><p num="0011">In addition, a thin film transistor using an oxide semiconductor film containing indium, gallium, and zinc. One of the issues is to reduce the variation in the electrical characteristics of. Especially in liquid crystal display devices Is a display caused by the variation in the TFT characteristics when the variation between individual elements is large. There is a risk of unevenness.</p><p num="0012">Further, even in a display device having a light emitting element, it is arranged so that a constant current flows through the pixel electrodes. TFT (TFT that supplies current to the light emitting element placed in the drive circuit or pixel) Current (I<sub>on</sub>) Is large, there is a risk that the brightness will vary on the display screen. There is.</p><p num="0013">As described above, one aspect of the present invention aims to solve at least one of the above problems.</p>
<p num="0014">One aspect of the present invention is an oxide semiconductor containing indium, gallium, and zinc as a semiconductor layer. Is used to provide a buffer layer between the semiconductor layer, the source electrode layer, and the drain electrode layer. The gist is to include a G-shaped (bottom gate structure) thin film transistor.</p><p num="0015">In the present specification, it is formed by using an oxide semiconductor film containing indium, gallium, and zinc. The semiconductor layer is also referred to as "IGZO semiconductor layer".</p><p num="0016">Ohmic contact is required between the source electrode and the IGZO semiconductor layer, and in addition, It is desirable to reduce the contact resistance of the above as much as possible. Similarly, the drain electrode and the IGZO semi-conduct Ohmic contact with the body layer is required, and the contact resistance is as low as possible. It is hoped that it will be reduced.</p><p num="0017">Therefore, the carrier concentration between the source electrode and the IGZO semiconductor layer is higher than that of the IGZO semiconductor layer. Ohmic contacts are formed by intentionally providing a high buffer layer.</p><p num="0018">As the buffer layer, a metal oxide having an n-type conductive type is used. As a metal oxide, eg For example, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, oxidation Magnesium, calcium oxide, tin oxide and the like can be used. Up to n type in the buffer layer Alternatively, it may contain an impurity that imparts a p-type conductive type. Impurities include indium and moth Rium, aluminum, zinc, tin and the like can be used.</p><p num="0019">Since the carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer and it is superior in conductivity, the source electrode Alternatively, the contact resistance can be reduced as compared with the case where the drain electrode and the semiconductor layer are directly bonded. Wear.</p><p num="0020">This buffer layer is n<sup>+</sup>It acts as a layer and can also be called the drain area or source area. Wear.</p><p num="0021">One form of the semiconductor device of the present invention includes a gate electrode, a gate insulating film covering the gate electrode, and a game. The IGZO semiconductor layer formed on the insulating film overlaps with the channel formation region of the IGZO semiconductor layer. A channel protection layer formed in the region, a buffer layer formed on the semiconductor layer, and a buff. It has a thin film transistor including a source electrode and a drain electrode formed on the layer. The buffer layer contains a metal oxide having an n-type conductive type, and contains a semiconductor layer, a source electrode, and a metal oxide. The rain electrodes are electrically connected via a buffer layer. Also, the carrier of the buffer layer It is preferable that the concentration is higher than the carrier concentration of the IGZO semiconductor layer.</p><p num="0022">Further, the carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer, and is higher than that of the buffer layer. A lower second buffer layer may be provided. The second buffer layer is n<sup>-</sup>Functions as a layer.</p><p num="0023">That is, one form of the semiconductor device of the present invention includes a gate electrode, an insulating film covering the gate electrode, and a device. The IGZO semiconductor layer formed on the insulating film and the channel forming region of the IGZO semiconductor layer A channel protection layer formed in the overlapping region and a two-layer buffer layer formed on the semiconductor layer. A thin film transport containing a source electrode and a drain electrode formed on a two-layer buffer layer. The buffer layer contains a metal oxide having an n-type conductive type, and has a semiconductor layer and a saw. The electrode and the drain electrode are electrically connected to each other via a buffer layer. IGZO half The buffer layer in contact with the conductor layer is n<sup>-</sup>Functions as a layer.</p><p num="0024">In the above configuration, the buffer layer preferably contains titanium. Also, the source electrode layer and drainage The in-electrode layer preferably contains titanium. For example, titanium film, aluminum film, and titanium When a multilayer film with laminated films is used, the resistance is low and the aluminum film does not generate hillocks. Peg.</p><p num="0025">Since the structure of the thin film transistor according to one aspect of the present invention is a structure provided with a channel protection layer, A region opposite to the surface of the IGZO semiconductor layer in contact with the gate insulating film, the so-called back channel, is constructed. Is it moderate damage (plasma during etching, film loss due to etching agent, oxidation, etc.)? It is possible to protect the semiconductor device and improve the reliability of the semiconductor device.</p><p num="0026">In one embodiment of the method for manufacturing a semiconductor device of the present invention, a gate electrode is formed on a substrate and is placed on the gate electrode. A gate insulating film is formed in the gate, a semiconductor layer is formed on the gate insulating film, and a channel type on the semiconductor layer is formed. A channel protection layer is formed in a region that overlaps with the growth region, and a bag having an n-type conductive type on the semiconductor layer. A fa layer is formed, a source electrode and a drain electrode are formed on the buffer layer, and the semiconductor layer is in. It is formed using an oxide semiconductor layer containing gallium, gallium, and zinc, and the buffer layer is n-type. It is formed using a metal oxide having a conductive type, and the carrier concentration of the buffer layer is determined by the key of the semiconductor layer. Higher than the carrier concentration, the semiconductor layer and the source and drain electrodes are connected via the buffer layer. Connect enthusiastically.</p><p num="0027">In other words, one aspect of the present invention is to form a gate electrode on the substrate and gate on the gate electrode. An oxide semiconductor that forms an insulating film and contains indium, gallium, and zinc on the gate insulating film. A layer is formed, and a channel protection layer is formed in a region overlapping the channel formation region on the semiconductor layer, and a semi A buffer layer is formed on the conductor layer using a metal oxide having an n-type conductive type, and is placed on the buffer layer. The semiconductor layer, source electrode, and drain electrode that form the source electrode and drain electrode are This is a method for manufacturing a semiconductor device that is electrically connected via a buffer layer.</p><p num="0028">Further, in one embodiment of the method for manufacturing a semiconductor device of the present invention, a gate electrode is formed on a substrate and a gate is formed. A gate insulating film is formed on the electrodes, a semiconductor layer is formed on the gate insulating film, and a cha on the semiconductor layer is formed. A channel protection layer is formed in the region overlapping the flannel forming region, and an n-type conductive type is provided on the semiconductor layer. A buffer layer is formed, a source electrode and a drain electrode are formed on the buffer layer, and a semiconductor layer is formed. Is formed using an oxide semiconductor layer containing indium, gallium, and zinc, and the buffer layer is It is formed using a metal oxide having an n-type conductive type, and the carrier concentration of the buffer layer is a semiconductor. The carrier concentration of the layer is higher than that of the layer, and the semiconductor layer and the source electrode and drain electrode are connected via a buffer layer. The gate insulating film, semiconductor layer and channel protection layer are formed without exposure to the atmosphere. To do.</p><p num="0029">In other words, in one aspect of the present invention, a gate electrode is formed on the substrate and is placed on the gate electrode. An oxide that forms a gate insulating film and contains indium, gallium, and zinc on the gate insulating film. A semiconductor layer is formed, and a channel protection layer is formed in a region overlapping the channel formation region on the semiconductor layer. Then, a buffer layer is formed on the semiconductor layer using a metal oxide having an n-type conductive type, and a buff is formed. A source electrode and a drain electrode are formed on the layer, and the gate insulating film, the semiconductor layer, and the buffer are formed. The semiconductor layer and the source and drain electrodes that form the layer continuously without exposing it to the atmosphere are buffed. This is a method for manufacturing a semiconductor device that is electrically connected via a layer.</p><p num="0030">When the gate insulating film, semiconductor layer and channel protection layer are continuously formed, atmospheric components such as water vapor and large amounts Since it is possible to form a laminated interface that is not contaminated by impurity elements or dust floating in the air. , It is possible to reduce variations in thin film transistor characteristics.</p><p num="0031">In the present specification, continuous film formation means from the first film forming step performed by the sputtering method to the second film forming method performed by the sputtering method. During the series of processes up to the film formation process, the atmosphere in which the substrate to be processed is placed becomes a polluted atmosphere such as the atmosphere. Always in vacuum or in an inert gas atmosphere (nitrogen atmosphere or noble gas atmosphere) without touching the surroundings It means that it is controlled by the surrounding air). A group to be treated that has been cleaned by continuous film formation. It is possible to form a film while avoiding reattachment of moisture or the like to the plate.</p><p num="0032">Performing a series of processes from the first film formation step to the second film formation step in the same chamber Is within the scope of continuous film formation in the present specification.</p><p num="0033">In addition, a series of processes from the first film formation process to the second film formation process is performed in different chambers. In this case, after completing the first film formation process, the substrate is transported between the chambers without touching the atmosphere. It is also assumed that performing the second film formation is within the scope of continuous film formation in the present specification.</p><p num="0034">Between the first film forming process and the second film forming process, the substrate transfer process, the alignment process, and the slow cooling process are performed. It has a process of heating or cooling the substrate to obtain the temperature required for the process or the second process. However, it is assumed that it is within the range of continuous film formation in the present specification.</p><p num="0035">However, the first process is to use a liquid such as cleaning process, wet etching, and resist formation. When it is between the film formation step of the above and the second film formation step, the scope of continuous film formation referred to in the present specification is applicable. I'm sorry.</p><p num="0036">Continuously forming a gate insulating film, a semiconductor layer and a channel protection layer by a sputtering method. As a result, not only the productivity is increased, but also a highly reliable laminated interface can be formed. Also, the gate is cut off By forming the edge film, semiconductor layer and channel protection layer in an oxygen atmosphere, reliability due to deterioration By reducing the decrease in thin film transistor characteristics and shifting the thin film transistor characteristics to the normally-on side. Wear.</p><p num="0037">One aspect of the semiconductor device of the present invention is a gate electrode, a gate insulating film covering the gate electrode, and a game. In the region where the oxide semiconductor layer formed on the insulating film overlaps with the channel formation region of the semiconductor layer. The formed channel protection layer, the buffer layer formed on the semiconductor layer, and the shape on the buffer layer. It has a thin film transistor including a source electrode and a drain electrode formed, and the buffer layer is a chi It contains tongue oxide, and the semiconductor layer is electrically connected through the source and drain electrodes and the buffer layer. It is a semiconductor device that is air-connected.</p><p num="0038">Further, it is a semiconductor device in which the carrier concentration of the buffer layer is higher than the carrier concentration of the semiconductor layer.</p><p num="0039">Further, the buffer layer is a semiconductor device containing impurities that impart n-type.</p><p num="0040">Further, the buffer layer is a semiconductor device containing indium, gallium or zinc as an impurity. To.</p><p num="0041">Further, the carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer and higher than that of the buffer layer. A semiconductor device having a low second buffer layer.</p><p num="0042">Further, the source electrode and the drain electrode are semiconductor devices containing titanium.</p><p num="0043">Further, the oxide semiconductor is a semiconductor device containing indium, gallium and zinc.</p><p num="0044">Another aspect of the disclosed invention is to form a gate electrode on a substrate and provide gate insulation on the gate electrode. A film is formed, a semiconductor layer is formed on the gate insulating film, and it overlaps with the channel forming region on the semiconductor layer. A channel protection layer is formed in the region, and titanium oxide is used on the semiconductor layer on the semiconductor layer. A fa layer is formed, a source electrode and a drain electrode are formed on the buffer layer, and a key of the buffer layer is formed. The carrier concentration is higher than the carrier concentration of the semiconductor layer, and the semiconductor layer, source electrode, and drain electricity A pole is a method of manufacturing a semiconductor device that is electrically connected via a buffer layer.</p><p num="0045">Further, in another aspect of the disclosed invention, a gate electrode is formed on a substrate and a game is formed on the gate electrode. The insulating film is formed, the semiconductor layer is formed on the gate insulating film, and the channel forming region on the semiconductor layer is formed. A channel protection layer is formed in the region overlapping with, and titanium oxide is used on the semiconductor layer on the semiconductor layer. A buffer layer is formed, a source electrode and a drain electrode are formed on the buffer layer, and a buffer is formed. The carrier concentration of the layer is higher than the carrier concentration of the semiconductor layer, and the semiconductor layer, the source electrode, and the drain are It is electrically connected to the in electrode via a buffer layer, and has a gate insulating film, a semiconductor layer, and a channel. The protective layer is a method for manufacturing a semiconductor device that is formed without being exposed to the atmosphere.</p><p num="0046">Further, the gate insulating film, the semiconductor layer and the channel protection layer are formed by a sputtering method. This is a method for manufacturing a semiconductor device.</p><p num="0047">Further, the gate insulating film, the semiconductor layer, and the channel protection layer are semiconductor components formed in an oxygen atmosphere. This is a method of making a table.</p><p num="0048">Further, the buffer layer is a method for manufacturing a semiconductor device formed in a noble gas atmosphere.</p>
<p num="0049">According to one aspect of the present invention, a thin film having a small photocurrent, a small parasitic capacitance, and a high on / off ratio. A transistor can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, it is possible to provide a semiconductor device having a thin film transistor having high electrical characteristics and high reliability. ..</p>
0050<figref num="1">The figure explaining the semiconductor device of one aspect of this invention.</figref><figref num="2">The figure explaining the manufacturing method of the semiconductor device of one aspect of this invention.</figref><figref num="3">The figure explaining the manufacturing method of the semiconductor device of one aspect of this invention.</figref><figref num="4">The figure explaining the manufacturing method of the semiconductor device of one aspect of this invention.</figref><figref num="5">The figure explaining the semiconductor device of one aspect of this invention.</figref><figref num="6">The figure explaining the semiconductor device of one aspect of this invention.</figref><figref num="7">The figure explaining the semiconductor device of one aspect of this invention.</figref><figref num="8">The figure explaining the semiconductor device of one aspect of this invention.</figref><figref num="9">Top schematic of a multi-chamber type manufacturing device.</figref><figref num="10">The figure explaining the block diagram of the display device.</figref><figref num="11">The figure explaining the structure of the signal line drive circuit.</figref><figref num="12">A timing chart that explains the operation of the signal line drive circuit.</figref><figref num="13">A timing chart that explains the operation of the signal line drive circuit.</figref><figref num="14">The figure explaining the structure of the shift register.</figref><figref num="15">The figure explaining the connection structure of the flip-flop shown in FIG.</figref><figref num="16">The figure explaining the liquid crystal display device to which one aspect of this invention is applied.</figref><figref num="17">The figure explaining the liquid crystal display device to which one aspect of this invention is applied.</figref><figref num="18">The figure explaining the liquid crystal display device to which one aspect of this invention is applied.</figref><figref num="19">The figure explaining the light emission display device to which one aspect of this invention is applied.</figref><figref num="20">The figure explaining the light emission display device to which one aspect of this invention is applied.</figref><figref num="21">The figure explaining the light emission display device to which one aspect of this invention is applied.</figref><figref num="22">The figure explaining the light emission display device to which one aspect of this invention is applied.</figref><figref num="23">The figure explaining the electronic paper to which one aspect of this invention is applied.</figref><figref num="24">The figure explaining the electronic device to which one aspect of this invention is applied.</figref><figref num="25">The figure explaining the electronic device to which one aspect of this invention is applied.</figref><figref num="26">The figure explaining the electronic device to which one aspect of this invention is applied.</figref><figref num="27">The figure explaining the electronic device to which one aspect of this invention is applied.</figref><figref num="28">The figure explaining the electronic device to which one aspect of this invention is applied.</figref>
0051Hereinafter, embodiments of one aspect of the present invention will be described in detail with reference to the drawings. However, The present invention is not limited to the following description, and does not deviate from the gist of the present invention and its scope. It is easily understood by those skilled in the art that various forms and details of the above can be changed. But Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. Na Oh, in the configuration of the present invention described below, the same parts or parts having similar functions are the same. One reference numeral is used in common among different drawings, and the repeated description thereof will be omitted.
0052(Embodiment 1) In the present embodiment, FIGS. 1 and 2 are used for the thin film transistor and the manufacturing process thereof. I will explain.
0053FIG. 1 shows a thin film transistor having a bottom gate structure according to this embodiment. Figure 1 (A) is flat It is a top view, and FIG. 1 (B) is a cross-sectional view taken along the line A1-A2 in FIG. 1 (A). Figure 1 In the thin film transistor shown in FIG. 1, a gate electrode 101 is formed on the substrate 100, and the gate electrode 1 is formed. A gate insulating film (102a, 102b) composed of a multilayer film is formed on 01, and a gate insulating film is formed. Functions as a channel forming region on the gate electrode 101 via (102a, 102b) Amorphous oxide semiconductor layer 103 is formed, and the channel type of amorphous oxide semiconductor layer 103 is formed. A channel protection layer 106 is formed in a region overlapping the growth region, and an amorphous oxide semiconductor layer 103 is formed. The buffer layers 104a and 104b are formed by superimposing the end on the gate electrode 101. Source and drain electrodes 105a and in contact with buffer layers 104a and 104b 105b is formed.
0054An oxide semiconductor film containing In, Ga, and Zn is used as the semiconductor layer 103, and the source electrode and And between the drain electrodes 105a and 105b and the semiconductor layer 103, more than the semiconductor layer 103. Omi by intentionally providing buffer layers 104a and 104b with high carrier concentration Form a contact.
0055The buffer layers 104a and 104b are formed of a metal oxide. Buffer layers 104a, 104 As metal oxides that function as b, titanium oxide, molybdenum oxide, zinc oxide, and in oxide Use didium, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, etc. However, titanium oxide is particularly preferable. In addition, different kinds of metals are doped into metal oxides. Can also be used. Dopants include indium, gallium, aluminum, Examples include zinc and tin. High carrier concentration in metal oxides by doping Can be squeezed.
0056The buffer layers 104a and 104b are n<sup>+</sup>Acts as a layer, drain area or source area Can also be called.
0057The method for manufacturing the thin film transistor shown in FIG. 1 will be described with reference to FIG.
0058First, on the substrate 100, the gate electrode 101, the gate insulating film 102, the semiconductor film 133, and the channel The protective layer 106 is formed (see FIG. 2 (A)).
0059The substrate 100 is barium borosilicate glass, aluminoborosilicate glass, or aluminum. Non-alkali glass group produced by fusion method or float method such as nosilicated glass In addition to plates and ceramic substrates, plastics with heat resistance that can withstand the processing temperature of this manufacturing process. A substrate or the like can be used. In addition, an insulating film is provided on the surface of a metal substrate such as a stainless alloy. A digit substrate may be applied. When the substrate 100 is mother glass, the size of the substrate is the first generation. Generation (320mm x 400mm), 2nd generation (400mm x 500mm), 3rd generation (55) 0mm x 650mm), 4th generation (680mm x 880mm, or 730mm x 920) mm), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 1st 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800mm, 24 50mm x 3050mm), 10th generation (2950mm x 3400mm), etc. Can be done.
0060Further, an insulating film may be formed on the substrate 100 as a base film. As a base film, the CVD method or Silicon oxide film, silicon nitride film, silicon oxide nitride film, or acid nitride using a sputtering method or the like. It may be formed by a single layer or a laminate of siliconized silicon films.
0061The gate electrode 101 is made of a metal material. Metal materials include aluminum, chrome, Titanium, tantalum, molybdenum, copper, etc. are applied. A good example of a gate electrode is aluminum. It is formed by a laminated structure of aluminum or aluminum and a barrier metal. As a barrier metal Is applied with refractory metals such as titanium, molybdenum and chromium. Barrier metal is aluminum It is preferable to provide it to prevent hilok and oxidation of um.
0062The gate electrode is formed with a thickness of 50 nm or more and 300 nm or less. Gate electrode thickness 300n By setting it to m or less, it is possible to prevent the semiconductor film and wiring to be formed later from being broken. Also, By setting the thickness of the gate electrode to 150 nm or more, it is possible to reduce the resistance of the gate electrode. It is possible to increase the area.
0063Since a semiconductor film and wiring are formed on the gate electrode 101, the end portion is formed to prevent step breakage. It is desirable to process it so that it has a tapered shape. Also, although not shown, the gate is used in this process. Wiring connected to the electrode and capacitive wiring can also be formed at the same time.
0064The gate electrode 101 is a sputtering method, a CVD method, a plating method, a printing method, or silver or gold. , Can be formed using a conductive nanopaste such as copper. Also, the inkjet method The gate electrode can be formed by ejecting and firing droplets containing conductive particles and the like. Here, as shown in Fig. 2 (A), an aluminum film and a molybdenum film are used as conductive films on the substrate. Are laminated by a sputtering method to form a film, and the first photomask in the present embodiment is used. Using the resist mask formed in the above, the conductive film formed on the substrate is etched and the game The electrode 101 is formed.
0065In this embodiment, an example is shown in which a multilayer film in which two insulating films are laminated is used as the gate insulating film 102. I will. The first gate insulating film 102a and the second gate insulating film 102b each have a thickness of 50 to Formed from a 150 nm silicon oxide film, silicon nitride film, silicon nitride film, or silicon nitride film Can be Here, a silicon nitride film or an acid nitride is used as the first gate insulating film 102a. A silicon oxide film is formed, and a silicon oxide film or a silicon nitride film is used as the second gate insulating film 102b. The form of forming and laminating is shown. In addition, the gate insulating film is not made into two layers, but a silicon oxide film and silicon nitride. It can be formed of a single layer of a base film, a silicon nitride film, or a silicon nitride film, and can also be formed. A three-layer gate insulating film may be formed.
0066Forming the first gate insulating film 102a using a silicon nitride film or a silicon nitride film. As a result, the adhesion between the substrate and the first gate insulating film 102a is enhanced, and a glass substrate is used as the substrate. In this case, it is possible to prevent impurities from the substrate from diffusing into the oxide semiconductor film. Further, it is possible to prevent oxidation of the gate electrode 101. That is, the film peeling can be prevented. At the same time, the electrical characteristics of the thin film transistor formed later can be improved. Also, The first gate insulating film 102a and the second gate insulating film 102b each have a thickness of 50 nm or more. Is preferable because it can cover the unevenness of the gate electrode 101.
0067Here, the silicon oxide film has a higher oxygen content than nitrogen as its composition. The concentration range is 55 to 65 atomic% for oxygen, 1 to 20 atomic% for nitrogen, and 25 to 25 for Si. It refers to those containing 35 atomic% and hydrogen in the range of 0.1 to 10 atomic%. Also, silica nitride oxide The base film has a higher nitrogen content than oxygen as its composition, and has a concentration range. Oxygen is 15 to 30 atomic%, nitrogen is 20 to 35 atomic%, Si is 25 to 35 atomic%, and hydrogen is Those contained in the range of 15 to 25 atomic%.
0068The second gate insulating film 102b in contact with the semiconductor layer 103 includes, for example, silicon oxide. Aluminum oxide, magnesium oxide, aluminum nitride, yttrium oxide, huff oxide You can use nium.
0069The first gate insulating film 102a and the second gate insulating film 102b are respectively used for the CVD method and the spa. It can be formed by using a tattering method or the like. Here, the first gate insulating film 102a A silicon nitride film is formed by the plasma CVD method.
0070The second gate insulating film 102b in contact with the semiconductor film 133 and the semiconductor film 133 are continuously formed. Is desirable. By continuously forming a film, atmospheric components such as water vapor and impurities sources floating in the atmosphere Since a laminated interface that is not contaminated by elements or dust can be formed, variations in thin film transistor characteristics Can be reduced.
0071In the active matrix type display device, the electricity of the thin film transistor constituting the circuit Characteristics are important, and these electrical characteristics affect the performance of the display device. Especially thin film transistors Of the electrical characteristics of, the threshold voltage (Vth) is important. High field effect mobility If the threshold voltage value is high or the threshold voltage value is negative, it can be controlled as a circuit. Is difficult. Thin film transition with a high threshold voltage value and a large absolute value of the threshold voltage In the case of data, it functions as a thin film transistor when the drive voltage is low. It cannot be added and may become a load. Also, if the threshold voltage value is negative, Even if the gate voltage is 0V, a current flows between the source electrode and the drain electrode, so-called normalio. It is easy to become
0072In the case of an n-channel thin film transistor, it is not until a positive voltage is applied to the gate voltage. A transistor in which a flannel is formed and a drain current flows out is desirable. Increase the drive voltage A transistor is not formed without it, and a channel is formed even in a negative voltage state. Transistors through which drain current flows are not suitable as thin film transistors used in circuits. is there.
0073Therefore, a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is also gated. It is desirable that the channel be formed at a positive threshold voltage where the voltage is as close to 0V as possible.
0074The threshold voltage of the thin film transistor is the interface between the semiconductor layers, that is, the semiconductor layer and the gate insulating film. It is thought that it greatly affects the interface.
0075Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistor It can improve the performance and prevent the manufacturing process from becoming complicated, resulting in both mass productivity and high performance. Realize a thin film transistor.
0076In particular, when water is present at the interface between the oxide semiconductor layer and the gate insulating film, the electric thin film transistor is charged. Problems such as deterioration of air characteristics, variation in threshold voltage, and tendency to become normally on Invite. By continuously forming an oxide semiconductor layer and a gate insulating film, such a hydrogen compound can be obtained. Can be excluded.
0077Therefore, the gate insulating film and the oxide semiconductor film are sputtered without being exposed to the atmosphere. It has a good interface by continuously forming a film under reduced pressure, has a low leakage current, and has a current drive capability. It is possible to realize a high-power thin film transistor.
0078In addition, the gate insulating film and the oxide semiconductor film containing In, Ga, and Zn are placed in an oxygen atmosphere (also). Is preferably formed with oxygen of 90% or more and a rare gas (argon or the like) of 10% or less).
0079When continuous film formation is performed using the sputtering method in this way, the productivity is high and the reliability of the thin film interface is high. Is stable. In addition, the gate insulating film and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen. If this is done, the reliability will decrease due to deterioration and the thin film transistor will become normally on. That can be alleviated.
0080In addition, the insulating film that serves as the channel protection layer 106 is also continuous, following the film formation of the semiconductor film. It is desirable to form a film. By continuously forming a film, it is opposite to the surface of the semiconductor film in contact with the gate insulating film. Atmospheric components such as water vapor and impurity elements suspended in the atmosphere in the contralateral region, the so-called back channel Since it is possible to form a laminated interface that is not contaminated by dust and dirt, it has the characteristics of a thin film transistor. Variation can be reduced.
0081As a method for continuously forming a film, a multi-chamber type sputtering phosphorus having a plurality of film forming chambers is used. It is sufficient to use a grinding device, a sputtering device with multiple targets, or a PLD device. I. When forming silicon oxide as an insulating film, silicon oxide (artificial quartz) as a target For high-frequency sputtering method or reactive sputtering method using single crystal silicon More film can be formed. Here, the single crystal silicon target and the target for the semiconductor film are used. A second-layer game in contact with the semiconductor using the equipped multi-chamber sputtering device. A silicon oxide film is formed as the insulating film 102b, and a semiconductor film is formed without exposure to the atmosphere. A silicon oxide film serving as a channel protective layer is continuously formed.
0082The semiconductor layer 103 is formed of an amorphous oxide semiconductor film. As an amorphous oxide semiconductor film Is a composite oxide of elements selected from indium, gallium, aluminum, zinc and tin Can be used. For example, oxides containing indium, gallium, and zinc (IGZO) ) Can be given as an example.
0083In the case of oxides consisting of indium oxide, gallium oxide and zinc oxide, the composition ratio of metal elements is self-existing. It has a high degree of susceptibility and functions as a semiconductor layer in a wide range of mixing ratios. Indium oxide and gallium oxide In: Ga, the abundance ratio of metal elements in the material and the material in which zinc oxide and zinc oxide are mixed in equimolar amounts An example is an oxide that exists in a ratio of: Zn = 2.2: 2.2: 1.0. ..
0084The oxide semiconductor film 133 used for the semiconductor layer 103 is 2 nm or more and 200 nm or less, preferably It is preferable to form it with a thickness of 20 nm or more and 150 nm or less. Also, when oxygen deficiency in the membrane increases Suppresses oxygen deficiency because the carrier concentration increases and the thin film transistor characteristics are impaired. To the composition.
0085The amorphous oxide semiconductor film 133 is prepared by a reactive sputtering method or a pulse laser vapor deposition method (P). A film can be formed by the LD method) or the sol-gel method. Here, an example of a method for forming the semiconductor film 133 As for the method using oxide containing indium, gallium, and zinc (IGZO) I will explain.
0086Indium oxide (In<sub>2</sub>O<sub>3</sub>) And gallium oxide (Ga)<sub>2</sub>O<sub>3</sub>) And zinc oxide (ZnO) Using a target with a diameter of 8 inches, which was mixed and sintered in moles, 17 from the target. Place the board at the 0mm position and DC (Direct Current) with an output of 500W. ) Sputter to form the semiconductor film 133. Chamber pressure is 0.4Pa, gas Composition ratio is Ar / O<sub>2</sub>A 50 nm film is formed under the condition of 10/5 sccm. Oxygen partial pressure during film formation Is set higher than the film formation conditions for transparent conductive films such as indium tin oxide (ITO), and the film formation atmosphere It is desirable to control the oxygen concentration of Qi to suppress oxygen deficiency. Also, pulsed direct current (DC) It is preferable to use a power source because dust can be reduced and the film thickness distribution becomes uniform.
0087The semiconductor layer 103 may be subjected to plasma treatment. By performing plasma processing Damage caused by etching of the semiconductor layer 103 can be recovered. Plasma processing is O<sub>2</sub>, H<sub>2</sub>O, N<sub>2</sub>O, preferably H containing oxygen<sub>2</sub>, N<sub>2</sub>, He, Ar, H, NH<sub>3</sub>atmosphere It is preferable to do it below. Also, Cl in the above atmosphere<sub>2</sub>, CF<sub>4</sub>Go in an atmosphere with May be good. The plasma treatment is preferably performed without bias.
0088In the present embodiment, the target provided with the single crystal silicon together with the target for the oxide semiconductor film is provided. A second gate insulating film formed in the previous process using a ruti-chamber type sputtering device 1 A semiconductor film 133 is formed on the 02b without exposing it to the atmosphere. Filmed semiconductor film The channel protection layer 1 is placed on the semiconductor film 133 in the next process without continuing to expose 133 to the atmosphere. An insulating film to be 06 is formed.
0089As shown in FIG. 2A, the channel protection layer 106 overlaps the channel formation region of the semiconductor layer 103. It is formed with an insulating film in the area. The insulating film that functions as the channel protection layer 106 is an inorganic material ( (Silicon oxide, silicon nitride, silicon oxide, silicon nitride, etc.) can be used. Also, Photosensitive or non-photosensitive organic material (organic resin material) (polyimide, acrylic, polyamide , Polyimide amide, resist, benzocyclobutene, etc.), or multiple types of membranes , Or a laminate of these films can be used. Alternatively, siloxane may be used. ..
0090The insulating film serving as the channel protection layer 106 is a vapor deposition method such as a plasma CVD method or a thermal CVD method. The film can be formed by the sputtering method or the sputtering method. In addition, a coating method such as a spin coating method, which is a wet method, can be used. Can be used. In addition, the droplet ejection method and printing method (screen printing and offset printing) It may be selectively formed by a method of forming a pattern) or the like.
0091Here, a multi-chamber equipped with a target for single crystal silicon and an oxide semiconductor film. The oxide semiconductor film formed in the previous process is exposed to the atmosphere using a-type sputtering device. Instead, a silicon oxide film to be the channel protection layer 106 is formed. Next, in the present embodiment Formed on the semiconductor film 133 using a resist mask formed using the second photomask. The silicon oxide film was selectively etched to form the channel protection layer 106 as shown in FIG. 2 (A). Form. Next, the resister formed by using the third photomask in the present embodiment. A semiconductor is formed by etching the oxide semiconductor film 133 formed on the gate insulating film using a screw. Form layer 103.
0092Those who etch oxide (IGZO) films containing indium, gallium, and zinc As a method, a wet etching method can be used. Equipped with organic acids such as citric acid and oxalic acid Can be used for chants. For example, 50 nm indium, gallium, and zinc The oxide (IGZO) film containing it is etched using ITO07N (manufactured by Kanto Chemical Co., Inc.) in 150 seconds. Can be processed.
0093The pair of buffer layers 104a and 104b formed on the amorphous oxide semiconductor film are metallic acids. Formed with a compound. Oxidation as a metal oxide that functions as buffer layers 104a, 104b Titanium, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide Umm, calcium oxide, tin oxide and the like can be used, but titanium oxide is particularly preferable. ..
0094Further, a metal oxide can be used by doping a different kind of metal. As a dopant Can include indium, gallium, aluminum, zinc, tin and the like. Dopi The carrier concentration in the metal oxide can be increased by the coating.
0095Carrier concentrations of buffer layers 104a, 104b include indium, gallium, and zinc Since it is higher in conductivity than the semiconductor layer 103 made of oxide (IGZO), the source electrode is also Or, compared to the case where the drain electrodes 105a and 105b and the semiconductor layer 103 are directly bonded, they are in contact with each other. It is possible to reduce the tactile resistance. Also, source electrodes or drain electrodes 105a, 105 By sandwiching the buffer layers 104a and 104b at the bonding interface between b and the semiconductor layer 103, the bonding is performed. The electric field concentrated on the interface can be relaxed.
0096In order to ensure that the buffer layer (104a, 104b) covers the semiconductor layer 103, the figure shows. As shown in 2 (B), putter so that the buffer layer rides on a part of the channel protection layer 106. You may do it.
0097The metal oxide film used as the buffer layer (104a, 104b) is 2 nm or more and 100 nm or more. It should be formed with the thickness below.
0098The metal oxide film to be the buffer layer (104a, 104b) is a sputtering method or a pulse. The film can be formed by the laser vapor deposition method (PLD method). In addition, here, spatterin A titanium oxide film is formed using the G method. Next, the fourth photomask in the present embodiment Formed on the semiconductor layer 103 and the channel protection layer 106 using the resist mask formed in The formed titanium oxide film is dry-etched or wet-etched to form a buffer layer 1 Form 04a and 104b. In addition, as an example of the etching method of titanium oxide, we Etching method can be mentioned. Diluted hydrofluoric acid, hydrochloric acid or sulfuric acid, or ammo A solution in which near water, hydrogen peroxide solution, and pure water are mixed at a volume ratio of 1: 1: 5 is used as an etchant. Can be
0099The source electrode and drain electrodes 105a and 105b are made of a conductive film, and the gate electrode 101 and The same material can be used, but in particular, the layer in contact with the buffer layers 104a and 104b is chita. It is preferably a membrane. As a specific example of the conductive film, a single titanium film or titanium A laminated film of a film and an aluminum film, or a titanium film, an aluminum film, and a titanium film are stacked in order. It may be a three-layer structure in which they are stacked.
0100Here, as shown in Fig. 2 (C), the buffer layers 104a and 104b and the channel protection layer are overlaid. A three-layer laminated film composed of a tongue film, an aluminum film, and a titanium film is formed by a sputtering method. Next In addition, using the resist mask formed by using the fifth photomask in the present embodiment, The conductive film formed on the channel protection layer 106 is etched and separated, and the source electrode and the drain are separated. The in-electrodes 105a and 105b are formed as shown in Fig. 2 (D). In addition, titanium film and aluminum The conductive film having a three-layer structure in which the um film and the titanium film are stacked in order is hydrogen peroxide solution or heated hydrochloric acid. Can be etched as an etchant.
0101In the present embodiment, the buffer layers 104a and 104b are formed, the source electrode and the source electrode and the buffer layers 104a and 104b are formed. Since the drain electrodes 105a and 105b are formed separately, the buffer layers 104a and 104b are formed separately. Easily overlap length at the ends of b and source and drain electrodes 105a and 105b Can be controlled.
0102Half of the oxide containing indium, gallium, and zinc (IGZO) described in this embodiment. The thin film transistor used for the conductor layer 103 is to heat-treat the formed semiconductor layer 103. And the characteristics are improved. Specifically, the on-current becomes large and the transistor characteristics vary. Decreases.
0103The heat treatment temperature of the semiconductor layer 103 is preferably in the range of 300 ° C to 400 ° C, and here Process at 350 ° C for 1 hour. The heat treatment can be performed at any time after the formation of the semiconductor layer 103. good. For example, the insulating film to be the semiconductor layer 103 and the channel protection layer 106 has been continuously formed. It may be after, or after patterning and forming the channel protection layer 106, or buff. It may be after the metal oxide films to be the layers 104a and 104b are formed. Also, the source electrode And it may be after the conductive film to be the drain electrodes 105a and 105b is formed, or it may be a thin film transformer. It may be after forming the sealing film of Gista, or the thermohardening of the flattening film formed on the thin film transistor. The chemical treatment may be combined with the heat treatment of the semiconductor layer 103.
0104According to the above description, the amorphous oxide semiconductor layer 103 and the channel protection layer 10 shown in FIG. 1 6, buffer layers 104a, 104b and source and drain electrodes 105a, 105b To form.
0105The thin film transistor according to one aspect of the present invention includes a gate electrode, a gate insulating film, and a semiconductor layer (In, G). Oxide semiconductor layer containing a and Zn), buffer layer, channel protection layer, source electrode and zinc It has a laminated structure called a rain electrode. A buffer layer with a higher carrier concentration than the semiconductor layer By using, the film thickness of the semiconductor layer remains thin and the parasitic capacitance is suppressed. Can be done.
0106The structure of the thin film transistor according to one aspect of the present invention is a structure in which the channel protection layer 106 is provided. Therefore, the region of the oxide semiconductor film opposite to the surface in contact with the gate insulating film 102b, the so-called back. Damage during the process of the channel (film loss due to plasma and etching agent during etching, Can be protected from oxidation etc.). Therefore, the reliability of the thin film transistor is improved. Can be done.
0107The channel protection layer 106 is etched in the etching process for forming the semiconductor layer 103. It can be said to be a channel stopper layer because it functions as a hang stopper.
0108Further, in the present embodiment, the source electrode and the drain electrode 105 are placed on the channel protection layer 106. The ends of a and 105b recede from the ends of the buffer layers 104a and 104b and are separated from each other. Leakage current and show between source and drain electrodes 105a and 105b Can be prevented.
0109Therefore, by applying one aspect of the present invention, the photocurrent is small, the parasitic capacitance is small, and e A thin film transistor with a high on-off ratio can be obtained and has good dynamic characteristics (f characteristics). A thin film transistor can be manufactured. Therefore, a thin film transistor with high electrical characteristics and high reliability It is possible to provide a semiconductor device having the above.
0110(Embodiment 2) In the present embodiment, the buffer layer has titanium oxide having a structure different from that of the first embodiment. The structure of the membrane transistor will be described with reference to FIG. Further, in the present embodiment, The same reference numerals are used for the same as those in the first embodiment, and detailed description thereof will be omitted.
0111Through the same steps as in the first embodiment, the channel protection layer 106 is half as shown in FIG. 3 (A-1). It is formed with an insulating film in a region overlapping the channel forming region of the conductor layer 103. Channel protection FIG. 3 shows the surface of the semiconductor layer 103 to be joined to the buffer layer in the etching process of the layer 106. Etching may be performed as in (A-2). Surface to be bonded to the buffer layer of the oxide semiconductor layer By etching, a better bond with the buffer layer can be obtained.
0112In other words, the gate electrode 101 on the semiconductor film 133 undergoes the same steps as in the first embodiment. The channel protection layer 106 is formed in the region overlapping the above. The channel protection layer 106 is formed. The surface of the semiconductor film 133 may be etched as shown in FIG. 3 (A-2). I. The surface of the semiconductor film 133 at the opening of the channel protection layer 106 is etched. As a result, the surface can be satisfactorily bonded to the metal oxide film 134 which is the buffer layer to be formed next. To. In this embodiment, the description will be continued based on the embodiment shown in FIG. 3 (A-2).
0113In the present embodiment, titanium oxide is used as a metal oxide film 134 as a buffer layer, as shown in FIG. 3 (B). The film is formed like this. The metal oxide film 134 serving as the buffer layer is formed in the same manner as described in the first embodiment. After filming, the source electrode and drain electrode 105 as shown in Fig. 3 (C) without patterning. The conductive film 105 to be a and 105b is laminated on the metal oxide film 134.
0114The conductive film 105 is formed in the same manner as described in the first embodiment. Here, as the conductive film 105, A three-layer laminated film is formed by a sputtering method. For example, source electrode and drain electrode 1 Titanium film as 05a1, 105b1, aluminum film as 105a2, 105b2, Titanium films can be used as 105a3 and 105b3.
0115In other words, titanium as the first conductive film, aluminum as the second conductive film, and the third A first conductive layer made of titanium, using a conductive film 105 in which titanium is laminated as the conductive film of 105a1, 105b1) and a second conductive layer (105a2, 105) made of aluminum Source electricity in which b2) and a third conductive layer (105a3, 105b3) made of titanium are laminated. Form pole and drain electrodes (105a, 105b).
0116Next, using the resist mask formed by using the fourth photomask in the present embodiment. The conductive film 105 is etched.
0117First, the source electrode and drain electrodes 105a1 and 105b1 are used as etching stoppers. Source and drain electrodes 105a2, 105a3, 105b2, 10 5b3 is formed by etching by wet etching. The above wet etching Source or drain electrodes 105a1, 105b1, buffer using the same mask as Formed by etching layers 104a, 104b and semiconductor layer 103 by dry etching To do. Therefore, as shown in Fig. 3 (D), the source electrode or drain electrode 105a1 is buffed. The end of layer 104a and the source or drain electrode 105b1 are of the buffer layer 104b. It coincides with the end, and the source electrode or drain electrode 105a2, 105a3, so The source electrode or drain electrode 105b2 and 105b3 are the source electrode or drain electrode 10. The end is retracted from 5a1 and 105b1.
0118In other words, first, the titanium film, which is the third conductive film, is etched to form the third conductive layer (10). 5a3, 105b3) are formed, and then the titanium film, which is the first conductive film, is etched. The second conductive film (105a) is etched by etching the aluminum film, which is the second conductive film. 2, 105b2) is formed. Furthermore, the same resist mask as the above wet etching is applied. Using the first conductive film, the titanium film and the metal oxide film 134 are dry-etched to obtain the first conductive film. Form 1 conductive layer (105a1, 105b1) and buffer layer (104a, 104b) To. A source electrode and a drain electrode (105a, 105b) are formed by such a process. Then, the first conductive layer (105a1, 105b1) is a buffer layer (104a, 104b). 2nd conductive layer (105a2, 105b2) and 3rd conductive layer (105a) 3, 105b3) has its end retracted from the first conductive layer (105a1, 105b1). Na A cross-sectional view of this stage is shown in Fig. 3 (D).
0119As described above, the conductive film used for the source electrode and the drain electrode, the buffer layer, and the semiconductor layer If the selectivity is low in the etching process, it acts as an etching stopper. The electrolytic films may be laminated and the etching steps may be performed a plurality of times under different etching conditions.
0120Further, the heat treatment of the formed semiconductor layer 103 is performed in the same manner as in the first embodiment.
0121According to this embodiment, the buffer layers 104a and 104b, the source electrode and the drain electrode 10 Using a resist mask formed from the same photomask for patterning 5a and 105b Therefore, the number of photomasks used can be reduced as compared with the first embodiment. As a result, multiple By combining the above processes into one process, the number of processes can be reduced, the yield can be improved, and manufacturing can be achieved. You can save time.
0122(Embodiment 3) In the present embodiment, a buffer layer having a structure different from that of the first and second embodiments is provided. The structure of the thin film transistor will be described with reference to FIG. In addition, in this embodiment Therefore, the same reference numerals are used for the same ones as in the first embodiment, and detailed description thereof will be omitted.
0123Through the same steps as in the second embodiment, the semiconductor layer 103 becomes indium, gallium, and sub On the lead-containing oxide (IGZO) semiconductor film 133, as shown in FIG. 4 (A), the channel protection layer 1 Form 06.
0124In the present embodiment, the semiconductor film 133 is selectively etched here to form the semiconductor layer 103. A metal oxide film serving as buffer layers 104a and 104b was formed on the semiconductor film 133. A film is formed by the same method as in Form 1. Next, the third photomask in the present embodiment is used. Using the resist mask formed in the above, as shown in Fig. 4 (B), the buffer layers 104a and 104b The semiconductor layer 103 is formed.
0125The source electrode and the drain electrodes 105a and 105b are made of a conductive film, and are the same as those in the first embodiment. To form a film. Here, it is derived on the buffer layers 104a and 104b and the channel protection layer 106. A three-layer laminated film consisting of a titanium film, an aluminum film, and a titanium film as an electric film is formed by a sputtering method. A film is formed. Next, the resister formed by using the fourth photomask in the present embodiment. The conductive film is etched and removed using a screw, and the source electrode and dray are shown as shown in Fig. 4 (C). Electrodes 105a and 105b are formed. FIG. 4 (D) is a plan view, and FIG. 4 (C) is FIG. 4 ( It is sectional drawing cut by A1-A2 in D).
0126Further, the heat treatment of the formed semiconductor layer 103 is performed in the same manner as in the first embodiment.
0127According to this embodiment, patterning of the buffer layers 104a and 104b and the semiconductor layer 103 Since the above is performed at the same time, the number of photomasks used can be reduced as compared with the first embodiment. resulting in , Reduce the number of processes and improve the yield by combining multiple processes into one process , The manufacturing time can be shortened.
0128(Embodiment 4) In this embodiment, a thin film tiger having a plurality of electrically connected gate electrodes and a buffer layer The engineer will be described with reference to FIGS. 5 to 7. FIG. 5 (A) is a plan view, and FIG. 5 (A) B) is a cross-sectional view taken along the line A1-A2 in FIG. 5 (A). Figure 6 (A) is a plan view Therefore, FIG. 6 (B) is a cross-sectional view taken along the line A1-A2 in FIG. 6 (A). Figure 7 (A) shows It is a plan view, and FIG. 7 (B) is a cross-sectional view taken along the line A1-A2 in FIG. 7 (A). Well Further, in the present embodiment, the same reference numerals are used for the same as those in the first embodiment, and the details are detailed. The explanation is omitted. In this embodiment, a structure in which two channel forming regions are connected is adopted. Raise, but not limited to, triples with three channel-forming regions connected So-called multi-gate structure such as gate structure (two or more channel formation regions connected in series) It may have a structure).
0129In the embodiment in which the two channel regions of the thin film transistor of the present embodiment are connected, two chasers are used. A form in which the flannel region is connected only by the buffer layer 104c (Fig. 5), and the buffer layer 104c and (Fig. 6) and the two channel regions are connected to the semiconductor layer 103. There are three forms of connecting the buffer layer 104c and the conductive layer 105c (Fig. 7). Applicable layer The part sandwiched between the first gate electrode 101a and the second gate electrode 101b of the photomask By changing the above, these thin film transistors are formed by the same method as in the first embodiment. it can.
0130Such a multi-gate structure is extremely effective in reducing the off-current value.
0131(Embodiment 5) In the present embodiment, a thin film transistor having a buffer layer having a structure different from that of the above-described first to fourth embodiments is used. The structure of the gista will be described with reference to FIG. The thin film transistor of the present embodiment Can be formed in the same manner as described in the first embodiment except for the buffer layer. Detailed explanation will be omitted.
0132The buffer layer of the present embodiment is composed of two layers, a first buffer layer and a second buffer layer. So The buffer layers 104a and 104b in contact with the boot electrode or the drain electrode are used as the first buffer. A second buff sandwiched between the first buffer layers 104a and 104b and the semiconductor layer 103 as a layer. Let the layers be 114a and 114b, respectively.
0133In other words, the buffer layer of this embodiment is in contact with either the source electrode or the drain electrode. The first buffer layer 104a, the first buffer layer 104b in contact with the other, and the first buffer A second buffer layer 114a sandwiched between the layer 104a and the semiconductor layer 103, and a first buffer layer. It is composed of a second buffer layer 114b sandwiched between 104b and the semiconductor layer 103.
0134Both the first buffer layers 104a and 104b and the second buffer layers 114a and 114b Formed of metal oxide. First buffer layers 104a, 104b and second buffer layer 1 As metal oxides that function as 14a and 114b, titanium oxide, molybdenum oxide, oxidation Zinc, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide Etc. can be used, but titanium oxide is particularly preferable.
0135Further, a metal oxide can be used by doping a different kind of metal. As a dopant Can include indium, gallium, aluminum, zinc, tin and the like. Dopi The carrier concentration in the metal oxide can be increased by the coating. For example, IGZO is the first Targeting, metal oxide as the second target, and at the same time using the sputtering method A mixed film is formed by forming a film (co-sputtering) and used as a buffer layer. May be good.
0136The capacity of the first buffer layers 104a and 104b and the second buffer layers 114a and 114b Rear concentration is a semiconductor layer consisting of oxide (IGZO) containing indium, gallium, and zinc. Higher and more conductive, and the first buffer layers 104a and 104b are the second buffers. Select materials with higher carrier concentrations in layers 114a and 114b. For example, the first buffer Metal oxide is used as the layer, and a mixed film of IGZO and metal oxide is used as the second buffer layer. Can be Source electrode or drain electrode 105a, 10 from semiconductor layer 103 Semiconductor layer 103 by grading so that the carrier concentration increases toward 5b. To reduce the contact resistance between the source electrode or the drain electrodes 105a and 105b. I can cut it.
0137Further, from the semiconductor layer 103 toward the source electrode or the drain electrode 105a and 105b. By sandwiching a buffer layer with a gradient that increases the carrier concentration at the junction interface, the junction boundary The electric field concentrated on the surface can be relaxed.
0138(Embodiment 6) Here, at least the gate insulating film and the oxide semiconductor film are continuously formed without being exposed to the atmosphere. An example of manufacturing an inverted staggered thin film transistor to form a film is shown below. Here, continuous film formation is performed. The process up to the process is shown, and the subsequent process is any one of the first to fifth embodiments. The thin film transistor may be produced according to the above.
0139Manufacture of multi-chamber type as shown in Fig. 9 when continuous film formation is performed without contacting the atmosphere. It is preferable to use an apparatus.
0140A transfer mechanism (typically, a transfer robot 81) for transporting a substrate is provided in the center of the manufacturing apparatus. A transport chamber 80 is provided, and the transport chamber 80 is provided with a plurality of substrates to be carried in and out of the transport chamber. A cassette chamber 82 for setting a cassette case to be stored is connected.
0141Further, a plurality of processing chambers are connected to the transport chamber 80 via gate valves 84 to 88, respectively. Is done. Here, an example of connecting five processing chambers to a transport chamber 80 having a hexagonal upper surface is shown. Na By changing the shape of the upper surface of the transport chamber 80, the number of processing chambers that can be connected can be changed. For example, if it is a quadrangle, three processing chambers can be connected, and if it is an octagon, seven processing chambers can be connected. it can.
0142Of the five processing chambers, at least one processing chamber is a sputtering chamber for sputtering. -. The sputtering chamber should be at least inside the chamber, A power application mechanism for sputtering a target, a gas introduction means, and holding a substrate in a predetermined position A board holder or the like is provided. Also, to reduce the pressure inside the sputtering chamber. , A pressure control means for controlling the pressure in the chamber is provided in the sputtering chamber.
0143The sputtering method includes the RF sputtering method, which uses a high-frequency power supply as the sputtering power supply, and the DC sputtering method. There is also a pulse DC sputtering method that gives a pulse bias. RF sputtering The method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film. Used for.
0144There is also a multi-dimensional sputtering device that can install a plurality of targets made of different materials. Multiple spatter The device can stack and deposit different material films in the same chamber, or multiple types in the same chamber. It is also possible to discharge similar materials at the same time to form a film.
0145In addition, a sputtering device that uses a magnetron sputtering method with a magnet mechanism inside the chamber. Or ECR sputtering using plasma generated using microwaves without using glow discharge There are sputtering equipment that uses the method.
0146As the sputtering chamber, the various sputtering methods described above are appropriately used.
0147In addition, as a film forming method, the target substance and the sputter gas component are chemically reacted during the film forming. The reactive sputtering method for forming these compound thin films and the application of voltage to the substrate during film formation. There is also a bias sputtering method.
0148Also, of the five processing chambers, one of the other processing chambers does not preheat the substrate before sputtering. A heating chamber for processing, a cooling chamber for cooling the substrate after sputtering, or a pump. The chamber is used for razor treatment.
0149Next, an example of the operation of the manufacturing apparatus will be described.
0150Set the substrate cassette containing the substrate 94 with the surface to be filmed facing down in the cassette chamber 82. , The cassette chamber is decompressed by the vacuum exhaust means provided in the cassette chamber 82. In addition, it should be noted. The inside of each processing chamber and the transport chamber 80 is depressurized in advance by the vacuum exhaust means provided in each. Keep it. By doing so, the substrate is exposed to the atmosphere while being transported between the processing chambers. It can be maintained in a clean state.
0151At least a gate electrode is provided in advance on the substrate 94 with the surface to be filmed facing downward. .. For example, a silicon nitride film and acid nitride obtained by the plasma CVD method between the substrate and the gate electrode. An underlying insulating film such as a siliconized silicon film may be provided. Gala containing alkali metal as substrate 94 When using a substrate, the underlying insulating film is semi-conducted by movable ions such as sodium from the substrate. It has the effect of invading the body region and suppressing changes in the electrical characteristics of the TFT.
0152Here, a silicon nitride film covering the gate electrode is formed by the plasma CVD method, and the first layer of the game is formed. Use a substrate on which an insulating film is formed. The silicon nitride film formed by the plasma CVD method is dense. Therefore, the occurrence of pinholes can be suppressed by using the first layer of the gate insulating film. .. An example in which the gate insulating film is laminated is shown here, but the present invention is not particularly limited, and a single layer or three layers are used. The above lamination may be used.
0153Next, the gate valve 83 is opened and the transfer robot 81 cassettes the first substrate 94. The gate valve 84 is opened and transported into the first processing chamber 89, and the gate valve 8 is removed. Close 4. In the first processing chamber 89, the substrate is heated by a heater or a lamp to heat the substrate 94. Removes moisture etc. adhering to. In particular, if the gate insulating film contains water, the TFT electric power Heating before sputter film formation is effective because the gas characteristics may change. The cassette If the moisture is sufficiently removed when the substrate is set in the chamber 82, this heat treatment is performed. Not needed.
0154In addition, a plasma processing means is provided in the first processing chamber 89, and a plastic is provided on the surface of the first layer of the gate insulating film. Zuma processing may be performed. Further, a heating means is provided in the cassette chamber 82, and water is provided in the cassette chamber 82. Heating may be performed to remove the minutes.
0155Next, the gate valve 84 is opened and the substrate is transferred to the transfer chamber 80 by the transfer robot 81. The gate valve 85 is opened and conveyed into the second processing chamber 90, and the gate valve 85 is closed.
0156Here, the second processing chamber 90 is a sputtering chamber using the RF magnetron sputtering method. -. In the second processing chamber 90, a silicon oxide film (SiO) is used as the second gate insulating film. An x film (x> 0)) is formed. As the second gate insulating film, in addition to the silicon oxide film, Aluminum oxide film (Al<sub>2</sub>O<sub>3</sub>Membrane), Magnesium Oxide Membrane (MgOx Membrane (x> 0)), Aluminum nitride film (AlNx film (x> 0)), yttrium oxide film (YOx film (x> 0)) )) Etc. can be used.
0157In addition, a small amount of halogen elements such as fluorine and chlorine are added to the second gate insulating film. However, mobile ions such as sodium may be immobilized. The method is a chamber Sputtering is performed by introducing a gas containing a halogen element inside. However, halogen elements When introducing gas containing it, it is necessary to install abatement equipment in the exhaust means of the chamber. Game SIMS (Secondary Ion Mass Spectrometer) was used to determine the concentration of halogen elements contained in the insulating film. Concentration peak obtained by analysis is 1 × 10<sup>15</sup>cm<sup>-3</sup>Above 1 × 10<sup>20</sup>cm<sup>-3</sup>below It is preferably within the range.
0158When obtaining a SiOx film (x> 0), use artificial quartz as the target, and use a rare gas, typically Uses a sputtering method using argon or single crystal silicon as a target, and oxygen gas. By using the reactive sputtering method to obtain a SiOx film (x> 0) by chemically reacting with Wear. Here, in order to include as much oxygen as possible in the SiOx film (x> 0), the target is Artificial quartz is used as the source, and the atmosphere is oxygen-only, or the oxygen content is 90% or more, and Ar is Sputtering is performed in an atmosphere of 10% or less to form a SiOx film (x> 0) with excess oxygen. To do.
0159After the SiOx film (x> 0) is formed, the gate valve 85 is opened and transported without touching the atmosphere. The board is transported to the transport chamber 80 by the robot 81, the gate valve 86 is opened, and the third processing chamber is opened. Transport into 91 and close the gate valve 86.
0160Here, the third processing chamber 91 is a sputtering chamber using a DC magnetron sputtering method. -. In the third processing chamber 91, a semiconductor layer (IGZO film) is formed. In, Ga, And in an oxide semiconductor target containing Zn, in a noble gas atmosphere or in an oxygen atmosphere Can be formed with. Here, in order to include as much oxygen as possible in the IGZO film, Oxide semiconductors containing In, Ga, and Zn are used as targets, and in an oxygen-only atmosphere. , Or pulse DC sputtering method in an atmosphere where oxygen is 90% or more and Ar is 10% or less. Sputtering is performed to form an oxygen-excessive IGZO film.
0161Thus, oxygen-rich SiOx (x> 0) membranes and oxygen-rich IG without contact with the atmosphere. By continuously forming a ZO film, the interface state is stabilized due to the oxygen-excessive films, and TF The reliability of T can be improved. If the substrate comes into contact with the atmosphere before the IGZO film is formed, Moisture adheres and adversely affects the interface condition, resulting in variation in threshold value and deterioration of electrical characteristics. It may cause symptoms such as normal-on TFT. Moisture is hydrogenated It is a compound, and hydrogen compounds are present at the interface by continuously forming a film without touching the atmosphere. Existence can be excluded. Therefore, by continuously forming a film, the threshold value varies. To reduce luck, prevent deterioration of electrical characteristics, and shift the TFT to the normally-on side. Reductions, preferably shifts, can be eliminated.
0162In addition, the target of artificial quartz and In, Ga, in the sputtering chamber of the second processing chamber 90 And an oxide semiconductor target containing Zn are installed and laminated sequentially using a shutter. It is also possible to carry out laminating in the same chamber by continuously forming a film. shutter Is provided between the target and the substrate, and the target for film formation opens the shutter to perform film formation. The target that does not move is closed by the shutter. The advantage of stacking in the same chamber is , The number of chambers used can be reduced, and the par can be used while transporting the substrate between different chambers. This is a point where it is possible to prevent tickles and the like from adhering to the substrate.
0163Next, the gate valve 86 is opened and the substrate is operated by the transfer robot 81 without touching the atmosphere. To the transport chamber 80, open the gate valve 87 and transport it into the fourth processing chamber 92, and the gate Close valve 87.
0164Here, the fourth processing chamber 92 is a sputtering chamber using the RF magnetron sputtering method. -. In the fourth processing chamber 92, a silicon oxide film (silicon oxide film) is used as an insulating film to be a channel protective layer. A SiOx film (x> 0)) is formed. Also, as a channel protection layer, a silicon oxide film Besides, aluminum oxide film (Al<sub>2</sub>O<sub>3</sub>Membrane), Magnesium Oxide Membrane (MgOx Membrane (x> 0) )), Aluminum nitride film (AlNx film), Yttrium oxide film (YOx film (x> 0)) Etc. can be used.
0165In addition, a small amount of halogen elements such as fluorine and chlorine are added to the film to protect the channel. Mobile ions such as thorium may be immobilized. The method is to put it in the chamber. Sputtering is performed by introducing a gas containing a logene element. However, moths containing halogen elements When introducing a gas, it is necessary to install abatement equipment in the exhaust means of the chamber. Channel protection The concentration of halogen elements contained in the protective layer is analyzed using SIMS (Secondary Ion Mass Spectrometer). The concentration peak obtained by<sup>15</sup>cm<sup>-3</sup>Above 1 × 10<sup>20</sup>cm<sup>-3</sup>The following range It is preferably inside.
0166When obtaining the SiOx film (x> 0) as the channel protection layer, use artificial quartz as the target. Noble gas, typically argon, or silicon as the target , Using the reactive sputtering method to obtain a SiOx film (x> 0) by chemically reacting with oxygen gas. Can be Here, in order to contain as much oxygen as possible in the SiOx film (x> 0) , Using artificial quartz as a target, in an oxygen-only atmosphere, or with 90% or more oxygen First, sputtering is performed in an atmosphere where Ar is 10% or less, and an oxygen-excessive SiOx film (x> Form 0).
0167In this way, oxygen-rich SiOx membrane (x> 0) and oxygen-rich IG without touching the atmosphere By continuously forming a ZO film and an oxygen-excessive channel protection layer, all three layers are oxygen-excessive. Since the film is used, the interface state is more stable and the reliability of the TFT can be improved. IGZO film If the substrate comes into contact with the atmosphere before and after the film formation, moisture etc. will adhere and adversely affect the interface state. Variations in threshold values, deterioration of electrical characteristics, symptoms of normal-on TFT, etc. May cause. Moisture is a hydrogen compound, and continuous film formation without contact with the atmosphere By doing so, it is possible to eliminate the presence of the hydrogen compound at the interface of the IGZO film. .. Therefore, by continuously forming three layers, the variation in the threshold value is reduced and the electrical characteristics are inferior. Prevents the shift of the TFT and reduces the shift of the TFT to the normally-on side, preferably no shift. Can be combed.
0168In addition, the target of artificial quartz and In, Ga, in the sputtering chamber of the second processing chamber 90 And an oxide semiconductor target containing Zn are installed and laminated sequentially using a shutter. By continuously forming three layers, the layers can be laminated in the same chamber. Same The advantage of stacking in a chamber is that the number of chambers used can be reduced. In that it is possible to prevent particles and the like from adhering to the substrate while transporting the substrate between the chambers. is there.
0169By repeating the above steps, a film formation process is performed on the substrates in the cassette case to process a plurality of substrates. After finishing, the vacuum in the cassette chamber is opened to the atmosphere, and the substrate and the cassette are taken out.
0170The channel protection layer is then selectively etched to pattern the IGZO film. Furthermore, the IGZO film is selectively etched. Dry etching and wet etching It may be formed by using it, or it may be divided into two etchings and selectively etched respectively. Good. At this stage, the surface of the gate insulating film is exposed in the region where the IGZO film has been removed.
0171Next, the position where the channel protection layer overlaps the gate electrode, that is, the channel shape of the IGZO film Etching is performed leaving only the portion that overlaps the position that becomes the growth region. Channel protection layer here Etching uses conditions where the etching rate is sufficiently different from that of the IGZO film. channel If there is not enough difference in etching rate by etching the protective layer, the surface of the IGZO film is a part. Etching is performed to form a region having a thinner film thickness than the region overlapping the channel protection layer. If the channel protection layer is made of the same material as the gate insulating film, it will be etched by this etching. The insulating film is also etched. Therefore, the gate insulating film should not be etched. It is preferable to use a material different from the gate insulating film for the channel protective layer. .. In this embodiment, the gate insulating film has two layers, and the upper layer is a SiOx film (x> 0). Although it may be removed, the lower layer is a silicon nitride film and functions as an etching stopper. To do.
0172Next, the substrate is set again in the cassette chamber of the multi-chamber type manufacturing apparatus shown in FIG. To.
0173Next, after decompressing the cassette chamber, the gate valve 83 is opened without touching the atmosphere. Then, the transfer robot 81 transfers the board to the transfer chamber 80, opens the gate valve 88, and the fifth Transport into the processing chamber 93 and close the gate valve 88.
0174Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. -. In the fifth processing chamber 93, a film is formed on the buffer layer. Spat in the 5th processing room 93 Install both the titanium target and the aluminum target in the tachamber. Lamination is performed in the same chamber by sequentially laminating using a cutter to form a continuous film. .. Here, the shutter shields the aluminum target and introduces oxygen gas to the rear. Titanium oxide film (TiOx film (x> 0)) is formed by performing active sputtering. This The TiOx membrane (x> 0) functions as a source or drain region. Then the 5th Oxygen gas is discharged from the processing chamber 93 of the above, argon gas is introduced, and sputtering is performed. A titanium film is formed. Next, the titanium target is shielded with a shutter and placed on the titanium film. Laminate the aluminum film, then shield the aluminum target with a shutter, A titanium film is laminated on the luminium film.
0175In this way, the TiOx film (x> 0) and the metal multilayer film are continuously formed without being exposed to the atmosphere. By forming a film, a good interface state is realized between the TiOx film (x> 0) and the metal multilayer film. And the contact resistance can be reduced.
0176By repeating the above steps, a film formation process is performed on the substrates in the cassette case to process a plurality of substrates. After finishing, the vacuum in the cassette chamber is opened to the atmosphere, and the substrate and the cassette are taken out.
0177Next, the metal multilayer film is selectively etched to form the source electrode and the drain electrode. To. Furthermore, etching is performed using the source electrode and drain electrode as masks, and a TiOx film ( The source or drain region is formed by selectively etching x> 0). TiO When etching x film (x> 0), the channel protection layer functions as an etching stopper. To.
0178By the above steps, an inverted staggered thin film transistor having a channel protection layer can be produced.
0179Further, in the above step, the TiOx film (x> 0) and the metal laminated film are formed in the same chamber. However, the film is not particularly limited, and the film may be formed in separate chambers.
0180Here, the explanation was given using a multi-chamber manufacturing device as an example, but a sputtering chamber is used. Continuous film formation is performed without touching the atmosphere using an in-line manufacturing device that is connected in series. You may.
0181Further, the apparatus shown in FIG. 9 is a so-called face-down method in which the substrate is set with the surface to be filmed facing downward. However, the processing chamber may be a vertical processing chamber in which the substrate is erected vertically. Vertical installation method The processing room has the advantage of having a smaller footprint than the face-down type processing room. Further, it is effective when a large-area substrate that may be bent due to the weight of the substrate is used.
0182This embodiment can be implemented in combination with other embodiments as appropriate.
0183(Embodiment 7) In the present embodiment, at least a part of the drive circuit and a thin film arranged in the pixel portion on the same substrate. An example of producing a Langista will be described below.
0184The thin film transistor to be arranged in the pixel portion is formed according to the first to fifth embodiments. .. Further, the thin film transistors shown in the first to fifth embodiments are n-channel TFTs. Therefore, among the drive circuits, a part of the drive circuits that can be configured with an n-channel TFT. Is formed on the same substrate as the thin film transistor of the pixel portion.
0185An example of a block diagram of the active matrix type liquid crystal display device is shown in FIG. 10 (A). Figure 10 The display device shown in (A) has a pixel unit 5 having a plurality of pixels having a display element on the substrate 5300. 301, a scan line drive circuit 5302 that selects each pixel, and a video signal to the selected pixel. It has a signal line drive circuit 5303 that controls the input of.
0186The pixel unit 5301 has a plurality of signals arranged so as to extend in the column direction from the signal line drive circuit 5303. A scanning line drive circuit connected to the signal line drive circuit 5303 by lines S1 to Sm (not shown). By a plurality of scanning lines G1 to Gn (not shown) arranged extending in the row direction from 5302. It is connected to the scanning line drive circuit 5302 and corresponds to the signal lines S1 to Sm and the scanning lines G1 to Gn. It has a plurality of pixels (not shown) arranged in a matrix. And each pixel is Line Sj (any one of signal lines S1 to Sm), scanning line Gi (scanning line G1 to Gn) Connect with any one).
0187Further, the thin film transistors shown in the first to fifth embodiments are n-channel TFTs. A signal line drive circuit composed of an n-channel TFT will be described with reference to FIG.
0188The signal line drive circuit shown in FIG. 11 is a driver IC 5601 and a switch group 5602_1 to 56. 02_M, 1st wiring 5611, 2nd wiring 5612, 3rd wiring 5613 and wiring 56 It has 21_1 to 5621_M. Switch group 5602_1 ~ 5602_M Each First thin film transistor 5603a, second thin film transistor 5603b and third thin film It has a transistor 5603c.
0189The driver IC5601 has the first wiring 5611, the second wiring 5612, and the third wiring 5613. And it is connected to wiring 5621_1 to 5621_M. And switch group 5602_1 ~ 5602_M Each is the first wire 5611, the second wire 5612, and the third wire 561. Wiring 5621_1 ~ 5 corresponding to 3 and switch group 5602_1 ~ 5602_M respectively Connected to 621_M. And each of the wirings 5621_1 to 5621_M is the first Thin film transistor 5603a, second thin film transistor 5603b and third thin film transistor It is connected to three signal lines via the Gista 5603c. For example, wiring in row J 5621 _J (any one of wiring 5621_1 to wiring 5621_M) is the switch group 5602. _J's first thin film transistor 5603a, second thin film transistor 5603b And through the third thin film transistor 5603c, signal line Sj-1, signal line Sj, signal line S Connected to j + 1.
0190The first wiring 5611, the second wiring 5612, and the third wiring 5613 are connected to each other. The number is entered.
0191The driver IC5601 is preferably formed on a single crystal substrate. further , Switch groups 5602_1 to 5602_M are the images shown in the first to fifth embodiments. It is desirable that it is formed on the same substrate as the element part. Therefore, the driver IC5601 And the switch group 5602_1 to 5602_M should be connected via FPC or the like.
0192Next, refer to the timing chart of FIG. 12 for the operation of the signal line drive circuit shown in FIG. I will explain it in the light. In the timing chart of FIG. 12, the scanning line Gi on the i-th line is selected. The timing chart when is shown. Furthermore, the selection period of the scan line Gi on the i-th line Is divided into a first subselection period T1, a second subselection period T2 and a third subselection period T3. It has been split. Further, the signal line drive circuit of FIG. 11 is a field where scanning lines of other lines are selected. In that case, the operation is the same as in FIG.
0193In the timing chart of FIG. 12, the wiring 5621_J in the Jth column is the first thin film transition. Star 5603a, 2nd thin film transistor 5603b and 3rd thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj + 1 via 3c Shown.
0194In the timing chart of FIG. 12, the timing at which the scanning line Gi on the i-th row is selected, the th-th On / off timing of 1 thin film transistor 5603a 5703a, 2nd thin film tiger On / off timing of engineer 5603b 5703b, 3rd thin film transistor 56 03c on / off timing Input to 5703c and wiring 5621_J in column J It shows signal 5721_J.
0195For wiring 5621_1 to wiring 5621_M, the first sub-selection period T1 and the second sub-selection In the selection period T2 and the third sub-selection period T3, different video signals are input. .. For example, the video signal input to wiring 5621_J during the first subselection period T1 Input to signal line Sj-1 and input to wiring 5621_J in the second subselection period T2 The video signal is input to the signal line Sj and wired 5621 during the third subselection period T3. The video signal input to _J is input to the signal line Sj + 1. In addition, the first subselection period Wiring 5621_ in the interval T1, the second subselection period T2, and the third subselection period T3. The video signal input to J is Data_j-1, Data_j, Data_j +, respectively. Let it be 1.
0196As shown in FIG. 12, the first thin film transistor 5603 during the first subselection period T1. When a is turned on, the second thin film transistor 5603b and the third thin film transistor 5603c Turns off. At this time, Data_j-1 input to wiring 5621_J is the first thin film. It is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 Then, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a is turned on. And the third thin film transistor 5603c is turned off. At this time, input to wiring 5621_J Data_j is input to the signal line Sj via the second thin film transistor 5603b. Is done. In the third subselection period T3, the third thin film transistor 5603c is turned on and the first The thin film transistor 5603a and the second thin film transistor 5603b are turned off. this When Data_j + 1 input to wiring 5621_J is the third thin film transistor 56 It is input to the signal line Sj + 1 via 03c.
0197From the above, the signal line drive circuit of FIG. 11 divides one gate selection period into three. , Input video signal to 3 signal lines from 1 wire 5621 during 1 gate selection period Can be done. Therefore, in the signal line drive circuit of FIG. 11, the driver IC5601 is formed. The number of connections between the board and the board on which the pixel part is formed is reduced to about 1/3 of the number of signal lines. be able to. The signal line drive circuit in Fig. 11 is reliable because the number of connections is reduced to about 1/3. Gender, yield, etc. can be improved.
0198As shown in FIG. 11, one gate selection period is divided into a plurality of sub-selection periods, and a plurality of sub-selections are performed. Input video signals from one wire to each of multiple signal lines in each of the selection periods If possible, the arrangement and number of thin film transistors, the driving method, etc. are not limited.
0199For example, one wire to three or more signal lines in each of three or more subselect periods. When inputting a video signal to each, control the thin film transistor and the thin film transistor. Wiring for this should be added. However, one gate selection period is divided into four or more sub-selection periods. When divided, one sub-selection period becomes shorter. Therefore, one gate selection period is two or It is desirable to be divided into three sub-selection periods.
0200As another example, as shown in the timing chart of FIG. 13, one selection period is pre-charged. In the period Tp, the first sub-selection period T1, the second sub-selection period T2, the third selection period T3 It may be divided. Furthermore, in the timing chart of FIG. 13, the scan line Gi on the i-th line is selected. Timing, on / off timing of the first thin film transistor 5603a 5803 a, On / off timing of the second thin film transistor 5603b 5803b, third thin film On / off timing of membrane transistor 5603c 5803c and J-th row wiring 562 Indicates the signal 5821_J input to 1_J. Precharge as shown in Figure 13 First thin film transistor 5603a, second thin film transistor 5603 in period Tp b and the third thin film transistor 5603c are turned on. At this time, enter the wiring 5621_J The precharge voltage Vp applied is the first thin film transistor 5603a and the second thin film transistor. Signal line Sj- via Gista 5603b and 3rd thin film transistor 5603c, respectively. 1. Input to signal line Sj and signal line Sj + 1. The first in the first subselection period T1 Thin film transistor 5603a is turned on, second thin film transistor 5603b and third thin film The membrane transistor 5603c turns off. At this time, Dat input to wiring 5621_J a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. .. In the second subselection period T2, the second thin film transistor 5603b is turned on and the first thin film transistor is turned on. The film transistor 5603a and the third thin film transistor 5603c are turned off. At this time , Data_j input to wiring 5621_J is the second thin film transistor 5603b It is input to the signal line Sj via. In the third subselection period T3, the third thin film transistor 5603c is turned on, the first thin film transistor 5603a and the second thin film transistor 5 603b turns off. At this time, the Data_j + 1 input to the wiring 5621_J is the first. It is input to the signal line Sj + 1 via the thin film transistor 5603c of 3.
0201From the above, the signal line drive circuit of FIG. 11 to which the timing chart of FIG. By setting a precharge selection period before the selection period, the signal line can be precharged. Therefore, the video signal can be written to the pixels at high speed. In addition, in Fig. 13. However, the same parts as in FIG. 12 are shown by using a common code, and the same part or the same function is used. A detailed description of the portion having the above will be omitted.
0202Further, the configuration of the scanning line drive circuit will be described. The scan line drive circuit is a shift register, I have a ffa. In some cases, it may have a level shifter. Scanning line drive In the circuit, the clock signal (CLK) and start pulse signal (SP) are stored in the shift register. ) Is input to generate a selection signal. The generated selection signal is buffered It is buffer amplified and supplied to the corresponding scan line. One line of pixels is included in the scanning line. The gate electrode of the Langista is connected. And the transistor of one line of pixels Since it must be turned on all at once, the buffer should be able to carry a large current. Used.
020314 and 15 are used for a form of the shift register used as a part of the scanning line drive circuit. I will explain.
0204Figure 14 shows the circuit configuration of the shift register. The shift register shown in FIG. 14 has a plurality of pretensions. It is composed of flip-flops (flip-flops 5701_1 to 5701_n). Also, the first 1 clock signal, 2nd clock signal, start pulse signal, reset signal are input Works.
0205The connection relationship of the shift register shown in FIG. 14 will be described. The shift register in Fig. 14 is the i-stage. Eye flip-flop 5701_i (flip-flop 5701_1 ~ 5701_n) In either one), the first wiring 5501 shown in Fig. 15 becomes the seventh wiring 5717_i-1. Connected, the second wire 5502 shown in Figure 15 is connected to the seventh wire 5717_i + 1. , The third wire 5503 shown in FIG. 15 is connected to the seventh wire 5717_i and is shown in FIG. The sixth wire 5506 is connected to the fifth wire 5715.
0206Further, the fourth wiring 5504 shown in FIG. 15 is the second wiring in the odd-numbered flip-flop. Connected to 5712, and in even-numbered flip-flops connected to third wire 5713, The fifth wire 5505 shown in FIG. 15 is connected to the fourth wire 5714.
0207However, the first wiring 5501 shown in FIG. 15 of the first-stage flip-flop 5701_1 is the first. No. 1 shown in FIG. 15 of the nth-stage flip-flop 5701_n connected to the wiring 5711 of 1. The second wire 5502 is connected to the sixth wire 5716.
0208The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Good. Furthermore, the 4th wiring 5714 and the 5th wiring 5715 are connected to the 1st power line and the 5th wiring, respectively. It may be called the power supply line of 2.
0209Next, the details of the flip-flop shown in FIG. 14 are shown in FIG. Pretending to be shown in FIG. The desktop is the first thin film transistor 5571, the second thin film transistor 5572, 3rd thin film transistor 5573, 4th thin film transistor 5574, 5th thin film transistor Gista 5575, 6th thin film transistor 5576, 7th thin film transistor 5577 And has an eighth thin film transistor 5578. The first thin film transistor 5571, 2nd thin film transistor 5572, 3rd thin film transistor 5573, 4th thin film transistor Gista 5574, 5th thin film transistor 5575, 6th thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel type. It is a transistor, and the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). It shall be in a conductive state at that time.
0210Next, the connection configuration of the flip-flop shown in FIG. 14 is shown below.
0211First Electrode of First Thin Film Transistor 5571 (either Source Electrode or Drain Electrode) Is connected to the fourth wire 5504, and the second electrode (saw) of the first thin film transistor 5571 The other of the electrode or drain electrode) is connected to the third wire 5503.
0212The first electrode of the second thin film transistor 5572 is connected to the sixth wire 5506, and the second Thin film transistor 5527 The second electrode is connected to the third wire 5503.
0213The first electrode of the third thin film transistor 5573 is connected to the fifth wire 5505, and the third The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5527. The gate electrode of the third thin film transistor 5573 is connected to the fifth wire 5505. Will be done.
0214The first electrode of the fourth thin film transistor 5574 is connected to the sixth wire 5506, and the fourth The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5527. The gate electrode of the 4th thin film transistor 5574 is connected to the 1st thin film transistor 5 It is connected to the gate electrode of 571.
0215The first electrode of the fifth thin film transistor 5575 is connected to the fifth wire 5505, and the fifth The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. The gate electrode of the fifth thin film transistor 5575 is connected to the first wire 5501. Will be done.
0216The first electrode of the sixth thin film transistor 5576 is connected to the sixth wire 5506, and the sixth The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. The gate electrode of the 6th thin film transistor 5576 is connected to the 2nd thin film transistor 5 Connected to the gate electrode of 572.
0217The first electrode of the seventh thin film transistor 5577 is connected to the sixth wire 5506, and the seventh The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. The gate electrode of the 7th thin film transistor 5577 is connected to the 2nd wiring 5502. Will be done. The first electrode of the eighth thin film transistor 5578 is connected to the sixth wire 5506. , The second electrode of the 8th thin film transistor 5578 is the device of the 2nd thin film transistor 557 The gate electrode of the 8th thin film transistor 5578 is connected to the electrode and the 1st wiring 550. Connected to 1.
0218The gate electrode of the first thin film transistor 5571 and the fourth thin film transistor 5574 Gate electrode, 5th thin film transistor 5575 2nd electrode, 6th thin film transistor Connect the 2nd electrode of 5576 and the 2nd electrode of 7th thin film transistor 5577. The mode is 5543. In addition, the gate electrode of the second thin film transistor 5527, the third thin film The second electrode of the membrane transistor 5573, the second electrode of the fourth thin film transistor 5574, The gate electrode of the 6th thin film transistor 5576 and the 8th thin film transistor 5578 The connection point of the electrode of 2 is node 5544.
0219The first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5 Even if 504 is called the first signal line, the second signal, the third signal line, and the fourth signal line, respectively. Good. Furthermore, the fifth wiring 5505 is the first power supply line, and the sixth wiring 5506 is the second power supply line. You may call it.
0220Further, the signal line drive circuit and the scanning line drive circuit are shown in the nchas shown in the first to fifth embodiments. It is also possible to make it only with a flannel type TFT. N shown in Embodiment 1 to Embodiment 5 Channel-type TFTs have high transistor mobility, so the drive frequency of the drive circuit is increased. It becomes possible. Further, the n-channel TFTs shown in the first to fifth embodiments are Since the parasitic capacitance is reduced by the buffer layer, the frequency characteristics (called f characteristics) are high. For example, the scanning line drive times using the n-channel TFT shown in the first to fifth embodiments. Since the road can be operated at high speed, increase the frame frequency or black. It is also possible to realize screen insertion.
0221Furthermore, the channel width of the transistor of the scanning line drive circuit can be increased, and multiple scanning lines can be used. A higher frame frequency can be realized by arranging a drive circuit, etc. To. When arranging multiple scan line drive circuits, scan line drive for driving even-numbered scan lines The circuit is placed on one side, and the scan line drive circuit for driving the odd-numbered lines is placed on the other side. By placing it, it is possible to increase the frame frequency.
0222Further, when manufacturing an active matrix type light emitting display device, it is duplicated in at least one pixel. In order to arrange a number of thin film transistors, it is preferable to arrange a plurality of scanning line drive circuits. An example of a block diagram of the active matrix type light emission display device is shown in FIG. 10 (B).
0223The display device shown in FIG. 10B is an image having a plurality of pixels having a display element on the substrate 5400. Element 5401, first scanning line drive circuit 5402 for selecting each pixel, and second scanning line drive Circuit 5404 and signal line drive circuit 540 that controls the input of video signals to selected pixels. Has 3 and.
0224When the video signal input to the pixels of the display device shown in Fig. 10 (B) is in digital format, Pixels are in a light emitting or non-light emitting state by switching the transistor on and off. .. Therefore, the gradation can be displayed by using the area gradation method or the time gradation method. Area floor The method is to divide one pixel into multiple sub-pixels, and each sub-pixel is driven independently based on the video signal. It is a driving method that displays gradation by making it. In addition, the time gradation method is the period when the pixels emit light. This is a drive method for displaying gradation by controlling the interval.
0225Since the light emitting element has a higher response speed than the liquid crystal element, it is more suitable for the time gradation method than the liquid crystal element. doing. Specifically, when displaying by the time gradation method, one frame period is divided into multiple subframes. Divide into periods. Then, according to the video signal, the luminescent elements of the pixels in each subframe period. Put the child in a luminous or non-luminous state. By splitting into multiple subframe periods The total length of the period during which the pixels actually emit light during one frame period is controlled by the video signal. It can be controlled and the gradation can be displayed.
0226In the light emitting device shown in FIG. 10B, a switching TFT and a current control are used for one pixel. When arranging two with your TFT, the first run, which is the gate wiring of the switching TFT The signal input to the inspection line is generated by the first scanning line drive circuit 5402, and the current control TFT game The signal input to the second scanning line, which is the wiring, is generated by the second scanning line drive circuit 5404. The signal input to the first scanning line and the signal input to the second scanning line are shown. The number and the number may be generated by one scanning line drive circuit. Also, for example, switch The operation of the switching element is controlled by the number of each transistor that the ching element has. It is possible that a plurality of first scanning lines used for the above are provided in each pixel. In this case, multiple All the signals input to the first scan line of the above may be generated by one scan line drive circuit, or may be duplicated. It may be generated by each scan line drive circuit of a number.
0227In addition, the light emitting device can also be configured with an n-channel TFT among the drive circuits. A part of the drive circuit can be formed on the same substrate as the thin film transistor of the pixel portion. Well Further, the signal line drive circuit and the scanning line drive circuit are shown in the n-channels shown in the first to fifth embodiments. It is also possible to make it only with a Le-shaped TFT.
0228Further, the drive circuit described above is not limited to the liquid crystal display device and the light emitting device, but also has a switching element and electricity. It may be used for electronic paper that drives electronic ink by using an element that is specifically connected. Electronic Paper is also called an electrophoresis display device (electrophoresis display), and has the same reading as paper. It has the advantages of ease of use, low power consumption compared to other display devices, and the ability to make it thinner and lighter. Have.
0229The electrophoretic display may take various forms, but the first grain with a positive charge Microcapsules containing children and second particles with a negative charge become a solvent or solute It is a plurality of dispersed microcapsules, and by applying an electric field to the microcapsules, the microcapsules are microscopic. Move the particles in the capsule in opposite directions to display only the color of the particles gathered on one side It is a thing. The first particle or the second particle contains a dye and smells when there is no electric field. It does not move. Also, the color of the first particle and the color of the second particle are different (colorless). Including).
0230In this way, in the electrophoresis display, a substance with a high dielectric constant moves to an electric field region with a high dielectric constant. It is a display that utilizes the so-called dielectrophoretic effect. The electrophoresis display is a liquid crystal The polarizing plate required for the display device and the opposing substrate are not required for the electrophoresis display device, and the thickness and weight are half. Decrease.
0231The microcapsules dispersed in a solvent are called electronic inks. Electronic ink can be printed on the surface of glass, plastic, cloth, paper, etc. Also Color display is also possible by using a color filter or particles having a dye.
0232In addition, the above microphone is appropriately sandwiched between two electrodes on the active matrix substrate. By arranging multiple locapsules, an active matrix type display device is completed, and a microcap The display can be performed by applying an electric field to the cell. For example, Embodiment 1 to Embodiment 5 can be used.
0233The first particles and the second particles in the microcapsules are conductor material, insulator material, and so on. Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electroluminescence Trochromic materials, a type of material selected from magnetic electrophoretic materials, or composite materials of these You can use it.
0234This embodiment can be implemented in combination with other embodiments as appropriate.
0235(Embodiment 8) A thin film transistor according to one aspect of the present invention is produced, and the thin film transistor is used as a pixel portion and further as a drive. A semiconductor device (also called a display device) having a display function can be manufactured by using it in a moving circuit. To. In addition, using the thin film transistor of one aspect of the present invention, a part or the whole of the drive circuit can be used. A system-on-panel can be formed by integrally forming on the same substrate as the pixel portion.
0236The display device includes a display element. Display elements include liquid crystal elements (also called liquid crystal display elements) and light emission. An element (also referred to as a light emitting display element) can be used. The light emitting element depends on the current or voltage. This category includes elements whose brightness is controlled, specifically, inorganic EL (Electr). o Luminescence) elements, organic EL elements, etc. are included. Also, it's electronic ink However, a display medium whose contrast changes due to an electric action can also be applied.
0237Further, the display device includes a panel in which the display element is sealed and a controller on the panel. Includes modules that are equipped with ICs and the like. Further, one aspect of the present invention is described in the table. Regarding the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device. However, the element substrate is provided with means for supplying a current to the display element in each of a plurality of pixels. element Specifically, the substrate may be in a state in which only the pixel electrodes of the display element are formed, or the pixels. In the state after forming the conductive film to be the electrode and before etching to form the pixel electrode. It may be, and all forms apply.
0238The display device in the present specification is an image display device, a display device, or an optical device. Refers to the source (including lighting equipment). Also, a connector, such as FPC (Flexible pr) inted circuit) or TAB (Tape Automated Bon) ding) Taken by tape or TCP (Tape Carrier Package) Attached module, module with printed wiring board at the end of TAB tape or TCP IC (Integrated Circuit) by COG (Chip On Glass) method for the display element All modules directly mounted on the road) shall be included in the display device.
0239In the present embodiment, an example of a liquid crystal display device is shown as a semiconductor device according to one aspect of the present invention.
024016 (A) and 16 (B) show an active matrix type liquid crystal display device to which one aspect of the present invention is applied. Indicates the position. FIG. 16 (A) is a plan view of the liquid crystal display device, and FIG. 16 (B) is shown in FIG. 16 (A). It is sectional drawing of the line VX in a place. As a thin film transistor 201 used in semiconductor devices Can be produced in the same manner as the thin film transistor shown in the fourth embodiment, and is an IGZO semiconductor layer and a metal. It is a highly reliable thin film transistor having a buffer layer containing an oxide. Also, the form of implementation The thin film transistor shown in the first to third embodiments and the fifth embodiment is also the thin film transistor of the present embodiment. It can also be applied as data 201.
0241The liquid crystal display device of the present embodiment of FIG. 16A has a source wiring layer 202 and a multi-gate structure. The reverse staggered thin film transistor 201, the gate wiring layer 203, and the capacitive wiring layer 204 are included.
0242Further, in FIG. 16B, the liquid crystal display device of the present embodiment is a thin film having a multi-gate structure. Used for transistor 201, insulating layer 211, insulating layer 212, insulating layer 213, and display element Substrate 2 provided with an electrode layer 255, an insulating layer 261 functioning as an alignment film, and a polarizing plate 268. 00, an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, and a color The liquid crystal layer 2 is the substrate 266 provided with the colored layer 264 and the polarizing plate 267 that function as an filter. It sandwiches 62 and faces each other, and has a liquid crystal display element 260.
0243Although FIG. 16 shows an example of a transmissive liquid crystal display device, one aspect of the present invention is a reflective liquid crystal display device. Can also be applied to semi-transmissive liquid crystal display devices.
0244Further, in the liquid crystal display device of FIG. 16, a polarizing plate 267 is provided on the outside (visual side) of the substrate 266. An example is shown in which the colored layer 264 is provided inside and the electrode layer 265 used for the display element is provided in this order. The plate 267 may be provided inside the substrate 266. The laminated structure of the polarizing plate and the colored layer is also shown in Fig. 16 Not limited to (B), it may be appropriately set depending on the material of the polarizing plate and the colored layer and the manufacturing process conditions. I. Further, a light-shielding film that functions as a black matrix may be provided.
0245The electrode layers 255 and 265 that function as the pixel electrode layer are indium containing tungsten oxide. Oxide, indium zinc oxide containing tungsten oxide, indium acid containing titanium oxide Indium tin oxide containing compound and titanium oxide, indium tin oxide (hereinafter referred to as ITO) .. ), Indium zinc oxide, indium tin oxide with silicon oxide added, etc. A conductive material having can be used.
0246Further, as the electrode layers 255 and 265, a conductor containing a conductive polymer (also referred to as a conductive polymer) is provided. It can be formed using an electric composition. Pixel electrodes formed using the conductive composition Sheet resistance is 10000Ω / or less, and light transmittance at wavelength 550nm is 70% or more. Is preferable. In addition, the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm. The following is preferable.
0247As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Or a derivative thereof, or a copolymer of two or more of these.
0248Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. ..
0249This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate. Is.
0250(Embodiment 9) In this embodiment, an example of electronic paper is shown as a semiconductor device according to one aspect of the present invention.
0251FIG. 23 shows an active matrix type electric device as an example of a semiconductor device to which one aspect of the present invention is applied. Shows child paper. As a thin film transistor 581 used in a semiconductor device, the embodiment It can be produced in the same manner as the thin film transistor shown in the state 4, and contains an IGZO semiconductor layer and a metal oxide. It is a highly reliable thin film transistor having a buffer layer. In addition, Embodiment 1 to Implementation The thin film transistor shown in the third and fifth embodiments is also the thin film transistor 581 of the present embodiment. Can also be applied.
0252The electronic paper of FIG. 23 is an example of a display device using the twist ball display method. Twist The Tobole display method is an electrode layer that uses spherical particles painted in black and white for the display element. It is placed between the first electrode layer and the second electrode layer, and the potential difference between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles.
0253The thin film transistor 581 is an inverted staggered thin film transistor with a multi-gate structure. An opening formed in the first electrode layer 587 and the insulating layer 585 by the loose electrode and the drain electrode. It is connected by and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588 Has a black region 590a and a white region 590b, and is filled with liquid around it. Spherical particles 589 including 594 are provided, and the periphery of the spherical particles 589 is filled with resin or the like. Filled with wood 595 (see Figure 23).
0254In FIG. 23, an electrode layer containing a translucent conductive polymer is used as the first electrode layer. First electricity An inorganic insulating film is provided on the polar layer 587, and the inorganic insulating film is formed from the first electrode layer 587. It functions as a barrier membrane that prevents the diffusion of impurities.
0255It is also possible to use an electrophoretic element instead of the twist ball. Clear liquid 10 μm to 20 in diameter, which encloses positively charged white fine particles and negatively charged black fine particles. Use microcapsules of about 0 μm. Provided between the first electrode layer and the second electrode layer The microcapsules are white when an electric field is applied by the first electrode layer and the second electrode layer. The fine particles and the black fine particles move in opposite directions, and white or black can be displayed. this A display element that applies the principle is an electrophoretic display element, which is generally called electronic paper. To. Electrophoretic display elements have higher reflectance than liquid crystal display elements, so no auxiliary light is required. In addition, the power consumption is low, and the display unit can be recognized even in a dim place. Also , Even when power is not supplied to the display unit, it is possible to retain the image once displayed. Therefore, it is equipped with a semiconductor device with a display function (simply a display device or a display device) from the radio wave transmission source. Keep the displayed image even when the semiconductor device is moved away. Is possible.
0256Through the above steps, highly reliable electronic paper can be produced as a semiconductor device. ..
0257This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate. Is.
0258(Embodiment 10) In the present embodiment, an example of a light emitting display device is shown as a semiconductor device according to one aspect of the present invention. Display equipment As the display element of the device, a light emitting element that utilizes electroluminescence is used here. Shown using. Light emitting elements that utilize electroluminescence are made of organic compounds. It is distinguished by whether it is an inorganic compound or not. Generally, the former is an organic EL device and the latter is an organic EL device. It is called an inorganic EL element.
0259An organic EL element is an electron and a hole from a pair of electrodes by applying a voltage to the light emitting element. Is injected into each layer containing a luminescent organic compound, and an electric current flows. And those ca The recombination of the rear (electrons and holes) causes the luminescent organic compound to form an excited state. Then, it emits light when its excited state returns to the ground state . From such a mechanism, like this A light emitting element is called a current excitation type light emitting element.
0260The inorganic EL element is divided into a dispersed inorganic EL element and a thin film type inorganic EL element depending on the element configuration. It is similar. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels. Ccepter recombination type luminescence. In the thin film type inorganic EL element, the light emitting layer is sandwiched between the dielectric layers, and the light emitting layer is sandwiched between the dielectric layers. Furthermore, it has a structure in which it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. Localized light emission to be used. Here, an organic EL element will be used as the light emitting element. To.
026119 (A) and 19 (B) show an active mat as an example of a semiconductor device to which one aspect of the present invention is applied. A lix-type light emitting display device is shown. FIG. 19 (A) is a plan view of the light emission display device, and FIG. 19 (A) shows. B) is a cross-sectional view of line YZ in FIG. 19 (A). In addition, in FIG. 20, the departure shown in FIG. 19 The equivalent circuit of the optical display device is shown.
0262The thin film transistors 301 and 302 used in the semiconductor device include the first embodiment and the actual thin film transistors 301 and 302. It can be manufactured in the same manner as the thin film transistor shown in Form 2, and the IGZO semiconductor layer and metal oxide can be formed. It is a highly reliable thin film transistor including a buffer layer having an n-type conductive type. Well Further, the thin film transistor shown in the third to fifth embodiments is also the thin film transistor of the present embodiment. It can also be applied as 301 and 302.
0263The light emitting display device of the present embodiment shown in FIGS. 19 (A) and 20 is a thin film having a multi-gate structure. Transistor 301, thin film transistor 302, capacitive element 304, source wiring layer 305, Includes gate wiring layer 306 and light emitting element 303. Thin film transistors 301 and 302 are ncha It is a flannel type thin film transistor.
0264Further, in FIG. 19B, the light emitting display device of the present embodiment is a thin film transistor 302. Used for the insulating layer 311, the insulating layer 312, the insulating layer 313, the partition wall 321 and the light emitting element 303. It has a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323.
0265The insulating layer 313 is an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferable to form using.
0266In the present embodiment, since the pixel thin film transistor 302 is n-type, it is the pixel electrode layer. It is desirable to use a cathode as the electrode layer 320 of 1. Specifically, as a cathode, work Materials with small functions such as Ca, Al, CaF, MgAg, AlLi, etc. can be used. it can.
0267The partition wall 321 is formed by using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Special A photosensitive material is used to form an opening on the first electrode layer 320, and the side walls of the opening are continuous. It is preferable to form the inclined surface so as to have a continuous curvature.
0268The electroluminescent layer 322 is configured such that a plurality of layers are laminated even if the electroluminescent layer 322 is composed of a single layer. It doesn't matter if it is.
0269A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. Second electricity The polar layer 323 uses the translucent conductive material listed as the pixel electrode layer in the eighth embodiment. It can be formed of a translucent conductive film that has been used. In addition to the above translucent conductive film, titanium nitride film May use a titanium film. First electrode layer 320, electroluminescent layer 322 and second electrode layer 32 The light emitting element 303 is formed by overlapping with 3. After this, the light emitting element 303 Second electrode layer 323 and partition wall 32 to prevent oxygen, hydrogen, water, carbon dioxide, etc. from entering 1 A protective film may be formed on the film. As the protective film, a silicon nitride film, a silicon oxide film, and a DLC A film or the like can be formed.
0270Furthermore, in reality, when completed up to Fig. 19 (B), it is airtight so that it will not be further exposed to the outside air. Protective film (bonded film, UV curable resin film, etc.) ) Or a cover material is preferable.
0271Next, the configuration of the light emitting element will be described with reference to FIG. Here, the driving TFT is n The cross-sectional structure of the pixel will be described by taking the case of a mold as an example. Figure 21 (A) (B) (C) The driving TFTs 7001, 7011 and 7021 used in the semiconductor device are in the first embodiment. A buff that can be manufactured in the same manner as the thin film transistor shown and contains an IGZO semiconductor layer and a metal oxide. It is a highly reliable thin film transistor having a layer. In addition, Embodiment 2 to Embodiment Apply the thin film transistor shown in 5 as driving TFT 7001, 7011, 7021 You can also do it.
0272The light emitting element may have at least one of the anode and the cathode transparent in order to extract light emission. So Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top surface injection that ejects, bottom surface injection that extracts light emission from the surface on the substrate side, and the opposite of the substrate side and the substrate There is a light emitting element having a double-sided injection structure that extracts light from the side surface, and the pixel configuration of one aspect of the present invention is It can be applied to a light emitting device having any injection structure.
0273A light emitting element having a top injection structure will be described with reference to FIG. 21 (A).
0274In Fig. 21 (A), the driving TFT7001 is n-type, and the light emitted from the light emitting element 7002 is emitted. The cross-sectional view of the pixel is shown when it comes out to the anode 7005 side. In FIG. 21 (A), the light emitting element 70 The cathode 7003 of 02 and the driving TFT 7001 are electrically connected, and on the cathode 7003. The light emitting layer 7004 and the anode 7005 are laminated in this order. Cathode 7003 has a small work function In addition, various materials can be used as long as it is a conductive film that reflects light. For example, C a, Al, CaF, MgAg, AlLi and the like are desirable. And the light emitting layer 7004 is singular It may be composed of layers or may be configured so that a plurality of layers are laminated. When composed of multiple layers, an electron injection layer, an electron transport layer, a light emitting layer, and an e The fuel transport layer and the hole injection layer are laminated in this order. It is not necessary to provide all of these layers. Yang The pole 7005 is formed using a light-transmitting conductive material, such as an oxide tongue. Indium oxide containing stainless steel, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tongue, indium tin oxide containing titanium oxide, indium tin oxide Indium with added substance (hereinafter referred to as ITO), indium zinc oxide, and silicon oxide. A conductive conductive film having translucency such as tin oxide may be used.
0275The region sandwiching the light emitting layer 7004 between the cathode 7003 and the anode 7005 is the light emitting element 7002. Equivalent to. In the case of the pixel shown in FIG. 21 (A), the light emitted from the light emitting element 7002 is an arrow. Inject to the anode 7005 side as indicated by the mark.
0276Next, a light emitting element having a bottom injection structure will be described with reference to FIG. 21 (B). Drive TFT7 When 011 is n-type and the light emitted from the light emitting element 7012 is emitted to the cathode 7013 side. , The cross-sectional view of the pixel is shown. In Figure 21 (B), it is electrically connected to the driving TFT7011. The cathode 7013 of the light emitting element 7012 is formed on the translucent conductive film 7017. , The light emitting layer 7014 and the anode 7015 are laminated in this order on the cathode 7013. Anode 7 If 015 is translucent, it reflects or shields light so that it covers the anode 7015. A shielding film 7016 may be formed. Cathode 7013 is the same as in Fig. 21 (A). As described above, various materials can be used as long as they are conductive materials having a small work function. However The film thickness of is set to the extent that light is transmitted (preferably about 5 nm to 30 nm). For example 20 An aluminum film having a film thickness of nm can be used as the cathode 7013. And Similar to FIG. 21 (A), the light emitting layer 7014 is composed of a single layer, but a plurality of layers are stacked. It may be configured to be layered. Anode 7015 does not need to transmit light However, as in FIG. 21 (A), it can be formed by using a conductive material having translucency. .. As the shielding film 7016, for example, a metal that reflects light can be used, but the metal film is used. Not limited to. For example, a resin to which a black pigment is added can also be used.
0277The region of the cathode 7013 and the anode 7015 that sandwiches the light emitting layer 7014 is the light emitting element 7012. Corresponds to. In the case of the pixel shown in FIG. 21 (B), the light emitted from the light emitting element 7012 is Eject to the cathode 7013 side as indicated by the arrow.
0278Next, a light emitting element having a double-sided injection structure will be described with reference to FIG. 21 (C). Figure 21 (C) Now, on the translucent conductive film 7027, which is electrically connected to the driving TFT 7021, The cathode 7023 of the light emitting element 7022 is formed on the cathode 7023, and the light emitting layer 7024, Anodes 7025 are stacked in order. Cathode 7023 is the same as in FIG. 21 (A). Various materials can be used as long as they are conductive materials having a small function. However, the film thickness is , To the extent that light is transmitted. For example, Al having a film thickness of 20 nm is used as the cathode 7023. Can be used. The light emitting layer 7024 is composed of a single layer as in FIG. 21 (A). It may be configured so that a plurality of layers are laminated. Anode 70 25 is formed by using a translucent conductive material that transmits light, as in FIG. 21 (A). Can be
0279The part where the cathode 7023, the light emitting layer 7024, and the anode 7025 overlap is the light emitting element 70. Corresponds to 22. In the case of the pixel shown in FIG. 21 (C), the light emitted from the light emitting element 7022. Is ejected to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.
0280Although the organic EL element has been described here as the light emitting element, the inorganic E as the light emitting element has been described. It is also possible to provide an L element.
0281In this embodiment, the thin film transistor (driving TFT) that controls the driving of the light emitting element is used. An example in which the light emitting element is electrically connected is shown, but a current is generated between the driving TFT and the light emitting element. The configuration may be such that a control TFT is connected.
0282The semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 21. Various modifications based on the technical idea of the present invention are possible.
0283Through the above steps, a highly reliable light emitting display device can be manufactured as a semiconductor device. ..
0284This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate. Is.
0285(Embodiment 11) Next, the configuration of the display panel, which is a form of the semiconductor device of the present invention, is shown below. Real In the form of application, a liquid crystal display device is a form of a liquid crystal display device having a liquid crystal element as a display element. A form of semiconductor device that has a flannel (also called a liquid crystal panel) and a light emitting element as a display element. A light emitting display panel (also referred to as a light emitting panel) will be described.
0286Next, regarding the appearance and cross section of the light emitting display panel corresponding to one form of the semiconductor device of the present invention. This will be described with reference to FIG. FIG. 22 (A) shows the IGZO semiconductor layer formed on the first substrate. And highly reliable thin film transistors and light emitting devices with a buffer layer containing metal oxides. , It is a top view of the panel sealed with a sealing material between the second substrate and FIG. 22 (B). Corresponds to the cross-sectional view of HI in FIG. 22 (A).
0287Pixel section 4502, signal line drive circuit 4503a, 450 provided on the first board 4501 Sealing material 4505 so as to surround 3b and scanning line drive circuits 4504a and 4504b. Is provided. In addition, the pixel section 4502, the signal line drive circuits 4503a, 4503b, and A second substrate 4506 is provided on the scanning line drive circuits 4504a and 4504b. Yo Pixel section 4502, signal line drive circuits 4503a, 4503b, and scanning line drive circuit 45 04a and 4504b are the first substrate 4501 and the sealing material 4505 and the second substrate 4506. Is sealed with filler 4507.
0288In addition, the pixel unit 4502, the signal line drive circuit 4503a, 4 provided on the first substrate 4501. The 503b and the scanning line drive circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 22 (B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4510 are shown. The thin film transistor 4509 included in the line drive circuit 4503a is illustrated.
0289Thin film transistors 4509 and 4510 are buffs containing an IGZO semiconductor layer and metal oxides. It corresponds to a thin film transistor having a layer, and is a thin film transistor shown in the first to fifth embodiments. An engineer can be applied. In this embodiment, the thin film transistor 4509, The 4510 is an n-channel thin film transistor.
0290Further, 4511 corresponds to a light emitting element, and is a first electrode which is a pixel electrode of the light emitting element 4511. Layer 4517 is electrically connected to the source or drain electrode layer of the thin film transistor 4510. It is connected to the. The configuration of the light emitting element 4511 is limited to the configuration shown in the present embodiment. I can't. The structure of the light emitting element 4511 according to the direction of the light extracted from the light emitting element 4511. The growth can be changed as appropriate.
0291In addition, signal line drive circuits 4503a, 4503b, scanning line drive circuits 4504a, 4504b , Or various signals and potentials given to the pixel unit 4502 are FPC4518a, 4518. Supplied from b.
0292In the present embodiment, the illustration provided on the insulating film covering the thin film transistors 4509 and 4510 is shown. Not through the contact hole pixel section 4502, signal line drive circuit 4503a, 4503 b, or the wiring 4516 that connects to the scanning line drive circuits 4504a and 4504b, is the source. It is formed using the same material as the electrode layer or drain electrode layer. Also, of the first substrate 4501 Connect terminal 4515 on end wiring 4516, using the same material as the first electrode layer 4517. Form.
0293The connection terminal 4515 is provided via the terminal of the FPC 4518a and the anisotropic conductive film 4519. It is electrically connected.
0294The second substrate 4506 located in the direction of extracting light from the light emitting element 4511 must be translucent. Must be. In that case, glass plate, plastic plate, polyester film or Use a translucent material such as an acrylic film.
0295In addition to the inert gas such as nitrogen and argon, the filler 4507 is a UV-cured tree. Fat or thermosetting resin can be used, PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, the filler 4507 Nitrogen was used as.
0296If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is provided on the ejection surface of the light emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. I. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, due to surface irregularities Anti-glare treatment that can diffuse the reflected light and reduce reflection can be applied.
0297The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b , Drive times formed by a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate It may be implemented on the road. Also, only the signal line drive circuit, or part of it, or the scanning line drive times. Only the road or only a part of the road may be formed and mounted separately, and the present embodiment has the configuration shown in FIG. Not limited.
0298Next, regarding the appearance and cross section of the liquid crystal display panel corresponding to one form of the semiconductor device of the present invention. This will be described with reference to FIGS. 17 (A1) and 17 (A2). FIGS. 17 (A1) and 17 (A2) show the first substrate 40. Reliable with an IGZO semiconductor layer formed on 01 and a buffer layer containing metal oxides High thin film transistors 4010, 4011, and liquid crystal element 4013, second substrate 400 It is a top view of the panel sealed with the sealing material 4005 between 6 and 17, FIG. 17 (B) is. , Corresponds to the cross-sectional view in MN of FIGS. 17 (A1) and 17 (A2).
0299Surrounding the pixel unit 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. In this way, the sealing material 4005 is provided. In addition, the pixel section 4002 and the scanning line drive times A second substrate 4006 is provided on the road 4004. Therefore, the pixel section 4002 and scanning The line drive circuit 4004 is the first board 4001, the sealing material 4005, and the second board 4006. It is sealed together with the liquid crystal 4008. Also, the sealing material on the first substrate 4001 Single crystal half on a separately prepared substrate in a region different from the region surrounded by 4005 A signal line drive circuit 4003 formed of a conductor film or a polycrystalline semiconductor film is mounted.
0300The method of connecting the separately formed drive circuit is not particularly limited, and the COG method, A wire bonding method, a TAB method, or the like can be used. Figure 17 (A1) Is an example of mounting the signal line drive circuit 4003 by the COG method, and Fig. 17 (A2) shows. This is an example of mounting the signal line drive circuit 4003 by the TAB method.
0301Further, the pixel unit 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 It has a plurality of thin film transistors, and in FIG. 17 (B), the thin film included in the pixel portion 4002. Transistor 4010 and thin film transistor 4011 included in scan line drive circuit 4004 Is illustrated.
0302The thin film transistors 4010 and 4011 are buffs containing an IGZO semiconductor layer and a metal oxide. It corresponds to a thin film transistor having a layer, and is a thin film transistor shown in the first to fifth embodiments. An engineer can be applied. In this embodiment, the thin film transistor 4010, 4011 is an n-channel thin film transistor.
0303Further, the pixel electrode layer 4030 included in the liquid crystal element 4013 is formed by the thin film transistor 4010 and the electric wire. It is connected airily. The counter electrode layer 4031 of the liquid crystal element 4013 is the second substrate 40. It is formed on 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal 4008 The overlapping portion corresponds to the liquid crystal element 4013. In addition, pixel electrode layer 4030, counter-electricity The polar layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films, respectively. The liquid crystal 4008 is sandwiched between the edge layers 4032 and 4033.
0304The first substrate 4001 and the second substrate 4006 include glass and metal (typically, glass). Tenless), ceramics, and plastic can be used. As plastic , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Rum can be used. Also, aluminum foil is made of PVC film or polyester. A sheet having a structure sandwiched between films can also be used.
0305The 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 It is provided in. A spherical spacer may be used.
0306Further, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or a pixel unit 4 Various signals and potentials given to 002 are supplied from FPC4018.
0307In the present embodiment, the connection terminal 4015 is the pixel electrode layer 4030 included in the liquid crystal element 4013. Formed from the same conductive film as the wiring 4016, the thin film transistor 4010, 4011 It is formed of the same conductive film as the electrode layer.
0308The connection terminal 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. It is connected airily.
0309Further, in FIG. 17, a signal line drive circuit 4003 is separately formed and actually mounted on the first substrate 4001. Although an example of disguising is shown, the present embodiment is not limited to this configuration. Scan line drive circuit May be separately formed and mounted, or a part of the signal line drive circuit or a part of the scanning line drive circuit. You may form and mount it separately.
0310FIG. 18 shows a semiconductor device using a TFT substrate 2600 manufactured by applying one aspect of the present invention. An example of configuring a liquid crystal display module is shown as.
0311FIG. 18 shows an example of a liquid crystal display module, in which the TFT substrate 2600 and the facing substrate 2601 are displayed. It is fixed by the material 2602, and includes the pixel part 2603 including the TFT, etc., and the liquid crystal layer between them. A display element 2604 and a colored layer 2605 are provided to form a display area. Colored layer 2605 Is required for color display, and in the case of RGB method, it corresponds to each color of red, green, and blue. Colored layers are provided corresponding to each pixel. TFT board 2600 and facing board 2601 A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged on the outside. Light source is cold It is composed of a cathode ray tube 2610 and a reflector 2611, and the circuit board 2612 has a flexible arrangement. It is connected to the wiring circuit section 2608 of the TFT board 2600 by the wire board 2609, and is controlled. External circuits such as a power circuit and a power supply circuit are incorporated. Also, the position between the polarizing plate and the liquid crystal layer It may be laminated with the phase difference plate.
0312The liquid crystal display module has TN (Twisted Nematic) mode and IPS (I). n-Plane-Switching) mode, FFS (Fringe Field S) witching) mode, MVA (Multi-domain Vertical A) lignment mode, PVA (Patterned Vertical Alig) nment) mode, ASM (Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui) d Crystal) mode, AFLC (Anti Ferroelectric Liq) uid Crystal) mode etc. can be used.
0313Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.
0314This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate. Is.
0315(Embodiment 12) The semiconductor device according to one aspect of the present invention can be applied to various electronic devices (including gaming machines). Can be done. Electronic devices include, for example, television devices (televisions or televisions). (Also called a receiver), monitors for computers, electronic paper, digital cameras, digital cameras, etc. Digital video camera, digital photo frame, mobile phone (mobile phone, mobile phone device and Large games such as portable game machines, personal digital assistants, audio playback devices, pachinko machines, etc. Machines and the like can be mentioned. In particular, as shown in Embodiments 8 to 11, one of the present inventions. Suitable for liquid crystal display devices, light emitting devices, electrophoresis display devices, etc. By using it, it can be used as a display unit of an electronic device. Specific examples are given below.
0316The semiconductor device of one aspect of the present invention can be applied to electronic paper as shown in the ninth embodiment. Can be done. Electronic paper is used for electronic devices in all fields as long as it displays information. It is possible to be. For example, using electronic paper, electronic books (electronic books), POS For in-car advertisements of vehicles such as trains and trains, display on various cards such as credit cards, etc. Can be applied. Examples of electronic devices are shown in FIGS. 24 and 25.
0317Figure 24 (A) shows the poster 1601 made of electronic paper. Advertising medium is paper In the case of printed matter, advertisements are exchanged manually, but a semi-introduction of one aspect of the present invention. If you use electronic paper to which the body device is applied, you can change the display of advertisements in a short time. Well In addition, because a thin film transistor with good electrical characteristics is used, the display is stable without being corrupted. An image is obtained. The poster may be configured so that information can be transmitted and received wirelessly.
0318In addition, FIG. 24 (B) shows an in-vehicle advertisement 1602 for a vehicle such as a train. Advertising medium In the case of printed matter on paper, the exchange of advertisements is performed manually, but half of one aspect of the present invention. If you use electronic paper to which a conductor device is applied, you can display advertisements in a short time without much labor. You can change the indication. In addition, because a thin film transistor with good electrical characteristics is used, the table A stable image can be obtained without breaking the display. In-house advertisements can send and receive information wirelessly. It may be configured as such.
0319In addition, FIG. 25 shows an example of the electronic book 2700. For example, the ebook 2700 It consists of two housings, a housing 2701 and a housing 2703. Housing 2701 and housing The body 2703 is connected by a shaft portion 2711, and opens and closes with the shaft portion 2711 as an axis. It can be performed. With such a configuration, it is possible to operate like a paper book. Become.
0320The display unit 2705 is incorporated in the housing 2701, and the display unit 2707 is assembled in the housing 2703. It is included. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. It may be configured to display different screens. Configure to display different screens So, for example, the text is displayed on the display unit on the right side (display unit 2705 in Fig. 25), and the display unit on the left side. An image can be displayed on (display unit 2707 in FIG. 25).
0321Further, FIG. 25 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, housing 2 The 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. .. The page can be sent by the operation key 2723. The key is on the same surface as the display of the housing. It may be configured to include a board, a pointing device, or the like. Also, on the back of the housing External connection terminals (earphone terminal, USB terminal, or AC adapter and USB) on the side A configuration that includes a terminal that can be connected to various cables such as cables), a recording medium insertion unit, etc. May be. Furthermore, the electronic book 2700 has a structure that has a function as an electronic dictionary. You may.
0322Further, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By radio Purchase desired book data, etc. from the e-book server and download it. Is also possible.
0323FIG. 26 (A) shows an example of the television device 9600. Television device 96 For 00, the display unit 9603 is incorporated in the housing 9601. Displayed by 9603 It is possible to display an image. Also, here, the stand 9605 makes the housing 9601 Shows the configuration that supports. The display unit 9603 is shown in the eighth to eleventh embodiments. Display devices can be applied.
0324The operation of the television device 9600 is performed by the operation switch provided in the housing 9601 and the separate remote control. It can be done by the controller 9610. Operation keys provided in the remote control device 9610 With the 9609, you can control the channel and volume, and it will be displayed on the display 9603. You can operate the video. In addition, the remote controller 9610 is equipped with the remote controller 9610. A display unit 9607 that displays information output from the 9610 may be provided.
0325The television device 9600 is configured to include a receiver, a modem, and the like. To the receiver It can receive more general TV broadcasts, and can be wired or wireless via a modem. One-way (sender to recipient) or two-way by connecting to a communication network It is also possible to perform information communication (between the sender and the receiver, or between the recipients, etc.).
0326FIG. 26B shows an example of the digital photo frame 9700. For example, Digita In the photo frame 9700, the display unit 9703 is incorporated in the housing 9701. display Part 9703 can display various images, for example, taken with a digital camera or the like. By displaying the image data, it can be made to function in the same way as a normal photo frame.
0327The digital photo frame 9700 has an operation unit and an external connection terminal (USB terminal, US). (Terminals that can be connected to various cables such as B cable), recording medium insertion part, etc. Succeed. These configurations may be incorporated on the same surface as the display unit, but on the side surface or the back surface. It is preferable to provide it because the design is improved. For example, a recording medium for digital photo frames Insert the memory that stores the image data taken by the digital camera into the body insertion part and insert the image data. Data can be captured and the captured image data can be displayed on the display unit 9703.
0328Further, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. .. It is also possible to adopt a configuration in which desired image data is captured and displayed wirelessly.
0329FIG. 27 shows an example of the digital player 2100, which is a portable audio device. To. The digital player 2100 has a main body 2130, a display unit 2131, and a memory unit 2132. , Operation unit 2133, earphone 2134, control unit 2137, etc. are included. In addition, earphone Headphones or wireless earphones can be used instead of 2134. Display 2131 Can apply the display device shown in the eighth to eleventh embodiments.
0330In addition, by operating the operation unit 2133 using the memory unit 2132, video and audio (video and audio ( Music) can be recorded and played back. The display unit 2131 has white characters on a black background. Power consumption can be suppressed by displaying. The memory provided in the memory unit 2132 is , It may be a structure that can be taken out.
0331FIG. 28 shows an example of the mobile phone 1000. The mobile phone 1000 has a housing 100 In addition to the display 1002 built into 1, the operation buttons 1003, external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc. The display unit 1002 is the embodiment 8 ~ The display device shown in the eleventh embodiment can be applied.
0332The mobile phone 1000 shown in FIG. 28 inputs information by touching the display unit 1002 with a finger or the like. Can force. To make a call or type an e-mail, point to the display 1002. It can be done by touching with.
0333The screen of the display unit 1002 mainly has three modes. The first is a table that mainly displays images. It is a display mode, and the second is an input mode mainly for inputting information such as characters. The third is the display It is a display + input mode in which two modes, mode and input mode, are mixed.
0334For example, when making a call or composing an email, enter characters on the display 1002. The main character input mode may be set, and the characters displayed on the screen may be input. in this case , It is preferable to display the keyboard or number button on most of the screen of the display unit 1002. Good.
0335In addition, a sensor that detects the inclination of the gyro, accelerometer, etc. is installed inside the mobile phone 1000. By providing the detection device to have, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined and the table can be determined. The screen display of the display unit 1002 can be automatically switched.
0336To switch the screen mode, touch the display unit 1002 or operate the housing 1001. It is done by operating button 1003. Also, for the type of image displayed on the display unit 1002 Therefore, it is possible to switch. For example, the image signal displayed on the display is a moving image. Switch to display mode for data and input mode for text data.
0337In addition, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected and displayed. If there is no input by touch operation of part 1002 for a certain period of time, the screen mode is input mode. It may be controlled to switch to the display mode from.
0338The display unit 1002 can also function as an image sensor. For example, display unit 10 By touching 02 with your palm or finger, you can authenticate yourself by capturing palm prints, fingerprints, etc. Wear. In addition, a backlight that emits near-infrared light or a sensor that emits near-infrared light is displayed on the display unit. It is also possible to image finger veins, palmar veins, etc. by using a light source for shooting.
0339This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate. Is.
034080 transport room 81 Transfer robot 82 cassette room 83 Gate valve 84 Gate valve 85 Gate valve 86 Gate valve 87 Gate valve 88 Gate valve 89 Processing room 90 processing room 91 Processing room 92 Processing room 93 Processing room 94 board 100 boards 101 Gate electrode 101a gate electrode 101b gate electrode 102 Gate insulating film 102a Gate insulating film 102b Gate insulating film 103 Semiconductor layer 104a buffer layer 104b buffer layer 104c buffer layer 105 Conductive 105a drain electrode 105a1 drain electrode 105a2 drain electrode 105b1 drain electrode 105b2 drain electrode 105c conductive layer 106 channel protection layer 114a buffer layer 114b buffer layer 133 Semiconductor film 134 Metal oxide film 200 substrate 201 thin film transistor 202 Source wiring layer 203 Gate wiring layer 204 Capacitive wiring layer 211 Insulation layer 212 Insulation layer 213 Insulation layer 255 Electrode layer 260 liquid crystal display element 261 Insulation layer 262 liquid crystal layer 263 Insulation layer 264 Colored layer 265 Electrode layer 266 board 267 Polarizing plate 268 Polarizing plate 301 thin film transistor 302 thin film transistor 303 light emitting element 304 Capacitive element 305 Source wiring layer 306 Gate wiring layer 311 Insulation layer 312 Insulation layer 313 Insulation layer 320 electrode layer 321 bulkhead 322 Electroluminescent layer 323 Electrode layer 581 Thin film transistor 585 Insulation layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b white area 594 cavity 595 Filler 1000 mobile phones 1001 Housing 1002 Display 1003 Operation buttons 1004 External connection port 1005 speaker 1006 microphone 1601 poster 1602 In-car advertising 2100 digital player 2130 body 2131 Display 2132 Memory section 2133 Operation unit 2134 earphones 2137 Control unit 2600 TFT board 2601 Opposed board 2602 Sealing material 2603 Pixel part 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 Cold cathode tube 2611 reflector 2612 Circuit board 2613 Diffusion plate 2700 ebook 2701 chassis 2703 chassis 2705 Display 2707 Display 2711 Shaft 2721 power supply 2723 Operation keys 2725 speaker 4001 board 4002 Pixel part 4003 Signal line drive circuit 4004 Scan line drive circuit 4005 Sealing material 4006 board 4008 LCD 4010 thin film transistor 4011 thin film transistor 4013 Liquid crystal element 4015 Connection terminal 4016 Wiring 4018 FPC 4019 Anisotropic conductive film 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4501 board 4502 Pixel part 4503a Signal line drive circuit 4504a Scan line drive circuit 4505 Sealing material 4506 board 4507 Filler 4509 thin film transistor 4510 thin film transistor 4511 Light emitting element 4515 Connection terminal 4516 Wiring 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 5300 board 5301 Pixel part 5302 Scan line drive circuit 5303 Signal line drive circuit 5400 board 5401 Pixel part 5402 Scan line drive circuit 5403 Signal line drive circuit 5404 Scan line drive circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 wiring 5506 Wiring 5543 nodes 5544 nodes 5571 thin film transistor 5572 thin film transistor 5573 thin film transistor 5574 Thin film transistor 5575 thin film transistor 5576 Thin film transistor 5577 thin film transistor 5578 Thin film transistor 5601 Driver IC 5602 Switch group 5603a thin film transistor 5603b thin film transistor 5603c thin film transistor 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 flip flop 5703a Timing 5703b Timing 5703c Timing 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 wiring 5716 Wiring 5717 Wiring 5721 signal 5803a Timing 5803b Timing 5803c Timing 5821 signal 7001 TFT for driving 7002 Luminescent element 7003 Cathode 7004 Light emitting layer 7005 Anode 7011 TFT for driving 7012 Light emitting element 7013 Cathode 7014 Light emitting layer 7015 Anode 7016 Shielding film 7017 Conductive 7021 TFT for driving 7022 Luminescent element 7023 Cathode 7024 Light emitting layer 7025 anode 7027 Conductive 9600 television device 9601 housing 9603 Display 9605 stand 9607 Display 9609 Operation keys 9610 Remote control device 9700 digital photo frame 9701 chassis 9703 Display
28 sheets
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Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP2003037268A | Cites | Japan |
| JP2006165527A | Cites | Japan |
| JP2004207221A | Cites | Japan |
| JP2007298627A | Cites | Japan |
| JP2007123861A | Cites | Japan |
32 members in 3 offices
Members32
| Document | Office | Kind | |
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| US2010025677A1 | United States of America | A1 | |
| KR20100014167A | Republic of Korea | A | |
| JP2010056541A | Japan | A | |
| KR20120096879A | Republic of Korea | A | |
| KR101349624B1 | Republic of Korea | B1 | |
| JP2014222764A | Japan | A | |
| US8945981B2 | United States of America | B2 | |
| US2015091009A1 | United States of America | A1 | |
| JP5857093B2 | Japan | B2 | |
| KR101606014B1 | Republic of Korea | B1 | |
| KR20160036022A | Republic of Korea | A | |
| JP5917762B1 | Japan | B1 | |
| JP2016096347A | Japan | A | |
| JP2016096348A | Japan | A | |
| JP5938136B2This record | Japan | B2 | |
| JP2016165009A | Japan | A | |
| KR101785924B1 | Republic of Korea | B1 | |
| KR20170115997A | Republic of Korea | A | |
| JP6225216B2 | Japan | B2 | |
| JP2018019096A | Japan | A | |
| KR101842871B1 | Republic of Korea | B1 | |
| KR20180031662A | Republic of Korea | A | |
| KR101885062B1 | Republic of Korea | B1 | |
| KR20180089888A | Republic of Korea | A | |
| KR101939044B1 | Republic of Korea | B1 | |
| US10326025B2 | United States of America | B2 | |
| JP2020038970A | Japan | A | |
| JP2021170646A | Japan | A | |
| JP7065233B2 | Japan | B2 | |
| JP2022109274A | Japan | A | |
| JP2023052516A | Japan | A | |
| JP2024129053A | Japan | A |
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Numbers
- Publication
- 5938136
- Application
- 242845
Titles2
- Japanese
- 半導体装置
- English
- Semiconductor device
Classification
- CPC, 7
- H10D30/6755
- H10D86/60
- H10D86/423
- H10P14/22
- H10P14/6329
- H10D30/031
- H10D30/6704
- IPC, 17
- H01L29 786
- H01L21 336
- H01L21 8234
- H01L27 088
- H01L27 08
- H01L29 417
- G02F1 1368
- H01L51 50
- H10D30 67
- H05B44 00
- H10D30 01
- H10D64 23
- H10D64 27
- H10D64 62
- H10D64 66
- H10D84 00
- H10D84 03
