Command and interrupt grouping for a data storage device

0001(Cross-reference of related applications) This application is incorporated herein by reference in its entirety, as well as US Provisional Application No. 61 / 167,709, entitled "DATA STORAGE DEVICE," filed April 8, 2009. Claiming the interests of US Provisional Application No. 61 / 187,835 entitled "PARTITIONING AND STRIPING IN A FLASH MEMORY DATA STORAGE DEVICE" filed June 17, 2009. Is.

0002(Technical field) This description relates to a data storage device.

0003(background) Data storage devices can be used to store data. The data storage device can be used with the computing device to meet the data storage needs of the computing device. In some cases, it may be desirable to store large amounts of data on a data storage device. It may also be desirable to execute commands to quickly read and write data to and from the data storage device.

<p num="0004">(Summary) This document describes a data storage device that includes one or more memory boards, each memory board containing a plurality of flash memory chips. The data storage device includes a controller board to which the memory board is functionally connected. The data storage device may be configured to use an interface to communicate with the host, receive commands from the host, and process those commands using a flash memory chip. For example, a host can send commands and a controller board can receive commands to read, write, copy, and delete blocks of data using a flash memory chip.</p><p num="0005"> In one exemplary embodiment, the controller comprises a field-programmable gate array controller, and the interface between the host and the controller board is, for example, (PCIe) (Peripheral Component Interconnect Express). It may be a high speed interface such as an interface. As such, the data storage device can include high storage volumes and may be configured to achieve high performance and high speed data transfer between the host and the flash memory chip.</p><p num="0006"> In one exemplary embodiment, the data storage device may consist of two memory boards, each containing a plurality of flash memory chips. A data storage device that includes a controller board and two memory boards may be configured in the form of disk drives so that the data storage device fits into the internal drive slot of the computing device. For example, the data storage device may be configured to fit into the server's internal drive slot to provide the server's data storage capacity. The data storage device can be easily removed from the computing device and may be configured to be removable so that it can be inserted into the internal drive slot of another computing device.</p><p num="0007"> Further, the data storage device is a modular system in which the memory board may be disconnected from the controller board and replaced with another memory board, and the other memory board can also include a plurality of flash memory chips. You may. The controller on the controller board may be configured to recognize that one or more memory boards have been disconnected and replaced by another memory board. The controller may be configured to recognize this type of swapout of memory boards and can handle commands between the host and other memory boards. In this way, the controller board can continue to be used even if one or more memory boards are no longer available. Unusable memory boards may be disconnected from the controller board or replaced by another memory board while continuing to use the same controller board and the same components on the controller board.</p><p num="0008"> In one exemplary embodiment, the data storage device may be configured to handle different types of flash memory chips. For example, the controller on the controller board may be configured to recognize and operate different types of flash memory chips on the memory board. For example, controllers can be of various types, including, for example, single-level cell (SLC) flash memory chips, multi-level cell (MLC) flash memory chips, NAND flash memory chips, NOR flash memory chips, and other types of flash memory chips. It may be an FPGA controller configured to recognize the flash memory chip of. The controller may be configured to recognize flash memory chips from various flash memory chip vendors. The controller is configured to recognize different types of flash memory chips and use the flash memory chips to execute commands from the host by translating commands based on the type of flash memory chips on the memory board. May be done. Therefore, the host does not need to translate commands or send different commands depending on the type of flash memory chip. The controller may be configured to translate commands from the host into native commands for certain types of flash memory chips.</p><p num="0009"> Thus, the same controller board with the same controller can be used with memory boards with different types of flash memory chips. For example, a first memory board and a second memory board may be connected to a controller board, and each board may include an SLC NAND flash memory chip manufactured by one vendor. The first memory board and the second memory board may be disconnected and replaced with two different memory boards, which are MLCs manufactured by different vendors. Includes NAND flash memory chip. The controller may be configured to automatically recognize the flash memory chips on the other memory boards and use the flash memory chips on the other memory boards to execute commands from the host. Thus, the data storage device varies on the memory board depending on the characteristics of one or more applications on the host and depending on the characteristics of the data storage device desired by the one or more applications on the host. The flash memory chip may be adjusted and configured.</p><p num="0010"> In other exemplary embodiments, each memory board may include a memory device other than a flash memory chip. For example, each memory board can contain multiple dynamic random access memory (DRAM) chips. Similar to the above description of flash memory chips, the data storage device may be configured to handle different types of DRAM chips. For example, the controller on the controller board may be configured to recognize and operate different types of DRAM chips on the memory board. One memory board of a DRAM chip can be removed from the data storage device and replaced with a memory board with a different type of DRAM chip. The controller can execute commands from the host using different types of DRAM chips by translating commands based on the type of DRAM chip on the memory board. In other exemplary embodiments, the memory board can include other types of memory devices, including, for example, phase change memory (PCM) chips and other types of memory devices.</p><p num="0011"> In another exemplary embodiment, the controller on the controller board recognizes and operates on one type of memory device on one memory board, yet at the same time on a different type of memory device on another memory board. It may be configured to work. For example, one of the memory boards can contain a flash memory chip and the other memory board can contain a DRAM chip.</p><p num="0012"> In one exemplary embodiment, the data storage device may be configured to handle flash memory chips with varying voltages. For example, the controller on the controller board may be configured to recognize and operate flash memory chips with different voltages on the memory board. For example, the controller can configure the power control circuit to sense the voltage of the flash memory chip and supply the required voltage. For example, the controller is configured to sense the voltage of the flash memory chip on the memory board and configure the power supply module on the controller board to supply the appropriate voltage to the flash memory chip based on the sensed voltage. It may be an FPGA controller configured in. The controller is configured to sense the voltage of the flash memory chip and use the flash memory chip to execute commands from the host without having to translate commands based on the voltage of the flash memory chip on the memory board. You may.</p><p num="0013"> Thus, the same controller board with the same controller can be used with memory boards with flash memory chips of different voltages. For example, a first memory board and a second memory board may be connected to a controller board, and each board may include a flash memory chip that operates at a first voltage. The first memory board and the second memory board may be disconnected and replaced with two separate memory boards, the other memory board containing a flash memory chip operating at a second voltage and a second. The voltage of is different from the first voltage. The controller automatically senses the second voltage of the flash memory chip on the other memory board, configures the power supply module to operate at the second voltage, and uses the flash memory chip on the other memory board. It may be configured to execute commands from the host. Thus, the data storage device is on the other memory board, depending on the characteristics of one or more applications on the host and depending on the characteristics of the data storage device desired by the one or more applications on the host. It may be tuned and configured with various flash memory chips.</p><p num="0014"> The use of a single controller board with a single controller on a board different from the flash memory chip on the memory board provides flexibility in configuring data storage devices. For example, a single controller with a single controller on the board configured to recognize and operate different types of flash memory chips and / or to recognize and operate flash memory chips with different voltages. The board allows data storage devices to be designed using a variety of flash memory chip technologies. Also, certain flash memory chip technologies may be selected and used on the memory board based on the type of application on the host that interfaces with the data storage device. Also, since flash memory chip technology can change, the same controller board and controller may be used with different flash memory chips on the memory board by swapping out the memory board. In this way, a controller board with a controller and other components can be considered as a universal controller board and controller that can be configured to accept multiple different types of flash memory chips on the memory board.</p><p num="0015"> According to one general aspect, the data storage device can include a first memory board and a second memory board, the first memory board and the second memory board each having a plurality of memory chips. To be equipped. The data storage device can include a first memory board and a controller board configured to be functionally connected to the second memory board, the controller board using a high speed interface and a high speed interface. The first memory board and the second memory board are each removable separately from the controller board, including a controller configured to receive commands from the host and execute commands. The data storage device may be implemented as a computer program product.</p><p num="0016"> Embodiments can include one or more of the following features: For example, the controller may be a field programmable gate array (FPGA) controller. The memory chip can include a flash memory chip. Flash memory chips can include single-level cell (SLC) NAND flash memory chips and / or multi-level cell (MLC) NAND flash memory chips. The high speed interface can include a PCI-e interface. In one exemplary embodiment, the flash memory chip can include a NAND flash memory chip, the high speed interface may be a PCI-e interface, and the controller may be a field programmable gate array (FPGA). ..</p><p num="0017"> The first memory board, the second memory board, and the controller board may be arranged and configured to fit the drive bays of the server. The first memory board may be functionally connected to the upper side of the controller board and the second memory board may be functionally connected to the lower side of the controller board.</p><p num="0018"> In one exemplary embodiment, the memory chip can include a dynamic random access memory (DRAM) chip. In another exemplary embodiment, the memory chip comprises a phase change memory (PCM) chip.</p><p num="0019"> The first memory board and the second memory board may be modular boards configured to be removed and arranged to be replaced by another memory board containing a plurality of memory chips. The controller can include a power supply module, which controls the command processing of multiple memory chips with different voltages, automatically recognizes the voltages of the first memory board and the memory chips on the second memory board, and the memory. The power supply module may be configured to operate at the recognized voltage of the chip, and may be arranged and configured to use the interface to receive commands from the host and use the memory chip to execute commands.</p><p num="0020"> The controller controls the command processing of several different types of memory chips, automatically recognizes the types of memory chips on the first and second memory boards, and uses the interface to issue commands from the host. It may be arranged and configured to receive and execute commands using memory chips.</p><p num="0021"> The controller can include multiple channels, each channel is associated with one or more memory chips, and each memory chip is associated with one of the channels. The controller can include a channel controller for each channel.</p><p num="0022"> In another general aspect, the computing device can include a host and a data storage device. The data storage device is a first memory board and a second memory board, and the first memory board and the second memory board are a memory board having a plurality of memory chips and a first memory board, respectively. And a controller board configured to be functionally connected to a second memory board. The controller board includes a high-speed interface and a controller configured to receive commands from the host and execute commands using the high-speed interface, and the first memory board and the second memory board are respectively. , Can be removed separately from the controller board. In some cases, the computing device may be implemented as a computer system or as part of a computer system. Embodiments can include one or more features described above and below.</p><p num="0023"> In another general aspect, a method for assembling a data storage device is to secure multiple memory chips to a first memory board and to secure multiple memory chips to a second memory board. Includes attaching a high-speed interface and controller to the controller board, functionally connecting the first memory board to the controller board, and functionally connecting the second memory board to the controller board. The first memory board and the second memory board can each be removed separately from the controller board.</p><p num="0024"> Embodiments can include one or more of the following features: For example, the method is to fix multiple memory chips to the third memory board, disconnect one of the first memory board or the second memory board from the controller board, and the third memory. It can further include connecting the board functionally to the controller board. Functionally connecting the first memory board to the controller board and functionally connecting the second memory board to the controller board are configured so that the drive bay form factor matches the drive bay of the server. As such, it can include forming a form factor for the drive bays of the first memory board, the second memory board, and the controller board. Functionally connecting the first memory board to the controller board can include functionally connecting the first memory board to the upper side of the controller board and functioning the second memory board to the controller board. Connecting a second memory board can include functionally connecting a second memory board to the underside of the controller board.</p><p num="0025"> In one embodiment, the memory chip can include a dynamic random access memory (DRAM) chip. In another embodiment, the memory chip can include a phase change memory (PCM) chip. In another embodiment, the memory chip can include a flash memory chip. The flash memory chip on the first memory board and the second memory can include a NAND flash memory chip, the high speed interface can include a PCI-e interface, and the controller is a field programmable gate array (FPGA). ) It may be a controller.</p><p num="0026"> Details of one or more embodiments are shown in the accompanying drawings and the following description. Other features will be apparent from the description and drawings, as well as the claims.</p>

0027<figref num="1">It is an exemplary block diagram showing a data storage device.</figref>

0028<figref num="2">It is an exemplary perspective block diagram which shows the printed circuit board of a data storage device.</figref>

0029<figref num="3">FIG. 5 is an exemplary block diagram showing an exemplary computing device for use with the data storage device of FIG.</figref>

0030<figref num="4">It is an exemplary block diagram showing a controller.</figref>

0031<figref num="5">FIG. 5 is an exemplary flow diagram showing an exemplary assembly of the data storage device of FIG.</figref>

0032<figref num="6">FIG. 5 is an exemplary block diagram illustrating an exemplary embodiment of the data storage device of FIG.</figref>

0033<figref num="7">It is an exemplary flow diagram which shows the exemplary operation of the data storage device of FIG.</figref>

0034<figref num="8">It is an exemplary flow diagram which shows the exemplary operation of the data storage device of FIG.</figref>

0035(Detailed explanation) This document describes devices, systems (one or more), and techniques for data storage. Such a data storage device can include a controller board having a controller that can be used with one or more different memory boards, each having a plurality of flash memory chips. The data storage device can communicate with the host using the interface on the controller board. Thus, the controller on the controller board may be configured to use the interface to receive commands from the host and use the flash memory chip on the memory board to execute those commands.

0036FIG. 1 is a block diagram showing a data storage device 100. The data storage device 100 can include a controller board 102 and one or more memory boards 104a and 104b. The data storage device 100 can communicate with the host 106 via interface 108. Interface 108 may be between host 106 and controller board 102. The controller board 102 can include a controller 110, DRAM 111, a plurality of channels 112, a power supply module 114, and a memory module 116. The memory boards 104a and 104b can include a plurality of flash memory chips 118a and 118b on each memory board. Memory boards 104a and 104b can also include memory devices 120a and 120b.

0037In general, the data storage device 100 may be configured to store data on the flash memory chips 118a and 118b. The host 106 can write and read data to and from the flash memory chips 118a and 118b, and may allow other operations to be performed on the flash memory chips 118a and 118b. Reading and writing data between the host 106 and the flash memory chips 118a and 118b, as well as other operations, may be processed and controlled through the controller 110 on the controller board 102. The controller 110 may receive commands from the host 106 and use the flash memory chips 118a and 118b on the memory boards 104a and 104b to execute those commands. Communication between host 106 and controller 110 may take place through interface 108. The controller 110 can use the channel 112 to communicate with the flash memory chips 118a and 118b.

0038The controller board 102 can include DRAM 111. The DRAM 111 may be functionally coupled to the controller 110 and may be used to store information. For example, DRAM 111 may be used to store a map from a logical address to a physical address and information on bad blocks. The DRAM 111 may also be configured to act as a buffer between the host 106 and the flash memory chips 118a and 118b.

0039In one exemplary embodiment, the controller board 102 and the respective memory boards 104a and 104b are physically separate printed circuit boards (PCBs). The memory board 104a may be on one PCB that is functionally connected to the PCB of the controller board 102. For example, the memory board 104a may be physically and / or electrically connected to the controller board 102. Similarly, the memory board 104b may be a PCB separated from the memory board 104a or may be functionally connected to the PCB of the controller board 102. For example, the memory board 104b may be physically and / or electrically connected to the controller board 102. The memory boards 104a and 104b may each be separately disconnected and removable from the controller board 102. For example, the memory board 104a may be disconnected from the controller board 102 and replaced with another memory board (not shown), which is functionally connected to the controller board 102. In this example, either or both of the memory boards 104a and 104b may be swapped out on the other memory board so that the other memory board can operate on the same controller board 102 and controller 110.

0040In one exemplary embodiment, the controller board 102 and the respective memory boards 104a and 104b may be physically connected by a disk drive form factor. The disk drive form factor can include various sizes, for example 3.5 "disk drive form factor and 2.5" disk drive form factor.

0041In one exemplary embodiment, the controller board 102 and the respective memory boards 104a and 104b may be electrically connected using a high density ball grid array (BGA) connector. For example, it includes a fine ball grid array (FBGA) connector, an ultra fine ball grid array (UBGA) connector, and a micro ball grid array (MBGA). Other variants of the BGA connector may be used. Other types of electrical connection means may be used.

0042In one exemplary embodiment, the controller board 102, which is its own PCB, may be physically located between its own separate PCBs, memory boards 104a and 104b, respectively. Further referring to FIG. 2, the data storage device 100 can include a memory board 104a on one PCB, a controller board 102 on a second PCB, and a memory board 104b on a third PCB. The memory board 104a includes a plurality of flash memory chips 118a, and the memory board 104b includes a plurality of flash memory chips 118b. The controller board 102 includes a controller 110, an interface 108 to a host (not shown), and other components (not shown).

0043In the example shown in FIG. 2, the memory board 104a may be functionally connected to the controller board 102 and located on one side 220a of the controller board 102. For example, the memory board 104a may be connected to the upper 220a of the controller board 102. The memory board 104b may be functionally connected to the controller board 102 and located on the second side 220b of the controller board 102. For example, the memory board 104b may be connected to the lower 220b of the controller board 102.

0044Other physical and / or electrical connection arrangements between the memory boards 104a and 104b and the controller board 102 are possible. Figure 2 shows just one exemplary sequence. For example, the data storage device 100 can include three or more memory boards, such as three memory boards, four memory boards, or more memory boards, all of which are single controller boards. Connected to. As such, the data storage device may be further configured with a disk drive form factor. Further, the memory board may be connected to the controller board in another arrangement, for example, the controller board is at the top and the memory card is at the bottom, or the controller board is at the bottom and the memory card is at the top.

0045The data storage device 100 may be arranged and configured to work with the computing device. In one exemplary embodiment, the controller boards 102 and memory boards 104a and 104b may be arranged and configured to fit within the drive bays of the computing device. With reference to FIG. 3, two exemplary computing devices are shown: server 330 and server 340. Servers 330 and 340 may be arranged and configured to provide a variety of different types of computing devices. Servers 330 and 340 can include a host (eg, host 106 in FIG. 1) that includes a computer program product that has instructions that cause one or more processors of servers 330 and 340 to provide computing services. The type of server depends on one or more application programs running on the server. For example, servers 330 and 340 can be application servers, web servers, email servers, search servers, streaming media servers, e-commerce servers, file transfer protocol (FTP) servers, other types of servers, or a combination of these servers. There may be. The server 330 may be configured to be a rack-mounted server operating in a server rack. The server 340 may be configured to be a stand-alone server that operates independently of the server rack. Even if the server 340 is not in the server rack, it may be configured to work with other servers or may be functionally connected to other servers. Servers 330 and 340 are shown to illustrate exemplary computing devices, and other computing devices may be used, including other types of servers.

0046In one exemplary embodiment, the data storage device 100 of FIGS. 1 and 2 fits within drive bay 335 of server 330 and drive bay 345 of server 340 to provide data storage capabilities for servers 330 and 340. It may be sized to do so. For example, the data storage device 100 may be sized to a 3.5 "disk drive form factor to fit drive bays 335 and 345. The data storage device 100 may also be configured in other sizes. The data storage device 100 can be functionally connected and communicated to servers 330 and 340 using interface 108. Thus, the host uses interface 108 to propagate commands to controller board 102. The controller 110 can execute commands using the flash memory chips 118a and 118b on the memory boards 104a and 104b.

0047Referencing back to FIG. 1, interface 108 can include a high speed interface between controller 110 and host 106. The high-speed interface can enable high-speed transfer of data between the host 106 and the flash memory chips 118a and 118b. In one exemplary embodiment, the high speed interface can include a PCIe interface. For example, the PCIe interface may be a PCIe x4 interface or a PCIe x8 interface. PCIe interface 108 can include a PCIe connector cable assembly to host 106. Other high speed interfaces, connectors and connector assemblies may be used.

0048In one exemplary embodiment, communication between the controller board 102 and the flash memory chips 118a and 118b on the memory boards 104a and 104b may be configured to be located on a plurality of channels 112. Each channel 112 can communicate with one or more flash memory chips 118a and 118b. The controller 110 may be configured such that commands received from the host 106 can be executed by the controller 110 simultaneously, or at least substantially simultaneously, using each channel 112. In this way, a plurality of commands can be executed simultaneously on different channels 112, and the throughput of the data storage device 100 can be improved.

0049In the example of FIG. 1, 20 channels 112 are shown. The full solid line shows the 10 channels between the controller 110 and the flash memory chip 118a on the memory board 104a. The mixed solid and dashed lines indicate the 10 channels between the controller 110 and the flash memory chip 118b on the memory board 104b. As shown in FIG. 1, each channel 112 can support multiple flash memory chips. For example, each channel 112 can support up to 32 flash memory chips. In one exemplary embodiment, each of the 20 channels may be configured to support and communicate with 6 flash memory chips. In this example, each of the memory boards 104a and 104b can contain 60 flash memory chips, respectively. Depending on the type and number of flash memory chips 118a and 118b, the data storage 100 device may be configured to store up to a large number of terabytes of data.

0050Controller 110 can include microcontrollers, FPGA controllers, other types of controllers, or combinations thereof. In one exemplary embodiment, the controller 110 is a microcontroller. The microcontroller may be implemented in hardware, software, or a combination of hardware and software. For example, when a microcontroller is executed, a computer program product containing instructions that can be executed by the microcontroller in a particular way may be loaded from memory (eg, memory module 116). The microcontroller may be configured to receive and execute commands from host 106 using interface 108. For example, commands can include commands that read, write, copy, and delete blocks of data using flash memory chips 118a and 118b, as well as other commands.

0051In another exemplary embodiment, the controller 110 is an FPGA controller. The FPGA controller may be implemented in hardware, software, or a combination of hardware and software. For example, an FPGA controller may, when executed, be loaded with firmware from memory (eg, memory module 116) that contains instructions that can cause the FPGA controller to execute in a particular way. The FPGA controller may be configured to receive and execute commands from host 106 using interface 108. For example, commands can include commands that read, write, copy, and delete blocks of data using flash memory chips 118a and 118b, as well as other commands.

0052In one exemplary embodiment, the FPGA controller can support multiple interfaces 108 with the host 106. For example, the FPGA controller may be configured to support multiple PCIe x4 or PCIe x8 interfaces with host 106.

0053The memory module 116 may be configured to store data that can be loaded into the controller 110. For example, memory module 116 may be configured to store one or more images of the FPGA controller, which contains the firmware used by the FPGA controller. The memory module 116 can interface with the host 106 to communicate with the host 106. The memory module 116 can interface directly with the host 106 and / or indirectly with the host 106 through the controller 110. For example, host 106 may propagate one or more images of firmware to memory module 116 for storage. In one exemplary embodiment, memory module 116 includes electrically erasable programmable read-only memory (EEPROM). The memory module 116 can also include other types of memory modules.

0054The power supply module 114 may be configured to receive power (Vin), perform any conversion of the received power, and output output power (Vout). The power supply module 114 can receive power (Vin) from the host 106 or from another power source. The power supply module 114 can provide power (Vout) to the controller board 102 and the components on the controller board 102 including the controller 110. The power supply module 114 can also provide power (Vout) to the memory boards 104a and 104b and the components on the memory boards 104a and 104b including the flash memory chips 118a and 118b.

0055In one exemplary embodiment, the power supply module 114 can include one or more DC (direct current) -DC converters. The DC-DC converter may be configured to receive input power (Vin) and convert the power to one or more different power levels (Vout). For example, the power supply module 114 receives + 12V (Vin), converts the power to 3.3V, 1.2V, or 1.8V and supplies the output power (Vout) to the controller board 102 and the memory boards 104a and 104b. It may be configured as follows.

0056The memory boards 104a and 104b may be configured to handle different types of flash memory chips 118a and 118b. In one exemplary embodiment, the flash memory chips 118a and the flash memory chips 118b are of the same type of flash memory, including requiring the same voltage from the power supply module 114 and being of the same flash memory chip vendor. It may be a chip. The terms vendor and manufacturer are used synonymously throughout this document.

0057In one exemplary embodiment, the flash memory chip 118a on the memory board 104a may be of a different type than the flash memory chip 118b on the memory board 104b. For example, the memory board 104a can include an SLC NAND flash memory chip and the memory board 104b can include an MLC NAND flash memory chip. In another example, the memory board 104a may include a rush memory chip from one flash memory chip manufacturer, and the memory board 104b may include a flash memory chip from another flash memory chip manufacturer. Due to the flexibility of having all the same type of flash memory chips or different types of flash memory chips, the data storage device 100 can be tuned for the various applications used in host 106. it can.

0058In another exemplary embodiment, the memory boards 104a and 104b can include different types of flash memory chips on the same memory board. For example, the memory board 104a can contain both SLC NAND chips and MLC NAND chips on the same PCB. Similarly, the memory board 104b can include both SLC NAND chips and MLC NAND chips. In this way, the data storage device 100 may be advantageously tuned to meet the specifications of host 106.

0059In another exemplary embodiment, the memory boards 104a and 104b may include other types of memory devices, including chips other than flash memory. For example, memory boards 104a and 104b can also include random access memory (RAM), such as dynamic RAM (DRAM) and static RAM (SRAM), as well as other types of RAM and other types of memory devices. In one exemplary embodiment, both memory boards 104a and 104 can include RAM. In another exemplary embodiment, one of the memory boards can include RAM and the other memory board can include a flash memory chip. Also, one of the memory boards can include both RAM and a flash memory chip.

0060The memory modules 120a and 120b on the memory boards 104a and 104b may be used to store information related to the flash memory chips 118a and 118b, respectively. In one exemplary embodiment, the memory modules 120a and 120b can store the device characteristics of the flash memory chip. The device characteristics are whether the chip is an SLC chip or MLC, whether the chip is a NAND or NOR chip, the number of chip select, the number of blocks, the number of pages per block, the number of bytes per page. , And the speed of the chip can be included.

0061In one exemplary embodiment, memory modules 120a and 120b can include serial EEPROM. EEPROM can store device characteristics. The device characteristics may be compiled once for any given type of flash memory chip, and the appropriate EEPROM image may be generated with the device characteristics. When the memory boards 104a and 104b are functionally connected to the controller board 102, the device characteristics are EEPROM so that the controller 110 can automatically recognize the type of flash memory chips 118a and 118b controlled by the controller 110. May be read from. In addition, device characteristics may be used to configure the controller 110 to the appropriate parameters of one or more specific types of flash memory chips 118a and 118b.

0062As described above, the controller 110 can include an FPGA controller. Referring to FIG. 4, an exemplary block diagram showing the FPGA controller 410 is shown. The FPGA controller may be configured to operate as described above for controller 110 in FIG. The FPGA controller 410 can include a plurality of channel controllers 450 for connecting the plurality of channels 112 to the flash memory chip 418. The flash memory chip 418 is represented as a plurality of flash memory chips connected to each channel controller 450. The flash memory chip 418 is representative of the flash memory chips 118a and 118b of FIG. 1, which are located on the separate memory boards 104a and 104b of FIG. A separate memory board is not shown in the example in Figure 4. The FPGA controller 410 can include a PCIe interface module 408, a bidirectional direct memory access (DMA) controller 452, a dynamic random access memory (DRAM) controller 454, a command processor / queue 456, and an information and configuration interface module 458.

0063Information may be communicated to and from a host (eg, host 106 in FIG. 1) using an interface. In this example of FIG. 4, the FPGA controller 410 includes a PCIe interface to communicate with the host and the PCIe interface module 408. The PCIe interface module 408 may be arranged and configured to receive commands from the host and send commands to the host. The PCIe interface module 408 can provide data flow control between the host and the data storage device. The PCIe interface module 408 can enable high-speed transfer of data between the host and the controller 410, and ultimately the flash memory chip 418. In one exemplary embodiment, the PCIe interface and PCIe interface module 408 can include a 64-bit bus.

0064Bidirectional DMA controller 452 may be configured to interface with PCIe interface 408, command processor / queue 456, and each channel controller 450. The bidirectional DMA controller 452 enables bidirectional direct memory access between the host and the flash memory chip 418.

0065The DRAM controller 454 may be arranged and configured to control the translation from a logical address to a physical address. For example, the DRAM controller 454 is the actual physical address in the flash memory chip 418 that the command processor / queue 456 is associated with the data being written or read to and from the logical address used by the host and the flash memory chip 418. It can assist the operation of translating the address. The logical address received from the host may be translated into the physical address at one location on the flash memory chip 418. Similarly, the physical address at one location of the flash memory chip 418 may be translated into a logical address and propagated to the host.

0066The command processor / queue 456 may be arranged and configured to receive commands from the host through the PCIe interface module 408 and control command execution through the channel controller 450. The command processor / queue 456 can hold a queue of multiple commands to be executed. Thus, multiple commands may be executed simultaneously and each channel 112 may be used simultaneously, or at least substantially simultaneously.

0067The command processor / queue 456 may be configured to process commands on different channels 112 out of order and maintain command ordering by channel. For example, commands received from a host and assigned to different channels may be processed in random order by the command processor / queue 456. Thus, the channel may be busy. Commands received from the host to be processed on the same channel may be processed in the order in which the commands were received from the host by the command processor / queue 456. In one exemplary embodiment, the command processor / queue 456 is configured to maintain a list of commands received from the host in chronological order to ensure that the commands are executed in a timely manner. May be good.

0068The channel controller 450 may be arranged and configured to process commands from the command processor / queue 456. Each channel controller 450 may be configured to handle commands from multiple flash memory chips 418. In one exemplary embodiment, each channel controller 450 may be configured to handle commands for up to 32 flash memory chips 418.

0069Channel controller 450 may be configured to process commands from command processor / queue 456 in the order specified by command processor / queue 456. Examples of commands that can be processed are flash page read, flash page programming, flash page copy, flash block erase, flash block metadata read, flash memory chip bad block mapping, flash memory chip reset. However, but is not limited to these.

0070Information and Configuration The interface module 458 may be arranged and configured to interface with a memory module (eg, memory module 116 in FIG. 1) to receive configuration information for the FPGA controller 410. For example, the information and configuration interface module 458 may receive one or more images from the memory module to provide firmware to the FPGA controller 410. Changes to the image and firmware may be provided by the host to controller 410 through the information and configuration interface module 458. Information and Configuration Changes received through interface module 458 are on any of the components of controller 410, including, for example, PCIe interface module 408, bidirectional DMA controller 452, DRAM controller 454, command processor / queue 456, and channel controller 450. May be applied. The information and configuration interface module 458 may include one or more registers, which may be modified as needed by instructions from the host.

0071The FPGA controller 410 may be arranged and configured to work with the host to process commands. FPGA controller 410 is capable of performing error correction, bad block management, logic-to-physics mapping, garbage collection, wear leveling, partitioning, and low-level formatting associated with flash memory chip 418, or at least. The operation can be assisted.

0072See Figure 5 to show the process 500 for assembling a data storage device. Process 500 can include fixing a plurality of flash memory chips to a first memory board (510) and fixing a plurality of flash memory chips to a second memory board (520). For example, further referring to FIG. 1, the plurality of flash memory chips 118a may be fixed to the memory board 104a, and the plurality of flash memory chips 118b may be fixed to the memory board 104b. The memory boards 104a and 104b may be printed circuit boards (PCBs) to which the flash memory chips 118a and 118b are mounted, respectively. The storage capacity of each memory board 104a and 104b may vary individually and collectively depending on the type and number of flash memory chips 118a and 118b fixed to the memory boards 104a and 104b. The flash memory chips 118a and 118b may be arranged in one or more channels so that a single channel can control command processing of a plurality of flash memory chips as described above.

0073The flash memory chips 118a and 118b may be of the same type of flash memory chip, or the flash memory chip on the memory board 104a may be different from the flash memory chip on the memory board 104b. Also, the memory boards 104a and 104b can include a different number of flash memory chips on each memory board. For example, memory board 104a can contain 60 flash memory chips, memory board 104b can contain 80 flash memory chips, but flash memory chips on memory board 104a are on memory board 104b. It may be the same type or a different type of flash memory chip as the flash memory chip.

0074Process 500 functionally attaches the high-speed interface and controller to the controller board (530), functionally connects the first memory board to the controller (540), and the second memory board to the controller board. It can include connecting and the first memory board and the second memory board can each be detached separately from the controller board (550). For example, interface 108 may be a high speed interface or may be mounted on controller board 102 (530). The controller 110 may be attached to the controller board 102. The controller board 102 may be a PCB to which a high speed interface and controller are mounted.

0075The memory board 104a may be functionally connected to the controller board 102 (540), and the memory board 104b may be functionally connected to the controller board (550). The memory board 104a is a different memory board separate from the memory board 104b, and the memory boards 104a and 104b may be separately removable from the controller board 102, respectively. The assembled controller board 102 and the two memory boards 104a and 104b can together form the data storage device 100.

0076In one exemplary embodiment, the memory boards 104a and 104b may be disconnected from the controller board 102 or replaced by two other memory boards with flash memory chips attached to the other memory boards. Good. Other flash memory boards may include the same type of flash memory chips as the flash memory chips 118a and 118b on the memory boards 104a and 104b, or other flash memory boards may contain different types of flash memory chips. Can be done. Other flash memory boards can also include a different number of flash memory chips than the memory boards 104a and 104b.

0077In one exemplary embodiment, the assembled data storage device 100, including memory boards 104a and 104b connected to the controller board 102, is configured to fit within the drive bay of the computing device. Factors can be formed. For example, referring to FIGS. 2 and 3, the data storage device 100 of FIG. 2 fits within a drive bay slot of a computing device, for example, drive bay slot 335 of server 330 or drive bay slot 345 of server 340. It may be configured to do so.

0078With reference to FIG. 6, an exemplary embodiment of the data storage device 100 of FIG. 1 is shown as the data storage device 600. The data storage device 600 can include a controller board 102 including a PCIe interface 608 with a host 106, an FPGA controller 610, a DRAM 611, a DC-DC converter 614, and an EEPROM 616. The data storage device can also include memory boards 104a and 104b with flash memory chips 618a and 618b, respectively. In one embodiment, the flash memory chips 618a and 618b are NAND flash memory chips. As shown in FIG. 1, the FPGA controller 610 can control the flash memory chips 618a and 618b using a plurality of channels 112, and the plurality of channels 112 control one or more flash memory chips 618a and 618b, respectively. can do.

0079Returning to FIG. 1, the controller 110 (including, for example, the FPGA controller 410 in FIG. 4 and the FPGA controller 610 in FIG. 6) controls the command processing of several different types of flash memory chips 118a and 118b. , Arranged and configured to automatically recognize the types of flash memory chips 118a and 118b on the flash memory boards 104a and 104b and execute commands received using different types of flash memory chips 118a and 118b. May be good. Controller 110 may be configured to process commands from different types of flash memory chips by translating the commands into commands from native flash memory chips. The host does not need to take into account the native flash memory chip commands, as the controller takes on the host's commands and translates the host's commands into native flash memory chip commands as needed. For example, a read command received from a host can be processed by the controller 110 without the host having to translate the read command into another command so that it can operate on a flash memory chip made by a particular vendor.

0080Referring to FIG. 7, process 700 shows that controller 110 may be configured to automatically recognize and operate different types of flash memory chips. Process 700 involves receiving power at the controller board, which includes interfaces to the host and controller (710). The controller may be configured to control the command processing of several different types of flash memory chips (710). For example, the controller board 102 can receive power (Vin) at the power supply module 114. In one exemplary embodiment, the power supply module 114 can include one or more DC-DC converters (eg, DC-DC converter 614 in FIG. 6). The controller board 102 can include an interface 108 and a controller 110. The controller 110 may be configured to control command processing for a plurality of different types of flash memory chips 118a and 118b.

0081Process 700 can include querying the first memory board for one or more characteristics of multiple flash memory chips fixed to the first memory board (720). In one exemplary embodiment, the controller 110 may be configured to query the memory module 120a for the device characteristics of the flash memory chip 118a fixed to the memory board 104a (720). Device characteristics include, for example, whether the chip is an SLC chip or an MLC chip, whether the chip is a NAND or NOR chip, the number of chip select, the number of blocks, the number of pages per block, the number of pages per page It can include the number of bytes and the speed of the chip. The memory module 120a can include a serial EEPROM (eg EEPROM 620a in FIG. 6).

0082In another exemplary embodiment, the controller 110 may be configured to query the flash memory chip 118a directly. For example, controller 110 may be configured to query the device ID page of each flash memory chip 118a to determine device characteristics.

0083Process 700 can include automatically recognizing the type of flash memory chip on the first memory board based on one or more characteristics of the flash memory chip (730). For example, the controller 110 can use the device characteristics to automatically recognize the type of flash memory chip 118a on the memory board 104a. The flash memory chip 118a may be an SLC or MLC device. The flash memory chip 118a may be a NAND chip, a NOR chip, or any other type of chip. The flash memory chip 118a may also be from one of several different flash memory manufacturers.

0084Process 700 can include receiving commands from the host using the interface (740) and executing commands using the flash memory chip (750). For example, controller 110 may be configured to use interface 108 to receive commands from host 106 and use flash memory chip 118a to execute commands. In this way, the controller 110 may be configured to operate automatically on any type of flash memory chip. When the data storage device 100 is powered on, the controller can determine what type of flash memory chips are on the memory boards and then operate on those memory boards to execute the commands received from the host. Can be started.

0085In one exemplary embodiment, the controller 110 can receive one or more configuration updates based on the type of flash memory chip determined to be present on the memory board. For example, controller 110 may determine that one of the memory boards is using a particular type of flash memory chip, and this information may be returned to the host for reporting. Host 106 can propagate one or more configuration updates to controller 110, which can receive and process those updates in the information and configuration interface module 458 of FIG.

0086In one exemplary embodiment, the controller 110 may be configured to automatically recognize different types of flash memory chips on the same memory board. For example, half of the flash memory chips 118a on the memory board 104a may be SLC NAND flash memory chips, and the other half of the flash memory chips 118s on the memory board 104a may be MLC NAND flash memory chips. .. Controller 110 may be configured to execute commands for both of those types of flash memory chips, even on the same memory board.

0087In another exemplary embodiment, the controller 110 recognizes when two memory boards are removed from the controller board 102 and replaced with new memory boards with or without different types of flash memory chips. It may be configured. In this way, the controller 110 can provide a high degree of flexibility in adjusting the data storage device 100 to meet the specific application needs of the host 106. Certain types of flash memory chips, including different types of chips on the same memory board and / or different types of chips on each memory board, meet the desired characteristics required for the particular application of host 106. May be used for.

0088Referring to FIG. 8, the exemplary process 800 shows that the controller is configured to operate on flash memory chips with different voltages. Process 800 can include receiving power at the controller board, the controller board including an interface and a controller, and the controller including a power supply module. The controller is configured to control command processing for multiple flash memory chips with different voltages (810). For example, the controller board 102 may be configured to receive power (Vin) from host 106, and the controller board may include interfaces 108 and controller 110 regardless of whether the controller can include a power supply module 114. Can be included. Controller 110 may be configured to control command processing for multiple flash memory chips with different voltages (810). For example, the controller 110 may be configured to control a flash memory chip operating at 1.2V, 1.8V, 3.3V, or other voltage.

0089Process 800 involves determining the voltage of the flash memory chip on the first memory board (810). For example, the controller 110 may be configured to sense the voltage of a flash memory chip based on the signal level of a pin on the connector between the controller board 102 and the memory board 104a. The signal level (eg, logic high and / or logic low grouping) can indicate the voltage required for the flash memory chip 118a. Process 800 involves configuring the power supply module to operate at the determined voltage of the flash memory chip (830). For example, the controller 110 may be configured to configure the power supply module 114 based on the voltage sensed at the pins on the connector between the controller board 102 and the memory board 104a. In one exemplary embodiment, the power supply module 114 comprises one or more DC-DC converters (eg, DC-DC converter 614 in FIG. 6). The power supply module 114 may be configured to operate at the sensed voltage.

0090Process 800 can include receiving commands from the host using the interface (840) and executing commands using the flash memory chip (850). For example, controller 110 may be configured to use interface 108 to receive commands from host 106 and use flash memory chip 118a to execute commands. Thus, the memory boards 104a and 104b can include chips with the same voltage, and the memory boards 104a and 104b are connected to the controller board 102. The memory boards 104a and 104b may be disconnected from the controller board 102 and replaced with other memory boards having flash memory chips of different voltages. The controller 110 is configured to automatically recognize the different voltages required for the flash memory chips on the other memory boards and configure the power supply module 114 to operate at different voltage levels.

0091Embodiments of the various techniques described herein may be implemented in digital electronic circuits or in computer hardware, firmware, software, or a combination thereof. An embodiment is an information carrier, such as a machine-readable storage device, for executing as a computer program product, i.e., for example by a data processing device such as a programmable processor, computer, or multiple computers, or for controlling its operation. It may be implemented as a computer program that is substantially embodied in. A computer program, such as the computer program (one or more) described above, may be written in any form of programming language, including compiled or interpreted languages, as a stand-alone program, or as a module. , Components, subroutines, or other units suitable for use in a computing environment. Computer programs may be arranged to run on one computer at one site, or on multiple computers distributed across multiple sites and interconnected by communication networks.

0092Method Steps may be performed by one or more programmable processors running a computer program to perform a function by manipulating input data to produce output. Method steps may also be performed by special purpose logic circuits such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits), and the devices may be performed as special purpose logic circuits.

0093Suitable processors for running computer programs include, for example, general purpose and special purpose microprocessors, and one or more processors of any kind of digital computer. Generally, the processor receives instructions and data from read-only memory and / or random access memory. A computer element can include at least one processor for executing instructions and one or more memory devices for storing instructions and data. In general, a computer can also include one or more mass storage devices for storing data, such as magnetic, magneto-optical disks, or optical disks, or receive data to and from a mass storage device. Alternatively, they may be functionally combined to perform transfer or both. Suitable information carriers for embodying computer program instructions and data are, for example, semiconductor memory devices such as EPROMs, EEPROMs, and flash memory devices; magnetic disks such as internal hard disks or removable disks; magneto-optical disks. Includes all forms of non-volatile memory, including CD-ROMs and DVD-ROM disks. The processor and memory may be complemented by special purpose logic circuits or may be incorporated into special purpose logic circuits.

0094To prepare for user interaction, embodiments include display devices for displaying information to the user, such as a brown tube (CRT) or liquid crystal display (LCD) monitor, as well as a keyboard and, for example, a mouse or trackball. It may be carried out on a computer having a pointing device capable of inputting to the computer by the user. Other types of devices may also be used to interact with the user; for example, the feedback provided to the user is perceptual in any form, such as visual feedback, auditory feedback, or tactile feedback. It may be feedback; the input from the user may be received in any form, including acoustic, spoken, or tactile input.

0095The embodiment includes a backend component, such as a data server, or a middleware component, such as an application server, or has a graphical user interface or web browser that allows the user to interact with the embodiment, for example. It may be implemented in a computing system that includes front-end components such as client computers, or any combination of such back-ends, middleware, or front-end components. The components may be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include local area networks (LANs) and wide area networks (WANs) such as the Internet.

0096Although the particular features of the described embodiments have been set forth herein, a number of modifications, alternatives, modifications, and equivalences will be devised by those skilled in the art. Therefore, it should be understood that the appended claims are intended to treat all such modifications and modifications as being within the scope of the embodiment.