Method and apparatus for calibrating write timing in a memory system

0001The present embodiment mainly relates to a method of calibrating the timing of a signal required to execute a write operation of a computer system memory.

0002<figref num="1">It is a figure which shows one Embodiment of a computer system.</figref><figref num="2">It is a figure which shows one Embodiment of a phase detector.</figref><figref num="3">It is a flowchart which shows one Embodiment of the memory timing calibration process.</figref><figref num="4">It is a flowchart which shows one Embodiment of the write-read-verification process which calibrates the memory timing.</figref><figref num="5">It is a flowchart which shows an example of the process of calibrating the read data alignment setting.</figref><figref num="6">It is a flowchart which shows another example of the process of calibrating the read data alignment setting.</figref><figref num="7">It is a flowchart which shows another example of the memory timing calibration process.</figref><figref num="8">It is a graph which shows the success area and the failure area.</figref><figref num="9">It is a figure which shows one Embodiment of the modified phase detection circuit.</figref><figref num="10">It is a timing diagram which shows an example of the calibration process.</figref><figref num="11">It is a figure which shows the modification form of the calibration phase detection circuit, and is the related timing diagram.</figref><figref num="12">It is a flowchart which shows an example of the writing timing calibration process.</figref><figref num="13">It is a block diagram which shows one Embodiment of a system.</figref>

0003The following description is made to enable those skilled in the art to create and use embodiments of the present disclosure, and is made in the context of specific uses and their requirements. Various modifications to the embodiments of the present disclosure will be obvious to those skilled in the art. In addition, the general principles defined herein are applicable to other embodiments and uses without departing from the spirit and scope of the specification. Accordingly, the present specification is not limited to the illustrated embodiments and is given the broadest scope consistent with the principles and features disclosed herein.

0004An embodiment of an apparatus for calibrating the timing relationship between a plurality of signals involved in executing a write operation will be described. One of these embodiments is a memory controller coupled to a set of memory chips. Each of these memory chips includes a phase detector, which is configured to allow calibration of the phase relationship between the data strobe signal and the clock signal received from the memory controller in the memory chip. ing. In addition, the memory controller is configured to perform one or more write-read-verify operations to calibrate the clock cycle relationship between the data strobe signal and the clock signal. -In the verification operation, the delay of the data strobe signal with respect to the clock signal is changed in clock cycle units.

0005In some embodiments, the set of memory chips is coupled to the memory controller via a fly-by topology and the clock signal is multi-dropped through a "fly bypass" from the memory controller to the set of memory chips. It is routed and the data and data strobe signals are routed from the memory controller to a set of memory chips by direct connection. Note that the "fly-by delay separation" due to the delay difference between the clock signal on the flybypass and the data strobe signal on the direct path may exceed one clock period. In some embodiments, the memory chips are calibrated in order of increasing delay along the fly bypass.

0006In some embodiments, the memory controller asserts variously delayed pulses on the data strobe signal to the data strobe signal when calibrating the phase relationship between the data strobe signal and the clock signal. It is configured to look for transitions in the output of the phase detector that indicate that the strobe and clock signals are aligned.

0007In some embodiments, the memory controller has a step of changing the delay of the data strobe signal with respect to the clock signal in clock cycle units and a step of writing a value to a specific location in the memory chip when calibrating the clock cycle relationship. Data strobe signals and clocks by verifying that the step of reading a value from a particular location in that memory chip and whether the value read from that particular location matches the value written to that particular location. It is configured to continuously perform steps to determine if a signal is calibrated.

0008In some embodiments, the device is configured to sequentially calibrate all memory chips in a set of memory chips.

0009In some embodiments, the calibration is performed at maximum memory rate with a robust data pattern.

0010In some embodiments, the memory controller is further configured to adjust the timing relationship between the data strobe signal and the data strobe enable signal during the read operation.

0011In some embodiments, another system is provided that calibrates the timing relationship between a plurality of signals involved in performing a write operation of the memory system. The system receives multiple signals on a memory chip in a set of memory chips when in calibration mode. These signals are a clock signal from a memory controller, a marking signal, a data strobe signal, and the like, and the marking signal includes a pulse that marks a specific clock cycle in the clock signal. Next, the system calibrates the timing relationship between the data strobe signal and the clock signal by using the marking signal to window a specific clock cycle in the clock signal to generate a windowed clock signal. make it easier. Next, the system captures the window clock signal using the data strobe signal in the phase detector on the memory chip. Finally, the system returns the captured window clock signal to the memory controller so that the memory controller can calibrate the timing relationship.

0012In some embodiments, the marking signal is transmitted from the memory controller to the memory through a selected signal line on the fly bypass. The selected signal line carries another signal if the memory system is not in calibration mode.

0013In some embodiments, the selected signal line carries a write enable signal if the memory system is not in calibration mode.

0014In some embodiments, when capturing a window clock signal using a data strobe signal, it is necessary to capture the window clock signal into a flip-flop using the data strobe signal as a clock.

0015Some embodiments disclose semiconductor memory devices that facilitate the calibration of timing relationships between a plurality of signals required to perform a write operation. The memory device includes a clock input that receives a clock signal. Further, the memory device includes a first input that receives a marking signal from the memory controller. The marking signal includes a pulse marking a specific clock cycle in the clock signal. The memory device further includes a second input that receives a data strobe signal from the memory controller and a phase detector. The phase detector uses the marking signal to window a specific clock cycle in the clock signal, and further uses the data strobe signal to capture the windowed clock cycle. The memory device includes an output that feeds the captured window clock cycle as a feedback signal to the memory controller.

0016In some embodiments, the memory controller is coupled with a memory chip that receives the clock signal and includes a calibration mode that calibrates the clock cycle relationship between the data strobe signal and the clock signal. The step of changing the delay of the data strobe signal with respect to the signal in clock cycle units, the step of writing the first value to a specific location in the memory chip, and the step of reading the second value from the specific location in the memory chip. A step and a step to determine if the data strobe signal and the clock signal are calibrated by verifying that the value read from that particular location matches the value written to that particular location. , By repeating.

0017In some embodiments, the system generates a window clock signal by passing a marking signal through a cascaded flip-flop whose overall delay corresponds to a DRAM write delay, with the rising edge of the clock signal as the clock. .. The output of this cascade connection is captured at the falling edge of the clock to create a phase detector enable signal. Next, the system generates a window clock signal by ANDing the phase detector enable signal and the clock signal.

0018Computer system Memory systems start operating at very high data rates (eg, above 1000 megatransfers / second (MT / s)), so flyby to achieve the required level of signaling performance. It is possible to use a memory topology. For example, see Computer System 100 shown in Figure 1. The computer system 100 includes a processing device 104, which communicates with a dual inline memory module (DIMM) 106 via a memory control device 102. The computer system has a fly-by layout topology in which control signals, including one or more request (RQ) and clock (CK) signals, are synchronously dynamic from memory controller 102. Random access memory (SDRAM or DRAM) Routed to chips 110-117. In this embodiment, DIMM The control signal and clock signal in 106 are coupled to each of the DRAM chips 110 to 117 by a multi-drop method using fly bypass 108. The request signal can include an address signal and is propagated by a plurality of signal lines (in one embodiment, the pattern lengths are equal to each other) and a clock signal line. The request signal and the clock signal propagate through the fly bypass 108 and are sequentially received in each of the DRAM chips 110 to 117. At the same time, the data strobe (DQS) and data (DQ) signals are routed directly to each of the DRAM chips 110-117 in the DIMM 106, so there is no delay due to fly bypass.

0019In one embodiment, the data strobe (DQS) and data (DQ) signals are routed point-to-point for each DRAM chip between the dedicated DQ interface port of memory controller 102 and the DQ interface. .. In systems that support multiple ranks, a direct connection is a data strobe (DQS) signal between the dedicated DQ interface port on memory controller 102 and the connection point for each DQ interface on the corresponding DRAM chip within each rank. And may require routing data (DQ) signals. A "rank" is a set of DRAM chips that contributes to a memory transfer performed in response to a memory access command given to a set of rank DRAM chips. In systems that support multiple DIMM modules (each with a single rank or dual rank), the direct connection is to each dedicated DQ interface port on the memory controller and each DQ interface on the corresponding DRAM chip within each DIMM module. It may be necessary to route data strobe (DQS) and data (DQ) signals to and from the connection point of (note that the "DRAM chip" is referred to as "DRAM" throughout this specification. In some cases).

0020In one embodiment, the data strobe signal (DQS) can be routed along with the data signal (DQ) and used to receive data at the receiver of an integrated circuit (ie, a memory controller or DRAM). .. For example, if the memory controller is sending data to the DRAM during the write operation, the memory controller will send the DQS signal along with the data, and the DQS signal will be used to receive the data in the DRAM. Be done. During the read operation, if the DRAM is transmitting data to the memory control unit, the DRAM transmits a DQS signal together with the data to be transmitted to the memory control unit. The DQS signal is used to strobe the data transmitted with the DQS signal after being received by the memory controller. The DQS signal may be transmitted by a single bidirectional signal line for both read and write operations, or separate unidirectional signal lines may be provided for each of the read and write operations.

0021In one embodiment characterized by a memory system configured with a flyby layout topology, the RQ / CK propagation delay increases with respect to each of the DRAMs receiving the RQ and CK signals from the flyby signal path. Therefore, the skew between the received RQ / CK signal and the DQ / DQS signal increases for each continuous DRAM. To compensate for this effect during a write transaction, the memory controller 102 introduces a DQ / DQS transmission delay that increases with respect to the timing at which RQ / CK is transmitted to each of the successive DRAMs. Similarly, during a read transaction, memory controller 102 introduces an increasing DQS read enable receive sample delay for each of the contiguous DRAMs. These write delays and read delays introduced by the memory controller 102 are referred to as "write leveling" delays and "read leveling" delays, respectively.

0022Also, during a read transaction, the optimal read data alignment settings for each of the successive DRAMs that receive the RQ and CK signals from the fly-by signal path increase, which is required for the DRAM at the end of the fly-by signal path. The read data alignment setting may be maximized. Once this maximum read data alignment setting is determined, it can be used to align the read data received in each of the DQ blocks of the memory controller 102 by calculating the settings for all DQ / DQS groups. It is possible.

0023In one embodiment, it is possible to incorporate a circuit that facilitates timing adjustment into a DRAM chip designed according to the DDR3 standard (JESD79-3 promulgated by the JEDEC Solid State Technology Association). For example, FIG. 2 shows a phase detection circuit inside the DRAM chip 200, which facilitates phase adjustment between the clock signal on the fly bypass and the data strobe signal on the direct path. In this phase detection circuit, the operational amplifier 209 converts the differential clock signal consisting of the CK signal 201 and the CK # signal 202 into the non-differential clock signal 212. Similarly, the operational amplifier 210 converts a differential strobe signal consisting of DQS signal 203 and DQS # signal 204 into a non-differential data strobe signal 214. Next, the non-differential clock signal 212 is taken into the flip-flop 206 with the non-differential data strobe signal 214 as a clock. The output of the flip-flop 206 goes through the feedback path 211, the multiplexing 207, the driver 208, and the data line DQ. Feeded to 205. The multiplexing device 207 selectively feeds the output of the flip-flop 206 to the data line DQ 205 based on the value of the leveling mode signal 213. This allows the memory controller 102 to determine if the clock signal 212 and the data strobe signal 214 are in phase, which causes the memory controller 102 (FIG. 1) to reach the clock signal 212. On the other hand, by asserting variously delayed pulses on the data strobe signal 214 and looking for the transition appearing on the data line DQ 205 at the output of the phase detector, between the data strobe signal 214 and the clock signal 212. It becomes possible to calibrate the phase relationship of.

0024In the embodiment described above with reference to FIG. 2, a situation may occur in which the result of timing adjustment by the phase detection circuit described above is incorrect because the write / read data integrity has not been verified in the adjustment process. In particular, when the flyby delay separation between the clock signal and the data strobe signal exceeds one clock period, the phase relationship is properly adjusted in the above-mentioned timing adjustment process, but this timing adjustment shifts in clock period units. there is a possibility.

0025In order to take such a situation into consideration, an embodiment for verifying the data integrity of write / read in the timing adjustment process is shown below. By performing such verification, those embodiments adjust the timing by writing and reading a robust data pattern in the target DRAM and simultaneously transmitting the data pattern to other DRAMs in the topology. In the process, it becomes possible to clarify the practical effect of switching noise.

0026DRAM calibration process FIG. 3 is a flowchart showing an embodiment of the memory timing calibration process. In the present embodiment, the following matters are premised on this calibration process. (1) It is assumed that the timing relationship between the request (RQ) signal and the clock (CK) signal is set to compensate for the estimated average skew between RQ and CK. (2) The timing relationship between the data signal (DQ) and the data strobe signal (DQS) for each DQ / DQS group is set to compensate for the estimated average skew between DQ and DQS. And. (3) In addition, DRAM shall be processed continuously in the order in which the RQ / CK delay increases. (4) Furthermore, the skew between any two DQ / DQS groups shall be significantly smaller than the 1CK cycle.

0027With reference to FIG. 3, the process begins with performing a read calibration (read leveling) process (operation 302), where operation 302 is coupled to the fly-by RQ and direct DQ topologies shown in Figure 1. A register or other storage device in each DRAM (of the DRAM set) supplies a predefined data pattern to the memory controller. The DRAM located closest to the memory controller on the fly-by RQ bus (and therefore has the least RQ / CK flight time delay) is located farthest from the memory controller on the fly-by RQ bus (and therefore RQ /). Sends a predefined data pattern before DRAM (which has the largest CK flight time delay). The memory controller can then determine the receive timing offset for each received DQ block in the memory controller, which may, for example, read the read data strobe enable delay of each received DQ block. This is possible by adjusting it so that it is exactly aligned with the data strobe. The arrival time of the received read data strobe depends on the propagation delay of the read command received in the corresponding DRAM.

0028If the system fails the calibration process in operation 302, the system signals an error (operation 304). If successful, the system performs a write calibration (write leveling) process (operation 306) (note that this write calibration process is in each DRAM, as shown in FIG. 2 in one embodiment. It is possible to use a phase detection circuit). In one embodiment, the write calibration process comprises supplying a DQS strobe signal, where each DRAM (of the set of DRAMs coupled to the fly-by RQ and direct DQ topologies shown in FIG. 1) delivers this DQS strobe signal. The clock signal CK is sampled using this, and the result is returned directly to the memory controller via DQ line. In the write calibration process, the memory controller then propagates the corresponding write commands that are continuously received in each DRAM, for example, by determining the transmit timing offset for each transmit DQ block in the memory controller. It is possible to level the write data skew due to the delay.

0029After the write calibration process (operation 306), the clock and data strobe signals should be in phase, but the timing of these signals may further be off by clock period. To solve this problem, in one embodiment, the system performs extended write-read-verify write calibration optimization (Operation 308) (this process will be detailed later with reference to FIG. 4). To do). The system can also perform extended write-read-verify read calibration optimizations (Operation 310).

0030FIG. 4 is a flowchart showing an example of a write-read-verify process for calibrating the write timing. At the beginning of this process, the system sets the delay of the data strobe signal to the clock signal to the value obtained in the write calibration process (operation 420). This assumes that in the write calibration process, the DQS delay search started with the minimum delay setting. The system then writes the value to a specific location in the DRAM (operation 422) and then reads the value from the same location (operation 424). The system then determines if the value written to that memory location matches the value read from that memory location (operation 426). If they do not match, the system increases the delay by one clock cycle (operation 428) and returns to operation 422. On the other hand, if the values match, the write operation is successful, which indicates that the system has been calibrated and therefore the calibration process is complete.

0031Read data alignment calibration In one embodiment, the system also requires calibration to compensate for deviations in read data from multiple different DRAM devices. Read data from multiple contiguous DRAM devices configured in a system using a flyby topology arrives at the memory controller with a continuously increasing delay. In one embodiment, the read alignment process includes queuing read data into a contiguous DQ receiver block in the memory controller.

0032Read data from multiple different DRAM devices arrives at the memory controller with a continuously increasing delay, is received by one circuit in the memory controller, is temporarily stored in this circuit, and then is memory controlled. It is internally aligned with the device clock for further processing. Read alignment (also called read data alignment) is read when read data is output from, for example, a first-in, first-out buffer (FIFO) in the memory controller and fed to the core of the memory controller. Includes synchronizing data with the same clock signal. This clock signal is not the same as the read data strobe enable signal, which is different for each slice of data, but allows the data to be written to the FIFO. It is possible to use buffer circuit elements and / or flip-flop circuit elements instead of or in combination with FIFOs.

0033More specifically, FIG. 5 is a flowchart showing an embodiment of a process of calibrating the read data alignment settings. The system first sets all DRAMs to the minimum possible read data alignment settings (Operation 502). The system then calibrates one DRAM using the technique already described in FIG. 3 (Operation 504) and then determines if the DRAM calibration process was successful (Operation 506). If the DRAM calibration process is unsuccessful, the system increases the current read data alignment settings (operation 508) and returns to operation 504. On the other hand, if the DRAM calibration process is successful, the system determines if there is another DRAM to calibrate (Operation 510). If present, the system returns to operation 504 and calibrates the next DRAM. If not present, the system determines the maximum read data alignment setting across all DRAMs (operation 512) and sets the read data alignment settings for all DRAMs to this maximum setting (operation 514).

0034The system then determines if there is another rank of DRAM to calibrate (Operation 516). If present, the system returns to operation 502 and calibrates the next rank of DRAM. On the other hand, if there is no higher rank DRAM, the process is completed.

0035In the alternative embodiment shown in FIG. 6, the read alignment setting is initialized to the maximum possible setting and then reduced. More specifically, in this alternative embodiment, the system first sets all DRAMs to the maximum read data alignment setting possible (Operation 602). The system then calibrates one DRAM using the technique already described in Figure 3 (Operation 604) and then determines if there is another DRAM to calibrate (Operation 606). If present, the system returns to operation 604 and calibrates the next DRAM. If not present, the system determines the read enable delay setting for each DRAM (operation 608) and then the maximum read data alignment setting across all DRAMs (operation 610). The system then sets the read data alignment settings for all DRAMs to this maximum setting (operation 612).

0036The system then determines if there is another rank of DRAM to calibrate (Operation 614). If present, the system returns to operation 602 and calibrates the next rank of DRAM. On the other hand, if there is no higher rank DRAM, the process is completed.

00372D write-read-verification calibration method for one DRAM FIG. 7 is a flowchart showing an alternative embodiment of the memory timing calibration process using the two-dimensional (2D) write-read-verification calibration method. This 2D search method uses a two-pass method. The first pass uses coarse step sizes for transmit and receive phase settings (write leveling delay and read leveling delay, respectively) (operation 702). The system first advances the transmission phase while incrementing it from the origin of the 2D search area. The system attempts to find a "coarse path" region by incrementing the receive phase for each transmit phase. The system continues to advance the transmission phase to the full until a sufficiently large coarse path region is found. When this occurs, the first pass is terminated and the final transmit phase is used as the seed for the second pass of the method.

0038If the system cannot find the coarse path region and therefore the first pass is unsuccessful, the system signals an error (operation 705).

0039On the other hand, if the system succeeds in finding the coarse path area, the system performs a fine step size search to find the DQS read enable delay center (operation 706), and then finds the DQ / DQS write delay center. Perform a fine-grained step-size search (Operation 708). More specifically, in the second pass, the fine step size is used in the receive phase setting to find the entire path area surrounding the first pass transmit phase, starting with the seed generated during the first pass transmit phase. .. After that, the center of this region is found, and the center reception phase is used as the optimum reception phase setting. In the second pass, the fine step size is then used for the receive phase setting to start from this center receive phase and find the entire path area surrounding the center receive phase setting. The system then finds the center of this region and uses that center transmit phase as the transmit phase setting.

0040The 2D calibration method described above can be used, for example, for DDR2 SDRAM chips or other types of memory devices. Therefore, if the operation 504 of the flow diagram of FIG. 5 is replaced with this 2D method, the flow diagram of FIG. 5 can be used. As an alternative, replacing operation 604 in the flow diagram of FIG. 6 with this 2D method makes the flow diagram of FIG. 6 available.

0041FIG. 8 is a graph showing success areas and failure areas. Note that the 2D search described above identifies the 2D success area 802 for all possible combinations of read enable delay and write enable delay.

0042Phase detection circuit 1 FIG. 9 shows an embodiment of a phase detection circuit (which can facilitate write timing calibration for DRAM flyby delay isolation larger than one clock cycle, for example). In this phase detection circuit, a marking pulse is received, for example, on the write enable (WE #) signal line 900, and the marking pulse uses the rising and falling edges of the clock signal 201 as clocks, respectively. Flip-flops (D-flops) are fed via 901 and 902. This produces a phase detector enable signal (PDEN) 906 with a window corresponding to the desired time slot. Next, the window clock signal 908 is generated by taking the logical product of the PDEN signal 906 and the clock signal 904. In one embodiment, WE # is routed and propagated along with CK through fly bypass.

0043Next, the window clock signal 908 is taken into the flip-flop 905 with the data strobe signal (DQS) 203 as the clock. The output of the flip-flop 905 is fed to the data line DQ 205 through the feedback path 905 and the multiplexing 918. The multiplexing device 918 selectively feeds the output of the flip-flop 206 to the data line DQ 205 based on the value of the leveling mode signal 910.

0044This feedback signal allows the memory controller to determine if the clock signals 201 and DQS 203 are aligned, which allows the memory controller to pulse various delays with respect to the clock signal 201. Is asserted on the DQS 203 and the transition appearing on the data line DQ 205 is searched for in the output of the phase detector, which makes it possible to calibrate the timing relationship between the DQS 203 and the clock signal 201.

0045Any command line or control line on the fly bypass can be used to transmit this marking pulse. Therefore, it is not mandatory to use a particular command line WE # for this purpose, as it is possible to use another command line or control line instead of the WE # command line (eg, various embodiments). In, instead of WE #, command lines such as RAS # and CAS #, or control lines such as chip select (CS #) and clock enable (CKE #) can be used). In this embodiment, the WE # command line is used because the WE # command line is associated with the memory write function during normal operation (that is, during non-calibration mode operation).

0046After the window clock signal 908 is generated, the DQS signal 203 is taken into the flip-flop 905 as a clock. Similar to the circuit shown in FIG. 2, the output of the flip-flop 905 is fed through the feedback path 907, the multiplexing device 918, and the data line DQ 205. In this process, the multiplexing device 918 selectively feeds the output of the flip-flop 905 to the data line DQ 205 based on the value of the leveling mode signal 910. Therefore, during the leveling mode operation, the memory controller can determine whether the window clock signal 908 and the data strobe signal DQS 203 are in phase. As a result, the memory controller asserts pulses variously delayed with respect to the window clock signal 908 on the DQS signal 203, and searches the output of the phase detector for the transition appearing on the data line DQ 205. This makes it possible to calibrate the timing relationship between the DQS signal 203 and the window clock signal 908.

0047On the other hand, when the DRAM fly-by delay separation exceeds one clock cycle, the circuit shown in FIG. 9 causes a transition from zero to one because the DQS signal 203 and the clock signal 201 are in phase. Only if these positions are aligned for the proper clock cycle. This point is different from the circuit shown in FIG. The circuit of FIG. 2 causes a zero-to-one transition when the DQS signal 203 and the clock signal 201 are in phase and are not aligned for the proper clock cycle.

0048Calibration process FIG. 10 is a timing diagram showing an example of the calibration process using the circuit shown in FIG. The upper part of FIG. 10 shows the timing of the signal on the memory control device side, and the lower part of FIG. 10 shows the timing of the signal on the memory chip (DRAM) side. In FIG. 10, the memory controller transmits a clock signal (CK 201) and a data strobe signal (DQS 203) to the DRAM.

0049As shown in FIG. 10, the DQS pulse is asserted by the memory controller. In this embodiment, the CK signal to the DIMM accommodating the DRAM and all the DQS signals are routed on the circuit board by equal-length wiring. Over time of flight on the circuit board, CK and DQS propagate to each DRAM in the DIMM. In this process, the DQS signals are routed to each DRAM in the DIMM via equal distances. On the other hand, CK is continuously routed to each DRAM through fly bypass. As a result, the skew between CK and DQS increases continuously at each DRAM along the fly bypass. As memory clock speeds continue to increase, these DRAM flyby delay isolations begin to exceed one clock cycle. As a result, the skew between CK and DQS is greater than one clock cycle. In one embodiment, at least one command signal (eg, WE #) is routed and propagated along with the CK through the fly bypass.

0050On the DRAM side of Figure 10, as indicated by the arrow attached to the DQS pulse, the calibration process is a transition from zero to one at the output of a standard phase detector by sweeping the DQS pulse delay relative to the CK. Find out. The detection of a zero-to-one transition indicates that the phases between CK and DQS are exactly aligned.

0051The memory controller asserts the WE # signal 900 one clock cycle before the DQS pulse is asserted. After the signal propagates between the memory controller and the DRAM, there is a skew of more than one clock cycle between the CK signal 201 and the DQS signal 203. As shown in the circuit of FIG. 9, the WE # signal 900 is staged, inverted, and windowed into the desired CK time slot. The resulting window signal PDEN prevents false detection of transitions, as shown at the bottom of FIG.

0052Phase detection circuit 2 FIG. 11 shows an embodiment of a phase detection circuit available in DRAM, along with related timing diagrams. This embodiment is similar to that shown in FIG. 9, where the WE # signal 900 is staged through the stage circuit for the WE # signal 900 on the DRAM (rather than through the flip-flop 901). The point is different.

0053More specifically, the WE # signal 900 is staged through the first variable length shifter 1102 and the second variable length shifter 1104, and the first variable length shifter 1102 is for additional delay (AL). The delay is programmed to AL, the second variable length shifter 1104 is for CAS write delay (CWL), the delay is programmed to = CWL-1, and this "1" is a flip-flop. Corresponds to the delay when passing through 902. An additional delay is a programmable delay between when a column command (for example, a read or write command) is received in DRAM and before the command is applied or posted internally, when the command is executed internally. It indicates whether it will be started. A write delay is a programmable delay from when a write command is internally applied or posted until the data associated with that write command is sampled by DRAM. By using this stage circuit, the memory control device can execute the write calibration process with the same write delay as in the normal operation.

0054Calibration process FIG. 12 is a flowchart showing an embodiment of the write timing calibration process. In this process, a clock signal, a marking signal, and a data strobe signal are transmitted from the memory controller to the memory chip (operation 1202). The marking signal is then used to "window" a particular clock cycle in the clock signal (operation 1204). As a result, a window clock signal is generated.

0055The pulse on the data strobe signal is then used to capture the window clock signal into the memory element (operation 1206). The captured window clock signal is then returned to the memory controller as a feedback signal (Operation 1208).

0056The memory controller then uses this feedback signal to calibrate the timing relationship between the clock signal and the data strobe signal (operation 1210). For example, this calibration process phase-detects a transition indicating that the data strobe signal and the clock signal are aligned, with asserting pulses on the data strobe signal that are delayed with respect to the clock signal. It can be found in the output of the vessel.

0057The number of components or operations included in FIGS. 1 to 12 may be less or more. In addition, it is possible to combine two or more components or operations into a single component or operation and / or reposition one or more components or operations.

0058In addition, the components and / or functionality shown in FIGS. 1-12 can be implemented in analog and / or digital circuits. In addition, the components and / or functionality of FIGS. 1-12 can be implemented in hardware and / or software.

0059The devices and circuits described herein can be implemented using computer-aided design tools available in the art and can be embodied by computer-readable files containing software descriptions of such circuits. These software descriptions may be behavior level, register transfer level, logical component level, transistor level, and layout geometry level descriptions. Further, the software description can be stored in a storage medium or transmitted by a carrier wave.

0060Data formats in which such descriptions can be implemented include formats that support behavioral languages such as C, formats that support register transfer level (RTL) languages such as Verilog and VHDL, and geometry description languages ( Formats that support (GDSII, GDSIII, GDSIV, CIF, MEBES, etc.) and other suitable formats and languages are included, but not limited to. Moreover, data transfer of such files on machine-readable media can be done electronically by a variety of media on the Internet (eg, e-mail). The actual file can be mounted on a machine-readable medium (4 mm magnetic tape, 8 mm magnetic tape, 3.5 inch floppy medium, CD, DVD, etc.).

0061FIG. 13 is a block diagram showing an embodiment of the system 1300 that stores such computer readable files. The system can include at least one data processing unit or central processing unit (CPU) 1310, memory 1324, and one or more signal lines or communication buses 1322 that connect these components to each other. is there. Memory 1324 can include random access memory and / or non-volatile memory, for example ROM, RAM, EPROM, EEPROM, flash, one or more smart cards, one or more magnetic disk storage devices. , And / or can include one or more optical storage devices.

0062Memory 1324 can store circuit compiler 1326 and circuit description 1328. Circuit description 1328 can include a circuit description, i.e., a subset of the circuits described above. Specifically, circuit description 1328 refers to one or more memory controllers 1330, one or more memory devices 1332, one or more phase detectors 1334, one or more flip-flops 1336, one. Or multiple amplifiers 1338, one or more modulators 1340, one or more drivers 1342, one or more logic circuits 1344, one or more driver circuits 1346, and / or one or more. It is possible to include a circuit description for the variable length shifter 1348.

0063It should be noted that the number of components included in the system 1300 may be less or more. In addition, it is possible to combine two or more components into a single component and / or reposition one or more components.

0064The description of the embodiments described above is for illustration and explanation purposes only. They are not intended to be exhaustive or to limit this specification to the form of disclosure. Therefore, various modifications and modifications will be obvious to those skilled in the art. Moreover, the above disclosure is not intended to limit this specification. The scope of the specification is defined by the appended claims.