Liquid crystal display device and method for driving liquid crystal display device

The present invention relates to a method for driving a liquid crystal display device. In particular, the present invention relates to a method of driving a liquid crystal display device that displays by a field sequential method.

As a display method of the liquid crystal display device, a color filter method and a field sequential method are known. In a liquid crystal display device that displays by the former, each pixel has a plurality of subs having a color filter (for example, R (red), G (green), B (blue)) that transmits only light having a wavelength having a specific color. Pixels are provided. Then, a desired color is formed by controlling the transmission of white light for each sub-pixel and mixing a plurality of colors for each pixel. On the other hand, in the liquid crystal display device that displays by the latter, a plurality of light sources (for example, R (red), G (green), B (blue)) that exhibit different colors are provided. Then, each of the plurality of light sources exhibiting different colors repeatedly blinks, and the transmission of light exhibiting each color is controlled for each pixel to form a desired color. That is, the former is a method of forming a desired color by dividing the area for each light exhibiting a specific color, and the latter is a method of forming a desired color by dividing the time for each light exhibiting a specific color. is there.

A liquid crystal display device that displays by a field sequential method has the following advantages as compared with a liquid crystal display device that displays by a color filter method. First, in a liquid crystal display device that displays by a field sequential method, it is not necessary to provide sub-pixels for each pixel. Therefore, it is possible to improve the aperture ratio or increase the number of pixels. In addition, it is not necessary to provide a color filter in the liquid crystal display device that displays by the field sequential method. That is, there is no loss of light due to light absorption in the color filter. Therefore, it is possible to improve the transmittance and reduce the power consumption.

Patent Document 1 discloses a liquid crystal display device that displays by a field sequential method. Specifically, each pixel is provided with a transistor for controlling the input of an image signal, a signal holding capacitance for holding the image signal, and a transistor for controlling the transfer of charge from the signal holding capacitance to the display pixel capacitance. The liquid crystal display device is disclosed. The liquid crystal display device having this configuration can input an image signal with respect to the signal holding capacity and display according to the electric charge held by the display pixel capacity in parallel.

Further, Patent Document 2 discloses a liquid crystal display device in which the power consumption of the backlight light source is reduced. Specifically, the maximum value detection circuit that detects the maximum value of gradation in one screen (one field) of each color of R, G, and B does not overlap the light of each color of R, G, and B according to the image signal. It is a liquid crystal display device provided with a backlight light source that outputs in the same manner.

In the liquid crystal display device described above, the maximum value detection circuit detects a pixel displaying the maximum gradation, drives the pixel so that its aperture ratio (in other words, the deflection angle of the liquid crystal) is maximized, and detects the pixel. The brightness of the backlight light source is adjusted so that the maximum gradation is displayed. Further, in the pixel displaying another gradation, the pixel is driven so as to reduce the aperture ratio (deflection angle of the liquid crystal) of the pixel according to the difference from the maximum detected gradation. It is possible to reduce power consumption by driving the backlight source according to the brightness that maximizes the gradation for each screen (1 field) of each color of R, G, and B.

<p num="0007"><patcit num="1"><text>JP 2009-42405</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2006-47594</text></patcit></p>

<p num="0008">As described above, the color information is time-divided in the liquid crystal display device that displays by the field sequential method. Therefore, specific display information is lost due to interruption of the display for a short time such as blinking of the user, and therefore, the display visually recognized by the user changes (deteriorates) from the display based on the original display information. There is (also called color break or color cracking).</p><p num="0009">In addition, a liquid crystal display device that expresses gradation by limiting the transmission of light emitted by a backlight source using an image signal wastes the energy emitted by the backlight source. Therefore, the liquid crystal display device described in Patent Document 2 that drives the pixels and the backlight light source according to the brightness that maximizes the gradation in one screen (one field) of each color of R, G, and B reduces power consumption. It exerts a certain effect on. However, if the maximum value detection circuit detects the gradation that the backlight source needs to shine with the maximum brightness even for one pixel in one screen (one field), how the gradation is distributed in other areas. Even so, the backlight source needs to emit light at the maximum brightness, and as a result, the power consumption cannot be reduced. That is, the effect of reducing the power consumption is obtained only when the bright gradation cannot be found on the full screen.</p><p num="0010">Therefore, one aspect of the present invention is to suppress deterioration of the image quality of the liquid crystal display device that displays by the field sequential method, and to effectively reduce the power consumption of the backlight.</p>

<p num="0011">In order to achieve the above object, the present invention focuses on the frequency of image signals input to a liquid crystal display device to which a field sequential method is applied and the transmittance of pixels displaying the brightest gradation in each frame. Then, by dividing the plurality of pixels and the backlight arranged in a matrix into a plurality of regions in the row direction and inputting the image signal, the frequency of inputting the image signal to each pixel is increased, and at the same time, one From the image signals related to the first color displayed in the area, the signal with the brightest gradation is detected, and then the transmission rate of the pixel displaying the signal is maximized, and the floor is higher than the pixel displaying the signal. For dark pixels, the image signal is gamma-corrected so as to reduce the transmission rate according to the darkening rate. Next, a backlight may be used to irradiate one region with light of the first color so that the display corresponding to the original image signal is performed in the pixel. Further, in the other region, the image signal is gamma-corrected and the backlight is adjusted by the same method as that performed in one region, and the light of another color is applied to the other region in one region. Is irradiated at the same time as the first color is irradiated. In this way, the pixel portion is divided into a plurality of regions, gamma correction and backlight adjustment are performed according to the image signal of the brightest gradation detected for each region, and the color is sequentially changed for each region. It should be displayed.</p><p num="0012">That is, one aspect of the present invention is one of a liquid crystal display device including a plurality of pixels arranged in a matrix of m rows and n columns (m and n are natural numbers of 4 or more) and a backlight provided behind the plurality of pixels. An image signal for controlling the transmission of light exhibiting the first color for a plurality of pixels arranged in a matrix in the rows A to A (A is a natural number of m / 2 or less) is input. In addition, in the period in which an image signal for controlling the transmission of light exhibiting a second color is input to a plurality of pixels arranged in a matrix in the A + 1 to 2A rows, the first The maximum image signal for controlling the transmission of light that exhibits color, which is related to a plurality of pixels arranged in the first to Bth lines (B is a natural number of A / 2 or less). The value detection circuit is used to detect the first image signal of the first brightest gradation, maximize the transparency of the first pixel displaying the first image signal, and maximize the transmission of the first brightest gradation. The image signal for controlling the transmission of the light exhibiting the first color is gamma-corrected so as to reduce the transmission rate of the pixel according to the rate at which the gradation becomes darker than that of the first line to the B line. It includes a step of outputting to a plurality of pixels arranged in the eye. Further, the maximum value is detected from the image signals for controlling the transmission of the light exhibiting the second color, which are related to a plurality of pixels arranged in the A + 1 to A + B rows. The circuit is used to detect the second image signal of the second brightest gradation, maximize the transmittance of the second pixel displaying the second image signal, and compare with the second brightest gradation. The image signal for controlling the transmission of the light exhibiting the second color is gamma-corrected so as to reduce the transmittance of the pixel according to the rate at which the gradation becomes darker, from the A + 1 line to the A +. It includes a step of outputting to a plurality of pixels arranged on the Bth line. Subsequently, the plurality of pixels arranged in the first to B rows are displayed with a gradation corresponding to the first image signal in the first pixel having the maximum transmittance. Light exhibiting the first color corresponds to the plurality of pixels arranged in the A + 1 to A + B rows, and corresponds to the second image signal in the second pixel having the maximum transmittance. The strength with which the gradation is displayed</p><p num="0013">According to one aspect of the present invention, a plurality of pixels arranged in a matrix of m rows and n columns are divided into a plurality of regions, and the liquid crystal panel is driven in each region in a field sequential manner. In addition, gamma correction is performed to maximize the transmittance of the liquid crystal element that displays the brightest gradation in each region, and the light intensity of the backlight is further controlled. As a result, not only the color break phenomenon can be suppressed and a high-quality image can be displayed, but also the power consumption of the liquid crystal display device can be effectively reduced.</p><p num="0014">Further, one aspect of the present invention is one of a liquid crystal display device including a plurality of pixels arranged in a matrix of m rows and n columns (m and n are natural numbers of 4 or more) and a backlight provided behind the plurality of pixels. An image signal for controlling the transmission of light exhibiting the first color is input to a plurality of pixels arranged in the rows A to A (A is a natural number of m / 2 or less), and A In the period in which the image signal for controlling the transmission of the light exhibiting the second color is input to the plurality of pixels arranged in the +1st line to the 2A line, the 1st line to the A line are p. The maximum of the image signals for controlling the transmission of light that exhibits the first color to a plurality of pixels arranged in any one of the first regions divided into pieces (p is a natural number of 2 or more). The value detection circuit is used to detect the first image signal with the brightest gradation, maximize the transparency of the pixel displaying the first image signal, and the gradation is higher than that of the first brightest gradation. A step is provided in which an image signal for controlling the transmission of light exhibiting the first color is output to a first region by performing gamma correction so as to reduce the transmission rate of the pixel according to the darkening rate. In addition, the light that exhibits a second color on a plurality of pixels arranged in any one of the second regions obtained by dividing the A + 1 to 2A rows into q (q is a natural number of 2 or more). From the image signals for controlling the transmittance, the second image signal with the brightest gradation is detected using the maximum value detection circuit, and the transmittance of the pixel displaying the second image signal is maximized. An image signal for controlling the transmission of light exhibiting the second color by gamma correction so as to reduce the transmittance of pixels according to the rate at which the gradation becomes darker than the second brightest gradation. Is provided with a step of outputting to the second area. Subsequently, it is arranged in the first region with a duty ratio of 1 / (p-1) or less by using a first pulse width modulation circuit to which a light source capable of independently illuminating p regions is connected. A light source that can independently illuminate q areas by irradiating light that exhibits the first color so that the gradation corresponding to the first image signal is displayed in the pixel with the maximum transmission is connected. Using the second pulse width modulation circuit, the second with a duty ratio of 1 / (q-1) or less.</p><p num="0015">According to one aspect of the present invention, a plurality of pixels arranged in a matrix of m rows and n columns are divided into a plurality of regions, and the liquid crystal panel is driven in each region in a field sequential manner. In addition, gamma correction is performed to maximize the transmittance of the liquid crystal element that displays the brightest gradation in each region, and the light intensity of the backlight is further controlled. As a result, not only the color break phenomenon can be suppressed and a high-quality image can be displayed, but also the power consumption of the liquid crystal display device can be effectively reduced.</p><p num="0016">In addition, a liquid crystal display device having a plurality of pixels arranged in a matrix of m rows and n columns (m and n are natural numbers of 4 or more) and a backlight behind them, using a small number of power supply circuits It can be driven and the number of parts of the liquid crystal display device can be reduced.</p><p num="0017">Further, one aspect of the present invention is a method of driving the above-mentioned liquid crystal display device using a backlight to which an LED is applied as a light source.</p><p num="0018">According to the above aspect of the present invention, an LED having excellent responsiveness to an input signal and high luminous efficiency is applied as a light source of a backlight. As a result, color break and power consumption can be reduced.</p><p num="0019">Further, one aspect of the present invention is a method of driving a liquid crystal display device using a backlight that lights up at a frequency of 100 Hz or more and 10 GHz or less.</p><p num="0020">According to the above aspect of the present invention, the light source applied to the backlight can be driven at a speed unrecognizable to the human eye. This can reduce the causes of eye fatigue such as flicker.</p>

<p num="0021">The liquid crystal display device according to one aspect of the present invention does not sequentially input an image signal and turn on the backlight on the entire surface of the pixel portion, but at the same time input an image signal and turn on the backlight for each specific area of the pixel portion. It can be done sequentially. This makes it possible to improve the input frequency of the image signal for each pixel of the liquid crystal display device. As a result, it is possible to suppress display deterioration such as color breaks that occur in the liquid crystal display device and improve the image quality. In addition, by detecting the image signal having the brightest gradation included in the image signal for each specific region of the pixel portion, it is possible to finely control the emission intensity of the backlight light source. As a result, the power consumption of the liquid crystal display device can be effectively reduced.</p>

<figref num="1">(A) A diagram showing a configuration example of a liquid crystal display device, and (B) a diagram showing a configuration example of pixels.</figref><figref num="2">(A) A diagram showing a configuration example of a scanning line drive circuit, (B) a timing chart showing an example of a signal used in the scanning line drive circuit, and (C) a diagram showing a configuration example of a pulse output circuit.</figref><figref num="3">(A) A circuit diagram showing an example of a pulse output circuit, and (B) to (D) a timing chart showing an example of the operation of the pulse output circuit.</figref><figref num="4">(A) A diagram showing a configuration example of a signal line drive circuit, and (B) a diagram showing an example of operation of the signal line drive circuit.</figref><figref num="5">The figure which shows the configuration example of the backlight.</figref><figref num="6">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="7">(A), (B) A circuit diagram showing an example of a pulse output circuit.</figref><figref num="8">(A), (B) A circuit diagram showing an example of a pulse output circuit.</figref><figref num="9">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="10">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="11">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="12">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="13">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="14">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="15">The figure explaining the operation example of the liquid crystal display device.</figref><figref num="16">The figure explaining the structure of the liquid crystal display device.</figref><figref num="17">The figure which shows the specific example of the transistor (A) to (D).</figref><figref num="18">Top view showing a concrete example of a pixel layout.</figref><figref num="19">The cross-sectional view which shows the specific example of the layout of a pixel.</figref><figref num="20">(A) top view and (B) sectional view showing a specific example of a liquid crystal display device.</figref><figref num="21">The perspective view which shows the specific example of the liquid crystal display device.</figref><figref num="22">(A)-(F) The figure which shows an example of the electronic device.</figref><figref num="23">(A) ~ (E), (C') ~ (E') The figure explaining one form of the substrate used in the liquid crystal display device.</figref><figref num="24">The figure which shows an example of the liquid crystal display device.</figref>

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used in different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

(Embodiment 1) In the present embodiment, the liquid crystal display device according to one aspect of the present invention will be described with reference to FIGS. 1 to 6.

&lt;Configuration example of liquid crystal display device&gt; FIG. 1A is a diagram showing a configuration example of a liquid crystal display device. In the liquid crystal display device shown in FIG. 1A, the pixel unit 10, the scanning line driving circuit 11, and the signal line driving circuit 12 are arranged in parallel or substantially parallel to each other, and the potential is increased by the scanning line driving circuit 11. It has m scanning lines 13 in which is controlled, and n signal lines 14 in which each is arranged in parallel or substantially parallel and the potential is controlled by the signal line driving circuit 12. Further, the pixel unit 10 is divided into three regions (regions 101 to 103), and has a plurality of pixels arranged in a matrix for each region. Each scanning line 13 is electrically connected to n pixels arranged in any one of the plurality of pixels arranged in m rows and n columns in the pixel unit 10. Further, each signal line 14 is electrically connected to m pixels arranged in any of the plurality of pixels arranged in m rows and n columns.

FIG. 1B is a diagram showing an example of a circuit diagram of pixels 15 included in the liquid crystal display device shown in FIG. 1A. In the pixel 15 shown in FIG. 1 (B), a transistor 16 in which the gate is electrically connected to the scanning line 13 and one of the source and the drain is electrically connected to the signal line 14 and one electrode is the transistor 16. A capacitive element 17 electrically connected to the other of the source and drain and electrically connected to a wiring (also called a capacitive wiring) to which the other electrode supplies a capacitive potential, and one electrode (also called a pixel electrode) A liquid crystal element 18 that is electrically connected to the other electrode of the source and drain of the transistor 16 and one electrode of the capacitance element 17, and the other electrode (also referred to as a counter electrode) is electrically connected to a wiring that supplies a counter electrode. , Have. The transistor 16 is an n-channel type transistor. Further, it is possible to make the capacitance potential and the counter potential the same potential.

&lt;Configuration example of scanning line drive circuit 11&gt; FIG. 2A is a diagram showing a configuration example of the scanning line drive circuit 11 included in the liquid crystal display device shown in FIG. 1A. The scanning line drive circuit 11 shown in FIG. 2A includes a wiring for supplying the clock signal for the first scanning line drive circuit (GCK1) and a wiring for supplying the clock signal for the fourth scanning line drive circuit (GCK4). , The wiring that supplies the first pulse width control signal (PWC1) to the wiring that supplies the sixth pulse width control signal (PWC6), and the scanning line 13 arranged on the first line are electrically connected. It has a first pulse output circuit 20_1, and an mth pulse output circuit 20_m electrically connected to a scanning line 13 arranged on the mth line. Here, the first pulse output circuit 20_1 to the kth pulse output circuit 20_k (k is a multiple of 4 less than m / 2) are electrically connected to the scanning line 13 arranged in the region 101. The second k + 1 pulse output circuit 20_k + 1 to the second k pulse output circuit 20_2k are electrically connected to the scanning line 13 arranged in the region 102, and the second k + 1 pulse output circuit 20_2k + It is assumed that the first to mth pulse output circuits 20_m are electrically connected to the scanning line 13 arranged in the region 103. Further, the first pulse output circuit 20_1 to the mth pulse output circuit 20_m generate a shift pulse for each shift period triggered by a scan line drive circuit start pulse (GSP) input to the first pulse output circuit 20_1. It has a function to shift sequentially. Further, it is possible to shift a plurality of shift pulses in parallel in the first pulse output circuit 20_1 to the mth pulse output circuit 20_m. That is, even during the period in which the shift pulse is shifted in the first pulse output circuit 20_1 to the mth pulse output circuit 20_m, the first pulse output circuit 20_1 has a start pulse for the scanning line drive circuit ( GSP) can be entered.

FIG. 2B is a diagram showing an example of a specific waveform of the signal. The clock signal (GCK1) for the first scanning line drive circuit shown in FIG. 2 (B) periodically has a high level potential (high power supply potential (Vdd)) and a low level potential (low power supply potential (Vss)). Repeatedly, it is a signal with a duty ratio of 1/4. The second scan line drive circuit clock signal (GCK2) is a signal that is 1/4 cycle out of phase with the first scan line drive circuit clock signal (GCK1), and is driven by a third scan line. The circuit clock signal (GCK3) is a signal that is 1/2 cycle out of phase with the first scan line drive circuit clock signal (GCK1), and the fourth scan line drive circuit clock signal (GCK4) is This is a signal that is 3/4 cycle out of phase with the clock signal (GCK1) for the first scanning line drive circuit. The first pulse width control signal (PWC1) is a signal with a duty ratio of 1/3 that periodically repeats a high level potential (high power supply potential (Vdd)) and a low level potential (low power supply potential (Vss)). Is. The second pulse width control signal (PWC2) is a signal that is 1/6 cycle out of phase with the first pulse width control signal (PWC1), and the third pulse width control signal (PWC3) is the third. The signal is 1/3 cycle out of phase with the pulse width control signal (PWC1) of 1, and the fourth pulse width control signal (PWC4) is 1/2 cycle phase with respect to the first pulse width control signal (PWC1). The fifth pulse width control signal (PWC5) is a signal that is 2/3 cycle out of phase with the first pulse width control signal (PWC1), and is a sixth pulse width control signal (PWC1). PWC6) is a signal that is 5/6 cycle out of phase with the first pulse width control signal (PWC1). Here, the pulse widths of the first scan line drive circuit clock signal (GCK1) to the fourth scan line drive circuit clock signal (GCK4) and the first pulse width control signal (PWC1) to the sixth The pulse width ratio of the pulse width control signal (PWC6) is 3: 2.

In the liquid crystal display device described above, circuits having the same configuration can be applied as the first pulse output circuit 20_1 to the mth pulse output circuit 20_m. However, the electrical connection relationship between the plurality of terminals of the pulse output circuit differs for each pulse output circuit. The specific connection relationship will be described with reference to FIGS. 2 (A) and 2 (C).

Each of the first pulse output circuit 20_1 to the mth pulse output circuit 20_m has terminals 21 to 27. The terminals 21 to 24 and 26 are input terminals, and the terminals 25 and 27 are output terminals.

First, the terminal 21 will be described. The terminal 21 of the first pulse output circuit 20_1 is electrically connected to the wiring that supplies the start pulse (GSP) for the scanning line drive circuit, and is the terminal of the second pulse output circuit 20_2 to the mth pulse output circuit 20_m. 21 is electrically connected to the terminal 27 of the pulse output circuit in the previous stage.

Next, the terminal 22 will be described. The terminal 22 of the first (4a-3) pulse output circuit (a is a natural number of m / 4 or less) is electrically connected to the wiring that supplies the clock signal (GCK1) for the first scanning line drive circuit. The terminal 22 of the pulse output circuit of the second (4a-2) is electrically connected to the wiring for supplying the clock signal (GCK2) for the second scanning line drive circuit, and is connected to the pulse output circuit of the second (4a-1). The terminal 22 is electrically connected to the wiring that supplies the clock signal for the third scanning line drive circuit (GCK3), and the terminal 22 of the pulse output circuit of the fourth a is the clock signal for the fourth scanning line drive circuit (GCK3). It is electrically connected to the wiring that supplies GCK4).

Next, the terminal 23 will be described. The terminal 23 of the fourth (4a-3) pulse output circuit is electrically connected to the wiring that supplies the clock signal (GCK2) for the second scanning line drive circuit, and is connected to the second (4a-2) pulse output circuit. The terminal 23 is electrically connected to the wiring that supplies the clock signal (GCK3) for the third scanning line drive circuit, and the terminal 23 of the pulse output circuit of the third (4a-1) is the fourth scanning line driving circuit. It is electrically connected to the wiring that supplies the clock signal (GCK4) for the first scan line, and the terminal 23 of the pulse output circuit of the fourth a is electrically connected to the wiring that supplies the clock signal (GCK1) for the first scanning line drive circuit. Will be done.

Next, the terminal 24 will be described. The terminal 24 of the second (2b-1) pulse output circuit (b is a natural number of k / 2 or less) is electrically connected to the wiring that supplies the first pulse width control signal (PWC1), and the second b The terminal 24 of the pulse output circuit is electrically connected to the wiring that supplies the fourth pulse width control signal (PWC4), and the (2c-1) pulse output circuit (c is (k / 2 + 1)). The terminal 24 of the natural number (k or less) is electrically connected to the wiring for supplying the second pulse width control signal (PWC2), and the terminal 24 of the pulse output circuit of the second c is the fifth pulse width control signal. It is electrically connected to the wiring that supplies (PWC5), and the terminal 24 of the first (2d-1) pulse output circuit (d is a natural number of (k + 1) or more and m / 2 or less) is the third pulse. It is electrically connected to the wiring that supplies the width control signal (PWC3), and the terminal 24 of the second pulse output circuit is electrically connected to the wiring that supplies the sixth pulse width control signal (PWC6).

Next, the terminal 25 will be described. The terminal 25 of the xth pulse output circuit (x is a natural number of m or less) is electrically connected to the scanning line 13_x arranged on the xth line.

Next, the terminal 26 will be described. The terminal 26 of the y-th pulse output circuit (y is a natural number less than or equal to m-1) is electrically connected to the terminal 27 of the (y + 1) th pulse output circuit, and is the terminal of the m-th pulse output circuit. The 26 is electrically connected to the wiring that supplies the stop signal (STP) for the mth pulse output circuit. The stop signal (STP) for the mth pulse output circuit is output from the terminal 27 of the (m + 1) th pulse output circuit if the th (m + 1) pulse output circuit is provided. It is a signal corresponding to the signal to be generated. Specifically, these signals are supplied to the m-th pulse output circuit by actually providing a (m + 1) th pulse output circuit as a dummy circuit, or by directly inputting the signal from the outside. be able to.

The connection relationship of the terminals 27 of each pulse output circuit has already been described. Therefore, the above description will be used here.

&lt;Pulse output circuit configuration example&gt; FIG. 3A is a diagram showing a configuration example of the pulse output circuit shown in FIGS. 2A and 2C. The pulse output circuit shown in FIG. 3A has transistors 31 to 39.

One of the source and the drain of the transistor 31 is electrically connected to a wiring (hereinafter, also referred to as a high power potential line) that supplies a high power potential (Vdd), and the gate is electrically connected to the terminal 21.

One of the source and drain of the transistor 32 is electrically connected to a wiring (hereinafter, also referred to as a low power potential line) that supplies a low power potential (Vss), and the other of the source and drain is the source and drain of the transistor 31. It is electrically connected to the other.

In transistor 33, one of the source and drain is electrically connected to terminal 22, the other of source and drain is electrically connected to terminal 27, and the gate is the other of source and drain of transistor 31 and the source and drain of transistor 32. It is electrically connected to the other side of the drain.

In the transistor 34, one of the source and the drain is electrically connected to the low power potential line, the other of the source and the drain is electrically connected to the terminal 27, and the gate is electrically connected to the gate of the transistor 32.

In transistor 35, one of the source and drain is electrically connected to the low power potential line, the other of the source and drain is electrically connected to the gate of transistor 32 and the gate of transistor 34, and the gate is electrically connected to terminal 21. Connected to.

In transistor 36, one of the source and drain is electrically connected to the high power potential line, and the other of the source and drain is electrically connected to the gate of transistor 32, the gate of transistor 34, and the other of the source and drain of transistor 35. Connected, the gate is electrically connected to terminal 26. It should be noted that one of the source and drain of the transistor 36 electrically supplies a power supply potential (Vcc) having a higher potential than the low power supply potential (Vss) and a lower potential than the high power supply potential (Vdd). It can also be configured to be connected.

In transistor 37, one of the source and drain is electrically connected to the high power potential line, and the other of the source and drain is the gate of transistor 32, the gate of transistor 34, the other of the source and drain of transistor 35, and the transistor 36. It is electrically connected to the other of the source and drain, and the gate is electrically connected to the terminal 23. It should be noted that one of the source and drain of the transistor 37 may be electrically connected to the wiring for supplying the power supply potential (Vcc).

In transistor 38, one of the source and drain is electrically connected to terminal 24, the other of the source and drain is electrically connected to terminal 25, and the gate is the other of the source and drain of transistor 31, the source and drain of transistor 32. It is electrically connected to the other side of the drain as well as the gate of transistor 33.

In the transistor 39, one of the source and the drain is electrically connected to the low power supply potential line, the other of the source and the drain is electrically connected to the terminal 25, and the gate is the gate of the transistor 32, the gate of the transistor 34, and the transistor 35. Is electrically connected to the other of the source and drain of the transistor 36, the other of the source and drain of the transistor 36, and the other of the source and drain of the transistor 37.

In the following, the other of the source and drain of the transistor 31, the other of the source and drain of the transistor 32, the gate of the transistor 33, and the node to which the gate of the transistor 38 is electrically connected are referred to as node A, and the gate of the transistor 32. , The gate of transistor 34, the other of the source and drain of transistor 35, the other of the source and drain of transistor 36, the other of the source and drain of transistor 37, and the node to which the gate of transistor 39 is electrically connected are described as node B. To do.

&lt;Operation example of pulse output circuit&gt; An operation example of the pulse output circuit described above will be described with reference to FIGS. 3 (B) to 3 (D). Here, by controlling the input timing of the start pulse (GSP) for the scanning line drive circuit input to the terminal 21 of the first pulse output circuit 20_1, the first pulse output circuit 20_1 and the first (k +) An operation example in which a shift pulse is output at the same timing from the terminal 27 of the pulse output circuit 20_k + 1 of 1) and the pulse output circuit 20_2k + 1 of the (2k + 1) th is described. Specifically, FIG. 3B shows the potential of the signal input to each terminal of the first pulse output circuit 20_1 when the start pulse (GSP) for the scanning line drive circuit is input, and the potentials of the signals A and The potential of node B is shown, and Fig. 3 (C) shows each terminal of the (k + 1) th pulse output circuit 20_k + 1 when a high level potential is input from the kth pulse output circuit 20_k. The potential of the signal input to is shown, and the potential of node A and node B is shown. FIG. 3 (D) shows the potential of the second (2k +) when a high level potential is input from the second k pulse output circuit 20_2k. The potential of the signal input to each terminal of the pulse output circuit 20_2k + 1 of 1) and the potential of node A and node B are shown. In FIGS. 3 (B) to 3 (D), the signals input to each terminal are shown in parentheses. In addition, the pulse output circuits arranged after each (second pulse output circuit 20_2, second (k + 2) pulse output circuit 20_k + 2, second (2k + 2) pulse output circuit 20_2k + 2). Signals output from terminal 25 (Gout2, Goutk + 2, Gout2k + 2) and output signal of terminal 27 (SRout2 = input signal of terminal 26 of the first pulse output circuit 20_1, SRoutk + 2 = (k +) The input signal of the terminal 26 of the pulse output circuit 20_k + 1 of 1) and the input signal of the terminal 26 of the pulse output circuit 20_2k + 1 of the SRout2k + 2 = (2k + 1) are also added. In the figure, Gout represents an output signal for the scanning line of the pulse output circuit, and SRout is the pulse output circuit in the subsequent stage of the pulse output circuit.

First, a case where a high-level potential is input to the first pulse output circuit 20_1 as a start pulse (GSP) for a scanning line drive circuit will be described with reference to FIG. 3 (B).

In the period t1, a high level potential (high power potential (Vdd)) is input to the terminal 21. As a result, the transistors 31 and 35 are turned on. Therefore, the potential of node A rises to a high level potential (potential lowered by the threshold voltage of the transistor 31 from the high power supply potential (Vdd)), and the potential of node B falls to a low power supply potential (Vss). .. Along with this, the transistors 33 and 38 are turned on, and the transistors 32, 34 and 39 are turned off. As described above, in the period t1, the signal output from the terminal 27 becomes the signal input to the terminal 22, and the signal output from the terminal 25 becomes the signal input to the terminal 24. Here, in the period t1, the signals input to the terminal 22 and the terminal 24 are both low-level potentials (low power supply potential (Vss)). Therefore, in the period t1, the first pulse output circuit 20_1 has a low level potential (low power supply potential (Vss)) on the terminal 21 of the second pulse output circuit 20_2 and the scanning line arranged in the first line in the pixel portion. )) Is output.

In the period t2, the signal input to each terminal does not change from the period t1. Therefore, the signals output from the terminals 25 and 27 do not change, and both output low-level potentials (low power potential (Vss)).

In the period t3, a high level potential (high power potential (Vdd)) is input to the terminal 24. The potential of the node A (the potential of the source of the transistor 31) has risen to a high level potential (the potential lowered by the threshold voltage of the transistor 31 from the high power supply potential (Vdd)) in the period t1. Therefore, the transistor 31 is in the off state. At this time, when a high level potential (high power supply potential (Vdd)) is input to the terminal 24, the potential of node A (potential of the gate of transistor 38) is further increased by the capacitive coupling between the source and gate of transistor 38. Ascend (bootstrap operation). Further, by performing the bootstrap operation, the signal output from the terminal 25 does not drop from the high level potential (high power supply potential (Vdd)) input to the terminal 24. Therefore, in the period t3, the first pulse output circuit 20_1 outputs a high level potential (high power supply potential (Vdd) = selection signal) to the scanning line arranged in the first line in the pixel portion.

At period t4, a high level potential (high power potential (Vdd)) is input to terminal 22. Here, since the potential of node A is increased by the bootstrap operation, the signal output from terminal 27 may decrease from the high level potential (high power supply potential (Vdd)) input to terminal 22. Absent. Therefore, in the period t4, the high level potential (high power supply potential (Vdd)) input to the terminal 22 is output from the terminal 27. That is, the first pulse output circuit 20_1 outputs a high level potential (high power supply potential (Vdd) = shift pulse) to the terminal 21 of the second pulse output circuit 20_2. Further, in the period t4, the signal input to the terminal 24 is arranged in the first line in the pixel section from the first pulse output circuit 20_1 in order to maintain a high level potential (high power supply potential (Vdd)). The signal output to the scan line remains at a high level potential (high power potential (Vdd) = selection signal). Although it is not directly related to the output signal of the pulse output circuit in the period t4, the transistor 35 is turned off because the low level potential (low power supply potential (Vss)) is input to the terminal 21.

In the period t5, a low level potential (low power potential (Vss)) is input to the terminal 24. Here, the transistor 38 remains on. Therefore, in the period t5, the signal output from the first pulse output circuit 20_1 to the scanning line arranged in the first line in the pixel portion has a low level potential (low power supply potential (Vss)).

In the period t6, the signal input to each terminal does not change from the period t5. Therefore, the signals output from the terminals 25 and 27 do not change, the low-level potential (low power supply potential (Vss)) is output from the terminal 25, and the high-level potential (high power supply potential (Vdd)) is output from the terminal 27. ) = Shift pulse) is output.

In the period t7, a high level potential (high power potential (Vdd)) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises to a high level potential (a potential lowered by the threshold voltage of the transistor 37 from the high power supply potential (Vdd)). That is, the transistors 32, 34, and 39 are turned on. Along with this, the potential of node A drops to a low level potential (low power supply potential (Vss)). That is, the transistors 33 and 38 are turned off. As a result, in the period t7, the signals output from the terminals 25 and 27 both have a low power supply potential (Vss). That is, in the period t7, the first pulse output circuit 20_1 outputs a low power supply potential (Vss) to the terminal 21 of the second pulse output circuit 20_2 and the scanning line arranged in the first line in the pixel portion. ..

Next, with reference to FIG. 3 (C), a case where a high-level potential is input as a shift pulse from the k-th pulse output circuit 20_k to the terminal 21 of the (k + 1) pulse output circuit 20_k + 1. explain.

In the period t1 and the period t2, the operation of the (k + 1) th pulse output circuit 20_k + 1 is the same as that of the first pulse output circuit 20_1 described above. Therefore, the above description will be used here.

In the period t3, the signal input to each terminal does not change from the period t2. Therefore, the signals output from the terminals 25 and 27 do not change, and both output low-level potentials (low power potential (Vss)).

In the period t4, a high level potential (high power potential (Vdd)) is input to the terminals 22 and 24. The potential of the node A (the potential of the source of the transistor 31) has risen to a high level potential (the potential lowered by the threshold voltage of the transistor 31 from the high power supply potential (Vdd)) in the period t1. Therefore, the transistor 31 is in the off state in the period t1. Here, when a high level potential (high power supply potential (Vdd)) is input to the terminals 22 and 24, the potential of the node A is formed by the capacitive coupling between the source and the gate of the transistor 33 and the source and the gate of the transistor 38. (The potential of the gates of transistors 33 and 38) rises further (bootstrap operation). Further, by performing the bootstrap operation, the signal output from the terminal 25 and the terminal 27 does not drop from the high level potential (high power supply potential (Vdd)) input to the terminal 22 and the terminal 24. Therefore, in the period t4, the (k + 1) th pulse output circuit 20_k + 1 has a scan line arranged on the k + 1 line in the pixel portion and the (k + 2) th pulse output circuit 20_k + 2. A high level potential (high power supply potential (Vdd) = selection signal, shift pulse) is output to the terminal 21 of.

In the period t5, the signal input to each terminal does not change from the period t4. Therefore, the signals output from the terminals 25 and 27 do not change, and a high level potential (high power supply potential (Vdd) = selection signal, shift pulse) is output.

In the period t6, a low level potential (low power potential (Vss)) is input to the terminal 24. Here, the transistor 38 remains on. Therefore, in the period t6, the signal output from the (k + 1) pulse output circuit 20_k + 1 to the scan line arranged on the k + 1 line in the pixel portion has a low level potential (low power supply). Potential (Vss)).

In the period t7, a high level potential (high power potential (Vdd)) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises to a high level potential (a potential lowered by the threshold voltage of the transistor 37 from the high power supply potential (Vdd)). That is, the transistors 32, 34, and 39 are turned on. Along with this, the potential of node A drops to a low level potential (low power supply potential (Vss)). That is, the transistors 33 and 38 are turned off. As a result, in the period t7, the signals output from the terminals 25 and 27 both have a low power supply potential (Vss). That is, in the period t7, the (k + 1) th pulse output circuit 20_k + 1 is arranged at the terminal 21 of the (k + 2) th pulse output circuit 20_2 and the k + 1 line in the pixel portion. Outputs low power potential (Vss) to the scanning line.

Next, with reference to FIG. 3 (D), a case where a high-level potential is input as a shift pulse from the second k pulse output circuit 20_2k to the terminal 21 of the second (2k + 1) pulse output circuit 20_2k + 1. explain.

In the period t1 to t3, the operation of the (2k + 1) th pulse output circuit 20_2k + 1 is the same as that of the above-mentioned (k + 1) th pulse output circuit 20_k + 1. Therefore, the above description will be used here.

At period t4, a high level potential (high power potential (Vdd)) is input to terminal 22. The potential of the node A (the potential of the source of the transistor 31) has risen to a high level potential (the potential lowered by the threshold voltage of the transistor 31 from the high power supply potential (Vdd)) in the period t1. Therefore, the transistor 31 is in the off state in the period t1. Here, when a high level potential (high power supply potential (Vdd)) is input to the terminal 22, the potential of node A (potential of the gate of the transistor 33) is further increased by the capacitive coupling between the source and the gate of the transistor 33. Ascend (bootstrap operation). Further, by performing the bootstrap operation, the signal output from the terminal 27 does not drop from the high level potential (high power supply potential (Vdd)) input to the terminal 22. Therefore, in the period t4, the second (2k + 1) pulse output circuit 20_k + 1 has a high level potential (high power supply potential (Vdd) =) at the terminal 21 of the second (2k + 2) pulse output circuit 20_k + 2. Shift pulse) is output. Although it is not directly related to the output signal of the pulse output circuit in the period t4, the transistor 35 is turned off because the low level potential (low power supply potential (Vss)) is input to the terminal 21.

In the period t5, a high level potential (high power potential (Vdd)) is input to the terminal 24. Here, since the potential of node A is increased by the bootstrap operation, the signal output from the terminal 25 may decrease from the high level potential (high power supply potential (Vdd)) input to the terminal 24. Absent. Therefore, in the period t5, the high level potential (high power supply potential (Vdd)) input to the terminal 22 is output from the terminal 25. That is, the (2k + 1) th pulse output circuit 20_1 outputs a high level potential (high power supply potential (Vdd) = selection signal) to the scanning line arranged on the 2k + 1th line in the pixel portion. Further, in the period t5, the signal input to the terminal 22 maintains a high level potential (high power supply potential (Vdd)), so that the first (2k + 1) pulse output circuit 20_2k + 1 to the second (2k + 2) The signal output to the terminal 21 of the pulse output circuit 20_2k + 2 of) remains at a high level potential (high power supply potential (Vdd) = shift pulse).

In the period t6, the signal input to each terminal does not change from the period t5. Therefore, the signals output from the terminals 25 and 27 do not change, and both output high-level potentials (high power supply potential (Vdd) = selection signal, shift pulse).

In the period t7, a high level potential (high power potential (Vdd)) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises to a high level potential (a potential lowered by the threshold voltage of the transistor 37 from the high power supply potential (Vdd)). That is, the transistors 32, 34, and 39 are turned on. Along with this, the potential of node A drops to a low level potential (low power supply potential (Vss)). That is, the transistors 33 and 38 are turned off. As a result, in the period t7, the signals output from the terminals 25 and 27 both have a low power supply potential (Vss). That is, in the period t7, the (k + 1) th pulse output circuit 20_k + 1 is arranged at the terminal 21 of the (k + 2) th pulse output circuit 20_2 and the k + 1 line in the pixel portion. Outputs low power potential (Vss) to the scanning line.

As shown in FIGS. 3B to 3D, in the first pulse output circuit 20_1 to the mth pulse output circuit 20_m, the input timing of the start pulse (GSP) for the scanning line drive circuit is controlled by controlling the input timing. It is possible to shift a plurality of shift pulses in parallel. Specifically, after inputting the start pulse (GSP) for the scan line drive circuit, the start pulse for the scan line drive circuit (GSP) is again performed at the same timing as the shift pulse is output from the terminal 27 of the kth pulse output circuit 20_k. By inputting GSP), it is possible to output a shift pulse from the first pulse output circuit 20_1 and the first (k + 1) pulse output circuit 20_k + 1 at the same timing. Similarly, by inputting the start pulse (GSP) for the scanning line drive circuit, the first pulse output circuit 20_1, the (k + 1) th pulse output circuit 20_k + 1, and the (2k + 1) th pulse output circuit 20_1 It is possible to output a shift pulse from the pulse output circuit 20_2k + 1 at the same timing.

In addition, the first pulse output circuit 20_1, the first (k + 1) pulse output circuit 20_k + 1, and the first (2k + 1) pulse output circuit 20_2k + 1 are respectively parallel to the above operation. It is possible to supply the selection signal to the scanning line at different timings. That is, in the scan line drive circuit described above, a plurality of shift pulses having a unique shift period are shifted, and a plurality of pulse output circuits to which shift pulses are input at the same timing transmit selection signals to the scan line at different timings. It is possible to supply.

&lt;Configuration example of signal line drive circuit 12&gt; FIG. 4A is a diagram showing a configuration example of a signal line drive circuit 12 included in the liquid crystal display device shown in FIG. 1A. In the signal line drive circuit 12 shown in FIG. 4 (A), a shift register 120 having a first output terminal to an nth output terminal, a wiring for supplying an image signal (DATA), and one of a source and a drain are images. It is electrically connected to the wiring that supplies the signal (DATA), the other of the source and drain is electrically connected to the signal line 14_1 arranged in the first row in the pixel section, and the gate is the first shift register 120. The transistor 121_1 electrically connected to the output terminal of the above, or one of the source and drain is electrically connected to the wiring that supplies the image signal (DATA), and the other of the source and drain is in the nth column in the pixel section. It has a transistor 121_n, which is electrically connected to the arranged signal line 14_n and whose gate is electrically connected to the nth output terminal of the shift register 120. The shift register 120 has a function of sequentially outputting a high-level potential from the first output terminal to the nth output terminal for each shift period, triggered by a signal line drive circuit start pulse (SSP). That is, the transistors 121_1 to 121_n are sequentially turned on for each shift period.

FIG. 4B is a diagram showing an example of the timing of the image signal supplied by the wiring that supplies the image signal (DATA). As shown in FIG. 4 (B), the wiring that supplies the image signal (DATA) supplies the image signal (data 1) for pixels arranged in the first line in the period t4, and k in the period t5. The pixel image signal (data k + 1) arranged on the +1st line is supplied, and the pixel image signal (data 2k + 1) arranged on the 2k + 1th line is supplied in the period t6. , Image signal for pixels (data) arranged in the second line in period t7 2) supply. Hereinafter, similarly, the wiring for supplying the image signal (DATA) sequentially supplies the image signals for pixels arranged for each specific row. Specifically, the pixel image signal arranged on the sth line (s is a natural number less than k) the pixel image signal arranged on the k + s line arranged on the 2k + s line. The image signal for the pixel is supplied in the order of the image signal for the pixel arranged the image signal for the pixel arranged on the s + 1 line. When the scan line drive circuit and the signal line drive circuit described above perform the operation, the input of the image signal to the three rows of pixels arranged in the pixel portion for each shift period in the pulse output circuit of the scan line drive circuit is input. It is possible to do.

&lt;Configuration example of backlight and backlight drive circuit&gt; FIG. 5 is a diagram showing a configuration example of a backlight panel 40 provided behind the pixel portion 10 of the liquid crystal display device shown in FIG. 1 (A). The backlight panel 40 shown in FIG. 5 (A) includes a plurality of backlight arrays 41 arranged side by side in the column direction, and each backlight array 41 has 3 of red (R), green (G), and blue (B). A plurality of backlight units 42 including a light source exhibiting color are provided side by side. The plurality of backlight units 42 may be arranged in a matrix, for example, behind the pixel unit 10 as long as the lighting can be controlled for each specific area.

As the light source used for the backlight unit 42, a light emitting element such as an LED (Light-Emitting Diode) or an OLED (Organic Light-Emitting Diode) having high luminous efficiency is suitable.

FIG. 5B shows the positional relationship between the plurality of pixels 15 arranged in m rows and n columns (not shown) and the backlight panel 40 provided behind them. The backlight panel is provided with a backlight array 41 at least every t rows (here, t is k / 4), and each backlight array 41 is arranged in t rows and n columns. Illuminates the pixel 15 of the above substantially uniformly. The arrangement of the backlight units 42 included in the backlight array 41 is not particularly limited, and any arrangement may be used as long as the plurality of pixels 15 arranged in t rows and n columns can be illuminated substantially uniformly. ..

The backlight array 41 can be turned on independently. That is, the backlight panel 40 is the backlight array 41a for at least the first row to the t-th row.₁~ 2k + 3t + 1 Backlight array for lines 1 to m 41c₄It is assumed that each backlight array can be turned on independently. Furthermore, in each backlight array, the light sources exhibiting the three colors of red (R), green (G), and blue (B) can be turned on independently. That is, in any one of the backlight arrays 41, by turning on a light source exhibiting any one of red (R), green (G), and blue (B), the specific region of the pixel portion 10 is covered. It is possible to irradiate light that exhibits red (R), green (G), or blue (B).

By turning on a light source that exhibits any two colors of red (R), green (G), and blue (B), the pixel portion 10 exhibits a chromatic color formed by a mixture of the two lights. White formed by mixing three lights with respect to the pixel portion 10 by irradiating light and turning on all light sources exhibiting red (R), green (G), and blue (B) colors. It may be configured so that it can irradiate light exhibiting (W).

When a light emitting element such as an LED or an OLED is used as a light source in the backlight unit 42, the luminous efficiency of the light emitting element changes depending on the input power. In the present embodiment, a method is used in which a light emitting element such as an LED or an OLED supplies electric power that emits light with high efficiency in a pulsed manner, and controls the duty ratio to adjust the light emission intensity. By this method, it is possible to drive under optimum conditions without impairing the luminous efficiency of light emitting elements such as LEDs and OLEDs, and power consumption can be reduced.

Further, since the temperature rise of the light emitting element can be suppressed by the method of driving the backlight unit 42 with pulsed electric power, the temperature of the light emitting element such as LED or OLED rises by the method of continuously supplying electric power, and the light is emitted. The problem of reduced efficiency can be avoided.

FIG. 16 shows an example of a configuration in which the backlight panel 40 is driven by using a pulse width modulation (PWM) circuit. The backlight drive circuit 45 includes three pulse width modulation circuits (46a, 46b, 46c), and each pulse width modulation circuit supplies power to the four backlight arrays 41 to control their emission color and emission intensity. It is configured to do. When the pulse width modulation circuit is used, the electric power emitted by the light emitting element with high efficiency can be supplied to the backlight panel 40 in a pulsed manner. The emission intensity may be controlled by changing the duty ratio. For example, LEDs can respond to input signals at high speed, so they can be driven at ultra-high frequencies (eg, 1 GHz). For example, it is possible to supply and drive 10 pulses to the LED during the period of 1 pulse signal for driving the liquid crystal element.

The means for controlling the emission intensity can be appropriately selected and used according to the type of the light source used for the backlight unit 42.

&lt;Example of image processing circuit configuration&gt; An example of a configuration in which the video signal V (data) input to the liquid crystal display device is output to the liquid crystal panel 19 and the backlight panel 40 via the image processing circuit 70 will be described with reference to FIG.

The image processing circuit 70 includes an AD converter 71 that converts a video signal V (data) into a digital signal, a frame memory 72 that stores at least one screen image included in the video signal, a maximum value detection circuit 73, and gamma. A correction circuit 74 is provided. The maximum value detection circuit 73 analyzes the brightness of each specific color included in a specific area of the display image and detects the maximum value of the gradation. The gamma correction circuit 74 is a circuit that performs gamma correction so that the liquid crystal element has the maximum transmittance at the maximum value of the detected gradation and the transmittance of the pixel is reduced according to the rate at which the gradation becomes dark. By using a backlight whose brightness is adjusted according to the maximum value of the gradation detected by the maximum value detection circuit 73 for the gamma-corrected liquid crystal element, display corresponding to the image data becomes possible. Each pixel 15 included in the liquid crystal panel 19 is driven by using image data corrected for each specific region by the gamma correction circuit 74.

Further, the image processing circuit 70 is connected to the backlight panel 40 via the backlight drive circuit 45.

The image processing circuit 70 applies the video signal V (data) to the first region (1st to kth rows), the second region (k + 1st to 2kth rows), and the third region (k + 1th to 2kth rows). 2k + 1st line to mth line), and a case where image data is output for each area of the liquid crystal panel 19 and a control signal is output to the backlight panel 40 will be described. The division position of the video signal V (data) is indicated by using the number of rows of pixels in which the video signal V (data) added in parentheses () of each area is displayed.

The maximum value detection circuit 73 includes a first maximum value detection circuit 73a that detects the maximum value of each color of the image data displayed in the first region (lines 1 to k), and a second region (k). The second maximum value detection circuit 73b that detects the maximum value of each color of the image data displayed in the + 1st line to the 2k line) and the third area (2k + 1st line to the mth line) are displayed. A third maximum value detection circuit 73c for detecting the maximum value of each color of the image data to be generated is provided. Further, the gamma correction circuit 74 includes a first gamma correction circuit 74a that gamma-corrects the image data displayed in the first region (1st line to kth line) and a second area (k + 1th line to k + 1th line). The second gamma correction circuit 74b that gamma-corrects the image data displayed in the 2k line) and the third gamma-correcting the image data displayed in the third area (2k + 1th line to mth line). The gamma correction circuit 74c is provided.

The input video signal V (data) is converted into digital image data by the AD converter 71 and stored in the frame memory 72. Next, the first maximum value detection circuit 73a, the second maximum value detection circuit 73b, and the third maximum value detection circuit 73c each detect the maximum value of each color of the image data to be displayed in a specific area. Then, each maximum value detection circuit outputs the maximum value of the detected gradation to the gamma correction circuit and the pulse width modulation circuit in the corresponding region.

For example, from the red (R) image data displayed by the first maximum value detection circuit 73a in the first to t lines of the first region (first to kth lines), the total gradation width is When the gradation 128 in 256 steps is detected as the brightest gradation, the first maximum value detection circuit 73a transfers the value 128 to the first gamma correction circuit 74a and the first pulse width modulation circuit 46a. Output.

In the first gamma correction circuit 74a, the transmittance of the liquid crystal element provided in the pixel in which the gradation 128 is detected is maximized, and the transmittance decreases as the gradation becomes darker, so that the first region (first line) The image data on the 1st to tth lines of (to kth line) is gamma-corrected and output.

On the other hand, in the first pulse width modulation circuit 46a of the backlight drive circuit 45, the pixels equipped with the liquid crystal element having the maximum transmittance are lit with a brightness that expresses the gradation 128 of the red (R) color. Backlight array 41a with modulated pulse width₁Turns on the red light source provided in the liquid crystal panel 19 and illuminates the first to kth rows of the first region (1st to kth rows) of the liquid crystal panel 19.

In this way, pixels having a red (R) color gradation of 128 can be displayed in the first to t rows of the first region (first to kth rows). Since the transmittance of the liquid crystal element is the maximum in the red (R) color gradation 128 pixels, the backlight array 41a₁It is possible to suppress the waste of energy generated by. Further, the first maximum value detection circuit 73a detects the maximum luminance from the limited range of the first row to the tth row of the first region (first row to kth row). Therefore, the backlight array 41a even when gradations higher than gradation 128 are detected in other areas of the full screen.₁The emission intensity of the light can be suppressed, and thus the power consumption can be reduced.

As in the above method, the second maximum value detection circuit 73b is displayed in blue (B) on the k + 1 to k + t lines of the second region (k + 1 to 2k lines). ) The color image data is analyzed, and the third maximum value detection circuit 73c displays green (G) in the 2k + 1st line to the 2k + t line in the third region (2k + 1st line to mth line). ) Analyze the color image data. Then, each outputs the analysis result to the gamma correction circuit in a specific region of the liquid crystal panel 19 and the pulse width modulation circuit in a specific region of the backlight drive circuit 45. As a result, the emission intensity of the backlight array can be optimized in each region, and the power consumption can be reduced.

&lt;Operation example of liquid crystal display device&gt; FIG. 6 shows the scanning of the selection signal in the liquid crystal display device described above and the backlight array 41a for the first to t-th rows of the backlight.₁~ 2k + 3t + 1 Backlight array for lines 1 to m 41c₄It is a figure which shows the lighting timing of. In FIG. 6, the vertical axis represents the rows (1st to mth rows) in the pixel portion, and the horizontal axis represents time. As shown in FIG. 6, in the liquid crystal display device, the selection signal is not sequentially supplied to the scanning lines arranged in the first line to the scanning line arranged in the mth line, but is separated by k lines. The selection signal is sequentially supplied to the scan lines arranged in the order (scan line arranged in the first line scan line arranged in the k + 1 line arranged in the 2k + 1 line). It is possible to supply the selection signal in the order of the scan line arranged the scan line arranged on the second line). Therefore, in the period (T1), n pixels arranged in the first row are sequentially selected from n pixels arranged in the tth row, and n arranged in the k + 1th row. N pixels arranged on the k + t line from the pixels are sequentially selected, and n arranged on the 2k + t line from the n pixels arranged on the 2k + 1 line. By sequentially selecting the pixels, it is possible to input an image signal to each pixel. Here, an image signal for controlling the transmission of light exhibiting red (R) is input to the n pixels arranged in the first line to the n pixels arranged in the t line. , An image signal that controls the transmission of light exhibiting blue (B) is input to the n pixels arranged on the k + 1 line to the n pixels arranged on the k + t line. , An image signal that controls the transmission of light exhibiting green (G) is input to the n pixels arranged on the 2k + 1th line to the n pixels arranged on the 2k + t line. I will do it.

Further, as shown in FIG. 6, in the liquid crystal display device, the backlight array is turned on during the period between the input of the image signal in a specific area. Specifically, in the period between the period T1 and the period T2, the backlight array 41a for the first to t rows₁In, the red (R) light source is turned on, and the backlight array 41b for the k + 1 to k + t lines₁In, the blue (B) light source is turned on, and the backlight array 41c for the 2k + 1st line to the 2k + tth line is turned on.₁Turn on the green (G) light source. In the liquid crystal display device, the pixels are formed by the operation from the input of the image signal for controlling the transmission of the light exhibiting red (R) to the lighting of the blue (B) light source in the backlight array as shown in FIG. It is assumed that one image is formed in the part.

Backlight array 41a for rows 1 to t in the interval between periods T1 and T2₁Since the method of turning on the red (R) light source of No. 1 has already been described in &lt;Example of configuration of image processing circuit&gt;, it will not be repeatedly described here.

Next, the details of how the pulse width modulation circuit drives a plurality of backlight arrays will be described with reference to FIGS. 5, 6 and 16 by taking the operation of the first pulse width modulation circuit 46a in the period T1 as an example. To do. Backlight array 41a in the first pulse width modulation circuit 46a₁To backlight array 41a₄4 backlight arrays are connected. In the present embodiment, the first region (1st to kth rows) is divided into four, and the backlight array 41a₁Use the backlight array 41a to change the first to t lines.₂To the t + 1st line to the 2t line using, the backlight array 41a₃2t + 1st line to 3t line, and backlight array 41a using₄Is used to illuminate the 3t + 1th to kth lines.

Backlight array 41a in period T1₁Is turned off, and image data is written to the pixels provided in the first to t lines. Backlight array 41a₂Illuminates the pixels provided in the t + 1 to 2t rows, and the backlight array 41a₃Illuminates the pixels provided in the 2t + 1st row to the 3tth row, and the backlight array 41a₄Illuminates the pixels provided in the 3t + 1st line to the kth line. The first pulse width modulation circuit 46a distributes the period T1 to three backlight arrays and drives them. Therefore, the duty ratio that each backlight array can turn on is up to 1/3.

By driving in such a manner, the number of pulse width modulation circuits used in the liquid crystal display device illustrated in the present embodiment can be reduced.

&lt;About the liquid crystal display device disclosed in this embodiment&gt; The liquid crystal display device of the present embodiment can input an image signal and turn on the backlight in parallel. Therefore, it is possible to improve the input frequency of the image signal for each pixel of the liquid crystal display device. As a result, it is possible to suppress a color break that occurs in a liquid crystal display device that displays by a field sequential method and improve the image quality displayed by the liquid crystal display device.

Further, the liquid crystal display device disclosed in the present embodiment can realize the above operation with a simple pixel configuration. Specifically, the pixels of the liquid crystal display device disclosed in Patent Document 1 require a transistor for controlling the movement of electric charges in addition to the pixel configuration of the liquid crystal display device disclosed in the present embodiment. .. In addition, a signal line for controlling the switching of the transistor is also required separately. On the other hand, the pixel configuration of the liquid crystal display device of the present embodiment is simple. That is, the liquid crystal display device of the present embodiment can improve the aperture ratio of the pixels as compared with the liquid crystal display device disclosed in Patent Document 1. Further, by reducing the number of wirings extending to the pixel portion, it is possible to reduce the parasitic capacitance generated between various wirings. That is, high-speed driving of various wirings extending to the pixel portion becomes possible.

Further, when the backlight is turned on as in the operation example shown in FIG. 6, the adjacent backlight units do not exhibit different colors. Specifically, when the backlight is turned on after the writing in the area where the image signal is input in the period T1, the adjacent backlight units do not exhibit different colors. For example, in the period T1, the transmission of light exhibiting blue (B) is controlled from the n pixels arranged on the k + 1 line to the n pixels arranged on the k + t line. When the blue (B) light source is turned on in the backlight unit for the k + 1st line to the k + t line after the input of the image signal for the purpose is completed, the backlight for the 3t + 1st line to the kth line In the unit and the backlight unit for the k + t + 1 to k + 2t lines, the blue (B) light source is turned on or not turned on (red (R), green (G)). Will not be lit). Therefore, it is possible to reduce the probability that light having a color different from the specific color is transmitted through the pixels into which the image information of the specific color is input.

&lt;Modification example&gt; The liquid crystal display device of the present embodiment is one aspect of the present invention, and the present invention also includes a liquid crystal display device having a difference from the liquid crystal display device.

For example, in the liquid crystal display device of the present embodiment, the configuration in which the pixel unit 10 is divided into three regions and an image signal is supplied in parallel to the three regions has been shown. , Not limited to the configuration. That is, in the liquid crystal display device of the present invention, the pixel unit 10 can be divided into a plurality of regions other than three, and an image signal can be supplied in parallel to the plurality of regions. It should be noted that when the number of the regions is changed, it is necessary to set the clock signal for the scanning line drive circuit and the pulse width control signal according to the number of regions.

Further, in the liquid crystal display device of the present embodiment, a configuration in which a capacitive element for holding the voltage applied to the liquid crystal element is provided (see FIG. 1 (B)) is shown, but the capacitive element is not provided. It is also possible to configure it. In this case, it is possible to improve the aperture ratio of the pixels. Further, since the capacitance wiring extending to the pixel portion can be deleted, various wirings extending to the pixel portion can be driven at high speed.

Further, as a pulse output circuit, one of the source and the drain is electrically connected to the high power supply potential line, and the other of the source and the drain is the gate of the transistor 32 and the transistor 34 in the pulse output circuit shown in FIG. Electrically connected to the gate of the transistor 35, the other of the source and drain of the transistor 36, the other of the source and drain of the transistor 36, the other of the source and drain of the transistor 37, and the gate of the transistor 39, and the gate to the reset terminal (Reset). It is possible to apply a configuration in which an electrically connected transistor 50 is added (see FIG. 7 (A)). A high-level potential is input to the reset terminal during the period after one image is formed in the pixel portion, and a low-level potential is input during the other period. The transistor 50 is a transistor that is turned on when a high-level potential is input. As a result, the potential of each node can be initialized, so that malfunction can be prevented. It should be noted that when the initialization is performed, it is necessary to provide an initialization period after a period in which one image is formed in the pixel portion. Further, as will be described later with reference to FIG. 9, when a period for turning off the backlight is provided after the period for forming one image in the pixel portion, the initialization can be performed during the period for turning off the backlight.

Further, as a pulse output circuit, one of the source and drain is electrically connected to the other of the source and drain of the transistor 31 and the other of the source and drain of the transistor 32 to the pulse output circuit shown in FIG. 3 (A). The other of the source and drain is electrically connected to the gate of transistor 33 and the gate of transistor 38, and the gate is added with transistor 51 electrically connected to the high power supply potential line (see FIG. 7 (B)). It is also possible to apply. The transistor 51 is turned off during the period (period t1 to period t6 shown in FIGS. 3B to 3D) when the potential of the node A becomes a high-level potential. Therefore, by adding the transistor 51, the electricity between the gate of the transistor 33 and the gate of the transistor 38 and the other of the source and drain of the transistor 31 and the other of the source and drain of the transistor 32 during the period t1 to t6. Connection can be cut off. As a result, it is possible to reduce the load during the bootstrap operation performed in the pulse output circuit during the period included in the period t1 to the period t6.

Further, as a pulse output circuit, one of the source and drain is electrically connected to the gate of the transistor 33 and the other of the source and drain of the transistor 51 to the pulse output circuit shown in FIG. 7 (B), and the source and drain are connected. It is also possible to apply a configuration in which the other is electrically connected to the gate of the transistor 38 and the gate is added to the transistor 52 electrically connected to the high power potential line (see FIG. 8 (A)). By providing the transistor 52 as described above, it is possible to reduce the load during the bootstrap operation performed in the pulse output circuit. In particular, when the pulse output circuit raises the potential of the node A only by capacitive coupling between the source and the gate of the transistor 33 (see FIG. 3D), the effect of reducing the load is large.

Further, as the pulse output circuit, the transistor 51 is deleted from the pulse output circuit shown in FIG. 8 (A), and one of the source and drain is the other of the source and drain of the transistor 31, and the other of the source and drain of the transistor 32. Also added is transistor 53, which is electrically connected to one of the source and drain of transistor 52, the other of the source and drain is electrically connected to the gate of transistor 33, and the gate is electrically connected to the high power potential line. It is also possible to apply the above configuration (see Fig. 8 (B)). By providing the transistor 53 as described above, it is possible to reduce the load during the bootstrap operation performed in the pulse output circuit. Further, it is possible to reduce the influence of the irregular pulse generated in the pulse output circuit on the switching of the transistors 33 and 38.

Further, in the liquid crystal display device of the present embodiment, light sources exhibiting three colors of red (R), green (G), and blue (B) are arranged horizontally in a straight line as a backlight unit (see FIG. 5). However, the configuration of the backlight unit is not limited to the configuration. For example, the light sources exhibiting the three colors may be arranged in three corners, the light sources exhibiting the three colors may be arranged vertically in a straight line, a red (R) backlight unit, and a green (G) backlight. A light unit and a blue (B) backlight unit may be provided separately. Further, in the liquid crystal display device described above, the configuration in which the direct type backlight is applied as the backlight (see FIG. 5) is shown, but it is also possible to apply the edge light type backlight as the backlight. is there.

Further, in the liquid crystal display device of the present embodiment, a configuration in which the selection signal is continuously scanned and the backlight unit is turned on (see FIG. 6) is shown, but the operation of the liquid crystal display device is limited to this configuration. Not done. For example, during the period of forming one image in the pixel section (in FIG. 6, the input of the image signal for controlling the transmission of the light exhibiting red (R) ~ the blue (B) light source is turned on in the backlight unit. It is possible to provide a period during which the selection signal is not scanned and the backlight unit is not turned on before and after (corresponding to the period) (see FIG. 9). As a result, it is possible to suppress a color break that occurs in the liquid crystal display device and improve the image quality displayed by the liquid crystal display device. Note that FIG. 9 illustrates a configuration in which neither scanning of the selection signal nor lighting of the backlight unit is performed, but an image signal for scanning the selection signal and not transmitting light to each pixel is used. It is also possible to have a configuration for inputting.

Further, in the liquid crystal display device of the present embodiment, a configuration in which one of the three light sources of the backlight unit is turned on for each specific area of the pixel portion is provided (see FIG. 6). It is also possible to provide a period in which one or all of the three light sources of the light unit are turned on (see FIG. 10). In this case, it is possible to further improve the display brightness of the liquid crystal display device and further subdivide the display color tone. In the operation example shown in FIG. 10, the input of the image signal for controlling the transmission of the light exhibiting red (R) to the red (R) light source, the green (G) light source, and the blue in the backlight unit. It is assumed that one image is formed in the pixel portion by the operation until the light source of (B) is turned on.

Further, in the liquid crystal display device of the present embodiment, one image is obtained by lighting the backlight unit in the order of red (R) green (G) blue (B) for each specific area of the pixel portion. Although the configuration (see FIG. 6) for forming the above is shown, the lighting order of the light sources in the liquid crystal display device of the present embodiment is not limited to that order. For example, it lights in the order of blue (B) blue (B) and green (G) green (G) green (G) and red (R) red (R) red (R) and blue (B). By doing so, one image is formed (see Fig. 11), blue (B) blue (B) and red (R) red (R) red (R) and green (G) green (G). ) Green (G) and Blue (B) to form one image (see Fig. 12), Blue (B) Red (R) and Green (G) Green (G) ) Blue (B) and Red (R) Red (R) Green (G) and Blue (B) to form one image by lighting in this order (see Fig. 13), Blue (B) ) Red (R) and Green (G) Blue (B) and Green (G) Red (R) Green (G) Red (R) and Blue (B) It is also possible to form a configuration (see FIG. 14) that forms the image of. Needless to say, it is necessary to appropriately design the input order of the image signals for controlling the transmission of the light exhibiting a specific color according to the lighting order of the light source.

Further, in the liquid crystal display device of the present embodiment, one image is formed by turning on each of the red (R), green (G), and blue (B) light sources of the backlight unit once. Although the configuration (see FIG. 6) is shown, it is also possible to make the number of times of lighting different for each light source in the liquid crystal display device of the present embodiment. For example, by turning on the backlight unit so that the light exhibiting red (R) and green (G) having high luminosity factor is lit twice and the blue (B) having low luminosity factor is lit three times. It is also possible to form a single image (see FIG. 15). In the operation example shown in FIG. 15, the operation from the input of the image signal for controlling the transmission of the light exhibiting red (R) to the lighting of the green (G) and blue (B) light sources in the backlight unit. It is assumed that one image is formed in the pixel portion.

Further, in the liquid crystal display device of the present embodiment, a configuration in which a combination of three color light sources of red (R), green (G), and blue (B) is used as a backlight is shown, but the liquid crystal display of the present invention has been described. The device is not limited to the configuration. That is, in the liquid crystal display device of the present invention, it is possible to form a backlight by combining light sources exhibiting arbitrary colors. For example, a combination of four color light sources: red (R), green (G), blue (B), white (W), or red (R), green (G), blue (B), and yellow (Y). It can be used, or a combination of three color light sources of cyan (C), magenta (M), and yellow (Y) can be used. When the backlight unit has a light source that emits light exhibiting white (W), the light exhibiting white (W) is not formed by mixing colors, but the light exhibiting white (W) using the light source. Can be formed. Since the light source has high luminous efficiency, it is possible to reduce power consumption by constructing a backlight using the light source. In addition, when the backlight unit has two light sources having a complementary color relationship (for example, when it has two light sources of blue (B) and yellow (Y)), the light exhibiting the two colors should be mixed. It is also possible to form a light that exhibits white (W). In addition, use a combination of six light sources, light red (R), green (G), and blue (B), and dark red (R), green (G), and blue (B). Alternatively, it is also possible to use a combination of six color light sources of red (R), green (G), blue (B), cyan (C), magenta (M), and yellow (Y). In this way, by using a wider variety of light sources in combination, it is possible to expand the color gamut that can be expressed by the liquid crystal display device and improve the image quality.

A liquid crystal display that sequentially inputs an image signal and turns on the backlight for each specific area of the pixel portion, instead of sequentially inputting an image signal and turning on the backlight as illustrated in the present embodiment. The device can improve the input frequency of the image signal for each pixel of the liquid crystal display device. As a result, it is possible to suppress display deterioration such as color breaks that occur in the liquid crystal display device and improve the image quality. In addition, by detecting the brightest gradation image signal included in the image signal for each specific region of the pixel portion, it is possible to finely control the emission intensity of the backlight light source. As a result, the power consumption of the liquid crystal display device can be effectively reduced.

It is also possible to apply a plurality of configurations described as a modification of the present embodiment to the liquid crystal display device of the present embodiment.

It is also possible to combine the content of this embodiment or a part of the content with the content of another embodiment or a part of the content.

(Embodiment 2) In the present embodiment, a specific configuration of the liquid crystal display device shown in the first embodiment will be described.

&lt;Specific example of transistor&gt; First, a specific example of the transistor used in the pixel portion of the liquid crystal display device or various circuits described above will be described with reference to FIG. In the liquid crystal display device, transistors having the same configuration may be applied to the transistors provided in the pixel unit and each of the various circuits, or transistors having different configurations may be applied.

In the transistor 2450 shown in FIG. 17 (A), the gate layer 2401 is formed on the substrate 2400, the gate insulating layer 2402 is formed on the gate layer 2401, the semiconductor layer 2403 is formed on the gate insulating layer 2402, and the semiconductor layer is formed. A source layer 2405a and a drain layer 2405b are formed on the 2403. Further, an insulating layer 2407 is formed on the semiconductor layer 2403, the source layer 2405a, and the drain layer 2405b. Further, the protective insulating layer 2409 may be formed on the insulating layer 2407. The transistor 2450 is one of the bottom gate structure transistors and one of the reverse stagger type transistors.

In the transistor 2460 shown in FIG. 17 (B), the gate layer 2401 is formed on the substrate 2400, the gate insulating layer 2402 is formed on the gate layer 2401, the semiconductor layer 2403 is formed on the gate insulating layer 2402, and the semiconductor layer is formed. The channel protection layer 2406 is formed on the 2403, and the source layer 2405a and the drain layer 2405b are formed on the channel protection layer 2406 and the semiconductor layer 2403. Further, the protective insulating layer 2409 may be formed on the source layer 2405a and the drain layer 2405b. The transistor 2460 is one of the bottom gate structure transistors called the channel protection type (also called the channel stop type), and is also one of the reverse stagger type transistors.

In the transistor 2470 shown in FIG. 17 (C), the base layer 2436 is formed on the substrate 2400, the semiconductor layer 2403 is formed on the base layer 2436, and the source layer 2405a and the source layer 2405a are formed on the semiconductor layer 2403 and the base layer 2436. The drain layer 2405b is formed, the gate insulating layer 2402 is formed on the semiconductor layer 2403, the source layer 2405a, and the drain layer 2405b, and the gate layer 2401 is formed on the gate insulating layer 2402. Further, the protective insulating layer 2409 may be formed on the gate layer 2401. The transistor 2470 is one of the transistors having a top gate structure.

In the transistor 2480 shown in FIG. 17 (D), the first gate layer 2411 is formed on the substrate 2400, the first gate insulating layer 2413 is formed on the first gate layer 2411, and the first gate insulating layer is formed. The semiconductor layer 2403 is formed on the layer 2413, and the source layer 2405a and the drain layer 2405b are formed on the semiconductor layer 2403 and the first gate insulating layer 2413. Further, a second gate insulating layer 2414 is formed on the semiconductor layer 2403, the source layer 2405a, and the drain layer 2405b, and a second gate layer 2412 is formed on the second gate insulating layer 2414. Further, the protective insulating layer 2409 may be formed on the second gate layer 2412.

The transistor 2480 has a structure in which the transistor 2450 and the transistor 2470 are combined. The first gate layer 2411 and the second gate layer 2412 can be electrically connected to function as one gate layer. Further, one of the first gate layer 2411 and the second gate layer 2412 may be simply called a "gate" and the other may be called a "back gate". By changing the potential of the back gate in the transistor 2480, the threshold voltage of the transistor 2480 when switching is controlled by the potential of the gate can be changed.

The substrate 2400 includes a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a conductive substrate having an insulating layer on the surface, a plastic substrate, a laminated film, or a fibrous form. There is a paper containing the material of the above, or a flexible substrate such as a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES), and synthetic resins having flexibility such as acrylic.

The gate layer 2401 and the first gate layer 2411 include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and the like. Elements selected from neodymium (Nd) and scandium (Sc), alloys containing the above-mentioned elements as components, or nitrides containing the above-mentioned elements as components can be applied. It is also possible to apply a laminated structure of these materials.

The gate insulating layer 2402, the first gate insulating layer 2413, and the second gate insulating layer 2414 include insulation of silicon oxide, silicon nitride, silicon oxide nitride, silicon nitride oxide, aluminum oxide, tantalum oxide, gallium oxide, and the like. The body can be applied. It is also possible to apply a laminated structure of these materials. The composition of silicon oxide nitride has a higher oxygen content than that of nitrogen, and the concentration range is 55 to 65 atomic% of oxygen, 1 to 20 atomic% of nitrogen, and 25 to 35 atoms of silicon. %, Hydrogen is contained in an arbitrary concentration in the range of 0.1 to 10 atomic% so as to have a total of 100 atomic%. The silicon nitride film has a higher nitrogen content than oxygen in its composition, and its concentration range is 15 to 30 atomic% for oxygen, 20 to 35 atomic% for nitrogen, and 25 to 35 for Si. In the range of atomic% and hydrogen of 15 to 25 atomic%, each element is contained in an arbitrary concentration so as to have a total of 100 atomic%.

The semiconductor layer 2403 includes a material whose main constituent element is a Group 14 element of the periodic table such as silicon (Si) or germanium (Ge), a compound such as silicon germanium (SiGe) or gallium arsenide (GaAs), and zinc oxide. Semiconductor materials such as oxides such as zinc oxide containing (ZnO) or indium (In) and gallium (Ga), or organic compounds exhibiting semiconductor properties can be applied. Further, a laminated structure of layers made of these semiconductor materials can also be applied.

Further, when silicon (Si) is applied as the semiconductor layer 2403, the crystal state of the semiconductor layer 2403 is not limited. That is, any one of amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon can be applied as the semiconductor layer 2403. The Raman spectrum of microcrystalline silicon is 520 cm, which indicates single crystal silicon.^-1It is shifting to the lower wavenumber side. That is, 520 cm showing single crystal silicon^-1And 480 cm showing amorphous silicon^-1There is a peak in the Raman spectrum of microcrystalline silicon between. It also contains at least 1 atomic% or more of hydrogen or halogen to terminate unbonded hands (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote the lattice strain, stability is increased and a good polycrystalline semiconductor can be obtained.

When an oxide (oxide semiconductor) is applied as the semiconductor layer 2403, it contains at least one or more elements selected from In, Ga, Sn, Zn, Al, Mg, Hf and lanthanoids. For example, In-Sn-Ga-Zn-O metal oxides, which are quaternary metal oxides, In-Ga-Zn-O metal oxides, which are ternary metal oxides, and In-Sn-Zn- O-based metal oxide, In-Al-Zn-O-based metal oxide, Sn-Ga-Zn-O-based metal oxide, Al-Ga-Zn-O-based metal oxide, Sn-Al-Zn-O-based Metal oxides, In-Hf-Zn-O metal oxides, In-La-Zn-O metal oxides, In-Ce-Zn-O metal oxides, In-Pr-Zn-O metal oxides In-Nd-Zn-O-based metal oxides, In-Pm-Zn-O-based metal oxides, In-Sm-Zn-O-based metal oxides, In-Eu-Zn-O-based metal oxides, In-Gd-Zn-O-based metal oxides, In-Tb-Zn-O-based metal oxides, In-Dy-Zn-O-based metal oxides, In-Ho-Zn-O-based metal oxides, In- Er-Zn-O-based metal oxide, In-Tm-Zn-O-based metal oxide, In-Yb-Zn-O-based metal oxide, In-Lu-Zn-O-based metal oxide, binary metal In-Ga-O-based metal oxides, In-Zn-O-based metal oxides, Sn-Zn-O-based metal oxides, Al-Zn-O-based metal oxides, Zn-Mg-O-based oxides Metal oxides, Sn-Mg-O metal oxides, In-Mg-O metal oxides, or unit metal oxides, In-O metal oxides, Sn-O metal oxides, Zn- O-based metal oxides and the like can be used. Further, the oxide semiconductor may contain silicon. Here, for example, the In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn, and the composition ratio thereof is not particularly limited. It may also contain elements other than In, Ga and Zn.

In addition, as an oxide semiconductor, the chemical formula InMO₃(ZnO)_mA thin film represented by (m&gt; 0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn and Co. For example, Ga, Ga and Al, Ga and Mn, or Ga and Co can be selected as M.

The source layer 2405a, drain layer 2405b, and second gate layer 2412 include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and the like. Elements selected from chromium (Cr), neodymium (Nd), scandium (Sc), alloys containing the above-mentioned elements as components, or nitrides containing the above-mentioned elements as components can be applied. It is also possible to apply a laminated structure of these materials.

Further, the conductive film serving as the source layer 2405a and the drain layer 2405b (including the wiring layer formed of the same layers) may be formed of a conductive metal oxide. Indium oxide (In) is a conductive metal oxide.₂O₃), Tin oxide (SnO)₂), Zinc oxide (ZnO), Indium tin oxide (In₂O₃SnO₂, ITO abbreviated), indium tin oxide (In)₂O₃-ZnO) or these metal oxide materials containing silicon oxide can be used.

As the channel protection layer 2406, an insulator such as silicon oxide, silicon nitride, silicon nitride nitride, silicon nitride oxide, aluminum oxide, tantalum oxide, and gallium oxide can be applied. It is also possible to apply a laminated structure of these materials.

Further, as the insulating layer 2407, an insulator such as silicon oxide, silicon oxide nitride, aluminum oxide, aluminum nitride oxide, or gallium oxide can be applied. It is also possible to apply a laminated structure of these materials.

Further, as the protective insulating layer 2409, an insulator such as silicon nitride, aluminum nitride, silicon nitride, or aluminum nitride can be applied. It is also possible to apply a laminated structure of these materials.

Further, as the base layer 2436, an insulator such as silicon oxide, silicon nitride, silicon oxide, silicon oxide, aluminum oxide, tantalum oxide, and gallium oxide can be applied. It is also possible to apply a laminated structure of these materials.

When an oxide semiconductor is applied as the semiconductor layer 2403, the insulating layer in contact with the oxide semiconductor (here, the gate insulating layer 2402, the insulating layer 2407, the channel protection layer 2406, the base layer 2436, and the first gate insulating layer). As 2413 (corresponding to the second gate insulating layer 2414), it is preferable to use an insulating material containing a Group 13 element and oxygen. Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements have good compatibility with oxide semiconductors. By using this as an insulating layer in contact with oxide semiconductors, oxides can be used. The state of the interface with the semiconductor can be kept good.

An insulating material containing a Group 13 element means an insulating material containing one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, gallium aluminum oxide, and aluminum gallium oxide. Here, aluminum gallium oxide means that the content of aluminum (atomic%) is higher than the content of gallium (atomic%), and gallium oxide aluminum oxide has a gallium content (atomic%) of aluminum. Indicates more than the amount (atomic%).

For example, when an insulating layer is formed in contact with a gallium-containing oxide semiconductor layer, the interface characteristics between the oxide semiconductor layer and the insulating layer can be kept good by using a material containing gallium oxide for the insulating layer. .. For example, by providing the oxide semiconductor layer and the insulating layer containing gallium oxide in contact with each other, it is possible to reduce the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer. When an element of the same group as the component element of the oxide semiconductor is used for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has a property of being difficult for water to permeate, it is preferable to use the material from the viewpoint of preventing water from entering the oxide semiconductor layer.

When an oxide semiconductor is applied as the semiconductor layer 2403, the insulating material in contact with the oxide semiconductor has more oxygen than the chemical quantitative composition ratio by heat treatment in an oxygen atmosphere, oxygen doping, or the like. It is preferable to keep it in a state. Oxygen doping refers to the addition of oxygen to the bulk. The term bulk is used for the purpose of clarifying that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. Further, the oxygen doping includes oxygen plasma doping in which plasmaized oxygen is added to the bulk. Further, oxygen doping may be performed by using an ion implantation method or an ion doping method.

For example, when gallium oxide is used as the insulating layer, the composition of gallium oxide is changed by performing heat treatment under an oxygen atmosphere or oxygen doping.₂O_XIt can be (X = 3 + α, 0 &lt;α &lt;1).

When aluminum oxide is used as the insulating layer, the composition of aluminum oxide is changed by heat treatment in an oxygen atmosphere or oxygen doping.₂O_XIt can be (X = 3 + α, 0 &lt;α &lt;1).

When gallium aluminum oxide (gallium aluminum oxide) is used as the insulating layer, the composition of gallium aluminum oxide (gallium aluminum oxide) can be changed by performing heat treatment in an oxygen atmosphere or oxygen doping._XAl_2-XO_{3 + α}It can be (0 &lt;X &lt;2, 0 &lt;α &lt;1).

By performing the oxygen doping treatment, an insulating layer having a region containing more oxygen than the stoichiometric composition ratio can be formed. When the insulating layer provided with such a region and the oxide semiconductor layer come into contact with each other, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer or the interface between the oxide semiconductor layer and the insulating layer The oxygen deficiency defect in the above can be reduced, and the oxide semiconductor layer can be made into an I-type or an oxide semiconductor as close as possible to the I-type.

When an oxide semiconductor is applied as the semiconductor layer 2403, of the insulating layers in contact with the semiconductor layer 2403, only one of the insulating layer located in the upper layer and the insulating layer located in the lower layer is oxygen based on the stoichiometric composition ratio. Although it is possible to use an insulating layer having a region having a large amount of oxygen, it is preferable to use both insulating layers as an insulating layer having a region having a large amount of oxygen than the stoichiometric composition ratio. The above effect can be obtained by using an insulating layer having a region containing more oxygen than the stoichiometric composition ratio as an insulating layer located in the upper layer and the lower layer of the insulating layer in contact with the semiconductor layer 2403, and sandwiching the semiconductor layer 2403. Can be further enhanced.

Further, when an oxide semiconductor is applied as the semiconductor layer 2403, the insulating layer used for the upper layer or the lower layer of the semiconductor layer 2403 may be an insulating layer having the same constituent elements in the upper layer and the lower layer, or insulation having different constituent elements. It may be a layer. For example, both the upper and lower layers have a Ga composition.₂O_XIt may be gallium oxide of (X = 3 + α, 0 &lt;α &lt;1), or the composition of one of the upper layer and the lower layer is Ga.₂O_XGallium oxide with (X = 3 + α, 0 &lt;α &lt;1), the other with Al composition₂O_XIt may be aluminum oxide with (X = 3 + α, 0 &lt;α &lt;1).

Further, when an oxide semiconductor is applied as the semiconductor layer 2403, the insulating layer in contact with the semiconductor layer 2403 may be a laminate of insulating layers having a region having more oxygen than the stoichiometric composition ratio. For example, the composition is Ga on the upper layer of the semiconductor layer 2403.₂O_XIt forms gallium oxide (X = 3 + α, 0 &lt;α &lt;1), and the composition is Ga on it._XAl_2-XO_{3 + α}(0 &lt;X &lt;2, 0 &lt;α &lt;1) gallium aluminum oxide (gallium aluminum oxide) may be formed. The lower layer of the semiconductor layer 2403 may be a laminate of an insulating layer having a region having more oxygen than the stoichiometric composition ratio, and both the upper layer and the lower layer of the semiconductor layer 2403 may be oxygenated from the stoichiometric composition ratio. An insulating layer having a large number of regions may be laminated.

&lt;Specific example of pixel layout&gt; Next, specific examples of the pixel layout of the liquid crystal display device described above will be described with reference to FIGS. 18 and 19. Note that FIG. 18 is a diagram showing a top view of the pixel layout shown in FIG. 1 (B), and FIG. 19 is a diagram showing a cross-sectional view taken along the line AB shown in FIG. In FIG. 18, the configurations of the liquid crystal layer, the counter electrode, and the like are omitted. Hereinafter, the specific structure will be described with reference to FIG.

The transistor 16 includes a conductive layer 222 provided on the substrate 220 via an insulating layer 221, an insulating layer 223 provided on the conductive layer 222, and a semiconductor provided on the conductive layer 222 via an insulating layer 223. It has a layer 224, a conductive layer 225a provided on one end of the semiconductor layer 224, and a conductive layer 225b provided on the other end of the semiconductor layer 224. The conductive layer 222 functions as a gate layer, the insulating layer 223 functions as a gate insulating layer, one of the conductive layer 225a and the conductive layer 225b functions as a source layer, and the other functions as a drain layer.

The capacitive element 17 is provided on the substrate 220 via the insulating layer 221, the insulating layer 227 provided on the conductive layer 226, and the insulating layer 227 on the conductive layer 226. It has a conductive layer 228 and. The conductive layer 226 functions as one electrode of the capacitive element 17, the insulating layer 227 functions as a dielectric of the capacitive element 17, and the conductive layer 228 functions as the other electrode of the capacitive element 17. Further, the conductive layer 226 is made of the same material as the conductive layer 222, the insulating layer 227 is made of the same material as the insulating layer 223, and the conductive layer 228 is made of the same material as the conductive layer 225a and the conductive layer 225b. Further, the conductive layer 226 is electrically connected to the conductive layer 225b.

An insulating layer 229 and a flattening insulating layer 230 are provided on the transistor 16 and the capacitive element 17.

The liquid crystal element 18 is formed by sandwiching the transparent conductive layer 231 provided on the flattening insulating layer 230, the transparent conductive layer 241 provided on the facing substrate 240, and the transparent conductive layer 231 and the transparent conductive layer 241. Has 250 and. The transparent conductive layer 231 functions as a pixel electrode of the liquid crystal element 18, and the transparent conductive layer 241 functions as a counter electrode of the liquid crystal element 18. Further, the transparent conductive layer 231 is electrically connected to the conductive layer 225b and the conductive layer 226.

An alignment film may be appropriately provided between the transparent conductive layer 231 and the liquid crystal layer 250, or between the transparent conductive layer 241 and the liquid crystal layer 250. The alignment film can be formed by using an organic resin such as polyimide or polyvinyl alcohol, and its surface is subjected to an alignment treatment such as rubbing for arranging liquid crystal molecules in a certain direction. Rubbing can be performed by rotating a roller wrapped with a cloth such as nylon so as to be in contact with the alignment film and rubbing the surface of the alignment film in a certain direction. It is also possible to directly form an alignment film having orientation characteristics by a vapor deposition method using an inorganic material such as silicon oxide without performing an orientation treatment.

Further, a dispenser type (dropping type) or a dip type (pumping type) may be used for injecting the liquid crystal to form the liquid crystal layer 250.

It should be noted that, in order to prevent the dispersion caused by the disorder of the orientation of the liquid crystal between the pixels from being visually recognized, or to prevent the diffused light from being incident on a plurality of adjacent pixels in parallel, the facing substrate 240 A shielding layer 242 capable of shielding light is provided above. For the shielding layer 242, an organic resin containing a black pigment such as carbon black or low-order titanium oxide having an oxidation number smaller than that of titanium dioxide can be used. It is also possible to form the shielding layer 242 with a film using chromium.

The transparent conductive layer 231 and the transparent conductive layer 241 are oxidized by adding, for example, indium tin oxide (ITSO) containing silicon oxide, indium tin oxide (ITO), zinc oxide (ZnO), zinc oxide (IZO), and gallium. A translucent conductive material such as zinc (GZO) can be used.

In FIG. 19, a liquid crystal element having a structure in which the liquid crystal layer 250 is sandwiched between the transparent conductive layer 231 and the transparent conductive layer 241 has been described as an example, but the liquid crystal display device according to one aspect of the present invention has been described. It is not limited to this configuration. A pair of electrodes may be formed on one substrate, such as an IPS type liquid crystal element or a liquid crystal element using a blue phase.

&lt;Specific example of liquid crystal display device&gt; Next, the appearance of the panel of the liquid crystal display device will be described with reference to FIG. FIG. 20 (A) is a top view of a panel in which the substrate 4001 and the opposing substrate 4006 are bonded by a sealing material 4005, and FIG. 20 (B) corresponds to a cross-sectional view taken along the CD line of FIG. 20 (A). ..

A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the substrate 4001 and the scanning line drive circuit 4004. Further, the facing substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the liquid crystal 4007 by the substrate 4001, the sealing material 4005, and the facing substrate 4006.

Further, the substrate 4021 in which the signal line drive circuit 4003 is formed is mounted in a region different from the region surrounded by the sealing material 4005 on the substrate 4001. FIG. 20B exemplifies the transistor 4009 included in the signal line drive circuit 4003.

Further, the pixel unit 4002 and the scanning line drive circuit 4004 provided on the substrate 4001 have a plurality of transistors. In FIG. 20B, the transistor 4010 and the transistor 4022 included in the pixel unit 4002 are illustrated.

Further, the pixel electrode 4030 included in the liquid crystal element 4011 is electrically connected to the transistor 4010. The counter electrode 4031 of the liquid crystal element 4011 is formed on the facing substrate 4006. The portion where the pixel electrode 4030, the counter electrode 4031, and the liquid crystal 4007 overlap corresponds to the liquid crystal element 4011.

Further, the spacer 4035 is provided to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. Although FIG. 20 (B) illustrates the case where the spacer 4035 is formed by patterning the insulating film, a spherical spacer may be used.

Further, various signals and potentials given to the signal line drive circuit 4003, the scanning line drive circuit 4004, and the pixel unit 4002 are supplied from the connection terminal 4016 via the routing wiring 4014 and the routing wiring 4015. The connection terminal 4016 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

Glass, ceramics, and plastic can be used for the substrate 4001, the opposed substrate 4006, and the substrate 4021. Plastics include FRP (Fiberglass-Reinforced Plastics) plates, PVF (polyvinyl fluoride) films, polyester films, acrylic resin films, and the like.

However, a translucent material such as a glass plate, plastic, polyester film or acrylic film is used for the substrate located in the direction of extracting light from the liquid crystal element 4011.

FIG. 21 is an example of a perspective view showing the structure of the liquid crystal display device according to one aspect of the present invention. The liquid crystal display device shown in FIG. 21 includes a panel 1601 having a pixel portion, a first diffuser plate 1602, a prism sheet 1603, a second diffuser plate 1604, a light guide plate 1605, a backlight panel 1607, and a circuit. It has a substrate 1608 and a substrate 1611 on which a signal line drive circuit is formed.

The panel 1601, the first diffuser plate 1602, the prism sheet 1603, the second diffuser plate 1604, the light guide plate 1605, and the backlight panel 1607 are laminated in this order. The backlight panel 1607 has a backlight 1612 composed of a plurality of backlight units. The light from the backlight 1612 diffused inside the light guide plate 1605 is applied to the panel 1601 by the first diffuser plate 1602, the prism sheet 1603 and the second diffuser plate 1604.

Although the first diffuser plate 1602 and the second diffuser plate 1604 are used here, the number of diffuser plates is not limited to this, and may be singular or 3 or more. The diffuser plate may be provided between the light guide plate 1605 and the panel 1601. Therefore, the diffuser plate may be provided only on the side closer to the panel 1601 than the prism sheet 1603, or the diffuser plate may be provided only on the side closer to the light guide plate 1605 than the prism sheet 1603.

Further, the prism sheet 1603 is not limited to the serrated shape in the cross section shown in FIG. 21, and may have a shape capable of condensing the light from the light guide plate 1605 toward the panel 1601.

The circuit board 1608 is provided with a circuit for generating various signals input to the panel 1601, a circuit for processing these signals, and the like. Then, in FIG. 21, the circuit board 1608 and the panel 1601 are connected via the COF tape 1609. Further, the substrate 1611 on which the signal line drive circuit is formed is connected to the COF tape 1609 by using the COF (Chip On Film) method.

FIG. 21 shows an example in which a control system circuit for controlling the drive of the backlight 1612 is provided on the circuit board 1608, and the control system circuit and the backlight panel 1607 are connected via the FPC 1610. There is. However, the circuit of the control system may be formed on the panel 1601, and in this case, the panel 1601 and the backlight panel 1607 are connected by an FPC or the like.

&lt;About various electronic devices equipped with a liquid crystal display device&gt; Hereinafter, an example of an electronic device equipped with a liquid crystal display device disclosed in the present specification will be described with reference to FIG. 22.

FIG. 22A is a diagram showing a notebook-type personal computer, which is composed of a main body 2201, a housing 2202, a display unit 2203, a keyboard 2204, and the like.

FIG. 22B is a diagram showing a personal digital assistant (PDA), and the main body 2211 is provided with a display unit 2213, an external interface 2215, an operation button 2214, and the like. There is also a stylus 2212 as an accessory for operation.

FIG. 22C is a diagram showing an electronic book 2220. The electronic book 2220 is composed of two housings, a housing 2221 and a housing 2223. The housing 2221 and the housing 2223 are integrated by a shaft portion 2237, and the opening / closing operation can be performed with the shaft portion 2237 as an axis. With such a configuration, the electronic book 2220 can be used like a paper book.

The display unit 2225 is incorporated in the housing 2221, and the display unit 2227 is incorporated in the housing 2223. The display unit 2225 and the display unit 2227 may be configured to display a continuous screen or may be configured to display different screens. By displaying different screens, for example, the text is displayed on the right display unit (display unit 2225 in FIG. 22 (C)), and the image is displayed on the left display unit (display unit 2227 in FIG. 22 (C)). Can be displayed.

Further, FIG. 22 (C) shows an example in which the housing 2221 is provided with an operation unit or the like. For example, the housing 2221, power 2231, operation keys 2233, speaker 2235 and a etc.. The page can be sent by the operation key 2233. A keyboard, a pointing device, or the like may be provided on the same surface as the display unit of the housing. Further, the back or side surface of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion part, and the like. .. Further, the electronic book 2220 may be configured to have a function as an electronic dictionary.

Further, the electronic book 2220 may be configured to be able to transmit and receive information wirelessly. It is also possible to purchase and download desired book data or the like from an electronic book server wirelessly.

FIG. 22 (D) is a diagram showing a mobile phone. The mobile phone is composed of two housings, a housing 2240 and a housing 2241. The housing 2241 includes a display panel 2242, a speaker 2243, a microphone 2244, a pointing device 2246, a camera lens 2247, an external connection terminal 2248, and the like. In addition, the housing 2240 includes a solar cell 2249 for charging the mobile phone, an external memory slot 2250, and the like. In addition, the antenna is built in the housing 2241.

The display panel 2242 has a touch panel function, and FIG. 22 (D) shows a plurality of operation keys 2245 displayed as images by dotted lines. The mobile phone is equipped with a booster circuit for boosting the voltage output from the solar cell 2249 to the voltage required for each circuit. Further, in addition to the above configuration, a non-contact IC chip, a small recording device, or the like may be incorporated.

The display direction of the display panel 2242 changes as appropriate according to the usage pattern. In addition, since the camera lens 2247 is provided on the same surface as the display panel 2242, a videophone call is possible. Speaker 2243 and microphone 2244 are not limited to voice calls, but can be used for videophone, recording, playback, etc. Further, the housing 2240 and the housing 2241 can be slid and changed from the unfolded state to the overlapping state as shown in FIG. 22 (D), and the miniaturization suitable for carrying is possible.

The external connection terminal 2248 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. In addition, a recording medium can be inserted into the external memory slot 2250 to support storage and movement of a larger amount of data. Further, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

FIG. 22 (E) is a diagram showing a digital camera. The digital camera is composed of a main body 2261, a display unit (A) 2267, an eyepiece unit 2263, an operation switch 2264, a display unit (B) 2265, a battery 2266, and the like.

FIG. 22F is a diagram showing a television device. In the television device 2270, the display unit 2273 is incorporated in the housing 2271. The display unit 2273 makes it possible to display an image. Here, the configuration in which the housing 2271 is supported by the stand 2275 is shown.

The operation of the television device 2270 can be performed by the operation switch provided in the housing 2271 or the separate remote controller 2280. The operation key 2279 provided in the remote controller 2280 can be used to control the channel and volume, and the image displayed on the display unit 2273 can be operated. Further, the remote controller 2280 may be provided with a display unit 2277 for displaying information output from the remote controller 2280.

The television device 2270 is preferably configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (sender to receiver) or two-way (sender and receiver, or between recipients, etc.). It is possible.

(Embodiment 3) In the present embodiment, one form of the substrate used in the liquid crystal display device according to one aspect of the present invention will be described with reference to FIGS. 23 and 24.

First, a peeled layer 6116 including elements necessary for an element substrate, such as a transistor, an interlayer insulating film, wiring, and a pixel electrode, is formed on the manufactured substrate 6200 via a peeling layer 6201.

As the fabrication substrate 6200, a quartz substrate, a sapphire substrate, a ceramic substrate, a glass substrate, a metal substrate, or the like can be used. It should be noted that by using a substrate having a thickness such that the flexibility is not clearly expressed, an element such as a transistor can be formed with high accuracy. The degree of flexibility that is not clearly expressed means that the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display is about or higher than that of a glass substrate.

The release layer 6201 can be made of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), etc. by the sputtering method, plasma CVD method, coating method, printing method, etc. Elements selected from cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), Alternatively, a layer made of an alloy material containing the above element as a main component or a compound material containing the above element as a main component is formed as a single layer or laminated.

When the release layer 6201 has a single-layer structure, it preferably forms a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum. Further, as the release layer 6201, a layer containing a tungsten oxide or an oxide nitride, a layer containing a molybdenum oxide or an oxide nitride, or a layer containing an oxide or an oxide nitride of a mixture of tungsten and molybdenum is formed. It is also possible. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

When the release layer 6201 has a laminated structure, a metal layer is preferably formed as the first layer, and a metal oxide layer is formed as the second layer. Typically, the first layer is a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum, and the second layer is tungsten, molybdenum, or an oxide of a mixture of tungsten and molybdenum, and nitrides thereof. It is preferable to form those oxidative nitrides or their nitride oxides. To form the second metal oxide layer, an oxide layer (for example, one that can be used as an insulating layer such as silicon oxide) is formed on the first metal layer to oxidize the metal on the surface of the metal layer. It may be applied that an object is formed.

Subsequently, a layer to be peeled 6116 is formed on the peeling layer 6201 (see FIG. 23 (A)). The peelable layer 6116 includes elements necessary for an element substrate, such as a transistor, an interlayer insulating film, wiring, and a pixel electrode. These can be produced by using a photolithography method or the like.

Next, the peeled layer 6116 is adhered to the temporary support substrate 6202 using the peeling adhesive 6203, and then the peeled layer 6116 is peeled from the peeling layer 6201 of the manufactured substrate 6200 and transposed (see FIG. 23 (B)). .. As a result, the layer to be peeled 6116 is provided on the temporary support substrate side. In the present specification, the step of transposing the layer to be peeled from the manufacturing substrate to the temporary support substrate is referred to as a transposition step.

As the temporary support substrate 6202, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. Further, a plastic substrate having heat resistance that can withstand the subsequent processing temperature may be used.

In addition, the peeling adhesive 6203 used here includes a temporary support substrate 6202 and a layer to be peeled 6116, which are soluble in water or a solvent and can be plasticized by irradiation with ultraviolet rays or the like. Use an adhesive that can separate and.

In addition, various methods can be appropriately used for the step of transposing to the temporary support substrate 6202. For example, when a film containing a metal oxide film is formed as the release layer 6201 on the side in contact with the layer to be peeled 6116, the metal oxide film is fragile by crystallizing to form the layer to be peeled 6116. Can be peeled off from. When an amorphous silicon film containing hydrogen is formed as the peeling layer 6201 between the fabrication substrate 6200 and the layer to be peeled 6116, the amorphous silicon film containing hydrogen is removed by irradiation or etching with laser light. Then, the layer to be peeled 6116 can be peeled off from the manufacturing substrate 6200. When a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, etc.) is used as the release layer 6201, a laser is used for the release layer 6201. By irradiating light, nitrogen, oxygen and hydrogen contained in the peeling layer 6201 are released as gas, and the separation between the peeled layer 6116 and the manufactured substrate 6200 can be promoted. As another method, the liquid to be peeled may be permeated into the interface between the peeling layer 6201 and the layer to be peeled 6116 to peel the layer 6116 to be peeled from the manufactured substrate 6200. There is also a method in which the release layer 6201 is formed of tungsten and the release layer 6201 is etched with a mixed solution of aqueous ammonia and hydrogen peroxide to perform the release.

In addition, the peeling step can be performed more easily by combining a plurality of the peeling methods. After irradiating the peeling layer 6201 with laser light, etching the peeling layer 6201 with gas or solution, and mechanically removing it with a sharp knife or knife to make the peeling layer 6201 and the layer to be peeled 6116 easy to peel off. , The process of peeling by physical force (by machine etc.) corresponds to this. When the release layer 6201 is formed by a laminated structure of metal and metal oxide, it is physically peeled off from the release layer 6201 triggered by a groove formed by irradiation with laser light or a scratch caused by a sharp knife or scalpel. Is also easy.

Further, when performing these peeling, the peeling may be performed while sprinkling a liquid such as water.

Other methods for separating the material to be peeled layer 6116 from the materialized substrate 6200 include a method for removing the materialized substrate 6200 on which the layer to be peeled 6116 is formed by mechanically polishing or the like, or a solution or NF.₃, BrF₃, ClF₃A method of removing by etching with a halogenous fluoride gas such as the above can also be used. In this case, it is not necessary to provide the release layer 6201.

Subsequently, the transfer substrate 6110 is adhered to the exposed peeling layer 6201 or the surface of the layer to be peeled 6116 by using a first adhesive layer 6111 with an adhesive different from the peeling adhesive 6203. (See Figure 23 (C)).

As the material of the first adhesive layer 6111, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable adhesive, a reaction curable adhesive, a thermosetting adhesive, or an anaerobic adhesive are used. be able to.

As the transposed substrate 6110, various substrates having high toughness can be used, and for example, an organic resin film or a metal substrate can be preferably used. A substrate with high toughness has excellent impact resistance and is not easily damaged. Since the organic resin film is lightweight and the thin metal substrate is lightweight, it is possible to significantly reduce the weight as compared with the case of using a normal glass substrate. By using such a substrate, it becomes possible to manufacture a display device that is light and is not easily damaged.

Examples of the material constituting such a substrate include polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), acrylic resin, polyacrylic nitrile resin, polyimide resin, polymethylmethacrylate resin, and polycarbonate resin (PC). ), Polyether sulphon resin (PES), polyamide resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyvinyl chloride resin and the like. Since the substrate made of these organic resins has high toughness, it has excellent impact resistance and is not easily damaged. Further, since these organic resin films are lightweight, it is possible to manufacture a display device that is extremely light in weight as compared with a normal glass substrate. Further, in this case, it is preferable that the transposed substrate 6110 further includes a metal plate 6206 having an opening at least in a portion overlapping the region where the light of each pixel is transmitted. With this configuration, it is possible to construct a transposed substrate 6110 that has high toughness, high impact resistance, and is not easily damaged while suppressing dimensional changes. Furthermore, by reducing the thickness of the metal plate 6206, a transposed substrate 6110 that is lighter than the conventional glass substrate can be constructed. By using such a substrate, it becomes possible to manufacture a display device that is light and is not easily damaged. (See Figure 23 (D)).

FIG. 24A is a diagram showing an example of a top view of the liquid crystal display device. As shown in FIG. 24 (A), the first wiring layer 6210 and the second wiring layer 6211 intersect, and the area surrounded by the first wiring layer 6210 and the second wiring layer 6211 transmits light. In the case of the liquid crystal display device having the area 6212, as shown in FIG. 24 (B), a metal plate having a grid-like opening with a portion overlapping the first wiring layer 6210 and the second wiring layer 6211 remains. 6206 may be used. By using such a metal plate 6206 attached to a liquid crystal display device, it is possible to suppress deterioration of alignment accuracy due to the use of a substrate made of organic resin and dimensional change due to elongation of the substrate (Fig. 24 (C). )reference). When a polarizing plate (not shown) is required, it may be provided between the transposed substrate 6110 and the metal plate 6206, or may be provided further outside the metal plate 6206. The polarizing plate may be attached to the metal plate 6206 in advance. From the viewpoint of weight reduction, it is preferable to use a thin substrate as the metal plate 6206 within the range in which the above-mentioned dimensional stabilization effect is exhibited.

Then, the temporary support substrate 6202 is separated from the layer to be peeled 6116. Since the peeling adhesive 6203 is made of a material capable of separating the temporary support substrate 6202 and the layer to be peeled 6116 when necessary, the temporary support substrate 6202 may be separated by a method suitable for the material. The backlight is illuminated as shown by the arrow in the drawing (see Fig. 23 (E)).

As described above, the peelable layer 6116 in which the transistor to the pixel electrode is formed can be formed on the transposed substrate 6110, and a lightweight and highly impact-resistant element substrate can be produced.

&lt;Modification example&gt; The display device having the above-described configuration is one aspect of the present invention, and the following display device having a configuration different from that of the present display device is also included in the present invention. After the above-mentioned transposition step (see FIG. 23 (B)), the metal plate 6206 may be attached to the surface of the exposed release layer 6201 or the layer to be peeled 6116 before the transfer substrate 6110 is attached (FIG. 23). See (C')). In this case, it is preferable to provide a barrier layer 6207 in between to prevent contaminants from the metal plate 6206 from adversely affecting the characteristics of the transistor in the layer 6116 to be peeled off. When the barrier layer 6207 is provided, the barrier layer 6207 may be provided on the surface of the exposed peeling layer 6201 or the layer to be peeled 6116, and then the metal plate 6206 may be attached. The barrier layer 6207 may be formed of an inorganic material, an organic material, or the like, and silicon nitride or the like is a typical example, but the barrier layer 6207 is not limited to these as long as it can prevent contamination of the transistor. The barrier layer 6207 is made of a material having translucency, or is made to be a thin film having translucency, so as to have at least translucency to visible light. The metal plate 6206 may be bonded by forming a second adhesive layer (not shown) using an adhesive different from the peeling adhesive 6203.

After that, the first adhesive layer 6111 is formed on the surface of the metal plate 6206, the transposed substrate 6110 is attached (Fig. 23 (D')), and the temporary support substrate 6202 is separated from the peeled layer 6116 (Fig. 23 (Fig. 23 (D')). By E')), it is possible to manufacture an element substrate which is similarly lightweight and has high impact resistance. The backlight is illuminated as shown by the arrow in the drawing.

A lightweight and highly impact-resistant liquid crystal display device is manufactured by sandwiching a liquid crystal layer between a lightweight and highly impact-resistant element substrate thus produced and fixing them with a sealing material. Can be done. As the facing substrate, a substrate having high toughness and translucency to visible light (similar to a plastic substrate that can be used for the transposed substrate 6110) can be used. A polarizing plate, a black matrix, and an alignment film may be provided on the polarizing plate, a black matrix, and an alignment film, if necessary. As a method for forming the liquid crystal layer, a dispenser method, an injection method, or the like can be applied.

The lightweight and highly impact-resistant liquid crystal display device manufactured as described above can manufacture fine elements such as transistors on a glass substrate having relatively good dimensional stability, and has been conventionally manufactured. Since the same manufacturing method can be applied, even a fine element can be formed with high accuracy. Therefore, it is possible to provide a high-definition and high-quality image while having impact resistance, and to provide a lightweight liquid crystal display device.

Further, the liquid crystal display device manufactured as described above can be made flexible.

10 pixel part 11 Scanning line drive circuit 12 Signal line drive circuit 13 scan line 14 signal line 15 pixels 16 transistors 17 Capacitive element 18 Liquid crystal element 19 LCD panel 20 pulse output circuit 21 terminals 22 terminals 23 terminals 24 terminals 25 terminals 26 terminals 27 terminals 31 transistor 32 transistors 33 transistor 34 transistor 35 transistor 36 transistor 37 transistor 38 transistor 39 transistor 40 backlight panel 41 Backlit array 41a₁ Backlight array 41a₂ Backlight array 41a₃ Backlight array 41a₄ Backlight array 41b₁ Backlight array 41c₁ Backlight array 41c₄ Backlight array 42 backlight unit 45 Backlight drive circuit 46a Pulse width modulation circuit 50 transistors 51 transistor 52 transistor 53 transistor 70 Image processing circuit 71 AD converter 72 frame memory 73 Maximum value detection circuit 73a Maximum value detection circuit 73b Maximum value detection circuit 73c Maximum value detection circuit 74 Gamma correction circuit 74a Gamma correction circuit 74b Gamma correction circuit 74c gamma correction circuit 101 area 102 area 103 area 120 shift register 121 transistor 220 board 221 Insulation layer 222 Conductive layer 223 Insulation layer 224 Semiconductor layer 225a Conductive layer 225b Conductive layer 226 Conductive layer 227 Insulation layer 228 Conductive layer 229 Insulation layer 230 Flattening insulation layer 231 Transparent conductive layer 240 Opposed board 241 Transparent conductive layer 242 Shielding layer 250 liquid crystal layer 265 Transparent conductive layer 1601 panel 1602 diffuser 1603 prism sheet 1604 diffuser 1605 Light guide plate 1607 backlight panel 1608 circuit board 1609 COF tape 1610 FPC 1611 board 1612 backlight 2201 body 2202 housing 2203 Display 2204 keyboard 2211 body 2212 stylus 2213 Display 2214 Operation buttons 2215 External interface 2220 e-book 2221 housing 2223 housing 2225 Display 2227 Display 2231 power supply 2233 Operation key 2235 speaker 2237 Shaft 2240 housing 2241 housing 2242 Display panel 2243 speaker 2244 microphone 2245 Operation key 2246 pointing device 2247 Camera lens 2248 External connection terminal 2249 Solar cell 2250 external memory slot 2261 body 2263 Eyepiece 2264 Operation switch 2265 Display (B) 2266 battery 2267 Display (A) 2270 television device 2271 housing 2273 Display 2275 stand 2277 Display 2279 Operation key 2280 remote control manipulator 2400 board 2401 Gate layer 2402 Gate insulating layer 2403 Semiconductor layer 2405a Source layer 2405b drain layer 2406 Channel protection layer 2407 Insulation layer 2409 Protective insulation layer 2411 Gate layer 2412 Gate layer 2413 Gate insulating layer 2414 Gate insulating layer 2436 Underlayer 2450 transistor 2460 transistor 2470 transistor 2480 Transistor 4001 board 4002 pixel part 4003 Signal line drive circuit 4004 Scan line drive circuit 4005 Sealing material 4006 Opposed board 4007 LCD 4009 transistor 4010 transistor 4011 Liquid crystal element 4014 Wiring 4015 Wiring 4016 Connection terminal 4018 FPC 4019 Anisotropic conductive film 4021 board 4022 transistor 4030 pixel electrode 4031 Opposite electrode 4035 spacer 6110 Transposed board 6111 Adhesive layer 6116 Stripe layer 6200 Fabrication board 6201 release layer 6202 Temporary support board 6203 Peeling adhesive 6206 Metal plate 6207 Barrier layer 6210 Wiring layer 6211 Wiring layer 6212 area