Integrated silicon circuit comprising a physically non-reproducible function, and method and system for testing such a circuit

0001The present invention relates to silicon integrated circuits that include physically non-copyable functions and methods of selecting such circuits based on reliability tests. This applies in particular to the field of authentication of cryptographic circuits and electronic components.

0002For many applications, it is useful to be able to uniquely identify electronic chips or integrated circuits. Prior art has proposed a solution that makes it particularly possible to distinguish a particular circuit from a series of circuits obtained from the same manufacturing equipment. Therefore, by incorporating a PUF (an acronym derived from the phrase "Physically Unclonable Function") type into an integrated circuit, the circuit Allows the generation of unique and unique signatures. This signature can be used to introduce an electronic system authentication mechanism.

0003This unique signature can also be used as a unique encryption key unique to this circuit. In this case, it is not necessary to store the key in the integrated circuit.

0004The signature is generated directly by the circuit. Since no human intervention is required, resistance to attacks, especially peep attack type attacks, is improved.

0005In the prior art, there are various ways to perform PUF functions. Therefore, a paper by R. Pappu entitled Physical One-Way Functions (PhD Thesis, Massachussetts Institute of Technology, March 2001) describes what an optical PUF is. The optical PUF consists of a transparent material containing randomly dispersed particles that allow the deflection of the laser beam.

0006Coated PUF is also used. This type of PUF is by P. Tuyls, B. Skoric and T. Kennar entitled Security with Noisy Data: Private Biometrics, Secure Key Storage and Anti-Counterfeiting (Secaucus, NJ USA: Springer-Verlag New York, 2007). It is described in the paper. In this case, the opaque material is randomly doped with dielectric particles and placed on top of the integrated circuit.

0007The family of PUFs, called silicon PUFs, takes advantage of the structural inconsistencies introduced by the method of manufacturing integrated circuits. Differences in dispersion between the wires and transistors that make up the circuit are actually significant from circuit to circuit, even if they form part of the same slice. This family includes, among other things, arbiter PUFs, ring oscillator PUFs and SRAM PUFs. Silicon PUFs can be implemented in ASIC or FPGA circuits without any technical changes.

0008The arbiter PUF is described in a paper by B. Gassend, DEClarke, M. van Dijk, and S. Devadas entitled Silicon physical random functions (ACM Conference on Computer and Communications Security, 2002, p.148-160). .. In this type of PUF, the exact same signal propagates by following two paths in the delay circuit, the two circuits are distinguishable and can be set using control words. The arbiter compares the delays between the two signals resulting from these two propagations, and the result of this comparison is the signature of the integrated circuit. One of the drawbacks of this type of PUF is that the elements that allow path parameterization must be balanced with respect to delay, which makes their design difficult.

0009PUFs with a pair of ring oscillators are also silicon PUFs. These are described in a paper by GESuh and S. Devadas entitled Physical unclonable functions for device authentication and secret key generation (DAC, 2007, p. 9-14). The frequencies produced by a pair of identical ring oscillators are compared. The result of this comparison is the signature of the integrated circuit. The disadvantage of ring oscillators is that the oscillators are sensitive to so-called secondary effects, such as those associated with the interconnection between the oscillators or the disturbances introduced into the oscillator during the attack period.

<p num="0010"> An object of the present invention is, in particular, to alleviate the above drawbacks.</p>

<p num="0011"> For this purpose, the subject of the present invention is a silicon integrated circuit containing a physically non-copyable function LPUF that allows the generation of signatures specific to said circuit. The function comprises a ring oscillator consisting of loops traversed by signal e, the loops being formed from N topologically identical lag chains and inverting gates connected in series with each other, one lag chain. , Consists of M delay elements connected in series with each other. It also includes a control module that produces N control words, which words are used by the lag chain to set the value of the delay introduced for the signal e traversing them. It also includes a measurement module that measures the frequency of the signal at the output of the last lag chain after the control word is updated. It also includes means of estimating the bits that make up the signature of the circuit from frequency measurements.</p><p num="0012"> The circuit is, for example, an ASIC circuit or FPGA.</p><p num="0013"> According to one embodiment, the signature is used as an encryption key.</p><p num="0014"> According to another embodiment, the signature is used for its authentication.</p><p num="0015"> The delay element includes, for example, means of steering signals traversing them according to at least two different paths, the path into which the delay value is introduced is unique to it, and the steering is at least one belonging to the control word. Controlled by bits.</p><p num="0016"> According to one aspect of the invention, a challenge word consisting of a concatenation of control words is presented at the input of a control module, which modules generate combinations based on the words so that a lag chain can be set.</p><p num="0017"> The bit of the signature is determined, for example, according to the frequency ranking measured for various combinations of control words.</p><p num="0018"> The bit of the signature is determined, for example, according to the estimated difference between the two measurement frequency values, and one measurement frequency value corresponds to one control word combination.</p><p num="0019"> The bit of the signature is determined, for example, according to the value of the ratio between the two estimated frequency differences.</p><p num="0020"> In one embodiment, the circuit comprises a random number generator and the generated numbers are used to select the order in which the frequencies corresponding to the combination of control words are measured.</p><p num="0021"> The circuit contains, for example, at least one parity bit, such bit used to correct the bit of the signature generated with the error.</p><p num="0022"> The subject of the present invention is also a method for testing integrated circuits including a physically non-copyable function LPUF. By applying a series of steps to the test circuit, a circuit can be selected that allows the generation of signatures specific to the circuit at the selected reliability level, and these steps are the parameters T for setting the test and A measurement phase in which a typical quantity representing the signature bit of a circuit is measured, corresponding to the selection of B combinations of Th and B control words having a humming distance equal to at least a predetermined value HD, for each signature bit. Up to T measurements are taken, and these T measurements are accumulated so that it can be determined whether the corresponding bit is indefinite, and this determination is at least estimated from the value of the parameter Th. Performed after being compared to a single value, the test circuit corresponds to the measurement phase, which is selected according to the number of indefinite bits detected.</p><p num="0023"> According to certain embodiments, the method of the invention comprises the step of determining the probability that a circuit will not be selected, the probability being:<maths num="1"><img id="000002" he="18" wi="64" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Determined by using in the formula: erf () is a Gaussian error function; σ is the variance of the quantity of measurements that is representative of the signature bits of the circuit.</p><p num="0024"> According to another aspect of the practice, the method of the present invention comprises the step of determining the probability of error for each signature bit, wherein the probability is:<maths num="2"><img id="000003" he="21" wi="56" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Determined by using in the formula: δ_jIs the frequency difference measured between the two frequencies corresponding to the application of two different combinations of control words; s is s²Is defined as the variance of the measured noise.</p><p num="0025"> For example, a circuit is selected if there are no signature bits that are indefinite.</p><p num="0026"> The LPUF function of the test circuit relates to a parity bit whose value is determined based on the signature of the circuit, for example, the circuit is selected when the number of indefinite bits is exactly less than 2.</p><p num="0027"> s²And σ²The value of is measured for, for example, a temperature substantially equal to + 70 ° C. and a supply voltage for the circuit that is substantially 5% lower than the nominal supply voltage, and the measurement phase is performed under the same circumstances.</p><p num="0028"> The subject of the present invention is also a test system that implements the method according to the present invention. The system consists of a computer with a user interface and equipment items that allow control of the measuring probe, the function of which the probe represents a signature bit and collects representative quantities of measurements produced by the test circuit. Yes, the processing operations associated with this phase are then performed by the computer and displayed on its interface.</p><p num="0029"> Other features and advantages of the invention will be apparent from the following statements provided in connection with the accompanying drawings, given as non-limiting examples.</p>

0030<figref num="1">An example of arbiter PUF is shown.</figref><figref num="2">Represents a delay element that can be used in an arbiter PUF.</figref><figref num="3">An example of a silicon PUF including a loop structure according to the present invention is shown.</figref><figref num="4">An example of a delay element that can be used in a lag chain included in LPUF is shown.</figref><figref num="5">Indicates an LPUF containing an N = 2 lag chain.</figref><figref num="6">An example scheme for combining the control words used in LPUF is shown.</figref><figref num="7">An example error function that enables estimation of the reliability of LPUF is shown.</figref><figref num="8">The principle of detecting bad bits in LPUF is shown.</figref><figref num="9">An example of a combination of control words and a comparison of frequency measurements associated with them, which can reduce the defective rate of circuits including LPUF, is shown.</figref><figref num="10">An example of a method for testing a circuit according to the present invention is shown.</figref><figref num="11">An example of a test system for carrying out the test method according to the present invention is shown.</figref>

0031Figure 1 shows an example of an arbiter PUF. The arbiter PUF usually comprises a chain of K delay elements 100,101,102 connected in series with each other and an arbiter element 103 connected to the last delay element of the chain. The signal e is introduced into the PUF and traverses two different electronic paths 104,105. Delay elements 100,101,102 have K bits C₁, C₂, ..., C_KCan be set using the binary control word of. Each setting of the two paths 104 and 105 corresponds to a word of K bits. This setting is unique for a particular binary control word, where each bit of the word is used to set one of the delay elements 100,101,102, which has steering function and controls. Involved in defining two unique paths associated with a word.

0032The arbiter element 103 compares the delays introduced by these two paths 104,105 between the two signals originating from e, and the result of this comparison is bit Q. By changing the control word, another bit Q is generated. Therefore, it is possible in this way to generate a binary word used as a signature for the circuit on which the arbiter PUF is implemented.

0033FIG. 2 represents a delay element that can be used in an arbiter PUF. This delay element is, for example, the j-th element in a chain of K elements. Two signals e_{0, j}And e_1,jIs shown as an input to this delay element. The output of the element is two signals s₀And s₁Corresponds to.

0034The input signal is the control bit C_jSteering according to the value obtained by, said bits controlling the two gates 205,206 enable this steering.

0035For example, signal e_{0, j}Is C_jIf = 0, the first path 200, or C_jIf = 1, the second path 201 can be followed. In the first case, the output signal s0 is the delay d associated with the first path 200.₀^jInput signal affected by e_{0, j}Corresponding to, in the second case, the output signal s1 is the delay d associated with the second path 201.₁^jInput signal affected by e_{0, j}Corresponds to.

0036Signal e_1,jAs for the latter, C_jIf = 0, the first path 202, or C_jIf = 1, the second path 203 can be followed. In the first case, the output signal s1 is the delay d associated with the first path 202.₀^jInput signal affected by e_1,jCorresponding to, in the second case, the output signal s1 is the delay d associated with the second path 203.₁^jInput signal affected by e_1,jCorresponds to.

0037In order for these delay elements to enable the implementation of the arbiter PUF, the internal paths to the elements must be balanced, that is, the parallel paths (200,202) are the same and the intersecting paths (201,203) are the same. It is necessary to be. This equilibrium is even more complex at the level of each delay element, as more paths can intersect. The implementation of arbiter PUF is therefore complicated.

0038FIG. 3 shows an example of a silicon PUF including a loop structure according to the present invention. The silicon PUF in this example is represented in the subsequent description by the acronym LPUF, which is derived from the phrase "Loop Physically Unclonable Function" ("Loop Physically Unclonable Function").

0039LPUF is a silicon PUF containing loop 300 formed from N lug chains 301,302. N is at least 2. This loop forms a simple ring oscillator.

0040The lug chains 301 and 302 are composed of M delay elements 303. Ring Oscillators Unlike PUFs, LPUF oscillators consist of a single oscillator.

0041One of the advantages of the LPUF structure is that noise is common to all delay chains. Moreover, since there is only one loop, there is no problem of interconnection between oscillators.

0042Each delay chain 301,302 receives a control word Ci of M bits, and the word corresponds to a delay value specific to the circuit.

0043Control word C_iBit C_{i, j}Corresponds to the lag value of the delay element number j among the M elements of the lag chain i.

0044During the LPUF design period, more specifically, during the placement routing, which is to convert logic gates and their interconnects into gates with transistors and real wires, the lag chains are exactly the same. It is duplicated N times in the form. This replication can be easily performed either within the design framework of the ASIC or FPGA circuit. This means that LPUF is particularly simple in design.

0045FIG. 4 shows an example of a delay element that can be used in a lag chain included in an LPUF.

0046Input signal e_{i, j}Is introduced into the delay element 405. The signal can be propagated by following two different paths 403,404. Path selection is the control bit C associated with the control element._{i, j}Determined by the value of, the bit has the purpose of selecting one of the two paths 403 or 404 using the multiplexer 400. The subscripts i and j indicate the index of the chain and the index of the elements in the chain, respectively.

0047As an example, C_{i, j}When = 0, the input signal e_{i, j}Follows the first path 403, and the output of the first delay element is the delay d._{i, j}⁰Affected signal e_{i, j}The delay is caused by the propagation of the signal along this first path. On the contrary, C_{i, j}When = 1, the input signal e_{i, j}Follows the second path 404, and the output of the first delay element is the delay d_{i, j}¹Affected signal e_{i, j}The delay is caused by the propagation of the signal along this second path.

0048Advantageously, it is sufficient to duplicate the delay element in order to have a replica of the original element 405 corresponding to the jth element in the exact same chain, and thus between the various paths 403,404 of the delay element. There is no need to balance. Therefore, since the various paths of the delay element do not intersect, equilibrium is more easily guaranteed compared to the arbiter PUF.

0049Since the delay element does not have the same physical characteristics in one chain and the next, it introduces different delays available to LPUF.

0050Figure 5 shows an LPUF with an N = 2 lag chain. Each of the two lug chains 500,501 contains M delay elements. These lag chains are topologically, i.e., functionally identical and have the same physical structure. The delay elements 506, 507 and their interconnect 508 are seen again in the second lug chain 501 in exactly the same way. The chains are connected in series with each other and the output of the second chain is looped by loop line 502 to the input of the first chain. The logic gate 503 that executes the inversion function is arranged on the loop 502. This looped assembly constitutes a configurable oscillator.

0051The two delay elements 500,501 each have two binary words C₁And C₂Is controlled by.

0052C₁And C₂Each of is C_1,1, C_1,2, ..., C_1,MAnd C_2,1, C_2,2, ..., C_2,MIt consists of M bits displayed as. These two words are generated by control module 505.

0053The frequency of the output signal of the last lag chain is analyzed by the measurement module 504. The measured frequency values are determined by the delays introduced by the various lag chains and therefore by the control words applied to them. The control module 505 is, for example, the first pair value (C).₁, C₂)=(0,2^j), That is, C_2,j= 1 (j [1; M]) and C₁And C₂The other bit of is equal to 0, then the second pair value (C)₁, C₂)=(2^j, 0) is applied continuously.

0054The measurement module 504 is a pair (C₁, C₂The frequencies of the signals corresponding to the application of the two values of) are continuously measured, and the measurements are freq (0,2, respectively).^j) And freq (2)^j, 0) is written. Estimated from these measurements are quantities that represent a bit of signature. For example, frequency difference δ_jIs then estimated by control module 505 using the following equation: δ_j= freq (0,2)^j)-freq (2^j,0) (1)

0055A pair that changes the path the signal follows (C)₁, C₂The difference in propagation lag in the lag chain, which is the result of applying the two values of), is not zero and can be utilized. In reality, this lag difference is the measured frequency difference δ._jAs a result, the latter can be used to generate bites of signatures that are unique to the circuit.

0056Therefore, a representative quantity δ indicating a bit of signature_jCustoms may be chosen to generate signature bits based on. For example, when N = 2, bit i is δ_jIf is positive, equal to 0, δ_jIs equal to 1 if is negative.

0057To generate the various bits of the signature, a binary word, referred to in the subsequent description as the "challenge word", is presented at the input of the LPUF and processed by the control module 505. Based on this, the control module 505 generates a combination of control words used to set the lag chain and to allow the measurement of frequency differences. In reality, one challenge word consists of N control words. These control words are N words C_iIt can be combined in various ways so that as many lagchain settings as possible can be obtained according to N! Possible control combinations (exclamation marks represent factorial operations). The response is then determined, for example, by the control module. When N = 2, the response example corresponding to the circuit signature can be represented according to the frequency difference described above. If N&gt; 2, the response can be determined, for example, according to the frequency order of N! Possible control combinations.

0058To compare and classify the frequencies obtained with various combinations of controls and thus lags, there is the word C_iThere must be at least two different combinations of. Word C_iConsidering the total Hamming distance HD of the combination of HD, the expression:<maths num="3"><img id="000004" he="17" wi="109" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Can be expressed using. In the equation, HW () is a function that determines the Hamming weight,<maths num="4"><img id="000005" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Represents an exclusive OR operation.

0059(C_i,C_i') Is two control words established based on a combination of words acting on N chains, it is expressed by the following equation to be sure that it has at least two different combinations. Conditions should preferably be met: i, i' [1, N] HD 1 (3)

0060In addition, the jth bit of the N lagchain must not remain at the value "1", otherwise the controller cannot detect the bit difference. By convention, the jth bit can always be equal to "0". For example, for N = 2 and M = 3, the pair value (C)₁, C₂) = Difference δ obtained for (0,1)_jIs a pair value (C) unless otherwise specified₁, C₂) = (2,3), (C₁, C₂) = (4,5), and (C₁, C₂The same is true for) = (6,7), and the following equation must be satisfied:<maths num="5"><img id="000006" he="16" wi="109" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0061LPUF can also include mechanisms to prevent attacks from snooping or fault injection. Therefore, a random number generator may be incorporated into the circuit. The latter can be used to select the order in which frequencies are measured. Therefore, since the frequency measurement is performed in a random sequence of control words, the attacker cannot force the bit value or unravel the bit value.

0062Advantageously, LPUF is resistant to environment-related noise and interference. In reality, the lag chains that make up the LPUF are affected by disturbance noise in exactly the same way. Therefore, if it has a longer duration than the measurement, the result of the frequency measurement is largely unaffected by this noise, so that the signature generation remains reliable, which means that of the ring oscillator. This may not be the case for PUFs with pairs.

0063For applications aimed at circuit authentication, LPUF can be used in conjunction with a CRP mechanism (an acronym derived from the phrase "Challenge-Response Pair").

0064This mechanism can be implemented by incorporating the LPUF into the circuit. The challenge message or word is presented to the LPUF, after which the latter determines a response message that allows authentication of the circuit. In practice, this response message corresponds to the signature generated by the PUF and is specific to the circuit.

0065LPUF can also be used to generate encryption keys. Thus, the LPUF itself uses a subset of challenge messages, and the signature thus generated can be used as an encryption key.

0066Challenge words are N control words C_iCorresponding to the concatenation of (i [1, ..., N]), one control word is used for each of the N lag chains. The response word is the result of the measurement and the result of the frequency comparison produced by N! Possible combinations of N words Ci, and the exclamation mark represents the factorial operation. Conditions (3) and (4) can be complemented by the fact that all control words Ci are different because they have N! Different combinations. is this,<maths num="6"><img id="000007" he="14" wi="107" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Can be represented by.

0067The measured frequencies are compared to each other so that a response can be formed according to a given protocol. For example, N! Combinations can be classified differently to obtain a (N!)! Arrangement.

0068Figure 6 shows an example scheme for combining the control words used in the LPUF. In this example, N = 3 and control word C_iCan take three values A, B and C600 that meet the conditions (3), (4) and (5). Therefore, six possible combinations 603 can be generated for the control words (C1, C2, C3) and a frequency arrangement of 720 can be obtained.

0069Advantageously, the number of possible challenge words is significantly higher than in the case of Arbiter PUF. In fact, for arbiter PUF, this number is 2^Mbe equivalent to. Considering equations (3), (4) and (5) for LPUF, the number of possible challenge words is given by Table (1) below for specific values of N and M.

0070<tables num="1"><img id="000008" he="62" wi="159" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></tables>

0071Advantageously, the number of different signatures that can be generated is, as a result, very large in the case of LPUF compared to arbiter PUF.

0072For applications aimed at generating encryption keys that are specific to the components on which LPUF is implemented, one scheme is to use a given control word, i.e., a control word stored by the circuit. This principle is the same as authentication, except that there is no challenge word delivery, and the consideration of a subset of challenge words in which the frequencies of the combinations are measured and compared is up to the LPUF.

0073To illustrate the principle of this scheme, consider the control module of the LPUF, using the same control word Ci, which causes the bits to be zero, except for the control word where one of the bits takes the value 1. The value associated with this control word is 2^jAnd j represents the j-th delay element used to generate one bit of the key. The LPUF control module then generates N! Combinations by applying permutations to N control words Ci. As in this example, all control words, apart from 1, are identical (zero) and the number of combinations is equal to N, not N !. The N frequencies corresponding to these N combinations are obtained by measurement.

0074The measured frequency value is the control word (C₁, C_N) Corresponds to the above value, freq (C)₁, ..., C_N) Is displayed. Therefore, N frequencies f corresponding to the above N combinations.₁, f₂, ..., f_NCan be written as: f₁= freq (0,0, ..., 2^j) f_N-1= freq (0,2)^j, , 0) f_N= freq (2^j,0,・・・,0)

0075These measured frequencies are classified, for example, so that the generated signature bits correspond to the difference or combination of measured frequencies.

0076As an example, when N = 2, the frequency difference δ_iTherefore, the j-th bit of the encryption key can be obtained, and the difference is determined by using the equation (1).

0077For N = 3, there are 3 possible frequency values, and as a result, there are 6 possible combinations. The three values are: f₁= freq (0,0,2^j) f₂= freq (0,2)^j, 0) f₃= freq (2^j, 0,0).

0078The encryption key bits can then be estimated using a table that shows an example below.

0079<tables num="2"><img id="000009" he="66" wi="98" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></tables>

0080A signature can be obtained by applying this same scheme with a given challenge word. The number of challenge words is related to the number of bits that can be extracted to constitute the response word used to authenticate the circuit, including the encryption key or LPUF.

0081For example, if N = 2 and M = 5, it is possible to obtain 121 different bits, considering Table (1).

0082If N is greater than 2, the number of bits obtained will increase exponentially because there are (N!)! Possible arrangements, as already described herein.

0083The maximum number of bits that make up a signature is equal to the number of possible challenge words multiplied by the base 2 logarithm of (N!) !. Table (1) shows that there are a large number of challenge words and thus signature bits. However, the latter allows the challenge word to share the same combination of bits (eg, if N = 3, the challenge word M1 = (0,1,2) becomes the challenge word M2 = (0,1,3). (Close), so it can be duplicated. This overlap remains low when choosing a combination of control words where there is a very large distance between them. Thus, this option can be performed, for example, with a distance constraint that the Hamming distance between one challenge word and N! Combinations of other words is greater than or equal to the minimum value. In the previous example, the distance between M1 and M2 is<maths num="7"><img id="000010" he="10" wi="55" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Is. If the minimum value selected is 2, one of these challenge words will be rejected.

0084The LPUF circuit can include a parity bit. In practice, one of the bits of the signature can be erroneously generated, especially due to the physical characteristics of the circuit after manufacture.

0085Parity bits are calculated by the circuit for all bits of the signature. One convention that can be used is to set the parity bit to "0" if the number of signature bits that is "1" is even.

0086This bit can be stored by using non-volatile memory. If an FPGA circuit is used, it is sufficient to have two configuration files that are unique to each value of the parity bit.

0087In order to reduce the probability of generating false signature bits, several measurements of a representative amount of signature bits, also called trials, may be made in succession by the LPUF measurement module for a particular control combination. After that, the values obtained by these trials are accumulated, and the signature bit is given by the sign of the accumulation result.

0088If the parity bit is related to the operation of the LPUF, the least reliable bit can be easily detected during the processing period corresponding to the trial.

0089Then, if it turns out that it does not follow parity, this bit can be easily modified by inversion.

0090This principle is shown in FIG. 8, where one of the curves 800 corresponds to the least reliable bit and the other curve corresponds to the more reliable bit of the signature. As previously described, once the measurement is finished, unreliable bits can be corrected if they do not follow parity.

0091LPUF features can be used to implement methods that allow to test and / or select integrated circuits with negligible probabilities of producing false signatures. Therefore, this method can improve the reliability of the use of LPUF, especially by disposing of unreliable circuits and also allowing them to be ranked by reliability level, and certain reliability. Circuits with levels can be used for certain family applications. This method may be applied at the end of the circuit manufacturing process, for example, to retain only the most reliable circuits.

0092Advantageously, this possibility of selecting the circuit makes it possible to save the trouble of executing the error correction code.

0093An object of the method of the present invention is, in particular, to discard circuits that have a probability of generating false signatures greater than a predetermined probability value.

0094An embodiment of this method is shown in the subsequent description. In this example, consider a circuit that includes an LPUF. The LPUF contains a lag chain of N = 2, and each signature bit has a frequency difference δ as previously defined._jEstimated from the measurement of.

0095By considering the population of circuits manufactured in exactly the same way, the variable δ_jIs zero mean and variance σ²Follow a Gaussian distribution with. That is, δ_j N (0, σ)²) (6) N (a, b) represents Gauss's law with mean a and variance b.

0096At the circuit level, δ_jEach measurement of is environmentally sensitive. Δ corresponding to the jth bit of the circuit signature_jThe measured value of<maths num="8"><img id="000011" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>And δ_jCentered on the variance s corresponding to the measurement noise²Follow a Gaussian distribution with. That is,<maths num="9"><img id="000012" he="13" wi="96" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0097δ_jThe value of is a reliable value for measurement<maths num="10"><img id="000013" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>To get, it needs to be from 0 as much as possible. P_{e, j}The probability of an error in bit j, described as, is, for example, a measured value.<maths num="11"><img id="000014" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>The sign of is the expected value δ_jMatches a probability different from the sign of. This probability can be expressed using the following equation:<maths num="12"><img id="000015" he="18" wi="97" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>In the equation, the function erf () is a Gaussian error function.

0098Figure 7 shows an example of a graph showing this error. P_{e, j}Is<maths num="13"><img id="000016" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Corresponds to the region 701 corresponding to the integral between - and 0 with a probability density of 700.

0099Probability of this error P_{e, j}Is δ_jSignificant when is close to 0. It can actually be reduced by performing T trials in which the measurement results are accumulated. Therefore, T measurements<maths num="14"><img id="000017" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Is executed. P_{e, j}Can be expressed using the following formula:<maths num="15"><img id="000018" he="20" wi="110" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0100Therefore, if δ_jIf is low and greater than the threshold Th, then a significant number of T trials need to be applied if the desired error probability is low. By fixing the Th threshold, it has a certain error probability and is smaller than Th while following the number of trials to be executed._jIt is possible to exclude circuits with a value of. Th can be advantageously selected, taking into account unfavorable circumstances regarding circuit temperature and supply voltage.

0101Considering a circuit with M delay elements, each associated with one signature bit, in order for the circuit to fail, δ_jIt is sufficient if at least one bit j such as &lt;Th is present. Therefore, in this example, the probability that the test circuit will fail can be predicted using the following equation: P_rej= 1-[1-P (| δ)_i| &lt;Th)]^M (Ten) During the ceremony<maths num="16"><img id="000019" he="17" wi="108" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Is.

0102The above example corresponds to a control word with only a single bit j at N = 2 and a value of 1. The error probability is reduced when N&gt; 2 or when the control words contain several non-zero bits with a constant Hamming distance HD between them, as expressed by equation (12). ..

0103Therefore, the signature bit is correlated with an HD delay element that functions to generate the difference between the two frequency measurements. It measures δ_iIs equivalent to being considered to consist of the sum of the HD values of. Therefore, then<maths num="17"><img id="000020" he="18" wi="118" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>The result is.

0104Probability of failing the circuit as a result by increasing the Hamming distance HD between the control words used P_rejCan be reduced. B signature bits can be much larger than M. The defective product rate in this case is the same as the formula in which M is replaced with the effective number of bits B of the signature:<maths num="18"><img id="000021" he="22" wi="107" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>

0105The method according to the invention makes a series of measurements as many as T times, and then bit by bit the result of the measurements.<maths num="19"><img id="000022" he="10" wi="30" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Is accumulated. The values obtained from these trials are compared to one or more predetermined thresholds. The result of this comparison matches either a bit of the signature on which the trial was run, 0, 1, or an indeterminate value if no threshold is obtained (in which case the bit is considered indeterminate or unreliable) It becomes possible to decide whether to do it. An indefinite value is a value at which it is impossible to determine whether a bit is at "0" or "1". This technique makes it possible to improve the reliability of the measurement results used to generate the signature bit and, as a result, reduce the probability that this signature bit will be generated with an error.

0106If the control module of the LPUF stops the calculation of the given signature bit when a certain threshold is obtained, the measurement time can be optimized advantageously.

0107For N = 2, the measurement is, for example, the difference δ as previously defined._iCorresponds to. Thus, two thresholds may be selected and compared to the bit-by-bit total measurement of the signature, which correspond to, for example, the following values: --Th × T, in this regard, 1 is selected if the total measurement is greater than this value; --Th × T, in this regard, 0 is selected if the total measurement is smaller than this value.

0108When the accumulation of measurement results corresponding to a given bit of the circuit signature gets one of these thresholds, the measurement is stopped and a decision about the value of the bit is made.

0109The principles of continuous measurement and comparison with thresholds can be applied within the framework of circuit testing methods, but can also be applied by the circuit itself, as previously described.

0110For circuits that are considered reliable, convergence systematically occurs following the application of the test method according to the invention. The most reliable bits converge sharply and the least reliable bits require more measurement trials.

0111When this test method is applied to a circuit containing an LPUF containing a parity bit associated with a signature, the defective product rate can be significantly reduced. In practice, this test scheme is a circuit with unreliable signature bits, ie δ._j&lt;Th circuit is not rejected.

0112FIG. 9 shows an example of a combination of control words that can reduce the defective rate of circuits including LPUF and a comparison of frequency measurements associated with them. When N&gt; 2, it is possible to use temperature-independent measurements by using the ratio between frequency differences rather than the difference between measurements. The signature bits of the circuit are then estimated from the values of these ratios. FIG. 9 shows six possible combinations of the three control words (A, B, C) for N = 3.

0113In this case, the signature bit is, for example,<maths num="20"><img id="000023" he="15" wi="85" file="JP5877415B2_D0001.tif" img-format="tif" img-content="drawing" /></maths>Weighing Δ corresponding to_{i, j}Estimated from.

0114In this equation, the value δ_iAnd δ_jCorresponds to the difference in measured frequencies, and this difference is measured between two different combinations of control words.

0115Next, the LPUF control module weighs Δ_{i, j}Is determined, and the signature bit of the circuit is estimated from it. The example in Figure 9 is Δ_1,2If&gt; 0, the first bit b of the signature₀Is set to 1 and otherwise equal to 0. Similarly, Δ_3,4If&gt; 0, the second bit of the signature b₁Is set to 1 and otherwise equal to 0.

0116FIG. 10 shows an example of a method for testing a circuit according to the present invention.

0117The purpose of the first step 1000 of this method is to select the configuration parameters of the test. Therefore, the values of the previously defined parameters T and Th are selected, which affect the probability of selecting or failing the circuit, as well as the duration of the test. This setting step also makes it possible to select the B combination of control words so as to guarantee the Hamming distance HD between two combinations in this B combination set.

0118The purpose of the second step 1001 of this method is to determine the probability of a bit error as well as the probability of failing the test circuit. These two probabilities, on the one hand, take into account the parameters T and Th as selected during the setup step, and on the other hand, the variance of the measured noise s.²And measurement variance by processing variance σ²It is determined using, for example, equations (9) and (13), taking into account the measured value of 1002. Measurement of these dispersions can be performed by any measuring means known to those of skill in the art.

0119The determination of these probabilities makes it possible to advantageously adapt the values of the setting parameters according to the needs of the user.

0120The purpose of the third step 1003, referred to as the measurement phase, is to determine if the test circuit is considered reliable. If not, the circuit fails. This measurement phase applies to all circuits that the user decides to test. Therefore, the LPUF control module included in the circuit being tested has a frequency difference of δ._jIs set to apply the B combination of control words selected during the first step so that it can be measured. Several measurement trials are performed bit by bit in the signature so that they are cumulative and compared to one or more thresholds as described above.

0121If the LPUF does not have free parity bits, the circuit fails if one bit less is not considered reliable.

0122If the LPUF has a free-use parity bit, then a single bit of the signature is not considered reliable. The test circuit is not rejected and the value of the parity bit is on the signature thus generated. It is calculated against. The bits then allow the circuit to detect and correct errors in unreliable bits.

0123To optimize the reliability of this test scheme, distribute s²And σ²It should be noted that the measurement and the measurement phase of the above can also be performed advantageously under the conditions corresponding to the limit operating conditions of the test circuit. These situations correspond, for example, to a temperature substantially equal to + 70 ° C and a supply voltage substantially 5% lower than the nominal supply voltage of the test circuit.

0124FIG. 11 shows an example of a test system that implements the test method according to the present invention. The test system 1100 consists of, for example, a computer 1105 with a user interface 1104. The system also includes equipment item 1101, which allows control of measurement probes 1106,1107. These measurement probes are routed to electronic card 1102, which includes the electronic circuit 1103 to be tested, which circuit includes the LPUF. The system implements the test method as described above. The user interface 1104 also allows you to configure tests and view results.