Apparatuses and methods comprising a channel region having different minority carrier lifetimes

0001<Priority application> This application claims priority to US Application No. 13 / 21,01,033 filed August 16, 2011, which is incorporated herein by reference in its entirety.

0002Higher density memory devices are always in demand. Laterally forming a memory device on the surface of a semiconductor chip uses a large chip area. There is a need for improved memory devices with new configurations to further increase memory density beyond traditional memory devices.

0003<figref num="1A">A memory device according to an embodiment of the present invention is shown.</figref><figref num="1B">The block diagram of the memory string from FIG. 1A according to the embodiment of the present invention is shown.</figref><figref num="1C">A model of carrier generation in the operation of the memory string according to the embodiment of the present invention is shown.</figref><figref num="1D">A model of carrier generation in the operation of the memory string according to the embodiment of the present invention is shown.</figref><figref num="2">The potential-time graph for the channel region of the memory string according to the embodiment of the present invention is shown.</figref><figref num="3A">Another memory device according to the embodiment of the present invention is shown.</figref><figref num="3B">Another memory device according to the embodiment of the present invention is shown.</figref><figref num="4A">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4B">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4C">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4D">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4E">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4F">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4G">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4H">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="4I">A processing operation for a memory device according to an embodiment of the present invention is shown.</figref><figref num="5">An information handling system using a memory device according to an embodiment of the present invention is shown.</figref>

0004In the following detailed description of the present invention, references are made to the accompanying drawings forming a portion of the present application, wherein specific embodiments in which the present invention can be carried out are shown for explanation. These embodiments will be described in sufficient detail so that those skilled in the art can practice the present invention. Other embodiments may be utilized and logical, electrical changes, etc. may be made.

0005FIG. 1A shows a device in the form of a memory device 100 formed on a substrate 102. FIG. 1B shows the memory string 101 from FIG. 1A. Charge storage structure 112 (eg, combination of tunnel dielectric, polysilicon, and charge blocking material, combination of nitrides, oxides, and nitrides, or currently known or future developed charge storage functions. A combination of any other material that can be provided substantially surrounds the elongated channel region 110, as shown in FIG. 1B, with multiple memory cell gates 114, which also include the elongated channel region 110 and charge storage structure (which also includes the elongated channel region 110 and charge storage structure). It forms each charge storage structure corresponding to each of (s), which can substantially surround each cross section of 112. The charge storage structure may be a plurality of parts of each of a single structure, or may consist of a plurality of separate and separate structures.

0006The first selection gate 120 and the second selection gate 122 are shown to selectively connect the elongated channel region 110 to the source region 130 and the drain region 132, respectively. The dielectric 104 can fill the space between components such as those mentioned above.

0007In one example, the elongated channel region 110 is formed from a semiconductor material such as p-type and / or non-doped polysilicon. The elongated channel region 110 is formed by a polysilicon deposition activity different from that used by the first termination 111 to form other portions of the elongated channel region 110, such as the second termination 113 and / or intermediate portions. As such, it can be formed in multiple process activities. The source region 130 and the drain region 132 are shown connected to the first termination 111 and the second termination 113 of the elongated channel region 110, respectively. In one example, the source region 130 and the drain region include an n-type semiconductor material such as n + polysilicon.

0008During operation, a path with a source area 130, an elongated channel area 110, and a drain area 132 has selection gates 120, 122, and memory cell gates 114 that operate to enable (or impede) signal transmission along the way. Works as an npn transistor. The component comprises a source area 130, an elongated channel area 110, a drain area 132, selection gates 120, 122, a charge storage structure 112, and a memory cell gate 114, which together form a memory string 101. In one example, the memory string is configured in the circuit and operates as a NAND memory string.

0009The source line 126 and the data line such as the bit line 128 are shown connected to the source area 130 and the drain area 132, respectively. The source wire 126 and the bit wire 128 include, consist of, or consist of metals such as aluminum, copper, or tungsten, or alloys of these or other conductor metals. In the present disclosure, the term "metal" further includes metal nitrides, or other metals that primarily act as conductors.

0010FIG. 1B shows a block diagram of the memory string 101 from FIG. 1A. Some memory cell gates 114 shown in the figure are for illustration purposes only. In one example, the memory string 101 comprises eight memory cell gates 114 between the selection gates 120, 122.

0011The channel region 110 is located between the first recombination region 106 and the second recombination region 108 (and between the first recombination region and the second recombination region, as shown in FIGS. 1A and 1B. Body area) can be included. The first recombination region 106 and the second recombination region 108 can be formed as part of an elongated channel region 110 and of the same conductive type. In one example, the first recombination region 106 and the second recombination region 108 are configured to have a minority carrier lifetime that is lower than the minority carrier lifetime of the body region of the elongated channel region 110. In one example, the first recombination region 106 and the second recombination region 108 are formed in substantially similar configurations and have substantially the same minority carrier lifetime. In one example, the first recombination region 106 and the second recombination region 108 have different minority carrier lifetimes, both minority carrier lifetimes being lower than the minority carrier lifetimes of the body region of the elongated channel region 110.

0012Several configuration and associated formation processes are possible for the first recombination region 106 and the second recombination region 108. In one example, the first recombination region 106 and the second recombination region 108 are doped to a higher concentration than the body region 110, providing a lower minority carrier lifetime. In one example, the elongated channel region, which comprises a first recombination region 106 and a second recombination region 108, is doped with a p-type dopant. Examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, and indium.

0013An example of doping concentration is about 5x10¹⁸Atom / cm³Approximately 1 × 10 with a first recombination region 106 and a second recombination region 108 doped at or higher concentrations¹⁸Atom / cm³Contains the body region of the elongated channel region 110 doped to the concentration of. Higher doping concentrations in the first recombination region 106 and the second recombination region 108 result in lower minority carrier lifetimes than in the body region of the elongated channel region 110. Another example includes a non-doping elongated channel region 110 with a first recombination region 106 and a second recombination region 108 that are doped to a higher effective concentration than the non-doping body region 110.

0014The lower minority carrier lifetime in the outer region of multiple memory cell gates 114 should provide better selective isolation of the elongated channel region 110 during memory operation. For example, string 101 may be selected for erasing during the erasing operation. In this case, it is desirable that the other string 101 be isolated. Lower minority carrier lifetimes in the first recombination region 106 and the second recombination region 108 make it harder for charge to flow through unselected strings, and memory operation is more reliable with higher performance. Will be high.

0015FIG. 1C shows a model example of an elongated channel region 110, a recombination region 108, and a memory cell gate 114. The figure shows that in the collision ionization region, the carrier generation is maintained by the potential drop for the unselected strings in the erasing operation and the like during the suppression condition. Without the application of embodiments of the invention, the boosted channel can lose its potential in a short period of time. For example, FIG. 1D shows the channel region potential 154 for devices that do not have a recombination region. As can be seen from the figure, the channel region potential 154 decreases with time. It is known that the channel region potential 152 is maintained in the same period by using the dopant processing example according to the embodiment of the present invention.

0016Other configuration and associated formation processes for the first recombination region 106 and the second recombination region 108 include strain engineering and selection of alternative materials. In the strain engineering example, impurity elements that may or may not contain dopant elements are injected into the lattice within the first recombination region 106 and the second recombination region 108. Will be or will be introduced separately. The strain provided to the lattice by the addition of the impurity element (s) modifies the region (ie, results in a region with a lattice strain state different from the body region), which is more than the body region of the elongated channel region 110. It provides a region with a low minority carrier life.

0017In the alternative material example, the first recombination region 106 and the second recombination region 108 are formed from a different semiconductor material than that used to form the body region of the elongated channel region 110. Different properties of the material choice result in lower minority carrier lifetimes at recombination regions 106, 108 than in the body region of the elongated channel region 110. Figure 1D shows a model example of an example in which the material is devised. As can be seen, the channel region potential 150 for the material-developed example is shown to be maintained over time.

0018In one example, the first recombination region 106 and the second recombination region 108 are at least from their respective positions inside the selection gates 122 and 120 (for region 106) and / or to individual locations (of region 108). If) stretch. FIG. 1B shows an example in which the first recombination region 106 and the second recombination region 108 extend from and / or the edges of the selection gates 122 and 120, respectively.

0019FIG. 2 shows the memory string 201. The memory string 201 includes a source area 230 and a drain area 232 to which an elongated channel area 210 is connected. Several memory cell gates 214 are shown adjacent to the elongated channel region 210 and separated from the elongated channel region 210 by several charge storage structures 212. The first selection gate 220 is located at the first termination 211 of the elongated channel region 210, and the second selection gate 222 is located at the second termination 213 of the elongated channel region 210.

0020The elongated channel region 210 comprises a first recombination region 206 and a second recombination region 208 (and an elongated body region between the first and second recombination regions 206, 208). In one example, the first recombination region 206 and the second recombination region 208 extend from and / or to their respective positions in front of and / or beyond the edges of the selection gates 220, 222, respectively. In the example shown in FIG. 2, the first recombination region 206 extends from a position in front of the edge of the selection gate 220 (eg, it extends from the edge 216 of the memory cell gate 214) and the second. The recombination region 208 extends beyond the edge of the selection gate 222 (eg, it extends to another edge 217 of the memory cell gate 214).

00211A, 1B, and 2 illustrate vertically oriented memory strings. Other configurations are also possible, including horizontal and "U" shapes. 3A and 3B illustrate examples of "U" shaped memory strings. FIG. 3A shows a memory string 300 with source area 332 and drain area 334 with several memory cell gates 314 located along the length of the elongated channel area 310 and the elongated channel area 310 connected between them. .. In the configuration shown, the source region 332 and the drain region 334 are facing upwards and the elongated channel region 310 forms a "U" shape.

0022In FIG. 3A, the elongated channel region 310 comprises a first recombination region 306 and a second recombination region 308 (and a body region in between). In one example, the first recombination region 306 and the second recombination region 308 are different material selections than those used to form the body region of higher concentrations of doping, strain engineering, or elongated channel regions 310. Is formed as described above using.

0023FIG. 3A shows a first recombination region 306 and a second recombination region 308 extending from each edge of the first selection gate 320 and the second selection gate 322, respectively. FIG. 3B shows a first recombination extending from a position in front of each edge of the first selection gate 320 and the second selection gate 322 (eg, extending from the edge 360 of some gates 314, respectively). Shown is a similar memory string 350 with region 356 and a second recombination region 358.

0024As described in connection with the above figure, several different configurations of memory strings such as vertical, horizontal, and "U" shapes are possible. Figures 4A-4I below illustrate examples of processes that can be used to form vertical memory strings. This process, in combination with other configurations, can be used as a general guideline for forming the aforementioned configurations.

0025FIG. 4A shows the formation of an n-type doped region 404 on a portion of substrate 402. In one example, a portion of substrate 402 forms a source line. In one example, the n-type doped region 404 is heavily doped so that it is n +. In FIG. 4B, the dielectric layer 405 is formed and the polysilicon 406 layer is formed.

0026In FIG. 4C, the polysilicon 406 is patterned and etched to form an opening 408 that partially isolates the polysilicon 406. In FIG. 4D, a first recombination region 410 is formed through a portion of polysilicon 406 that forms the first selection gate 416. In one example, the first recombination region 410 is deposited as doped polysilicon. In another example, the material for the first recombination region 410 is deposited and subsequently doped by diffusion, ion implantation, or other doping methods. In one example, the first recombination region 410 is heavily doped to p +. In one example, the first recombination region 410 is about 5 × 10.¹⁸Atom / cm³Includes the dopant concentration of.

0027In one example, the first recombination region 410 is formed by strain engineering. An example of strain engineering is the formation of a polysilicon structure and the injection of impurity elements that distort the lattice in the first recombination region 410 to correct the minority carrier lifetime in the first recombination region 410. Or it includes forming together differently.

0028In one example, the first recombination region 410 is formed from a material having a minority carrier lifetime lower than the body region 412 of the subsequently formed elongated channel region. In one example, the material selection for the first recombination region 410 includes non-silicon semiconductors such as gallium arsenide and germanium.

0029In the example shown in FIG. 4D, the first recombination region 410 extends from the doped region 404 through polysilicon 406 to the edge of the first selection gate 416. In another example, as shown in FIG. 2, the first recombination region 410 extends beyond the edge of the first selection gate 416 to the edge of some memory cell gates. In many embodiments, the first recombination region 410 is part of an elongated channel region formed in multiple processing operations.

0030FIG. 4E shows the formation of the body region 412 of the elongated channel region and the formation of several memory cell gates 414 along the length of the body region 412 of the elongated channel region. In one example, the body region 412 is doped in type p, but in other examples it may be doped differently or undoped. In one example, area 412 is about 1x10¹⁸Atom / cm³Includes p-type dopant concentration. As mentioned above, the body region 412 is part of an elongated channel region formed in multiple processing operations.

0031FIG. 4F shows the formation of another polysilicon layer 418. In FIG. 4G, the polysilicon layer 418 is patterned and etched to form a second selection gate 420. In the example shown, each second selection gate 420 is dedicated to a separate memory string 422, while the first selection gate 416 is shared by two adjacent strings 422. Other examples include a combination of a shared second selection gate 420 and an individual first selection gate 420, depending on the requirements of the memory device configuration.

0032In FIG. 4H, the second recombination region 424 is formed through the second selection gate 420. Like the first recombination region 410, in one example, the second recombination region 424 is deposited as doped polysilicon. In another example, the material for the second recombination region 424 is deposited and subsequently doped by diffusion, ion implantation, or other doping methods. In one example, the second recombination region 424 is heavily doped to p +. In one example, the second recombination region 424 is about 5 × 10.¹⁸Atom / cm³Includes the dopant concentration of. Other examples such as strain engineering, or material selection as in the case of the first recombination region 410, can be used within the second recombination region 424 and are lower minority carriers than the body region 412 of the elongated channel region. Provides life.

0033In the example shown in FIG. 4H, the second recombination region 424 extends from the edge of the second selection gate 420. In another example, as shown in FIG. 2, the second recombination area 424 extends from the edges of some memory cell gates 414. As mentioned above, the second recombination region 424 is part of an elongated channel region formed in multiple processing operations.

0034In FIG. 4I, an n-type doped region 426 is formed to connect to the second recombination region 424. In embodiments where the elongated channel region is a p-type doped region, an n-type doped region 426, an elongated channel region (second recombination region 424, body region 412, and first recombination region 410). The n-type doped region 404 forms an npn junction that acts as a memory string. Finally, in FIG. 4I, a data line 428 (eg, a bit line) is formed and connected to the memory string to form a memory device.

0035An embodiment of a device in the form of an information handling system such as a computer is included in FIG. 5 and shows an embodiment for the present invention of high level device application. FIG. 5 is a block diagram of an information handling system 500 incorporating one or more memory devices 507 according to the embodiment of the present invention described above. The information handling system 500 is merely an embodiment of an electronic system in which the memory device of the present invention can be used. Other examples include, but are not limited to, tablet computers, cameras, personal digital assistants (PDAs), mobile phones, MP3 players, aircraft, satellites, military vehicles, and the like.

0036In this example, the information handling system 500 includes a data processing system including a system bus 502 that connects various components of the system. System bus 502 provides communication links between the various components of the information handling system 500 and can be implemented in a single bus, a combination of buses, or any other suitable method.

0037The chip assembly 504 is connected to the system bus 502. Chip assembly 504 may include any circuit or any operably compatible combination of circuits. In one embodiment, the chip assembly 504 comprises a processor 506 which can be of any kind. As used herein, "processor" includes, but is not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processor circuit. Means.

0038In one embodiment, the memory device 507 is contained within the chip assembly 504. In one embodiment, the memory device 507 includes a memory device such as a NAND memory device according to the embodiment described above. The memory device 507 formed by the process described herein is integrated as a separate device or chip (does not combine with the processor 506 and / or logic 508 to form part of the chip assembly 504) and is coupled to bus 502. May be done.

0039In one embodiment, the chip assembly 504 includes an additional logical chip 508 in addition to the processor chip. An example of another logic chip 508 of the processor comprises an analog-to-digital converter. In one embodiment of the invention, other circuits on the logic chip 508, such as custom circuits, application specific integrated circuits (ASICs), are also included.

0040The information handling system 500 may also include an external memory 511, which is one or more memory elements and / or compact discs (CDs) suitable for a particular application, such as one or more hard drives 512. It can include one or more drives that handle removable media 513, such as flash drives, digital video discs (DVDs), and equivalents. As described in the above example, the configured semiconductor memory die is included in the information handling system 500, probably as part of the memory 511.

0041The information handling system 500 may also include a display device 509 such as a monitor or touch screen, an additional peripheral component 510 such as a speaker, and a keyboard and / or controller 514, which are a mouse, touch screen, trackball, game controller. , Voice recognition devices, or any other device that allows a system user to enter and receive information from the information handling system 500.

0042The term "horizontal" as used in the present application is defined as a plane parallel to a conventional plane such as a wafer or die or the surface of a substrate, regardless of the orientation of the substrate. The term "vertical" refers to the orientation perpendicular to the horizontal as defined above. Prepositions such as "upper", "side" (found on the "side wall"), "higher", "lower", "upper", "lower" are substrates regardless of substrate orientation. Defined with respect to a conventional plane or surface on the top surface of the surface. The following detailed description is therefore not taken in a restrictive sense, and the scope of the invention is defined only by the appended claims, together with the entire scope of the equivalent to which such claims are entitled. The right.

0043Although some embodiments of the present invention have been described, the above enumeration is not intended to be exhaustive. Although specific embodiments have been described and described herein, it will be appreciated by those skilled in the art that any arrangement planned to achieve the same objective can replace the specific embodiments shown. Will be recognized. The present application is intended to include any adaptation or modification of the present invention. It is understood that the above description is intended to be descriptive and not intended to be restrictive. A combination of the above embodiments and other embodiments will be apparent to those skilled in the art upon reading the above description.