Data writing method and system

The present invention relates to a method of writing data to a flash memory and a system having the flash memory.

In a non-volatile semiconductor memory such as a flash memory, the reliability of the data is improved by storing the error correction code together with the data. The reliability of the data is further improved by rewriting the data of the block in which the error is corrected to another block (see, for example, Patent Document 1).

<p num="0003"><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2002-108722</text></patcit></p>

<p num="0004"> The error correction code is automatically generated by a memory control circuit or the like based on the write data. Therefore, the data processing device that writes the data to the flash memory cannot directly read the error correction code. Generally, in a flash memory, rewriting from logic 0 indicating a write state to logic 1 indicating an erase state cannot be performed. Therefore, for example, when the data storage area is erased and the bit of logic 0 exists in the error correction code storage area, the error correction code generated based on the write data is stored in the error correction code storage area. I can't write correctly. At this time, it cannot be determined whether the problem is due to the product life of the flash memory or the problem is due to the error correction code storage area not being erased. In order to prevent this problem, it is necessary to perform the erasing operation every time before writing the data for the first time for each block which is the erasing unit. As a result, the number of erasures increases and the product life is shortened.</p><p num="0005"> An object of the present invention is to reduce the number of block erasures and extend the product life in a flash memory having an error correction code storage area.</p>

<p num="0006"> In one form of the data writing method of the present invention, in the data writing method of writing data to the flash memory including the data storage area and the error correction code storage area, the initial value is written to the data storage area and the writing is performed based on the write flag. It is characterized by judging whether or not it was performed normally, writing data to the data storage area when writing is performed normally, and erasing the block containing the data storage area when writing is not performed normally. And.</p>

<p num="0007"> By writing the initial value to the data storage area before writing the data, it is possible to confirm whether or not the error correction code storage area is the initial value. By performing the block erasing operation only when the error correction code storage area is not the initial value, the number of times the block is erased can be reduced and the product life can be extended.</p>

<figref num="1">An example of the system in one embodiment is shown.</figref><figref num="2">An example of the system in another embodiment is shown.</figref><figref num="3">An example of the data structure of the flash memory block shown in Fig. 2 is shown.</figref><figref num="4">An example of the operation of writing data to the flash memory shown in Fig. 2 is shown.</figref><figref num="5">An example of the processing executed by the flash memory control circuit in the writing operation shown in FIG. 4 is shown.</figref>

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows an example of the system SYS in one embodiment. The system SYS (user system) constitutes at least a part of a microcomputer system such as a mobile device.

For example, the system SYS has a non-volatile semiconductor memory such as a CPU (Central Processing Unit), a flash memory control circuit MCNT, and a flash memory FLASH. The CPU operates, for example, by executing a program stored in the ROM built into the CPU, and flashes to read and write data to the flash memory FLASH or to erase data held in the flash memory FLASH. Memory control circuit Controls MCNT. The flash memory control circuit MCNT controls the flash memory FLASH to execute the read operation, the write operation, and the erase operation of the flash memory FLASH based on the instruction from the CPU.

The flash memory FLASH has at least one block BLK including a data storage area DATAA and an error correction code storage area ECCA, and a write flag WFLG. For example, the write flag WFLG is formed by a latch circuit. The data storage area DATAA holds the data DATA supplied from the CPU. The error correction code storage area ECCA holds an error correction code ECC for error correction of the data written in the data storage area DATAA. The error correction code ECC is generated by the flash memory control circuit MCNT based on the data DATA supplied from the CPU. A plurality of sets of data storage area DATAA and error correction code storage area ECCA may be formed in the block BLK. Moreover, a plurality of blocks BLK may be formed. For example, a block BLK is a unit that executes an erase operation. The write flag WFLG holds information on whether or not the data DATA and the error correction code ECC were normally written to the data storage area DATAA and the error correction code storage area ECCA in the write operation.

For example, the data storage area DATAA and the error correction code storage area ECCA are 32 bits and 7 bits, respectively. The error correction code storage area ECCA may be formed by 8 bits including a 1-bit unused area, and the data DATA and the error correction code ECC may be stored using 40 bits (5 bytes). For example, the data storage area DATAA and the error correction code storage area ECCA are formed by a plurality of memory cells having memory transistors including a floating gate. Therefore, the data DATA and the error correction code ECC written in the data storage area DATAA and the error correction code storage area ECCA are retained without being lost even when the flash memory FLASH is not supplied with power.

For example, the data storage area DATAA and the error correction code storage area ECCA indicate logic 1 in the erased state and are changed to logic 0 by the write operation. The data storage area DATAA and error correction code storage area ECCA set to logical 0 cannot be changed to logical 1 on a bit-by-bit basis. At this time, the data held in the data storage area DATAA and the error correction code storage area ECCA must be collectively erased in logical 1 in block BLK units.

When the flash memory control circuit MCNT receives a write operation instruction from the CPU, it generates an error correction code ECC corresponding to the write data DATA, and writes the write data DATA and the error correction code ECC to the flash memory FLASH. The write operation is an operation of changing a predetermined bit of the data storage area DATAA and the error correction code storage area ECCA from logical 1 to logical 0. The flash memory FLASH sets the write flag WFLG to a value indicating normality when the write data DATA and the error correction code ECC can be normally written to the data storage area DATAA and the error correction code storage area ECCA. The flash memory FLASH sets the write flag WFLG to a value indicating an error when the write data DATA and the error correction code ECC cannot be written to the data storage area DATAA or the error correction code storage area ECCA.

Whether or not the writing operation can be performed normally is determined by, for example, a verification operation automatically performed in the flash memory FLASH during the writing operation. In the write operation, a program operation for programming the memory cell to logical 0 and a verification operation for confirming that the memory cell is set to logical 0 are executed in order. A write error is detected when logic 0 cannot be confirmed in the final verify operation after the program operation and the verify operation have been performed a predetermined number of times (at least once). For example, a write error occurs when logic 1 is written to a bit set to logic 0 in the data storage area DATAA or the error correction code storage area ECCA. At this time, the write flag WFLG is set to a value indicating an abnormality.

When the flash memory control circuit MCNT receives a read operation instruction from the CPU, it reads the data DATA from the data storage area DATAA and outputs the read data DATA to the CPU. When the flash memory control circuit MCNT detects that there is an error in the read data DATA, it corrects the error by using the error correction code ECC read together with the data DATA, and outputs the corrected data DATA to the CPU. Note that the CPU cannot access the error correction code storage area ECCA and cannot read the error correction code ECC.

The flash memory control circuit MCNT causes the flash memory FLASH to execute the erasing operation when the CPU instructs the erasing operation. In the erase operation, all the values held in the data storage area DATAA and the error correction code storage area ECCA in the block BLK instructed to be erased are set to logical 1.

When the flash memory control circuit MCNT receives an instruction for the first write operation from the CPU after the erase operation, the flash memory control circuit MCNT writes the initial value to the data storage area DATAA before writing the data DATA. For example, the initial value is a value (erased state) in which all bits of the data storage area DATAA indicate logic 1. Therefore, the data held in the erased data storage area DATAA and the error correction code storage area ECCA does not change due to the writing of logic 1.

In the flash memory FLASH, when the initial value is received in the write operation, all bits of the data DATA held in the data storage area DATAA and the error correction code ECC held in the error correction code storage area ECCA are logical 1. Make sure that. Then, the flash memory FLASH sets the write flag WFLG to a value indicating normality. In other words, when the write flag WFLG indicates normal, it is confirmed that the erase state of the error correction code storage area ECCA is normal. The flash memory control circuit MCNT recognizes that the write result of the initial value is normal by reading the value of the write flag WFLG, and writes the data DATA received from the CPU to the flash memory FLASH.

On the other hand, the flash memory FLASH receives an initial value in the write operation, and when it is confirmed that at least one bit of the data DATA and the error correction code ECC is logical 0, the write flag WFLG is set to a value indicating an abnormality. For example, when the power supplied to the flash memory FLASH is cut off during the erasing operation, some bits of the error correction code storage area ECCA may not be set to logic 1. If the error correction code ECC is written to the error correction code storage area ECCA including logic 0, the correct error correction code ECC may not be written.

For example, when "101 0101" is written to the error correction code storage area ECCA in which "111 1110" is set in binary, logic 1 is about to be written to the 7th bit (rightmost bit) of logic 0. .. At this time, due to a write error, a value indicating the error is written to the write flag WFLG. However, the flash memory control circuit MCNT cannot determine whether the abnormality is due to improper erasure or the life of the flash memory FLASH. Here, the life of the flash memory FLASH is a hardware failure that occurs when the number of erases exceeds the upper limit value.

The flash memory control circuit MCNT can recognize that the write result of the initial value is abnormal by reading the write flag WFLG after writing the initial value. As a result, it can be confirmed that the error correction code storage area ECCA is not in the erased state. In other words, it is possible to identify that the cause of the abnormality is not the product life. After that, the flash memory control circuit MCNT executes an erase operation of the block BLK instructed to write the initial value in order to set the error correction code storage area ECCA to the erase state. After the erasing operation, the flash memory control circuit MCNT writes the data DATA received from the CPU to the block BLK.

As described above, in this embodiment, it is possible to confirm whether or not the error correction code storage area ECCA is the initial value by writing the initial value to the data storage area DATAA before writing the data DATA. By performing the erase operation of the block BLK only when the error correction code storage area ECCA is not the initial value, the number of times the block BLK is erased can be reduced and the product life can be extended.

Although FIG. 1 shows an example in which the write flag WFLG is formed in the flash memory FLASH, the write flag WFLG may be formed in the flash memory control circuit MCNT. At this time, in the writing operation, the flash memory control circuit MCNT reads the error correction code ECC held in the error correction code storage area ECCA. Then, the flash memory control circuit MCNT determines whether or not the writing operation is normally completed.

Further, the CPU may have the function of the flash memory control circuit MCNT. At this time, the CPU executes the instruction of writing the initial value to the flash memory FLASH, confirming the write flag WFLG, and erasing after writing the initial value.

FIG. 2 shows an example of system SYS in another embodiment. The same elements as those described in the above-described embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The system SYS (user system) constitutes at least a part of a microcomputer system such as a mobile device. The system SYS may be formed by integrating a plurality of macros on a silicon substrate, or may be formed by mounting a plurality of chips on a package substrate.

For example, the system SYS has a CPU, ROM, RAM, a flash memory control circuit MCNT and a flash memory FLASH. The CPU, ROM, RAM and flash memory control circuit MCNT are connected to each other by the system bus SBUS. The flash memory control circuit MCNT and the flash memory FLASH are connected to each other by a dedicated bus. For example, the bit width N of the data on the dedicated bus is 16 bits. The flash memory control circuit MCNT has an error correction code generation circuit ECCG that calculates an error correction code ECC for correcting an error of data read from the flash memory FLASH based on the write data. The CPU may be provided with the function of the flash memory control circuit MCNT, and the data on the flash memory FLASH may be directly accessed by the CPU without going through the flash memory control circuit MCNT.

The CPU accesses the ROM and RAM, and also accesses the flash memory FLASH via the flash memory control circuit MCNT to control the operation of the entire system. The flash memory FLASH executes a write operation, a read operation, and an erase operation in response to an access request from the flash memory control circuit MCNT that operates according to an instruction from the CPU. Although not particularly limited, the flash memory FLASH has a plurality of blocks BLK (BLK0, BLK1, ..., BLKn). For example, the ROM stores the program PGM executed by the CPU and the data used by the program PGM. For example, RAM temporarily stores data used in the program PGM. An example of block BLK is shown in Figure 3.

FIG. 3 shows an example of the data structure of the blocks BLK0-BLKn of the flash memory FLASH shown in FIG. Since the data structure of each block BLK0-BLKn is the same, block BLK0 will be described.

Block BLK0 has a plurality of data storage areas DATAA and a plurality of error correction code storage areas ECCA corresponding to the data storage area DATAA, respectively. Each data storage area DATAA has a 16-bit wide data area DATAD and a 16-bit wide DATAU. That is, the bit width of the data storage area DATAA is 32 bits. In the following description, the data DATA stored in the data areas DATAD and DATAU will also be referred to as DATAD and DATAU.

In this example, the data written from the CPU to the flash memory FLASH and the data read from the flash memory FLASH to the CPU are, for example, 16 bits. That is, the CPU inputs / outputs data DATAD or data DATAU by one write operation or one read operation. The CPU may read 8-bit, 16-bit, or 32-bit data from the flash memory FLASH via the memory controller MCNT. The address AD of the data storage area DATAA is assigned every 1 byte (8 bits). On the other hand, the address DTAD in units of the 32-bit width data storage area DATAA is assigned every 4 bytes. That is, one address DTAD is assigned to the 32-bit width data storage area DATAA. The numbers after the data areas DATAD and DATAU indicate the address DTAD.

The error correction code storage area ECCA is formed corresponding to a pair of data areas DATAD and DATAU. Each error correction code storage area ECCA holds the error correction code ECC (ECC0, ECC1, ... ECCm) of the 32-bit data DATAD and DATAU written in the corresponding data areas DATAD and DATAU. Similar to FIG. 1, the error correction code ECC cannot be accessed by the CPU, but only by the flash memory control circuit MCNT.

For example, each error correction code storage area ECCA is assigned to an address AD different from the data storage area DATAA. Each error correction code storage area ECCA may be assigned to the same address AD as the data storage area DATAA.

FIG. 4 shows an example of data writing operation to the flash memory FLASH shown in FIG. FIG. 4 shows the operation when it is known that the data storage area DATAA and the error correction code storage area ECCA of the block BLK for writing the data of the flash memory FLASH are all erased by the logic 1. The CPU sequentially outputs the data DATAD0 and DATAU0 to the flash memory control circuit MCNT in order to write the 32-bit data DATAD0 and DATAU0 to the flash memory FLASH (Fig. 4 (a, b)).

The flash memory control circuit MCNT writes the first 16-bit data DATAD0 supplied from the CPU to the data area DATAD0 of the flash memory FLASH (Fig. 4 (c)). Next, the flash memory control circuit MCNT writes the hexadecimal number FF to the error correction code storage area ECCA corresponding to the data area DATAD0 (Fig. 4 (d)). Next, the flash memory control circuit MCNT writes the next 16-bit data DATAU0 supplied from the CPU to the data area DATAU0 of the flash memory FLASH (Fig. 4 (e)).

After that, the flash memory control circuit MCNT calculates the error correction code ECC of the 32-bit data DATAD0 and DATAU0 supplied from the CPU (Fig. 4 (f)). Next, the flash memory control circuit MCNT writes the calculated error correction code ECC to the error correction code storage area ECCA corresponding to the data area DATAD0 (Fig. 4 (g)). This completes the writing of the 32-bit data DATAD0, DATAU0 and the error correction code ECC to the flash memory FLASH.

When the flash memory control circuit MCNT writes the data DATAD (or DATAU) to the flash memory FLASH, the flash memory control circuit MCNT also performs a write operation for the error correction code storage area ECCA following the writing of the data DATAD (or DATAU). Therefore, when writing the first data DATAD in which the error correction code ECC cannot be calculated, the dummy (hexadecimal number FF) error correction code ECC is written to the error correction code storage area ECCA. By patterning the write control to the flash memory FLASH in this way, the circuit and operation of the flash memory control circuit MCNT can be simplified.

FIG. 5 shows an example of the processing performed by the flash memory control circuit MCNT in the writing operation shown in FIG. The processing of FIG. 5 may be realized by the hardware formed in the flash memory control circuit MCNT, or may be realized by the program executed by the flash memory control circuit MCNT.

First, in step S100, the flash memory control circuit MCNT receives write data DATAD from the CPU. Next, in step S102, the flash memory control circuit MCNT determines whether or not the write data DATAD is written for the first time after the erase operation of the corresponding block BLK. When the first write operation to the data area DATAD is performed after the erase operation of the block BLK, the process proceeds to step S104. If the write operation has already been performed after the block BLK erase operation, the process proceeds to step S112.

For example, the presence or absence of a write operation is determined by reading the value of the erase confirmation flag provided for each block BLK. The erase confirmation flag is set to logic 1 after the erase operation of the corresponding block BLK, and is set to logic 0 when the write operation is performed for the first time after the erase operation of the block BLK. The erasure confirmation flag may be formed in the flash memory control circuit MCNT or in the flash memory FLASH. When the erase confirmation flag is formed in the flash memory FLASH, one of the memory cells in each block BLK may be used.

In step S104, the flash memory control circuit MCNT writes "0xFFFF" as an initial value to the data area DATAD of the flash memory FLASH. Here, "0x" indicates a hexadecimal number. That is, "FFFF" (16 bits) is written in hexadecimal in the data area DATAD. The flash memory FLASH receives an instruction from the flash memory control circuit MCNT and executes a write operation of writing "FFFF" to the data area DATAD. At this time, the flash memory FLASH confirms that "FFFF" and "FF" are set in the data area DATAD and the error correction code storage area ECCA by the verify operation, respectively.

When the values of the data area DATAD and the error correction code storage area ECCA are "FFFF" and "FF", respectively, the flash memory FLASH sets the write flag WFLG to the value indicating normality. When the value of the data area DATAD is not "FFFF" or the value of the error correction code storage area ECCA is not "FF", the flash memory FLASH sets the write flag WFLG to the value indicating an error. When the data DATAD and DATAU are stored in the plurality of data storage areas DATAA shown in FIG. 3, the initial value "0xFFFF" is written to all the data areas DATAD to be used.

Next, in step S106, the flash memory control circuit MCNT reads the value of the write flag WFLG. In step S108, when the write flag WFLG shows a normal value, the flash memory control circuit MCNT determines that the writing of the initial value "FFFF" is successful, and performs the process of step S112. When the write flag WFLG shows an abnormal value, the flash memory control circuit MCNT determines that writing of the initial value "FFFF" has failed, performs the process of step S110, and then performs the process of step S112.

In step S110, the flash memory control circuit MCNT causes the block BLK including the data area DATAD in which the initial value "FFFF" is written to perform the erasing operation. By the erase operation, all data storage areas DATAA and all error correction code storage areas ECCA in the block BLK are set to logic 1.

In step S112, the flash memory control circuit MCNT performs the processing of the write operation shown in FIG. As described above, when the power supplied to the flash memory FLASH is cut off during the erasing operation, some bits of the error correction code storage area ECCA may not be set to logic 1. By writing the initial value "0xFFFF" to the data area DATAD in step S104, it can be easily confirmed that all the bits of the error correction code storage area ECCA are set to logic 1. As a result, the erase operation of the block BLK can be performed only when the error correction code storage area ECCA is not normal. As a result, the number of times the block BLK is erased can be reduced, and the product life can be extended.

As described above, even in this embodiment, the same effect as that of the above-described embodiment can be obtained. When the CPU includes the function of the flash memory control circuit MCNT, the process shown in FIG. 5 may be executed by the CPU.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. In addition, a person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention of limiting the scope of the embodiments having invention to the above-mentioned embodiments. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

AD .. address; BLK .. block; DATA .. data; DATA A .. data storage area; DATAD, DATA U .. data area; DTAD .. address; ECC .. error correction code; ECCA .. error correction code storage area FLASH .. flash memory; MCNT .. flash memory control circuit; SYS .. system; WFLG .. write flag