Light-emitting element, light-emitting element unit, and light-emitting element package

0001The present invention relates to a light emitting element, a light emitting element unit including the light emitting element, and a light emitting element package in which the light emitting element unit is covered with a resin package.

0002A semiconductor light emitting device according to one prior art is disclosed in Patent Document 1. In this semiconductor light emitting device, an n-GaN layer is laminated on a sapphire substrate from which light is extracted. A light emitting layer is laminated on the n-GaN layer, and a p-GaN layer, a reflective electrode, a p electrode, a barrier layer and an AuSn layer are further laminated on the light emitting layer in this order from the sapphire substrate side. Has been done. On the other hand, the end region of the p-GaN layer and the light emitting layer is partially removed to expose the end region of the n-GaN layer, and the exposed end region of the n-GaN layer is laid on the light emitting layer. The n electrodes are laminated in a separated and insulated state. A barrier layer and an AuSn layer are laminated on the n electrode in this order from the sapphire substrate side. Each of the AuSn layer on the n-electrode and the AuSn layer on the p-electrode is joined to the wiring board. When a voltage is applied between the n electrode and the p electrode in this state, light is generated from the light emitting layer and taken out from the sapphire substrate.

<p num="0003"><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2008-263130</text></patcit></p>

<p num="0004"> In a configuration in which the n electrode is directly laminated on the n-GaN layer as in the semiconductor light emitting device of Patent Document 1, it is necessary to increase the contact portion in order to reduce the contact resistance between the n electrode and the n-GaN layer. .. Therefore, it is necessary to secure a certain amount of space for arranging the n electrodes on the n-GaN layer. As a result, the area where the light emitting layer can be arranged is eroded and narrowed. Therefore, it is difficult to improve the luminous efficiency because the light emitting layer cannot be enlarged.</p><p num="0005"> Moreover, according to the research of the inventor of the present application, since the current tends to flow through the shortest path between the p electrode and the n electrode, the structure of Patent Document 1 in which the n electrode is formed in the end region , The current cannot be sufficiently dispersed. Therefore, only the region near the n electrode emits light, and the entire light emitting layer cannot be uniformly illuminated. In order to solve this problem, the inventor of the present application examined the structure of an exposed n-type semiconductor layer having an end region and a plurality of branches extending from the end region, and an n electrode arranged on the exposed n-type semiconductor layer.</p><p num="0006"> However, in such an electrode structure, it was found that the light emitting layer is further eroded, the area of the light emitting layer is reduced, and the luminous efficiency is deteriorated because the branch portion of the n electrode is arranged. More specifically, as the area of the light emitting layer is reduced, the current density in the light emitting layer becomes higher, so that a loss occurs in the light output due to the droop phenomenon. The droop phenomenon is a phenomenon in which the emission recombination probability decreases due to heat generation due to current concentration, and the internal luminous efficiency deteriorates.</p><p num="0007"> Therefore, the present invention provides a light emitting element capable of overcoming the above-mentioned technical problems and improving luminous efficiency, a light emitting element unit including the light emitting element, and a light emitting element package in which the light emitting element unit is covered with a resin package. To do.</p>

<p num="0008"> The light emitting element of the present invention has a first conductive semiconductor layer (first conductive semiconductor layer) having a stepped portion formed at an end thereof, and a region other than the stepped portion on the first conductive semiconductor layer. On the light emitting layer laminated on the light emitting layer, the second conductive type semiconductor layer laminated on the light emitting layer (the second conductive type semiconductor layer different from the first conductive type), and the second conductive type semiconductor layer. A transparent electrode layer that is laminated and transparent to the emission wavelength of the light emitting layer, a reflective electrode layer that is laminated on the transparent electrode layer and reflects light transmitted through the transparent electrode layer, and a reflective electrode layer. The laminated insulating layer, the first electrode layer laminated on the insulating layer, the second electrode layer laminated on the insulating layer in a state of being separated and insulated from the first electrode layer, and the first electrode layer. The conductive semiconductor layers are arranged discretely in a plan view from the thickness direction of the conductive semiconductor layer, and continuously penetrate the reflective electrode layer, the transparent electrode layer, the second conductive semiconductor layer, and the light emitting layer from the insulating layer. A plurality of insulating tube layers that reach the first conductive semiconductor layer, and a first layer that is continuous from the first electrode layer and connected to the first conductive semiconductor layer through the insulating layer and the insulating tube layer. The first contact, the second contact continuous from the second electrode layer, penetrating the insulating layer and connected to the reflective electrode layer, and the light emitting layer in the plan view as a part of the insulating layer. 2 Includes an extension portion that covers the outer end faces of the conductive semiconductor layer, the transparent electrode layer, and the reflective electrode layer, and the stepped portion of the first conductive semiconductor layer.<u style="single">The first electrode layer includes a second reflective electrode layer that is in contact with the insulating layer and has the first contact and reflects light transmitted through the insulating layer, and the insulating layer is the reflective electrode. The layers are laminated on the reflective electrode layer so as to cover all but the insulating tube layer and the opening by the second contact in the plan view.</u>(Claim 1).</p><p num="0009"> Specifically, "transparent to the emission wavelength" means, for example, a case where the transmittance of the emission wavelength is 60% or more. According to this configuration, the first electrode layer on the insulating layer is relative to the insulating layer, the reflective electrode layer, the transparent electrode layer, the second conductive semiconductor layer, and the first conductive semiconductor layer separated by sandwiching the light emitting layer. , Connected via the first contact. The first contact is separated and insulated from the reflective electrode layer, the transparent electrode layer, the second conductive semiconductor layer, and the light emitting layer by passing through the insulating tube layer. The second electrode layer on the insulating layer is connected to the reflective electrode layer under the insulating layer via the second contact.</p><p num="0010"> When a voltage is applied between the first electrode layer and the second electrode layer, a current can flow between the second electrode layer and the first electrode layer. As a result, one of the carriers of electrons and holes is supplied to the light emitting layer from the second electrode layer through the second contact, the reflective electrode layer, the transparent electrode layer and the second conductive semiconductor layer, and the first The other carrier is supplied to the light emitting layer from the electrode layer through the first contact and the first conductive semiconductor layer. This causes light emission due to carrier recombination in the light emitting layer. For example, most of the generated light is taken out through the first conductive semiconductor layer, and some light is transmitted through the second conductive semiconductor layer and the transparent electrode layer in order, and then reflected with the transparent electrode layer. After being reflected at the interface with the electrode layer, it is taken out from the first conductive semiconductor layer side.</p><p num="0011"> Since the plurality of insulating tube layers are arranged discretely in a plan view, there are also a plurality of first contacts passing through the insulating tube layers and are arranged discretely. In this case, the first electrode layer and the first conductive semiconductor layer are separated from each other, but are connected via a plurality of discretely arranged first contacts, so that the first electrode layer is the first conductive semiconductor layer. A current can flow smoothly between the first electrode layer and the first conductive semiconductor layer as in the case of being directly laminated on the top.</p><p num="0012"> Then, a plurality of first contacts discretely arranged as compared with the contact area between the first electrode layer and the first conductive semiconductor layer when the first electrode layer is directly laminated on the first conductive semiconductor layer. The contact area between the and the first conductive semiconductor layer can be kept small. This is because the first contacts are discretely arranged, so that even if the total contact area is small, the current can be easily dispersed over a wide area range and the light can be efficiently emitted over a wide range. As a result, it is possible to prevent the region for arranging the light emitting layer in the first conductive semiconductor layer from being eroded by the configuration for connecting the first electrode layer and the first conductive semiconductor layer. Therefore, in the light emitting element, since the area of the light emitting layer can be increased, the current density in the light emitting layer can be suppressed, and the light emitting efficiency can be improved accordingly.<u style="single">Further, the light reflection efficiency is improved by reflecting the light transmitted through the insulating layer without being reflected by the reflective electrode layer (first reflective electrode layer) laminated on the transparent electrode layer by the second reflective electrode layer. It can be improved, and the light emitting efficiency of the light emitting element can be improved accordingly.</u></p><p num="0013"> It is preferable that the plurality of first contacts are evenly distributed in the plan view (claim 2). According to this configuration, the contact portion between the first contact and the first conductive semiconductor is evenly distributed over a wide range in the first conductive semiconductor layer, so that the current is evenly distributed over a wide range in the light emitting layer. .. As a result, the number of shining portions in the light emitting layer can be further increased, so that the luminous efficiency of the light emitting element can be further improved. In addition, carriers can be smoothly supplied from the first electrode layer to the first conductive semiconductor layer through the contact portions evenly distributed over a wide range.</p><p num="0014"> In order to disperse the plurality of the first contacts evenly in the plan view, the plurality of the first contacts have a distance between the one first contact and the other first contact closest to the first contact. It is preferable that they are arranged so as to be constant (claim 3). At this time, the interval is preferably 50 μm or more and 150 μm or less (claim 4). The plurality of first contacts are preferably arranged in a matrix (claim 5).</p><p num="0015"> It is preferable that the plurality of first contacts are arranged so as to be point-symmetrical with respect to the position of the center of gravity of the first electrode layer as a reference (center of symmetry) in the plan view (claim 6). The plurality of first contacts preferably include first edge-side contacts arranged along the edge of the first electrode layer in the plan view (claim 7). According to this configuration, the contact portion is arranged at least on the edge side of the first conductive semiconductor layer according to the contact on the first edge side. As a result, the current can be distributed to the veranda in the light emitting layer on the first conductive type semiconductor layer. Therefore, since the portion of the light emitting layer that shines can be increased, the luminous efficiency of the light emitting element can be improved.</p><p num="0016"> The plurality of first contacts preferably include second edge-side contacts arranged along an edge of the first electrode layer opposite to the second electrode layer side in the plan view (claim 8). .. According to this configuration, in the first conductive semiconductor layer, the contact portion is arranged at least on the edge side opposite to the second electrode layer side according to the second edge side contact. As a result, in the light emitting layer on the first conductive type semiconductor layer, the current can be distributed to the edge side opposite to the second electrode layer side. Therefore, since the portion of the light emitting layer that shines can be increased, the luminous efficiency of the light emitting element can be improved.</p><p num="0017"> The contact portion of the first contact with the first conductive semiconductor layer is preferably circular (claim 9). According to this configuration, at the contact portion of the first contact, the carrier can be isotropically supplied from the entire circumference of the circular shape. As a result, the carrier can be smoothly supplied from the first contact to the first conductive semiconductor layer. In this case, the diameter of the contact portion is preferably 20 μm or more and 40 μm or less (claim 10).</p><p num="0018"> Further, the first contact preferably has a cylindrical shape (claim 11). The total area of the contact portions of all the first contacts with respect to the first conductive semiconductor layer is 3000 μm.²More than 25000 μm²The following is preferable (Claim 12). According to this configuration, in the light emitting element, it is possible to improve the light emitting efficiency while lowering the forward voltage.</p><p num="0019"> The insulating layer is preferably made of SiN (claim 13). The reflective electrode layer is preferably made of an alloy containing silver, a platinum group metal, and copper (claim 14). The platinum group metal is preferably platinum or palladium (claim 15). The transparent electrode layer is preferably made of ITO (indium tin oxide) (claim 16).</p><p num="0021"> The second reflective electrode layer is preferably made of Al (claim 1).<u style="single">7</u>). The light emitting element is transparent to the emission wavelength of the light emitting layer, and preferably further includes a substrate on which the first conductive semiconductor layer is laminated (claim 1).<u style="single">8</u>). In the light emitting element, when the light emitting layer emits light, the light is taken out from the substrate. The first conductive semiconductor layer and the second conductive semiconductor layer are preferably made of a nitride semiconductor (claim).<u style="single">19</u>)。 </p><p num="0022"> The insulating layer preferably covers an end face exposed between the first conductive semiconductor layer and the second conductive semiconductor layer in the light emitting layer (claim 2).<u style="single">0</u>). Thereby, the end face of the light emitting layer can be protected. Further, when the light emitting layer emits light, it is possible to prevent the light from leaking from the end surface of the light emitting layer, so that the luminous efficiency of the light emitting element can be improved. It is preferable to further include an etching stop layer laminated on the reflective electrode layer and arranged between the reflective electrode layer and the second contact (claim 2).<u style="single">1</u>). According to this configuration, when a trench for arranging the second contact is formed in the insulating layer by etching, the etching is stopped at the etching stop layer, so that the reflective electrode layer can be prevented from being eroded.</p><p num="0023"> It is preferable that the light emitting element further includes a bonding layer laminated on each of the first electrode layer and the second electrode layer (claim 2).<u style="single">2</u>). The bonding layer is preferably made of AuSn (claim 2).<u style="single">3</u>). As a result, a light emitting element unit including the light emitting element and the submount bonded to the bonding layer is configured (claim 2).<u style="single">4</u>), A voltage can be applied to the light emitting element from the submount.</p><p num="0024"> Then, a light emitting element package including the light emitting element unit and the resin package containing the light emitting element unit can be configured (claim 2).<u style="single">5</u>)。 </p>

0025<figref num="1">FIG. 1 is a schematic plan view of a light emitting device according to an embodiment of the present invention.</figref><figref num="2">FIG. 2 is a cross-sectional view taken along the cutting plane line II-II of FIG.</figref><figref num="3">FIG. 3 is a cross-sectional view taken along the cutting plane line III-III of FIG.</figref><figref num="4">FIG. 4 is a schematic perspective view of the light emitting element.</figref><figref num="5A">FIG. 5A is a schematic cross-sectional view showing a method of manufacturing the light emitting element shown in FIG.</figref><figref num="5B">FIG. 5B is a schematic cross-sectional view showing the next step of FIG. 5A.</figref><figref num="5C">FIG. 5C is a schematic cross-sectional view showing the next step of FIG. 5B.</figref><figref num="5D">FIG. 5D is a graphical cross-sectional view showing the next step of FIG. 5C.</figref><figref num="5E">FIG. 5E is a graphical cross-sectional view showing the next step of FIG. 5D.</figref><figref num="5F">FIG. 5F is a schematic cross-sectional view showing the next step of FIG. 5E.</figref><figref num="5G">FIG. 5G is a schematic cross-sectional view showing the next step of FIG. 5F.</figref><figref num="5H">FIG. 5H is a schematic cross-sectional view showing the next step of FIG. 5G.</figref><figref num="6">FIG. 6 is a cross-sectional view illustrating the structure of the submount graphically.</figref><figref num="7">FIG. 7 is a schematic plan view of the submount.</figref><figref num="8A">FIG. 8A is a cross-sectional view illustrating the structure of the light emitting device.</figref><figref num="8B">FIG. 8B is a schematic perspective view showing a configuration example of the light emitting device.</figref><figref num="9">FIG. 9 is a schematic perspective view of the light emitting element package.</figref><figref num="10">FIG. 10 is a graph showing the relationship between the current density and the light output.</figref><figref num="11">FIG. 11 is a graph showing the relationship between the current density and the luminous efficiency.</figref><figref num="12">FIG. 12 is a graph showing the relationship between the total area of the first contact and the forward voltage (VF).</figref><figref num="13">FIG. 13 is a graph showing the relationship between the total area of the first contact and the luminous efficiency.</figref><figref num="14">FIG. 14 is a schematic plan view of the light emitting element according to the first modification.</figref><figref num="15">FIG. 15 is a schematic plan view of the light emitting element according to the second modification.</figref>

0026Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic plan view of a light emitting device 1 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the cutting plane line II-II of FIG. FIG. 3 is a cross-sectional view taken along the cutting plane line III-III of FIG. FIG. 4 is a schematic perspective view of the light emitting element 1. The light emitting element 1 is insulated from the substrate 2, the first conductive semiconductor layer 3, the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6, the reflective electrode layer 7, and the insulating layer 8. Tube layer 9, first electrode layer 10 (n-side electrode), first contact 11, second electrode layer 12 (p-side electrode), second contact 13, etching stop layer 14, and barrier layer 15 And a bonding layer 16.

0027The first conductive semiconductor layer 3, the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6, the reflective electrode layer 7, and the insulating layer 8 are laminated on the substrate 2 in this order. The substrate 2 is made of a material (for example, sapphire, GaN or SiC) that is transparent to the emission wavelength (for example, 450 nm) of the light emitting layer 4 and has a predetermined thickness. The substrate 2 is formed in a rectangular shape having a longitudinal direction in the left-right direction in FIG. 2 and a lateral direction in the depth direction in FIG. 2 in a plan view from the thickness direction (see FIG. 1). .. The longitudinal dimension of the substrate 2 is, for example, about 1000 μm, and the lateral dimension of the substrate 2 is, for example, about 500 μm. In the substrate 2, the lower surface in FIG. 2 is the front surface 2A, and the upper surface in FIG. 2 is the back surface 2B. Surface 2A is a light extraction surface from which light is extracted. The back surface 2B is a bonding surface of the substrate 2 with the first conductive semiconductor layer 3. A plurality of convex portions 17 projecting toward the first conductive semiconductor layer 3 are formed on the back surface 2B of the substrate 2. The plurality of convex portions 17 are arranged discretely. Specifically, the plurality of convex portions 17 may be arranged in a matrix or in a staggered pattern on the back surface 2B of the substrate 2 at intervals from each other. Each convex portion 17 may be formed of SiN.

0028The first conductive semiconductor layer 3 is laminated on the substrate 2. The first conductive semiconductor layer 3 covers the entire area of the back surface 2B of the substrate 2. The first conductive semiconductor layer 3 is an n-type semiconductor layer in this embodiment, and more specifically, it is made of an n-type nitride semiconductor (for example, GaN) and has an emission wavelength of the light emitting layer 4. Is transparent to. Regarding the first conductive semiconductor layer 3, in FIG. 2, the lower surface covering the back surface 2B of the substrate 2 is referred to as the front surface 3A, and the upper surface opposite to the front surface 3A is referred to as the back surface 3B. In a plan view seen from the thickness direction of the substrate 2 (which is also the thickness direction of the first conductive semiconductor layer 3), the end portion of the back surface 3B of the first conductive semiconductor layer 3 is recessed toward the front surface 3A side. A stepped portion 3C is formed.

0029The light emitting layer 4 is laminated on the first conductive semiconductor layer 3. The light emitting layer 4 covers the entire area other than the stepped portion 3C on the back surface 3B of the first conductive semiconductor layer 3. In this embodiment, the light emitting layer 4 is made of a nitride semiconductor containing In (for example, InGaN), and its thickness is, for example, about 100 nm. The emission wavelength of the light emitting layer 4 is, for example, 440 nm to 460 nm.

0030The second conductive semiconductor layer 5 is laminated on the light emitting layer 4 in the same pattern as the light emitting layer 4. Therefore, in a plan view, the region of the second conductive semiconductor layer 5 coincides with the region of the light emitting layer 4. The second conductive semiconductor layer 5 is a p-type semiconductor layer in this embodiment, and more specifically, it is made of a p-type nitride semiconductor (for example, GaN) with respect to the emission wavelength of the light emitting layer 4. And transparent. As described above, a light emitting diode structure is formed in which the light emitting layer 4 is sandwiched between the first conductive type semiconductor layer 3 which is an n-type semiconductor layer and the second conductive type semiconductor layer 5 which is a p-type semiconductor layer. The thickness of the second conductive semiconductor layer 5 is, for example, about 200 nm. In this case, the total thickness of the first conductive semiconductor layer 3, the light emitting layer 4, and the second conductive semiconductor layer 5 is, for example, about 4.5 μm.

0031The transparent electrode layer 6 is laminated on the second conductive semiconductor layer 5 in the same pattern as the second conductive semiconductor layer 5. The transparent electrode layer 6 is made of ZnO (zinc oxide) or ITO (indium tin oxide) and is transparent to the emission wavelength of the light emitting layer 4. In this embodiment, the transparent electrode layer 6 is made of ITO. The reflective electrode layer 7 is laminated on the transparent electrode layer 6 in the same pattern as the transparent electrode layer 6. The reflective electrode layer 7 is made of an alloy containing silver, a platinum group metal, and copper. Platinum or palladium can be used as the platinum group metal. The compounding ratio of each metal is about 98% for silver and about 1% for each of platinum group metals and copper. The reflective electrode layer 7 made of such an alloy has good conductivity.

0032The insulating layer 8 is laminated on the reflective electrode layer 7. At the end of the insulating layer 8 in a plan view, an extending portion 8A extending toward the substrate 2 side is integrally provided. The extension portion 8A is a part of the insulating layer 8. The extending portion 8A includes the outer end faces of the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6 and the reflective electrode layer 7 in a plan view, and the stepped portion 3C of the first conductive semiconductor layer 3. Covers the entire area. The outer end face of the light emitting layer 4 is an end face 4A exposed from between the first conductive type semiconductor layer 3 and the second conductive type semiconductor layer 5 in the light emitting layer 4. The insulating layer 8 and the extension 8A are made of an insulating material (eg, SiN).

0033The insulating tube layer 9 is formed of an insulating material (here, the same material as the insulating layer 8). The insulating tube layer 9 is a tubular layer that is continuous from the insulating layer 8 and extends toward the substrate 2 along the thickness direction of the substrate 2. In this embodiment, the insulating tube layer 9 is a straight circular tube, the outer diameter thereof is 30 μm or more and 50 μm or less, and the thickness thereof is about 10 μm to 20 μm. The insulating tube layer 9 penetrates the reflective electrode layer 7, the transparent electrode layer 6, the second conductive semiconductor layer 5, and the light emitting layer 4, and reaches halfway through the thickness of the first conductive semiconductor layer 3.

0034A plurality of insulating tube layers 9 are provided, and the plurality of insulating tube layers 9 are arranged discretely in a plan view. Specifically, the plurality of insulating tube layers 9 are evenly distributed in a plan view. With reference to FIG. 1, the plurality of insulating tube layers 9 intersect the first array line A extending in the first direction X parallel to the main surface of the substrate 2 in the first direction X and reach the main surface of the substrate 2. It is arranged along each of the second array lines B extending in the parallel second direction Y. In this embodiment, the number of insulating tube layers 9 is 15, and they are arranged in a matrix of 3 rows and 5 columns. In this case, the first direction X (row direction) coincides with the lateral direction of the substrate 2, the second direction Y (column direction) coincides with the longitudinal direction of the substrate 2, and the first array line A (first). The direction X) and the second array line B (second direction Y) are orthogonal to each other. Three insulating tube layers 9 are arranged at equal intervals on one first arrangement line A, and five insulating tube layers 9 are arranged at equal intervals on one second arrangement line B. ing.

0035The first sequence line A and the second sequence line B pass through the circular center of the circular tubular insulating tube layer 9. Therefore, the distance between the insulating tube layers 9 adjacent to each other on one first arrangement line A is the distance C between the second arrangement lines B extending adjacently and in parallel. Further, the distance between the insulating tube layers 9 adjacent to each other on one second arrangement line B is the distance D of the first arrangement line A extending in parallel adjacent to each other.

0036Consider a third array line E that extends at an angle with respect to both the first array line A and the second array line B in a plane parallel to the main surface of the substrate 2. The third array line E passes through the circular center of the insulating tube layer 9 on the adjacent first array line A and on the adjacent second array line B. When the intervals C and D are equal, the third sequence line E extends at an angle of 45 ° with respect to both the first sequence line A and the second sequence line B, and extends on one third sequence line E. A plurality of insulating tube layers 9 are arranged at equal intervals F. As described above, the plurality of insulating tube layers 9 are the insulation closest to one insulating tube layer 9 and the insulating tube layer 9 in each of the first array line A, the second array line B, and the third array line E. They are arranged so that the distance from the pipe layer 9 (distance C, D, F) is constant. When the insulating tube layers 9 are arranged in a matrix as in this embodiment, the interval F is larger than the intervals C and D. When the intervals C and D are equal, the interval between one insulating tube layer 9 and the other insulating tube layer 9 closest to it is equal to the intervals C and D. The intervals C and D (distance between the closest insulating tube layers 9) are set to be 50 μm or more and 150 μm or less.

0037Considering a line segment connecting the circular centers of a pair of insulating tube layers 9 adjacent to each other on the third array line E, the midpoint of this line segment is the farthest point (farthest) from the insulating tube layer 9 existing around the line segment. Point). The plane of the insulating tube layer 9 so that the distance between such the farthest point and the insulating tube layer 9 closest to it (the first contact 11 arranged in the insulating tube layer 9) is 150 μm or less. It is preferable to design the arrangement.

0038With reference to FIG. 2, the first electrode layer 10 is laminated on the insulating layer 8 in a region biased to the left in FIG. The first electrode layer 10 is formed in a rectangular shape having a longitudinal shape in the left-right direction (longitudinal direction of the substrate 2) in FIGS. 1 and 2 in a plan view, and occupies a region of more than half of the insulating layer 8 in a plan view. It is in contact with the insulating layer 8 in the region (see FIG. 1). The first electrode layer 10 is made of a conductive material (for example, Al (aluminum) or Ag (silver)). The thickness of the first electrode layer 10 is 100 nm or more, preferably about 350 nm. With reference to FIG. 1, the first electrode layer 10 includes a pair of longitudinal edges 10A extending laterally in FIG. 1 and a pair of minor edges 10B extending orthogonally to the pair of longitudinal edges 10A. I'm out. The long edge 10A and the short edge 10B are sides that define the outer shape (contour) of the first electrode layer 10 in a plan view.

0039In a plan view, one of the plurality of insulating tube layers 9 is arranged at the center of gravity position G of the rectangular first electrode layer 10, and the remaining insulating tube layer 9 is located at the center of gravity position G. Is arranged so as to be point-symmetrical with reference to (center of symmetry). Further, the plurality of insulating tube layers 9 include the first edge side insulating tube layer 9A arranged along the longitudinal edge 10A and the lateral edge 10B of the first electrode layer 10. In FIG. 1, twelve first edge-side insulating tube layers 9A form a rectangular frame shape as a whole so as to border the outer lines (longitudinal edge 10A and short edge 10B) of the first electrode layer 10. It is placed adjacent to the outline.

0040The first contact 11 is made of a conductive material (here, the same material as the first electrode layer 10). When the first contact 11 is made of the same material as the first electrode layer 10, it may be integrated with the first electrode layer 10 and may be considered as a part of the first electrode layer 10. The first contact 11 is continuous from the first electrode layer 10 and is formed in a columnar shape extending toward the substrate 2 along the thickness direction of the substrate 2. In this embodiment, the first contact 11 has a linear cylindrical shape. A plurality of first contacts 11 are provided. In this embodiment, the same number (15) of the first contacts 11 as the insulating tube layer 9 is provided. Each first contact 11 penetrates the insulating layer 8 and is embedded in the hollow portion of the corresponding insulating tube layer 9. In this state, each first contact 11 is connected to the first conductive semiconductor layer 3 through the insulating layer 8 and the insulating tube layer 9. The first contact 11 is separated and insulated from the reflective electrode layer 7, the transparent electrode layer 6, the second conductive semiconductor layer 5, and the light emitting layer 4 by passing through the insulating tube layer 9. The contact portion 18 of the cylindrical first contact 11 with respect to the first conductive semiconductor layer 3 has a circular shape. The diameter of the contact portion 18 may be, for example, 20 μm or more and 40 μm or less, and is preferably about 30 μm in consideration of the dimensional error of the first contact 11 and the error of the distance between the adjacent first contacts 11. When the diameter of the contact portion 18 is made smaller than 20 μm, the electrical resistance (contact resistance) at the contact portion 18 increases.

0041The total area (contact area) of the contact portion 18 of the first contact 11 of all (15 in this case) is 3000 μm.²More than 25000 μm²The following is preferable. With reference to FIG. 1, in a plan view, the circular center of the cylindrical insulating tube layer 9 and the circular center of the cylindrical first contact 11 embedded in the hollow portion of the insulating tube layer 9 coincide with each other. There is. Therefore, in a plan view, the plurality of first contacts 11 are arranged in the same arrangement pattern as the plurality of insulating tube layers 9. That is, the plurality of first contacts 11 are arranged on the intersection of the first arrangement line A and the second arrangement line B in a plan view, and are evenly distributed so as to form a matrix. Further, the plurality of first contacts 11 are the first contact 11 on the first sequence line A, the second sequence line B, and the third sequence line E, and the first contact closest to the first contact 11. The distance from 11 is arranged so as to be constant at the above-mentioned intervals C, D, and F, respectively. The plurality of first contacts 11 are arranged so as to be point-symmetrical with respect to the position G of the center of gravity of the first electrode layer 10 in a plan view. Of the plurality of first contacts 11, the first contact 11 embedded inside the first edge-side insulating tube layer 9A described above is referred to as the first edge-side contact 11A. The first veranda contact 11A is arranged along the longitudinal edge 10A and the minor edge 10B of the first electrode layer 10 in a plan view.

0042With reference to FIG. 2, the second electrode layer 12 is made of the same material as the first electrode layer 10 in this embodiment, and is laminated on the insulating layer 8 in a region biased to the right in FIG. The second electrode layer 12 is smaller than the first electrode layer 10 in a plan view, but has, for example, the same thickness as the first electrode layer 10. The second electrode layer 12 is longitudinal in a direction orthogonal to the longitudinal direction of the first electrode layer 10 (horizontal direction in FIGS. 1 and 2) (direction orthogonal to the paper surface in FIG. 2) (see FIG. 1). .. On the insulating layer 8, the first electrode layer 10 formed unevenly on the left side and the second electrode layer 12 formed unevenly on the right side are separated and insulated by, for example, a distance of about 60 μm.

0043In the above-mentioned first edge side insulating tube layer 9A, it is arranged along the edge of the first electrode layer 10 opposite to the second electrode layer 12 side (the left short edge 10B in FIG. 1) in a plan view. The three first edge-side insulating tube layers 9A will be referred to as the second edge-side insulating tube layer 9B. Then, among the first edge-side contacts 11A embedded inside the first edge-side insulating tube layer 9A, the first edge-side contact 11A embedded inside the three second edge-side insulating tube layers 9B is referred to as the second edge-side contact 11B. I will say that. These second porch contacts 11B are arranged along the left short edge 10B in a plan view.

0044The second contact 13 is made of a conductive material (here, the same material as the second electrode layer 12). The second contact 13 is continuous from the second electrode layer 12 and is formed in a columnar shape extending toward the substrate 2 along the thickness direction of the substrate 2. A plurality of (three in this case) second contacts 13 are provided. The plurality of second contacts 13 are arranged along the longitudinal direction of the second electrode layer 12 (the direction orthogonal to the paper surface of FIG. 2) (see FIG. 1). Each second contact 13 penetrates the insulating layer 8.

0045The etching stop layer 14 is laminated on the reflective electrode layer 7 at a position corresponding to each second contact 13 in a plan view, and is formed larger than the second contact 13 in a plan view. The etching stop layer 14 is made of a conductive material, and specifically, it is formed by laminating Cr (chromium) and Pt (platinum) in this order from the reflective electrode layer 7 side. The etching stop layer 14 is sandwiched between the reflective electrode layer 7 and the second contact 13. The second contact 13 is connected to the reflective electrode layer 7 via the etching stop layer 14.

0046The barrier layer 15 is laminated on the first electrode layer 10 in the same pattern as the first electrode layer 10, and is laminated on the second electrode layer 12 in the same pattern as the second electrode layer 12. The barrier layer 15 is formed by laminating Ti (titanium) and Pt in this order from the first electrode layer 10 and the second electrode layer 12 side. The bonding layer 16 is laminated on the barrier layer 15 on the first electrode layer 10 in the same pattern as the first electrode layer 10, and the second electrode layer is on the barrier layer 15 on the second electrode layer 12. It is laminated in the same pattern as 12. The bonding layer 16 is made of, for example, Ag, Ti or Pt or an alloy thereof. The bonding layer 16 may be made of solder or AuSn (gold tin). In this embodiment, the junction layer 16 is made of AuSn. The barrier layer 15 suppresses the diffusion of Sn (tin) from the bonding layer 16 to the first electrode layer 10 and the second electrode layer 12.

0047In the bonding layer 16, the surface of the first electrode layer 10 and the second electrode layer 12 in contact with the barrier layer 15 is the lower surface, and the upper surface opposite to the lower surface is referred to as the bonding surface 16A. The bonding surface 16A of the bonding layer 16 on the first electrode layer 10 side and the bonding surface 16A of the bonding layer 16 on the second electrode layer 12 side are both flat surfaces and have the same height position (thickness direction of the substrate 2). (Position in) is flush with each other. Since the first electrode layer 10 and the second electrode layer 12 are separated and insulated as described above, the bonding layer 16 on the first electrode layer 10 side and the bonding layer 16 on the second electrode layer 12 side are separated. It is insulated.

0048The portion of the first conductive semiconductor layer 3 excluding the stepped portion 3C, the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6, and the reflective electrode layer 7 are in agreement in a plan view. Therefore, it has a rectangular shape that is long in the left-right direction (longitudinal direction of the substrate 2) of FIGS. 1 and 2 (see FIG. 1). The first conductive semiconductor layer 3, the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6 and the reflective electrode layer 7, respectively, in the region where the insulating tube layer 9 and the first contact 11 are not formed, respectively. It exists over the entire area of the substrate 2 in the longitudinal direction (see FIG. 3). In a plan view, the first electrode layer 10, the second electrode layer 12, the barrier layer 15 and the bonding layer 16 are inside the light emitting layer 4 (second conductive semiconductor layer 5, transparent electrode layer 6, reflective electrode layer 7). It is located (see Figure 1).

0049In this light emitting element 1, when a forward voltage is applied between the first electrode layer 10 and the second electrode layer 12, a current flows from the second electrode layer 12 to the first electrode layer 10. The current flows from the second electrode layer 12 toward the first electrode layer 10 through the second contact 13, the etching stop layer 14, and the reflective electrode layer 7 in this order. Since the reflective electrode layer 7 has good conductivity, the current spreads over the entire area in the plan view of the reflective electrode layer 7, and then the transparent electrode layer 6, the second conductive semiconductor layer 5, the light emitting layer 4, and the first conductive type. It flows through the semiconductor layer 3 and the first contact 12 in this order. As a result of the current flowing in this way, electrons are injected from the first conductive semiconductor layer 3 into the light emitting layer 4, holes are injected from the second conductive semiconductor layer 5 into the light emitting layer 4, and these holes and electrons are injected. Are recombined in the light emitting layer 4 to generate blue light having a wavelength of 440 nm to 460 nm. This light passes through the first conductive semiconductor layer 3 and the substrate 2 in this order and is taken out from the surface 2A of the substrate 2.

0050At this time, there is also light directed from the light emitting layer 4 toward the second conductive semiconductor layer 5, and this light passes through the second conductive semiconductor layer 5 and the transparent electrode layer 6 in this order, and the transparent electrode layer 6 is transmitted. Is reflected at the interface between the light and the reflective electrode layer 7. The reflected light passes through the transparent electrode layer 6, the second conductive semiconductor layer 5, the light emitting layer 4, the first conductive semiconductor layer 3 and the substrate 2 in this order, and is taken out from the surface 2A of the substrate 2.

0051In addition, there is also light that travels through the insulating tube layer 9 without being reflected by the reflective electrode layer 7, and this light passes through the insulating tube layer 9 and the insulating layer 8 to pass through the insulating tube layer 9 and the insulating layer 8 to the insulating layer 8 and the first electrode layer 10. And reflected at the interface with the second electrode layer 12. The reflected light passes through the insulating layer 8, the insulating tube layer 9, the transparent electrode layer 6, the second conductive semiconductor layer 5, the light emitting layer 4, the first conductive semiconductor layer 3 and the substrate 2, and the surface 2A of the substrate 2 Taken from. That is, the light emitting element 1 includes a first electrode layer 10 and a second electrode layer 12 as a second reflective electrode layer in addition to the reflective electrode layer 7 as the first reflective electrode layer. In order for the first and second electrode layers 10 and 12 to function as the reflective electrode layer, the thickness of the first and second electrode layers 10 and 12 must be 100 nm or more.

0052As described above, a plurality of convex portions 17 are formed on the back surface 2B of the substrate 2. These convex portions 17 can suppress the total reflection of light incident on the back surface 2B of the substrate 2 from the first conductive semiconductor layer 3 side toward the substrate 2 from various angles on the back surface 2B of the substrate 2. As a result, the light directed from the first conductive semiconductor layer 3 to the substrate 2 is suppressed from being reflected toward the first conductive semiconductor layer 3 at the interface between the first conductive semiconductor layer 3 and the substrate 2. That is, the light extraction efficiency is improved.

00535A to 5H are schematic cross-sectional views showing a method of manufacturing the light emitting element shown in FIG. First, as shown in FIG. 5A, a layer made of SiN (SiN layer) is formed on the back surface 2B of the substrate 2, and the SiN layer is formed into a plurality of protrusions by etching using a resist pattern (not shown) as a mask. Separate into parts 17. Next, a process of epitaxially growing a semiconductor layer on the back surface 2B of the substrate 2 is performed by arranging the substrate 2 in a reaction vessel (not shown) and flowing a gas (silane gas or the like) into the reaction vessel. At that time, by changing the flow rate ratio of the gas, the first conductive semiconductor layer 3, the light emitting layer 4 and the second conductive semiconductor layer 5 are continuously formed in this order on the back surface 2B of the substrate 2. Can be done.

0054The transparent electrode layer 6 is then patterned, for example, by using a lift-off method, as shown in FIG. 5B. The transparent electrode layer 6 is formed in a pattern having through holes 19 penetrating the transparent electrode layer 6 at positions corresponding to each insulating tube layer 9 (see FIGS. 1 and 2). The second conductive semiconductor layer 5 is exposed from each through hole 19. Next, a layer of an alloy containing silver, a platinum group metal, and copper covers the entire area above the transparent electrode layer 6 and above the portion of the second conductive semiconductor layer 5 where each through hole 19 is exposed. An (alloy layer) is formed, and as shown in FIG. 5C, the alloy layer is subjected to dry etching using a resist pattern 20 having the same pattern as the transparent electrode layer 6 as a mask. As a result, the alloy layer is selectively removed, and the remaining alloy layer becomes the reflective electrode layer 7 and is formed on the transparent electrode layer 6 in the same pattern as the transparent electrode layer 6. In the reflective electrode layer 7, a through hole 21 having the same size as the through hole 19 is formed at a position corresponding to each through hole 19 of the transparent electrode layer 6 in a plan view.

0055Then, as shown in FIG. 5D, the resist pattern 20 is removed, and then another resist pattern 22 is formed on the reflective electrode layer 7. In the resist pattern 22, an opening 23 having the same size as the through hole 21 is formed at a position corresponding to each through hole 21 of the reflective electrode layer 7 in a plan view. The opening 23 is continuous with the through holes 19 and 21 at the same position in a plan view. Further, in a plan view, the resist pattern 22 does not exist in the portion where the stepped portion 3C of the first conductive semiconductor layer 3 is to be located.

0056Next, each of the reflective electrode layer 7, the transparent electrode layer 6, the second conductive semiconductor layer 5, the light emitting layer 4, and the first conductive semiconductor layer 3 is selectively removed by dry etching using the resist pattern 22 as a mask. .. As a result, the position corresponding to each opening 23 of the resist pattern 22 in the plan view penetrates the second conductive semiconductor layer 5 and the light emitting layer 4 and reaches halfway through the thickness of the first conductive semiconductor layer 3. A trench 24 (a cylindrical trench in this embodiment) is formed, and a stepped portion 3C is formed on the first conductive semiconductor layer 3. Each trench 24 is continuous with openings 23 and through holes 19, 21 that are co-located in plan view. Through holes 19, 21 and trenches 24, which are continuous at the same position in a plan view, constitute one trench 25. The trench 25 is formed at a plurality of (here, 15) dispersed positions that coincide with the insulating tube layer 9 in a plan view. In this embodiment, each trench 25 has a cylindrical shape extending linearly in the thickness direction of the substrate 2, and the circular shape of the cross section thereof has the same size at any position in the thickness direction of the substrate 2. Each trench 25 penetrates the reflective electrode layer 7, the transparent electrode layer 6, the second conductive semiconductor layer 5, and the light emitting layer 4, and reaches halfway through the thickness of the first conductive semiconductor layer 3. The depth (dimension in the thickness direction of the substrate 2) from the semiconductor layer surface of the trench 25 (the surface of the second conductive semiconductor layer 5) is, for example, about 1.5 μm. Further, in each of the reflective electrode layer 7, the transparent electrode layer 6, the second conductive semiconductor layer 5, and the light emitting layer 4, the portion corresponding to the stepped portion 3C in a plan view (see FIG. 5C) is the trench 25 formed by dry etching. It is removed at the same time as the formation.

0057Then, after removing the resist pattern 22, as shown in FIG. 5E, at a position on the reflective electrode layer 7 that is expected to coincide with the second contact 13 (see FIG. 2) in a plan view, for example, by using a lift-off method. , The etching stop layer 14 is formed. Next, as shown in FIG. 5F, a layer (SiN layer) 26 made of SiN is formed on the reflective electrode layer 7 and the etching stop layer 14 by, for example, a CVD method. The SiN layer 26 is filled in each trench 25, and has the outer end faces of the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6, and the reflective electrode layer 7 in a plan view, and the first conductive type. It is formed so as to cover the stepped portion 3C of the semiconductor layer 3 over the entire area. In the SiN layer 26, the portions on the reflective electrode layer 7 and the etching stop layer 14 become the insulating layer 8, and the light emitting layer 4, the second conductive semiconductor layer 5, the transparent electrode layer 6, and the reflective electrode layer 7 in a plan view. The portion covering each of the outer end faces of the above and the stepped portion 3C of the first conductive semiconductor layer 3 is the extension portion 8A. Further, in the SiN layer 26, the portion embedded in the trench 25 forms the insulating tube layer 9.

0058Next, as shown in FIG. 5G, a resist pattern 27 is formed on the insulating layer 8. In the resist pattern 27, an opening 28 is formed at a position where it is planned to coincide with each first contact 11 (see FIG. 2) in a plan view, and coincides with each second contact 13 (see FIG. 2) in a plan view. An opening 29 is formed at the position where it is planned to be used. Next, the insulating layer 8 and the SiN layer 26 in each trench 25 are selectively removed by dry etching using the resist pattern 27 as a mask. As a result, the insulating layer 8 and the SiN layer 26 at positions corresponding to the openings 28 of the resist pattern 27 in a plan view are removed from the resist pattern 27 side. The dry etching conditions are such that the first conductive semiconductor layer 3 is not etched. Therefore, the etching at each opening 28 stops before the first conductive semiconductor layer 3 on the bottom surface of the trench 25. As a result, a trench 30 is formed at a position corresponding to each opening 28 of the resist pattern 22 in a plan view, penetrating the insulating layer 8 and the SiN layer 26 and reaching the first conductive semiconductor layer 3.

0059The trench 30 has a cylindrical shape extending in the thickness direction of the substrate 2, and the circular shape of the cross section thereof has the same size over the entire area in the thickness direction of the substrate 2. The number of trenches 30 is the same as that of the first contact 11 (15 in this case), and each trench 30 is arranged inside one of the trenches 25. Since each trench 25 reaches halfway through the thickness of the first conductive semiconductor layer 3, each trench 30 also reaches halfway through the thickness of the first conductive semiconductor layer 3. At the bottom of each trench 30, the first conductive semiconductor layer 3 is exposed. The SiN layer 26 filled in each trench 25 becomes an insulating pipe layer 9 by forming the trench 30.

0060By the dry etching here, the insulating layer 8 at a position corresponding to each opening 29 of the resist pattern 27 in the plan view is removed from the resist pattern 27 side. Etching at each opening 29 is stopped at the etching stop layer 14. That is, since the etching stop layer 14 protects the reflective electrode layer 7 immediately below it from dry etching, it is possible to prevent the reflective electrode layer 7 from being etched. As a result, a trench 31 is formed at a position corresponding to each opening 29 of the resist pattern 27 in a plan view, penetrating the insulating layer 8 and reaching the etching stop layer 14. The same number of trenches 31 as the second contacts 13 (here, three) are formed, and these trenches 31 are evenly spaced in the lateral direction of the substrate 2 in a plan view (direction orthogonal to the paper surface of FIG. 5G). Lined up in.

0061Next, after removing the resist pattern 27, as shown in FIG. 5H, a layer made of Al (Al layer 32) is formed over the entire area on the insulating layer 8 by, for example, thin-film deposition. The Al layer 32 is filled in each trench 30 and each trench 31. The Al layer 32 in the trench 30 becomes the first contact 11, and the Al layer 32 in the trench 31 becomes the second contact 13.

0062Next, a layer made of Ti (Ti layer) and a layer made of Pt (Pt layer) are laminated in this order from the Al layer 32 side over the entire area on the Al layer 32 on the insulating layer 8, for example, by a sputtering method. .. As a result, the barrier layer 15 having a laminated structure of the Ti layer and the Pt layer is formed on the Al layer 32. Next, a layer made of AuSn (AuSn layer) is formed over the entire area on the barrier layer 15 by, for example, an electrolytic plating method. The AuSn layer is the bonding layer 16.

0063Next, by etching using a resist pattern (not shown) as a mask, each of the Al layer 32, the barrier layer 15 and the bonding layer 16 on the insulating layer 8 is brought into contact with the second contact 13 in the longitudinal direction of the substrate 2 in a plan view. And the first contact 11 closest to the second contact 13 (see FIG. 5H). As a result, as shown in FIG. 2, in the Al layer 32 on the insulating layer 8, the portion covering all the first contacts 11 in the plan view becomes the first electrode layer 10, and all the second contacts 13 in the plan view. The portion covering the second electrode layer 12 is formed. As a result, the light emitting element 1 is completed. The first electrode layer 10 and the second electrode layer 12 are formed on the insulating layer 8 in a separated and insulated state.

0064A large number of light emitting elements 1 are simultaneously formed on, for example, one wafer (not shown) as the original substrate. Therefore, when the wafer is diced after grinding and polishing the wafer as necessary to adjust the thickness, the light emitting elements 1 having the structures shown in FIGS. 1 to 4 are finally cut out individually. The trench 30 in which the first contact 11 is embedded has a circular cross section having the same size as the first contact 11, and its diameter (inner diameter) is 20 μm or more and 40 μm or less. On the other hand, the trench 31 in which the second contact 13 is embedded is larger than the trench 30 in a plan view (see FIG. 1). Therefore, as described above, when the Al layer 32 is formed on the insulating layer 8 (see FIG. 5H), if the Al layer 32 is filled in each trench 31, the insulating layer 8 has traces of each trench 31. 90 appears as a dent, and finally appears on the joint surface 16A of the joint layer 16 on the second electrode 12 (see FIG. 4). However, since the plurality of trenches 31 are spaced apart in the lateral direction of the substrate 2 (see FIG. 1), the trace 90 of each trench 31 is larger than the case where these trenches 31 are connected in a row. , Very small and unobtrusive. Therefore, the bonding surface 16A of the bonding layer 16 on the second electrode 12 becomes almost flat.

0065FIG. 6 is a cross-sectional view illustrating the structure of the submount graphically. As shown by the alternate long and short dash line in FIG. 6, the light emitting element 1 is bonded to the submount 50 by the bonding layer 16 to form the light emitting element unit 64. The submount 50 includes a base substrate 51, an insulating layer 52, an electrode layer 53, and a bonding layer 54.

0066The base substrate 51 is made of, for example, Si. The insulating layer 52 is, for example, SiO.₂It covers the entire surface of the base substrate 51 (upper surface in FIG. 6). The electrode layer 53 is made of, for example, Al. The electrode layer 53 is provided in two separated regions on the insulating layer 52, and in FIG. 6, the two electrode layers 53 are formed on the insulating layer 52 in a state of being separated from each other on the left and right. Of the two electrode layers 53, the left electrode layer 53 in FIG. 6 is referred to as the first mount electrode layer 53A, and the right electrode layer 53 in FIG. 6 is referred to as the second mount electrode layer 53B. The first mount electrode layer 53A and the second mount electrode layer 53B are separated and insulated from each other with a distance substantially equal to the distance between the first electrode 11 and the second electrode 12, for example, a distance of about 60 μm.

0067The bonding layer 54 is laminated on each electrode layer 53. In this embodiment, the bonding layer 54 has a two-layer structure including a Ti layer 55 on the base substrate 51 side and an Au layer 56 laminated on the Ti layer 55. The surface of the bonding layer 54 opposite to the surface in contact with the electrode layer 53 (upper surface in FIG. 6) is referred to as the surface 54A. The surface 54A is a flat surface, and the surface 54A of the bonding layer 54 on each electrode layer 53 is flush with each other.

0068FIG. 7 is a schematic plan view of the submount. In a plan view, the junction layer 54 on the first mount electrode layer 53A has the same size as the junction layer 16 on the first electrode layer 10 of the light emitting element 1, and the junction layer 54 on the second mount electrode layer 53B is , It is the same size as the bonding layer 16 on the second electrode layer 12 of the light emitting element 1 (see FIG. 1). FIG. 8A is a cross-sectional view illustrating the structure of the light emitting device.

0069With reference to FIG. 8A, the light emitting device 60 includes a light emitting element 1, a submount 50, and a support substrate 61. The support substrate 61 is provided so as to be exposed from both ends of the insulating substrate 62 formed of an insulating material and both ends of the insulating substrate 62, and a pair of metal leads 63 for electrically connecting the light emitting element 1 and the outside. And have. The insulating substrate 62 is formed, for example, in a rectangular shape in a plan view, and a pair of leads 63 are formed in a strip shape along a pair of opposite sides thereof. Each lead 63 is folded along a pair of edge edges of the insulating substrate 62 from the top surface across the sides to the bottom surface and is formed to have a lateral U-shaped cross section.

0070At the time of assembly, for example, the submount 50 is arranged so that the surface 54A of the bonding layer 54 faces upward as shown in FIG. 8A. Further, the light emitting element 1 shown in FIG. 2 is placed in a posture in which the joining surface 16A of the joining layer 16 faces downward (the posture is upside down from that in FIG. 2) with respect to the submount 50 in the posture shown in FIG. 8A. Make them face each other from above. When the light emitting element 1 is brought close to the submount 50, as shown in FIG. 8A, the bonding surface 16A of the bonding layer 16 of the light emitting element 1 and the surface 54A of the bonding layer 54 of the submount 50 come into surface contact with each other. Specifically, the bonding surface 16A of the bonding layer 16 on the first electrode layer 10 side comes into surface contact with the surface 54A of the bonding layer 54 on the first mount electrode layer 53A side, and the bonding on the second electrode layer 12 side. The bonding surface 16A of the layer 16 makes surface contact with the surface 54A of the bonding layer 54 on the second mount electrode layer 53B side. If reflow (heat treatment) is performed in this state, the first electrode layer 10 and the first mount electrode layer 53A are joined via the bonding layers 16 and 54, and the second electrode layer 12 and the second mount electrode layer 53B are joined together. Is bonded via the bonding layers 16 and 54, and the light emitting element 1 is flip-chip connected to the submount 50. That is, the bonding layer 16 and the bonding layer 54 are melted and fixed to bond with each other. As a result, a light emitting element unit 64 in which the light emitting element 1 and the submount 50 are integrated is obtained.

0071As described above, the junction surface 16A of the junction layer 16 on the second electrode 12 has traces 90 of each trench 31 but is very small, so that the junction surface 16A is almost flat (see FIG. 4). Therefore, the trace 90 of each trench 31 does not affect the surface contact between the joint surface 16A and the surface 54A of the joint layer 54 on the second mount electrode layer 53B side, and these joint surfaces 16A and these joint surfaces 16A and The surface 54A is in surface contact over almost the entire area. Further, the first electrode layer 10 and the second electrode layer 12 on the light emitting element 1 side are separated by a sufficient distance of about 60 μm, and the first mount electrode layer 53A and the second mount electrode layer 53B on the submount 50 side are separated from each other. And are also separated by a sufficient distance. Therefore, even if there is some mounting error, the first electrode layer 10 is not connected to the second mount electrode layer 53B, and the second electrode layer 12 is not connected to the first mount electrode layer 53A. The light emitting element 1 can be securely flip-chip connected to the submount 50.

0072The light emitting element unit 64 is joined to the insulating substrate 62 with the base substrate 51 of the submount 50 facing one surface of the insulating substrate 62. Then, the first mount electrode layer 53A connected to the first electrode layer 10 and the lead 63 on the first mount electrode layer 53A side are connected by the bonding wire 65. Further, the second mount electrode layer 53B connected to the second electrode layer 12 and the lead 63 on the second mount electrode layer 53B side are connected by the bonding wire 65. As a result, the light emitting element unit 64 and the support substrate 61 are integrated to complete the light emitting device 60.

0073As shown in the schematic perspective view in FIG. 8B, the support substrate 61 may be formed in an elongated shape (strip shape), and a plurality of light emitting element units may be formed on the surface of such an elongated support substrate 61. 64 may be mounted to form an LED (light emitting diode) bar. FIG. 8B shows a light emitting device 60 in which a plurality of light emitting element units 64 are linearly arranged in a line on one surface of the support substrate 61. Such a light emitting device 60 can be used, for example, as a light source for a backlight of a liquid crystal display device. The plurality of light emitting element units 64 on the support substrate 61 do not have to be linearly arranged in a single row, and may be arranged in two rows or in a staggered manner. Further, a sealing resin containing a phosphor may be potted on each light emitting element unit 64.

0074FIG. 9 is a schematic perspective view of a light emitting element package using the light emitting device unit 64. The light emitting element package 70 includes a light emitting device 60 having the structure shown in FIG. 8A, a resin package 71, and a sealing resin 72. The resin package 71 is a ring-shaped case filled with resin, and is fixed to the support substrate 61 in a state in which the light emitting element unit 64 is housed (covered) inside and surrounded and protected from the side. There is. The inner wall surface of the resin package 71 forms a reflecting surface 71a for reflecting the light emitted from the light emitting element 1 of the light emitting element unit 64 and taking it out to the outside. In this embodiment, the reflecting surface 71a is composed of an inclined surface that is inclined so as to approach the support substrate 61 toward the inward direction, and the light from the light emitting element 1 is directed toward the light extraction direction (normal direction of the substrate 2). It is configured to reflect.

0075The sealing resin 72 is made of a transparent resin (for example, silicone, epoxy, etc.) that is transparent to the emission wavelength of the light emitting element 1, and seals the light emitting element 1 and the bonding wire 65. Alternatively, a phosphor may be mixed with this transparent resin. When the light emitting device 60 emits blue light and a yellow light emitting body is arranged as the phosphor, natural light emission can be obtained. FIG. 9 shows a structure in which one light emitting element unit 64 is mounted on the support board 61. Of course, a plurality of light emitting element units 64 are commonly mounted on the support board 61, and they are mounted on the support board 61. May be commonly sealed by the sealing resin 72.

0076FIG. 10 is a graph showing the relationship between the current density and the light output in the light emitting diode. With reference to FIG. 10, for light emitting diodes, in theory, the higher the current density, the more linearly the light output is expected to increase (the dashed theoretical line in FIG. 10). However, in reality, when the current density is high, a so-called droop phenomenon occurs and a loss of light output occurs. Therefore, the light output is shifted downward (decreasing side) from the theoretical line (Fig. 10). Along the solid line).

0077In order to improve the luminous efficiency by keeping the current applied to the light emitting element 1 constant, it is necessary to reduce the loss of the light output, and for that purpose, it is necessary to relax (lower) the current density. In order to reduce the current density, it is effective to increase the light emitting layer 4 in the plan view shown in FIG. 1, but if the substrate 2 (the entire chip) is increased for that purpose, an increase in cost is unavoidable. Therefore, it is desirable to increase the light emitting layer 4 in a plan view and increase the proportion of the light emitting layer 4 in the substrate 2 (referred to as the actual light emitting area ratio) without changing the size (chip size) of the substrate 2. Therefore, the light emitting element 1 according to the embodiment of the present invention has the configuration described above.

0078That is, as shown in FIG. 2, in the light emitting element 1, the first electrode layer 10 and the first conductive semiconductor layer 3 are sandwiched between the light emitting layer 4, the second conductive semiconductor layer 5, and the transparent electrode layer 6. , The reflective electrode layer 7 and the insulating layer 8 are spaced apart from each other. The first electrode layer 10 is connected to the first conductive semiconductor layer 3 via a plurality of first contacts 11 discretely arranged in a plan view. Therefore, a current should flow smoothly between the first electrode layer 10 and the first conductive semiconductor layer 3 to the same extent as when the first electrode layer 10 is directly laminated on the first conductive semiconductor layer 3. Can be done.

0079A plurality of discretely arranged first electrode layers 10 compared to the area of the contact portion between the first electrode layer 10 and the first conductive semiconductor layer 3 when the first electrode layer 10 is directly laminated on the first conductive semiconductor layer 3. The total area of the contact portion 18 between the first contact 11 and the first conductive semiconductor layer 3 can be kept small. This is because the first contacts 11 are discretely arranged so that the current can be sufficiently dispersed throughout the first conductive semiconductor layer 3. As a result, it is possible to prevent the light emitting layer 4 from being eroded by the configuration for connecting the first electrode layer 10 and the first conductive semiconductor layer 3. Therefore, in the light emitting element 1, since the area of the light emitting layer 4 on the first conductive semiconductor layer 3 can be increased, the current density can be suppressed, and the light emitting efficiency can be improved accordingly.

0080As described above, the inventor of the present application has developed the structure described in Patent Document 1 and arranged it on an exposed n-type semiconductor layer having an end region and a plurality of branches extending from the end region. The structure (comparative example) of the n-electrode (having a plurality of branches like the n-type semiconductor layer) was examined. The relationship between the current density and the luminous efficiency in this comparative example is shown by a broken line in FIG. That is, in the structure of this comparative example, since the branch portion of the n electrode is arranged, the light emitting layer is largely eroded, so that the area of the light emitting layer becomes small, and as a result, the luminous efficiency deteriorates.

0081Therefore, the inventor of the present application further researched and came up with the structure of the light emitting device 1 of this embodiment having a plurality of first contacts 11, and by applying this structure, while increasing the area of the light emitting layer 4, while increasing the area of the light emitting layer 4. We succeeded in making the entire light emitting layer 4 shine uniformly. The results of investigating the relationship between the current density and the luminous efficiency of the examples corresponding to the structure of this embodiment are shown by solid lines in FIG. From the comparison of the two curves in FIG. 11, it can be seen that the luminous efficiency is improved in the entire region of the current density. Further, since the first electrode layer 10 is not directly laminated on the first conductive semiconductor layer 3 but is laminated on the insulating layer 8, the first electrode layer 10 is laminated on the first conductive semiconductor layer 3. It was possible to increase the size without being affected by the light emitting layer 4.

0082Further, in the structure of this embodiment, the plurality of first contacts 11 are evenly distributed in a plan view (see FIG. 1). Therefore, since the portion (contact portion 18) for taking the current into the first electrode layer 10 is evenly distributed in a wide range in the first conductive semiconductor layer 3, the current is evenly distributed in a wide range in the light emitting layer 4. Spread around. As a result, the number of shining portions in the light emitting layer 4 can be further increased, so that the luminous efficiency of the light emitting element 1 can be further improved. In addition, a current can be smoothly passed from the first conductive semiconductor layer 3 to the first electrode layer 10 side through the intake portion evenly distributed over a wide range.

0083Also, referring to FIG. 1, in order to disperse the plurality of first contacts 11 evenly in a plan view, the plurality of first contacts 11 are the first contact 11 and the most from the first contact 11. It is arranged so that the distance from the closest first contact 11 (distances C and D described above) is constant. The plurality of first contacts 11 include the first porch 11A arranged along the edges of the first electrode layer 10 (longitudinal edge 10A and minor edge 10B) in plan view, so that the first porch 11A In the first conductive semiconductor layer 3, the intake portion (contact portion 18 in FIG. 2) is arranged at least on the edge side. As a result, the current can be distributed to the veranda in the light emitting layer 4 on the first conductive semiconductor layer 3. Therefore, since the portion of the light emitting layer 4 that shines can be increased, the luminous efficiency of the light emitting element 1 can be improved.

0084The plurality of first contacts 11 are the second veranda contacts arranged along the edge of the first electrode layer 10 opposite to the second electrode layer 12 side (the left short edge 10B in FIG. 1) in a plan view. Since 11B is contained, the intake portion is arranged on the edge side of the first conductive semiconductor layer 3 opposite to the second electrode layer 12 side at least according to the second edge side contact 11B. As a result, in the light emitting layer 4 on the first conductive semiconductor layer 3, the current can be distributed to the edge side opposite to the second electrode layer 12 side. Therefore, since the portion of the light emitting layer 4 that shines can be increased, the luminous efficiency of the light emitting element 1 can be improved.

0085Since the contact portion 18 of the first contact 11 with respect to the first conductive semiconductor layer 3 has a circular shape, the contact portion 18, that is, the intake portion, can capture current over the entire circumference of the circular shape. it can. As a result, a current can be smoothly passed from the first conductive semiconductor layer 3 to the first contact 11. The total area of the contact portions 18 of all the first contacts 11 with respect to the first conductive semiconductor layer 3 (total area of the first contacts) is 3000 μm.²More than 25000 μm²It is as follows.

0086FIG. 12 is a graph showing the relationship between the total area of the first contact and the forward voltage (VF). As shown in FIG. 12, as the total area of the first contact increases, the forward voltage (VF) in the light emitting element 1 decreases, and the total area of the first contact is 3000 μm.²With the above, the forward voltage becomes almost constant. That is, when the total area of the first contact is increased, the resistance at the contact portion 18 becomes smaller and the current easily flows, but the total area of the first contact is 3000 μm.²In the above range, it can be seen that the forward voltage VF tends to saturate.

0087FIG. 13 is a graph showing the relationship between the total area of the first contact and the luminous efficiency. As shown in FIG. 13, as the total area of the first contact increases, the luminous efficiency of the light emitting element 1 improves, and the total area of the first contact becomes 3000 μm.²With the above, the luminous efficiency becomes almost constant at the maximum value. On the other hand, the total area of the first contact is 25000 μm.²If it exceeds, the effect of the area of the light emitting layer 4 becoming smaller (narrower) becomes larger, and the luminous efficiency decreases.

0088In this way, in the light emitting element 1, the total area of the first contact is 3000 μm.²More than 25000 μm²By doing the following, it is possible to improve the luminous efficiency while lowering the forward voltage VF. With reference to FIG. 2, the first electrode layer 10 has a first contact 11 as well as being in contact with the insulating layer 8, and constitutes a second reflective electrode layer that reflects light transmitted through the insulating layer 8. Therefore, the light reflection efficiency can be improved by reflecting the light transmitted through the insulating layer 8 without being reflected by the reflective electrode layer 7 laminated on the transparent electrode layer 6 by the first electrode layer 10. Therefore, the luminous efficiency of the light emitting element 1 can be improved.

0089Since the insulating layer 8 covers the end face 4A exposed from between the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5 in the light emitting layer 4, when the light emitting layer 4 emits light, the light is emitted. It is possible to prevent leakage from the end face 4A of 4. As a result, the luminous efficiency of the light emitting element 1 can be improved. In the light emitting element 1 according to the embodiment of the present invention, by enlarging the light emitting layer 4 (widening it in a plan view), the above-mentioned actual light emitting area ratio becomes, for example, about 79%. In the light emitting device according to the above-mentioned comparative example in which the structure of Patent Document 1 is improved, for example, the actual light emitting area ratio is about 63%. Therefore, the actual emission area ratio could be improved by about 16% compared to this comparative example. As a result, as shown by the solid line (Example) in FIG. 11, the luminous efficiency was improved by about 1% over the entire current density. The current density when about 100 mA is applied to the light emitting element according to the comparative example described above is, for example, 300 mA / mm.²However, the luminous efficiency is about 28% (point A in FIG. 11). On the other hand, in the light emitting element 1 according to the embodiment to which this embodiment is applied, for example, the current density when the same current is applied is about 200 mA / mm.²As shown at point B in FIG. 11, the luminous efficiency increased to about 31%.

0090FIG. 14 is a schematic plan view of the light emitting element according to the first modification. FIG. 15 is a schematic plan view of the light emitting element according to the second modification. As shown in FIG. 14, the first contact 11 may include only the first porch 11A arranged along the longitudinal edge 10A of the first electrode layer 10 in a plan view. Further, as shown in FIG. 15, the first contacts 11 may be arranged in a staggered pattern in a plan view. In this case, the first edge-side contact 11A along the longitudinal edge 10A of the first electrode layer 10 is arranged side by side on the second array line B described above, and the other first contacts 11 are the third contact described above. They are arranged side by side on the array line E.

0091In both cases of FIGS. 14 and 15, the first contact 11 is arranged so as to be point-symmetric with respect to the position G of the center of gravity of the first electrode layer 10 as a reference (center of symmetry). However, in addition to the above description, the arrangement of the first contact 11 can be changed as appropriate, and may not be arranged so as to be point-symmetric with respect to the center of gravity position G (center of symmetry), for example. .. In this case, in order to spread the current widely in the light emitting layer 4, it is preferable to arrange at least the second edge side contact 11B along the short edge 10B on the side far from the second electrode 12 in the first electrode layer 10.

0092In addition to the above, the present invention may take various embodiments. For example, in the above-described embodiment, the first contact 11 has a cylindrical shape, but the first contact 11 may have a polygonal prism shape. Further, the first contact 11 does not have to have a uniform cross-sectional shape perpendicular to the axis, and may be designed so that the cross-sectional area increases as the distance from the contact portion 18 increases. Further, in the above-described embodiment, the example in which the first conductive type is the n type and the second conductive type is the p type has been described, but the first conductive type is the p type and the second conductive type is the n type. May be configured. That is, in the above-described embodiment, the structure in which the conductive type is inverted between the p-type and the n-type is also one embodiment of the present invention. Further, in the above-described embodiment, GaN is exemplified as the nitride semiconductor, but other nitride semiconductors such as aluminum nitride (AlN) and indium nitride (InN) may be used. Nitride semiconductors are generally Al_xIn_yGa_1-xyIt can be expressed as N (0 x 1,0 y 1,0 x + y 1). Further, the present invention may be applied not only to nitride semiconductors but also to other compound semiconductors such as GaAs and light emitting devices using semiconductor materials (for example, diamond) other than compound semiconductors.

00931 Light emitting element 2 board 3 First conductive semiconductor layer 4 light emitting layer 4A end face 5 Second conductive semiconductor layer 6 Transparent electrode layer 7 Reflective electrode layer 8 Insulation layer 9 Insulation tube layer 10 1st electrode layer 10A longitudinal edge 10B short edge 11 1st contact 11A 1st porch contact 11B 2nd porch contact 12 2nd electrode layer 13 Second contact 14 Etching stop layer 16 Bonding layer 18 Contact 50 submount 64 Light emitting element unit 70 Luminescent element package 71 Resin package C interval D interval F interval G Center of gravity position