Semiconductor device and display device
8 claims: 8 independent, 0 dependent
- 1第1乃至第6のトランジスタを有し、 前記第1乃至第6のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続されることを特徴とする半導体装置。
- 2第1乃至第7のトランジスタを有し、 前記第1乃至第7のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第6のトランジスタのゲートと電気的に接続されることを特徴とする半導体装置。
- 3第1乃至第8のトランジスタを有し、 前記第1乃至第8のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第8のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第6のトランジスタのゲートと電気的に接続されることを特徴とする半導体装置。
- 4画素部と、ゲート線駆動回路と、を有し、 前記画素部は、基板上に設けられ、 前記ゲート線駆動回路は、前記基板上に設けられ、 前記ゲート線駆動回路は、前記画素部と電気的に接続され、 前記ゲート線駆動回路は、第1乃至第6のトランジスタを有し、 前記第1乃至第6のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続されることを特徴とする表示装置。
- 5画素部と、ゲート線駆動回路と、を有し、 前記画素部は、基板上に設けられ、 前記ゲート線駆動回路は、前記基板上に設けられ、 前記ゲート線駆動回路は、前記画素部と電気的に接続され、 前記ゲート線駆動回路は、第1乃至第7のトランジスタを有し、 前記第1乃至第7のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第6のトランジスタのゲートと電気的に接続されることを特徴とする表示装置。
- 6画素部と、ゲート線駆動回路と、を有し、 前記画素部は、基板上に設けられ、 前記ゲート線駆動回路は、前記基板上に設けられ、 前記ゲート線駆動回路は、前記画素部と電気的に接続され、 前記ゲート線駆動回路は、第1乃至第8のトランジスタを有し、 前記第1乃至第8のトランジスタは、同じ極性であり、 前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第3のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第5のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第4のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのゲートと電気的に接続され、 前記第3のトランジスタのソース又はドレインの他方は、前記第5のトランジスタのソース又はドレインの他方と電気的に接続され、 前記第2のトランジスタのゲートは、前記第5のトランジスタのゲートと電気的に接続され、 前記第4のトランジスタのゲートには、第1の信号が入力され、 前記第5のトランジスタのゲートには、第2の信号が入力され、 前記第1のトランジスタのソース又はドレインの一方からは、 第3の 信号が出力され、 前記第6のトランジスタのソース又はドレインの一方は、前記第1のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第8のトランジスタのソース又はドレインの一方と電気的に接続され、 前記第7のトランジスタのソース又はドレインの一方は、前記第6のトランジスタのゲートと電気的に接続されることを特徴とする表示装置。
- 7請求項1乃至請求項 3 のいずれか一項に記載の半導体装置と、 操作キー、アンテナ、キーボード、バッテリー、音声入力部、又はスピーカーと、 を有することを特徴とする電子機器。
- 8請求項 4 乃至請求項 6 のいずれか一項に記載の表示装置と、 操作キー、アンテナ、キーボード、バッテリー、音声入力部、又はスピーカーと、 を有することを特徴とする電子機器。
Independent claims8
130 paragraphs, as filed
0001The present invention relates to the configuration of a digital circuit. More specifically, using a bootstrap circuit The present invention relates to a technique for increasing the amplitude of the output signal. And for display devices that use it Related.
0002In recent years, display devices in which a semiconductor thin film is formed on an insulator, especially on a glass substrate, particularly a thin film transformer. The spread of active matrix type display devices using Jista (hereinafter referred to as TFT) is remarkable. It has become. Active matrix type display devices using TFTs are arranged in a matrix. It has hundreds of thousands to millions of pixels, and the charge of each pixel is charged by the TFT placed on each pixel. The image is displayed by controlling.
0003As a more recent technology, in addition to the TFTs that make up the pixels, TFTs are used in the peripheral area of the pixel area. Technology related to polysilicon TFTs, which are used to simultaneously form drive circuits, has been developed. It has greatly contributed to the miniaturization and low power consumption of the device, and along with this, the field of application has expanded significantly in recent years. Display devices have become indispensable devices for display units of mobile information terminals.
0004A combination of N-channel TFT and P-channel TFT is used as the drive circuit of the display device. CMOS circuits are commonly used. A characteristic of CMOS circuits is the moment when logic changes. Current flows only between them, and no current flows while holding a certain logic (actually, a minute leak current) Because of the existence of), it is possible to keep the current consumption of the entire circuit low, and for high-speed driving. There are advantages.
0005Organic EL elements, FED (field emission display), liquid crystal display The demand for display devices that use self-luminous elements such as the elements used in (a) and liquid crystal elements is Demand for mobile electronic devices is increasing rapidly as they become smaller and lighter, but there are many. Since it is necessary to manufacture a large number of TFTs, the manufacturing cost is ten, in terms of yield, etc. It is difficult to keep it low. It is easy to predict that future demand will increase even more rapidly. Therefore, it is desired that the display device can be supplied at a lower cost.
0006As a method of forming a drive circuit on an insulator, a plurality of photomasks are used to form an active layer. The general method is to expose and etch patterns such as wiring, but this is the method. Since the large number of processes at the time directly affects the manufacturing cost, the number of processes should be as small as possible. Ideal to manufacture. Therefore, the drive times that were conventionally configured by CMOS circuits The path is made using only one conductive type TFT, either N-channel type or P-channel type. Attempts have been made to configure. This method omits part of the ion doping process. And the number of photomasks can be reduced. As a result, costda You can try to get rid of it.
0007Figure 9 (A) shows a TFT load type inverter circuit configured using a TFT with only one polarity. An example is shown. The operation will be described below.
0008FIG. 9B shows the waveform of the signal input to the inverter circuit. Here, the input signal The amplitude shall be between the high potential side power supply VDD and the low potential side power supply GND. For simplicity, GND Think of it as = 0V.
0009The circuit operation will be described. For the sake of clarity and simplicity, the N that make up the circuit The threshold voltage of the channel type TFT is uniformly (VthN) assuming that there is no variation. To do. Similarly, the P-type TFT is uniformly (VthP).
0010Consider the case where a signal as shown in Fig. 9 (B) is input. First, the input signal is the L signal ( When the low potential side power supply is GND), the N-channel type TFT904 is turned off. On the other hand, load TFT Since the 903 is always operating in the saturation region, the potential of the output terminal is the high potential side power supply V. It is pulled up in the direction of DD. On the other hand, when the input signal is an H signal (high potential side power supply VDD), The N-channel TFT904 is turned on. Here, N than the current capacity of the load TFT903 By keeping the current capacity of the channel type TFT904 sufficiently high, the potential of the output node Is lowered in the direction of the low potential side power supply GND.
0011However, in this case, there are the following problems. Figure 9 (C) shows the TFT load type Invar. It shows the output waveform of the circuit. As shown in Fig. 9 (C), the input signal is the L signal. In addition, the potential of the output terminal is the amount indicated by 907, that is, the threshold value of the load TFT903. The potential is lower than VDD by the amount of pressure. This is between the gate and source of the load TFT903 When the voltage becomes smaller than the threshold voltage, almost no current flows through the load TFT903. This is because it becomes sick and turns off. Here, the source terminal of the load TFT903 It is an output terminal, and the gate terminal is connected to VDD. Therefore, the potential of the output terminal is The potential is lower than the potential of the gate terminal by the threshold voltage. That is, the potential of the output terminal Only rises up to (VDD-VthN) at the maximum. In addition, loads TFT903 and N Depending on the ratio of the current capacity of the channel type TFT904, when the input signal is an H signal, the output end The potential of the child is higher than that of GND by the amount indicated by 908. This is close enough to GND In order to attach it, the current capacity of the N-channel type TFT904 is sufficient for the load TFT903. Need to be large.
0012In this way, if an inverter circuit configured using a TFT with only one polarity is used, the input signal will be used. The amplitude of the output signal is attenuated with respect to the amplitude of.
0013Therefore, there are some ways to avoid the problem that the amplitude of the output signal becomes small. (For example, Patent Document 1, Patent Document 2, Patent Document 3, Patent) See Reference 4).
0014FIG. 33 shows a circuit diagram of the inverter circuit shown in Patent Document 1 and Patent Document 2. In Figure 33 In the circuit, the gate terminal of the transistor 3302 is in a floating state, and the capacitive element 3304 It utilizes the fact that the voltage across both ends (potential difference between both ends) does not change.
0015Therefore, next, the operation of FIG. 33 will be described. Input terminal 3305 and input terminal 3306 are connected to each other. The inverted signal is input to. First, the H signal (high potential side power supply VDD) is input to the input terminal 3306. It is assumed that the L signal (low potential side power supply GND) is input to the input terminal 3305. Then, Langista 3303 turns on. As a result, the potential of terminal 3308 is the L signal (low potential side power supply GND. ). Further, in the transistor 3301, the potential of the input terminal 3305 is an L signal (low potential side electric potential). Since it is the potential of the source GND), it is turned on. As a result, terminal 3307 has an L signal (low potential side power supply). It becomes the potential of GND). That is, the voltage across the capacitive element 3304 (potential difference between both ends) is 0V. Become.
0016Next, the H signal (high potential side power supply VDD) is input to the input terminal 3305, and the L signal is input to the input terminal 3306. No. (low potential side power supply GND) is input. Then, the transistor 3303 is turned off. Since the potential of the input terminal 3305 is the potential of the H signal (high potential side power supply VDD), the transistor 3301 turns on and the potential of terminal 3307 rises. And the gate source of transistor 3302 When the voltage between them becomes higher than the threshold voltage, the transistor 3302 turns on and the potential of terminal 3308 turns on. Begins to rise. At that time, when the potential of terminal 3307 rises, finally, the tran Gista 3301 turns off. Because the terminal 3307 becomes the source terminal of the transistor 3301. Therefore, as the potential of terminal 3307 rises, between the gate and source of transistor 3301. This is because the voltage becomes smaller and eventually becomes equal to the threshold voltage. Transi When the gate-source voltage of the Star 3301 becomes equal to the threshold voltage, the transition The data 3301 is turned off. Therefore, the current flow from terminal 3305 to terminal 3307 has stopped. Let's go. That is, the terminal 3307 is in a floating state. As a result, the capacitive element 33 The voltage across 04 (potential difference between both ends) does not change.
0017When transistor 3301 was turned off, the potential of terminal 3308 still continued to rise. Suppose it was. In that case, transistor 3302 is in the on state. That is, the transistor The gate-source voltage of 3302, that is, the voltage across the capacitive element 3304 (potential difference between both ends) is It is larger than the threshold voltage of transistor 3302. Therefore, the potential of terminal 3308 further rises. To do. At this time, at the same time, the potential of the terminal 3307 also rises. Because, at both ends of the capacitive element 3304 Since the voltage (potential difference between both ends) does not change, one terminal (terminal) of the capacitive element 3304 This is because when 3308) rises, the other terminal (terminal 3307) also rises. And as it is , The potential of terminal 3308 continues to rise and finally reaches the high potential side power supply VDD. Terminal 3308 Transistor 3302 stays on until the potential reaches the high potential side power supply VDD. is there. Then, the voltage at the time when the transistor 3301 is turned off is applied to the capacitance element 3304. It is kept as it is. Therefore, the potential of terminal 3307 is more capacitive than that of the high potential side power supply VDD. It is higher by the voltage stored in the child 3304.
0018That is, the potentials of terminals 3307 and 3308 are equal to or higher than the high potential side power supply VDD. It will be ranked. Therefore, the amplitude of the output signal is smaller than the amplitude of the input signal. You can prevent that.
0019Such circuits are commonly referred to as bootstrap circuits.
<p num="0020"><patcit num="1"><text>Japanese Unexamined Patent Publication No. 8-50790</text></patcit><patcit num="2"><text>Japanese Patent No. 3330746</text></patcit><patcit num="3"><text>Patent No. 3092506</text></patcit><patcit num="4"><text>Japanese Patent Application Laid-Open No. 2002-328643</text></patcit></p>
<p num="0021"> However, the inverter circuit shown in FIG. 33 has two major problems.</p><p num="0022"> The first problem is that the H signal (high potential side power supply VDD) is input to the input terminal 3305, and the input terminal Transistor 3301 turns off when L signal (low potential side power supply GND) is input to child 3306. If it is slow, the potential of terminal 3307 and terminal 3308 will not rise sufficiently. That is. Suppose that the transistor 3302 was turned off first. In that case, capacity Since element 3304 is located between the gate and source of transistor 3302, capacitive element 3304 The threshold voltage of the transistor 3302 is stored in. At that point, Since the Langista 3301 is still on, the potential of terminal 3307 is rising. Soshi Finally, the transistor 3301 turns off. At this time, the capacitive element is a transistor 33. The threshold voltage of 02 is stored and transistor 3302 is off. Therefore, The potentials of terminals 3308 and 3307 do not rise any further.</p><p num="0023"> The second problem is that the potential of the H signal input to the input terminal 3305 is the high potential side power supply VDD. If it is too low, it means that the potentials of terminals 3307 and 3308 do not rise sufficiently. Enter If the circuit that outputs the signal to the power terminal 3305 is, for example, the circuit shown in Fig. 9 (A), the H signal It is possible that the potential of No. is lower than that of the high potential side power supply VDD. So tentatively , The difference between the potential of the H signal input to the input terminal 3305 and the high potential side power supply VDD is the transition. Consider the case where the voltage is larger than the threshold voltage of the data 3301. In such a case, input terminal 33 When the H signal is input to 05 and the L signal (low potential side power supply GND) is input to the input terminal 3306, Transistor 3301 does not turn off even if the potential of terminal 3307 stops rising. In other words , Terminal 3307 does not float, and charge is supplied to terminal 3307 from terminal 3305. Continue to be done. Therefore, the potentials of the terminal 3305 and the terminal 3307 are maintained in the same state. But Therefore, for operations such as the voltage across the capacitive element 3304 (potential difference between both ends) does not change. It doesn't become. As a result, the potentials of terminals 3307 and 3308 do not rise sufficiently.</p><p num="0024"> If an inverter circuit with a similar configuration is connected to the output terminal of such an inverter circuit, The signal amplitude of the output terminal becomes even lower. That is, every time you connect a circuit , The amplitude of the output signal becomes smaller and smaller, and it does not operate normally.</p><p num="0025"> On the other hand, in the inverter circuit shown in Patent Document 4, the second problem described above is solved. It has been resolved. FIG. 34 shows the inverter circuit shown in Patent Document 4. Input terminal 3405 The H signal lower than the high potential side power supply VDD is input to, and the L signal (low potential side) is input to the input terminal 3406. When the power supply GND) is input, the potential of terminal 3407 rises and the gate of transistor 3401 Transistor 3401 turns off when the source voltage equals the threshold voltage. In other words Terminal 3407 is in a floating state. Therefore, both ends of the capacitive element 3404 at that time Voltage (potential difference between both ends) is stored. Therefore, when the transistor 3401 is turned off, If transistor 3402 is in the on state, the potential of terminal 3408 will continue to rise, resulting in an end. The potential of the child 3407 also rises.</p><p num="0026"> However, even with the circuit of FIG. 34, the above first problem has not been solved.</p><p num="0027"> In view of the above-mentioned problems, it is necessary to provide a semiconductor device in which the amplitude of the output signal does not easily decrease. Make it an issue. In addition, a circuit can be configured using transistors with only one polarity. An object of the present invention is to provide a semiconductor device.</p><p num="0028">Semiconductor devices are elements (transistors, diodes), capacitors, and capacitors that use semiconductors. It refers to a device that constitutes a circuit including a resistor and the like. Of course, these elements are limited I'm not doing it.</p>
<p num="0029"> The present invention uses the means shown below in order to solve the above problems.</p><p num="0030"> In the present invention, the first transistor, the second transistor, the third transistor, and the first transistor are inserted. A semiconductor device having a power terminal and a second input terminal, which is the source end of the first transistor. The child and the drain terminal of the second transistor are connected, and the drain end of the third transistor The child is connected to the gate terminal of the first transistor, and the first input terminal is the third transition. It is connected to the gate terminal of the star and the gate terminal of the second transistor, and the second input terminal is , It is characterized by being connected to the gate terminal of the first transistor via a rectifying element. Semiconductor devices are provided.</p><p num="0031"> Further, the present invention has the above configuration. A semiconductor device characterized in that the rectifying element is a diode-connected transistor. Is provided.</p><p num="0032"> That is, in the present invention, such as a transistor connected to a signal input portion by a diode. A rectifying element is arranged.</p><p num="0033"> Then, when the diode-connected transistor is turned off, the first transition The gate terminal of the star is in a floating state. At that time, the first transistor is The gate-source voltage is applied to the capacitive element (transistor gate capacitance). It will be saved. After that, when the potential of the source terminal of the first transistor rises, the bootstra Due to the pop effect, the potential of the gate terminal of the first transistor also rises. As a result, the output signal It is possible to prevent the amplitude of</p><p num="0034"> Further, the present invention has the above configuration. A semiconducting element characterized in that a second rectifying element is connected in series with a third transistor. Body equipment is provided.</p><p num="0035"> Further, the present invention has the above configuration. A semiconducting element characterized in that the second rectifying element is a diode-connected transistor. Body equipment is provided.</p><p num="0036"> That is, in the present invention, a diode is connected to the gate terminal portion of the first transistor. A second rectifying element such as a transistor is arranged.</p><p num="0037"> Then, the diode-connected transistor, which is the second rectifying element, turns off. Therefore, it is possible to prevent the potential of the gate terminal of the first transistor from dropping too much. To. As a result, it is possible to prevent the amplitude of the output signal from becoming small.</p><p num="0038"> Further, the present invention has the above configuration. The diode-connected transistor and the first transistor have the same conductive type. A semiconductor device characterized by this is provided.</p><p num="0039"> That is, the first transistor and the diode-connected transistor are of the same conductive type. By having, all the transistors that make up the circuit can have the same conductive type. It will be possible. As a result, the cost can be reduced.</p><p num="0040"> Further, the present invention has the above configuration. A diode-connected transistor, which is the second rectifying element, and the first transistor However, there is provided a semiconductor device characterized by having the same conductive type.</p><p num="0041"> That is, the first transistor and the diode-connected transistor, which is the second rectifying element. Since the Gista has the same conductive type, the magnitude of the threshold voltage of both transistors Can be made approximately the same. The threshold voltage of the first transistor and the second rectifying element The threshold voltage of the child diode-connected transistor is approximately the same. Therefore, it is possible to prevent the current from leaking when the first transistor should be turned off. come.</p><p num="0042">Further, in the above configuration, the present invention has a capacitive element, and one terminal of the capacitive element is a first unit. It is connected to the gate terminal of the Langista, and the other terminal is the source terminal of the first transistor. A semiconductor device characterized by being connected is provided.</p><p num="0043"> The Langista in the present invention is made of any material, means, and manufacturing method. It can be a Langista or any type of transistor. For example, thin film tran It may be a Gista (TFT). Among TFTs, the semiconductor layer is amorphous. It may be polycrystalline, polycrystal, or single crystal. Other tran The transistor may be a transistor made on a single crystal substrate, or it may be on an SOI substrate. It may be a transistor made of It may be a transistor formed on a glass substrate. Besides, organic matter and cars It may be a transistor formed of bon nanotubes. Also, even with MOS type transistors It may be a bipolar transistor.</p><p num="0044"> In the present invention, being connected is synonymous with being electrically connected. To. Therefore, another element, circuit, or the like may be arranged between them.</p>
<p num="0045"> According to the above configuration, the present invention provides one terminal of a capacitive element that constitutes a bootstrap circuit. It can be easily floated. As a result, the amplitude of the output signal is small. It is possible to prevent it from becoming. Also, even if the amplitude of the input signal is small, the boot strike One terminal of the capacitive element constituting the lap circuit can be floated. Therefore, it is possible to prevent the amplitude of the output signal from becoming small. Also, the polarity is A circuit can be configured using only one transistor. Therefore, the manufacturing cost is reduced. It can be suppressed.</p>
0046<figref num="1">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="2">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="3">The figure which shows the graphic symbol which represents the inverter circuit to which this invention is applied.</figref><figref num="4">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="5">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="6">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="7">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="8">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="9">The figure which shows the structure and operation of the conventional inverter circuit.</figref><figref num="10">The figure which shows the circuit structure when this invention is applied to a clocked inverter circuit.</figref><figref num="11">The figure which shows the graphic symbol which represents the clocked inverter circuit to which this invention is applied.</figref><figref num="12">The figure which shows the circuit structure when this invention is applied to the NAND circuit.</figref><figref num="13">The figure which shows the graphic symbol which represents the NAND circuit to which this invention was applied.</figref><figref num="14">The figure which shows the circuit structure when this invention is applied to a NOR circuit.</figref><figref num="15">The figure which shows the circuit structure when this invention is applied to a transfer gate circuit.</figref><figref num="16">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="17">The figure which shows the circuit structure when this invention is applied to a clocked inverter circuit.</figref><figref num="18">The figure which shows the circuit structure when this invention is applied to the NAND circuit.</figref><figref num="19">The figure which shows the circuit structure when this invention is applied to a NOR circuit.</figref><figref num="20">The figure which shows the circuit structure when this invention is applied to a transfer gate circuit.</figref><figref num="21">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="22">The figure which shows the graphic symbol which represents the inverter circuit to which this invention is applied.</figref><figref num="23">The figure which shows the circuit structure when this invention is applied to a clocked inverter circuit.</figref><figref num="24">The figure which shows the graphic symbol which represents the clocked inverter circuit to which this invention is applied.</figref><figref num="25">The figure which shows the circuit structure when this invention is applied to the NAND circuit.</figref><figref num="26">The figure which shows the graphic symbol which represents the NAND circuit to which this invention was applied.</figref><figref num="27">The figure which shows the circuit structure when this invention is applied to an inverter circuit.</figref><figref num="28">The figure which shows the structure of the display device of this invention.</figref><figref num="29">The figure which shows the circuit structure when this invention is applied to a DFF circuit.</figref><figref num="30">The figure which shows the circuit structure when this invention is applied to a DFF circuit.</figref><figref num="31">The figure which shows the circuit structure when the present invention is applied to a shift register.</figref><figref num="32">The figure of the electronic device to which this invention is applied.</figref><figref num="33">The figure which shows the structure of the conventional inverter circuit.</figref><figref num="34">The figure which shows the structure of the conventional inverter circuit.</figref>
0047The circuit configuration of the semiconductor device of the present invention will be described below.
0048(Embodiment 1) In the present embodiment, first, the second question explained in the problem to be solved by the invention. An inverter circuit that addresses the subject will be described. That is, the H signal input to the input terminal When the potential is lower than the high potential side power supply VDD, the potential of a certain terminal does not rise sufficiently. An inverter circuit that addresses this problem will be described.
0049Figure 2 shows that even if the potential of the H signal input to the input terminal 105 is lower than the high potential side power supply VDD. , An inverter circuit is shown in which the potentials of terminals 107 and 108 can be sufficiently increased. input Terminal 105 is the gate of transistor 102 via diode-connected transistor 101. It is connected to the terminal. Since the transistor 101 is diode-connected, its game The G terminal is connected to the input terminal 105. Therefore, the current from terminal 105 to terminal 107 Can flow, and no current can flow from terminal 107 to terminal 105. Also, A capacitive element 104 is connected between the gate terminal and the source terminal of the Langista 102. Tiger The drain terminal of the transistor 103 is connected to the source terminal of the transistor 102, and the transistor The gate terminal of the Gista 103 is connected to the input terminal 106. And the transistor 109 The gate terminal is connected to the input terminal 106, and the drain terminal is the gate terminal of the transistor 102. Is connected to.
0050The source terminal of the transistor 109 and the source terminal of the transistor 103 are power supplies on the low potential side. It is connected to GND, but is not limited to this. Each source terminal has a different potential distribution It may be connected to a wire or a pulse signal may be input.
0051Further, the input terminal 106 includes a gate terminal of the transistor 109 and a gate terminal of the transistor 103. Connected to, but not limited to. Each gate terminal is connected to a separate input terminal It may have been.
0052Further, although the drain terminal of the transistor 102 is connected to the high potential side power supply VDD, Not limited to this. It may be connected to wires of different potentials, or a pulse signal is input. May be.
0053Next, the operation of FIG. 2 will be described. Input terminals 105 and 106 are usually opposite to each other. The converted signal is input. However, it is not possible to operate without always inputting the inverted signal. It is possible. First, the H signal (high potential side power supply VDD) is input to the input terminal 106, and the input terminal 1 It is assumed that the L signal (low potential side power supply GND) is input to 05. Then, transistor 109 and Langista 103 turns on. As a result, the potential of the terminal 108 becomes GND. And terminal 10 Since the potential of 7 becomes GND, the transistor 102 is turned off. Also, terminals 105 and 107 Since the potential is the same, the transistor 101 is turned off. Also, the voltage across the capacitive element 104 (both ends). The potential difference) is 0V.
0054Next, the H signal (high potential side power supply VDD) is input to the input terminal 105, and the L signal is input to the input terminal 106. (Low potential side power supply GND) is input. Then, transistor 109 and transistor 1 03 is off. Since the potential of the input terminal 105 is the potential of the H signal (high potential side power supply VDD) , Transistor 101 is turned on, and the potential of terminal 107 rises. And the transistor 102 When the voltage between source and source becomes higher than the threshold voltage, the transistor 102 turns on and ends. The potential of the child 108 begins to rise. At that time, when the potential of terminal 107 rises, finally Turns off the transistor 101. Because the terminal 107 is the source terminal of the transistor 101 Therefore, as the potential of the terminal 107 rises, the gate and so on of the transistor 101 The boot-to-phase voltage (drain-source voltage) becomes smaller and finally equals the threshold voltage. Because it becomes. Transistor 101 gate-source voltage equals threshold voltage Then, the transistor 101 is turned off. Therefore, the current flow from terminal 105 to terminal 107 Stops. That is, the terminal 107 is in a floating state. As a result, the capacitive element 104 The voltage across both ends (potential difference between both ends) does not change.
0055When the transistor 101 was turned off, the potential of terminal 108 still continued to rise. Suppose you were there. In that case, the transistor 102 is in the on state. That is, transistor 102 The gate-source voltage of, that is, the voltage across the capacitive element 104 (potential difference between both ends) is It is larger than the threshold voltage of the engineer 102. Therefore, the potential of the terminal 108 further rises. At this time, the potential of the terminal 107 also rises at the same time. Because the voltage across the capacitive element 104 (both) Since the potential difference at the end) does not change, one terminal (terminal 108) of the capacitive element 104 is on the top. This is because when it rises, the other terminal (terminal 107) also rises. And as it is, of terminal 108 The potential continues to rise, eventually reaching the high potential side power supply VDD. The potential of terminal 108 is high Transistor 102 remains on until the side power supply VDD is reached. Capacitive element The child 104 holds the voltage at the time when the transistor 101 is turned off as it is. Therefore, the potential of the terminal 107 is stored in the capacitive element 3304 rather than the high potential side power supply VDD. It is higher by the voltage.
0056That is, the potentials of terminals 107 and 108 are equal to or higher than the high potential side power supply VDD. Will be. Therefore, the amplitude of the output signal is smaller than the amplitude of the input signal. , Can be prevented.
0057In this way, the signal input to terminal 106 is an inverted signal at terminals 107 and 108. To. Therefore, in the inverter circuit shown in FIG. 2, the input terminal is the terminal 106, and the output It can be said that the terminal is terminal 107 or 108. And terminal 105 has terminal 106 Should input the inverted signal. Therefore, you can think of terminal 105 as one of the input terminals. I.
0058Also, whether the output terminal is terminal 107 or terminal 108 is the input of the circuit connected to that end. It can be determined by the magnitude of impedance. That is, the terminal 107 is in the operating state. Therefore, it is necessary to make it floating. Therefore, terminal 107 is an input impedance. -Cannot connect to a circuit with low dance. However, at terminal 107, when there is an H signal The potential of can be higher than VDD. On the other hand, in the case of terminal 108, floatin Since it is not necessary to put it in a state, it does not matter even if it is connected to a circuit whose input impedance is not low. There is no title. However, the potential at the time of H signal does not become higher than VDD. In this way, each Because there is a difference between, it is appropriate to decide whether to use terminal 107 or terminal 108 as the output terminal. Just do it.
0059Here, the graphic symbol 301 representing the inverter circuit shown in FIG. 2 is shown in FIG. Input terminal 303 is the end It corresponds to the child 106, and the input terminal 304 corresponds to the terminal 105. Output terminal 302 is terminal 108 or terminal 107 Corresponds to. Signals inverted from each other are input to the terminals 303 and 304. Inverter circuit The signal input to the terminal 303 is inverted and output to the output terminal 302. To. Therefore, it can be said that the terminal 303 is an input terminal as an inverter circuit.
0060Next, when the potential of the H signal input to the input terminal 105 is lower than that of the high potential side power supply VDD. Think about it. Temporarily, the potential of the H signal input to the input terminal 105 and the high potential side power supply VDD Consider the case where the difference between the two is larger than the threshold voltage of the transistor 101. like that Even in this case, the H signal is input to the input terminal 105, and the L signal (low potential side power supply) is input to the input terminal 106. When GND) is input, the potential of terminal 107 rises and between the gate and source of transistor 101. When the voltage becomes equal to the threshold voltage, the transistor 101 turns off and the terminal 107 floats. It becomes a state. Therefore, when the transistor 101 is turned off, the transistor 102 is turned on. If so, the gate-source voltage of the transistor 102 at that time is held by the capacitive element 104. Will be done. Therefore, the potentials of the terminals 108 and 107 rise sufficiently.
0061In this way, even in a normal CMOS circuit, a transistor that uses a P-channel transistor is used. Regarding the gista, even if the polarity is reversed, transistors 101, 109, capacitive element 104, etc. are used. By doing so, it becomes possible to operate normally. This is not just the inverter circuit , Applicable to any circuit.
0062In FIG. 2, the drain terminal of the transistor 102 is connected to the wiring of the potential VDD. However, it is not limited to this. The potential of the drain terminal of the transistor 102 depends on the situation. May change. For example, a pulse signal may be input. Similarly, transistor 103 and The source terminal of transistor 109 is connected to the wiring of potential GND, but it is limited to this. I can't. The potential of the source terminal of transistor 103 or transistor 109 changes depending on the situation. Alternatively, different potentials and signals may be input to each.
0063For example, as shown in FIG. 4, the drain terminal of the transistor 102 is connected to the input terminal 105. It may be. Even in this case, the H signal (high potential side power supply VDD) is sent to the input terminal 106. When the L signal (low potential side power supply GND) is input to the input terminal 105, the output end The potential of the child 108 becomes GND, and the L signal (low potential side power supply GND) is input to the input terminal 106. When the H signal (high potential side power supply VDD) is input to the input terminal 105, the potential of the output terminal 108 Is VDD. Therefore, it works without any problem.
0064Alternatively, by inputting a pulse signal to the drain terminal of the transistor 102, the shift is performed. It is also possible to form a register, a latch circuit, or a part thereof.
0065In FIG. 2, the transistor used was an N-channel type, but the transistor is limited to this. Absent. The circuit may be configured by using a P-channel transistor, or it may be a CMOS type. A circuit may be configured. When all the transistors in the circuit in Fig. 2 are P-channel type May just switch the potentials of VDD and GND.
0066The transistor 101 in FIG. 2 is a transistor having the same polarity as the transistor 102 and the like. However, it is not limited to this. Any element with rectifying property may be used. For example, Instead of the Langista 101, a PN or PIN junction diode or Schottky die Aude or the like may be used. Also, as shown in FIG. 5, the polarity is opposite to that of the transistor 102 and the like. The transistor 101P of the above is connected by a diode, or the like may be used.
0067The capacitive element 104 can be omitted. That is, the transistor 102 It is possible to substitute the capacity. Regarding the gate capacitance of transistor 102, The gate electrode overlaps with the boot region, drain region, LDD region, etc. The capacitance may be formed in such a region, or the capacitance may be formed between the channel region and the gate electrode. May be formed.
0068(Embodiment 2) In the first embodiment, the second problem described in the problem to be solved by the invention is solved. The processed inverter circuit was explained. In the present embodiment, the section to which the invention is to be solved The inverter circuit that addresses the first problem explained in the title will be explained.
0069Here, we return to the circuit of FIG. 33 and analyze the factors that cause the first problem. First, enter H signal (high potential side power supply VDD) is input to power terminal 3306, and L signal (low potential side power supply VDD) is input to input terminal 3305. When the side power supply GND) is input, the terminal 3307 is connected to the L signal (low potential side power supply GND). It will be ranked. That is, the voltage across the capacitive element 3304 (potential difference between both ends) is 0V.
0070Next, the H signal (high potential side power supply VDD) is input to the input terminal 3305, and the L signal is input to the input terminal 3306. When No. (low potential side power supply GND) is input, is the potential of terminal 3307 GND (0V)? Starts to rise. And the potential (VDD-VthN) which is lower than VDD by the threshold voltage. After becoming, it becomes a floating state. In other words, it is necessary to increase the potential difference by that amount. There is. Therefore, that much charging time is required. Therefore, terminal 3307 It will be slower to float.
0071Therefore, in the present invention, the potential of terminal 3307 (or a terminal corresponding thereto) is set to GND (0V). I decided to operate it without lowering it to). However, when the transistor should be turned off, Since it is necessary to make it fluctuate, the potential of the terminal should be lowered to a potential near the threshold voltage. did. As a result, the capacitive element stores the threshold voltage instead of 0V. in this way Since the electric charge is retained from the beginning, the amount of increase in potential can be small. Therefore, charging time Is reduced, and the time until the terminal becomes floating is also reduced.
0072Based on the above principle, configure the circuit and deal with the first problem.
0073In the present embodiment, the first is by improving the circuit described in the first embodiment. Address the problem. Therefore, it is possible to solve both the first problem and the second problem at the same time. Become. Therefore, the basic configuration and operation are the same as in the case of the first embodiment. The explanation is omitted.
0074Figure 1 shows a circuit diagram that is an improvement of Figure 2 and solves both the first and second problems. Figure 1 Now, in order to solve the second problem explained in the problem that the invention is trying to solve, Transistor 110 with diode connection (gate terminal and drain terminal connected) Place in series with Gista 109. In FIG. 1, the transistor 109 is located on the drain terminal side. The Langista 110 is connected, but is not limited to this. For example, a tiger as shown in Figure 6. It may be connected to the source terminal side of the engineer 109.
0075By arranging the diode-connected transistor 110 as shown in FIG. 1, the terminal 107 The potential of is not lower than the threshold voltage. That is, the capacitive element The voltage across 104 (potential difference between both ends) does not become 0V, but becomes a voltage higher than the threshold voltage. Can be done.
0076Therefore, the operation will be briefly described. First, H signal to input terminal 106 (high potential side power supply VDD) Is input, and an L signal (low potential side power supply GND) is input to the input terminal 105. Then , Transistor 109 and transistor 103 are turned on. As a result, the potential of terminal 108 is GND. Will be. However, the potential of the terminal 107 becomes the threshold voltage of the transistor 110. Because Transistor 101 is off. And the gate terminal of the transistor 110 is the drain end. Since it is connected to the child, the source-drain voltage of the transistor 110 becomes the threshold voltage. This is because the transistors 110 are turned off when they become equal. The potential of terminal 107 becomes the threshold voltage Therefore, the voltage across the capacitive element 104 (potential difference between both ends) also becomes the threshold voltage. But Therefore, it is assumed that the threshold voltage of the transistor 110 and the threshold voltage of the transistor 102 are equal to each other. Then, the transistor 102 is turned off.
0077Next, the H signal (high potential side power supply VDD) is input to the input terminal 105, and the L signal is input to the input terminal 106. (Low potential side power supply GND) is input. Then, transistor 109 and transistor 1 03 is off. Since the potential of the input terminal 105 is the potential of the H signal (high potential side power supply VDD) , Transistor 101 is turned on, and the potential of terminal 107 rises. However, in the case of Fig. 2, the potential is It starts to rise from GND (0V), but in the case of Fig. 1, terminal 107 rises from the threshold voltage. start. Therefore, the potential of the terminal 107 rises quickly. As a result, the transistor 101 It quickly turns off and terminal 107 also floats. At that point, terminal 108 Since the potential of is still rising, the transistor 102 is also in the ON state. Therefore, It is possible to deal with the problem that the potentials of terminals 108 and 107 do not rise sufficiently.
0078Note that the transistor 110 allows the amount of change in the potential of the terminal 107 to be small, and the change in potential can be made. Become quick. As a result, the operation of the circuit becomes faster.
0079By using such a configuration, the problem to be solved by the invention has been described. You can solve both the first problem and the second problem at the same time.
0080In addition, in FIGS. 1 and 6, the transistor used was an N-channel type, but the transistor is limited to this. Not done. If all the transistors in the circuits shown in Fig. 1 and Fig. 6 are P-channel type, VD The potentials of D and GND may be exchanged. All transistors in the circuit in Fig. 1 are P-channel The circuit diagram in the case of the shape is shown in FIG.
0081The transistor 110 in FIGS. 1 and 6 has the same polarity as the transistor 102 and the like. Gista, but not limited to this. Any element with rectifying property may be used. For example , PN junction or PIN junction diode instead of transistor 110, Schottky type A diode connected to a transistor with the opposite polarity to the iode, transistor 102, etc. , Etc. may be used. In other words, if the potential of terminal 107 does not drop too much Good.
0082However, the transistor 110 and the transistor 102 are transistors having the same polarity and have a threshold value. It is desirable that the voltages are also approximately equal. Because the transistor 110 and the transistor 102 If the voltage is different, the H signal (high potential side power supply VDD) is input to the input terminal 105, and the input terminal When the L signal (low potential side power supply GND) is input to the child 106, the transistor 102 turns on. This is because there is a possibility that it will go around. Therefore, the transistors 110 and 102 are placed close to each other. It is desirable to make it easier to align the characteristics by doing so. For example, laser the semiconductor layer When crystallizing using, make sure that the same shot hits transistors 110 and 102. Is desirable. However, if it does not interfere with the operation, the transistor 110 and the transistor There is no problem even if the threshold voltage of the engineer 102 is slightly different.
0083In this embodiment, an improved version of the circuit described in the first embodiment will be described. There is. Therefore, the contents described in the first embodiment can be applied to the present embodiment as well. And is possible.
0084(Embodiment 3) In the present embodiment, the invention may be solved by improving the circuit described in the first embodiment. For the inverter circuit that addresses the first and second problems explained in the problem to be solved. I explained about it. In this embodiment, the first problem is solved by improving the circuit shown in FIG. The inverter circuit that has been dealt with will be described.
0085FIG. 8 shows an inverter circuit that is an improvement of the circuit of FIG. 34. In series with transistor 3409 A transistor 801 connected with iodes is arranged. In FIG. 8, the transistor 3409 is displayed. Transistor 801 is placed between the rain terminal and terminal 3407, but it is not limited to this. I. For example, it may be connected to the source terminal side of the transistor 3409.
0086By arranging the transistor 801 in this way, the potential of the terminal 3407 drops too much. Never. Therefore, the potential of terminal 3407 rises quickly. As a result, transistor 34 01 quickly turns off, and terminal 3407 also floats. At that point, Since the potential of terminal 3408 is still rising, transistor 3402 is also on. Therefore, it is possible to deal with the problem that the potentials of terminals 3408 and 3407 do not rise sufficiently. ..
0087Note that the transistor 801 requires a small amount of change in the potential of the terminal 3407, and the change in potential is small. Becomes quicker. As a result, the operation of the circuit becomes faster.
0088By using such a configuration, the problem to be solved by the invention has been described. You can solve both the first problem and the second problem at the same time.
0089In FIG. 8, the transistor used was an N-channel type, but the transistor is limited to this. Absent. The circuit may be configured by using a P-channel transistor, or it may be a CMOS type. A circuit may be configured. When all the transistors in the circuit of Fig. 8 are P-channel type May just switch the potentials of VDD and GND.
0090The transistor 801 in FIG. 8 is a transistor having the same polarity as the transistor 3402 and the like. However, it is not limited to this. Any element with rectifying property may be used. For example, PN junction or PIN junction diode, Schottky type diode instead of Langista 801 A diode with a transistor of the opposite polarity to the transistor 3402, etc. You may use any of them. That is, it is sufficient that the potential of the terminal 3407 does not drop too much. ..
0091However, the transistor 801 and the transistor 3402 are transistors with the same polarity, and the threshold is It is desirable that the value and voltage are also approximately equal. Because of transistor 801 and transistor 3402 If the threshold voltage is different, the H signal (high potential side power supply VDD) is input to the input terminal 3405 and turned on. Transistor 3402 turns on when L signal (low potential side power supply GND) is input to power terminal 3406. This is because there is a possibility of doing so. Therefore, transistor 801 and transistor 3402 It is desirable to make it easier to align the characteristics by arranging them in close proximity. For example , When crystallizing the semiconductor layer with a laser, the same shots are the transistors 801 and 340 It is desirable to hit 2. However, as long as it does not interfere with operation , There is no problem even if the threshold voltages of the transistor 801 and the transistor 3402 are slightly different.
0092(Embodiment 4) In the first to third embodiments, the case where the application is applied to an inverter circuit has been described. Next In this embodiment, an example of application to other circuits will be shown.
0093First, FIG. 10 shows a configuration when applied to a clocked inverter circuit. The circuit in Figure 10 , It is configured by expanding the inverter circuit shown in Fig. 2. But the form of implementation A clocked inverter circuit is configured by extending another circuit shown in states 1 to 3. It is also possible to do.
0094In FIG. 10, transistors 1002B and 1003B are connected to the output terminals of the clocked inverter circuit. , Controls whether the signal is output or not. Usually a clock signal or sampler On / off is controlled in synchronization with the gpulse signal. Therefore, transistor 1002B , 1003B are turned on and off at the same time in synchronization with the signal input to the input terminal 1005B. On the other hand The Langistas 1002 and 1003 invert the input signal input to the input terminal 1005, and the output terminal 10 This is the part that operates to output to 10.
0095As shown in Fig. 10, when the clocked inverter is configured with CMOS type, P channel Transistors 1001, 1009, 1001B, 1009B, capacitive elements in the part where the type transistor is used The child 1004, 1004B, etc. are used to prevent the amplitude of the output signal from becoming small. In FIG. 10, the gate terminal of the transistor 1003B is connected to the input terminal 1005B. , Not limited to this. The gate terminal of transistor 1003B is connected to terminal 1007B May be good.
0096As shown in Fig. 1, a transistor connected in series with transistors 1009, 1009B, etc. by a diode. An engineer may be placed. Also, connect the transistors 1001 and 1001B to the transistor in Fig. 8. By modifying it like the Gista 3401, the inverter circuit in Figure 8 is extended and clocked. An inverter may be configured.
0097The operation of the circuit of FIG. 10 is the same as that described in the first to third embodiments. Therefore, it is omitted.
0098Here, FIG. 11 shows the graphic symbol 1101 representing the clocked inverter shown in the present embodiment. .. Terminal 1105 corresponds to terminal 1005B, and terminal 1106 corresponds to terminal 1006B. Terminal 1105 and terminal 1106 Signals that are inverted from each other are input to. Output terminal when H signal is input to terminal 1105 It is assumed that the signal is output to 1102. And the input terminal 1103 corresponds to the terminal 1006, and the input terminal The child 1104 corresponds to the terminal 1005. When considered as a clocked inverter circuit, input terminal 11 The signal input to 03 is inverted and output to the output terminal 1102. Therefore, terminal 1103 is It can be said that it is an input terminal as a locked inverter circuit. In addition, to terminal 1103 and terminal 1104 Is input with signals that are inverted from each other.
0099Next, FIG. 12 shows a configuration when applied to a NAND circuit. The circuit of FIG. 12 is shown in FIG. It is configured by expanding the inverter circuit. However, in the first to third embodiments It is also possible to configure a NAND circuit by extending the other circuit shown above.
0100In Fig. 12, when the NAND circuit is composed of CMOS type, the P channel type transistor is used. In the part to be used, that is, the transistors 1202, 1202B, the transistors 1201, 1209, 120 Using 1B, 1209B, capacitive elements 1204, 1204B, etc., the amplitude of the output signal becomes small. And are prevented. And when configuring with CMOS type, use N channel type transistor The part, that is, the transistors 1203 and 1203B, is the same as when it is configured with CMOS type. To.
0101As shown in Fig. 1, a transistor connected in series with transistors 1209, 1209B, etc. by a diode. An engineer may be placed. Also, connect the transistors 1201 and 1201B to the transistor in FIG. By changing like Gista 3401, the inverter circuit in Fig. 8 can be expanded and NAND times. Roads may be constructed.
0102The operation of the circuit in FIG. 12 is the same as that described in the first to third embodiments. Therefore, it is omitted.
0103Here, FIG. 13 shows a graphic symbol 1301 representing the NAND circuit shown in the present embodiment. Input end The child 1303 corresponds to terminal 1206, and the input terminal 1305 corresponds to terminal 1206B. Also, input terminal 1304 Corresponds to terminal 1205, and input terminal 1306 corresponds to terminal 1205B. For terminals 1303 and 1304, Signals inverted to each other are input, and signals inverted to each other are input to terminals 1305 and 1306. Is done. The output terminal 1302 corresponds to the terminal 1201. When considering logical operation as a NAND circuit , Terminal 1303 and terminal 1305 can be said to be input terminals as a NAND circuit.
0104Next, FIG. 14 shows a configuration when applied to a NOR circuit. The circuit of FIG. 14 is shown in FIG. It is configured by expanding the inverter circuit. However, the odors of Embodiments 1 to 3 It is also possible to configure a NOR circuit by extending another circuit shown in the above.
0105Similarly in FIG. 14, when the NOR circuit is configured with the CMOS type, the P-channel type transition In the part that uses the data, that is, the transistors 1402 and 1402B, the transistors 1401 and 1409 , 1401B, 1409B, capacitive elements 1404, 1404B, etc. are used to reduce the amplitude of the output signal. It prevents it from turning. And when configuring with CMOS type, N channel type transit The part that uses the data, that is, the transistors 1403 and 1403B, is the same as when configuring the CMOS type. To do.
0106As shown in Fig. 1, a transistor connected in series with transistors 1409, 1409B, etc. by a diode. An engineer may be placed. Also, the connections of transistors 1401 and 1401B are connected in FIG. By changing like Gista 3401, the inverter circuit in Fig. 8 is expanded to the NOR circuit. May be configured.
0107The operation of the circuit in FIG. 14 is the same as that described in the first to third embodiments. Therefore, it is omitted.
0108Next, Fig. 15 shows the case where it is applied to the transfer gate circuit (analog switch circuit). The configuration is shown. The circuit of FIG. 15 is configured by extending the inverter circuit shown in FIG. ing. However, by extending another circuit shown in the first to third embodiments, the transition is performed. It is also possible to configure a spargate circuit.
0109In the case of FIG. 15, which of the input / output terminals, terminals 1510 and 1511, has a higher potential? It depends on the situation. Therefore, it is unclear which side of the terminal will be the source terminal. .. Therefore, in FIG. 15, the transistor 1502 and the transistor 1502B are arranged in parallel, and the capacitive element 1 is arranged. The connection between 504 and 1504B was changed and placed. As a result, the potential of either terminal 1510 or 1511 is low. However, the potentials of the gate terminals of transistor 1502 and transistor 1502B are sufficiently raised. Can be done.
0110Therefore, in the case of a transfer gate circuit, when configuring with CMOS type, P-cha Not only for the part that uses the flannel type transistor, but for both transistors Then, using transistors 1501, 1509, 1501B, 1509B, capacitive elements 1504, 1504B, etc. It prevents the amplitude of the force signal from becoming small. In this way, the amplitude of the output signal is small. A diode-connected transistor or a device for the part of the transistor that becomes fragile By arranging a metering element or the like, it is possible to operate normally.
0111As shown in Fig. 1, a transistor connected in series with transistors 1509, 1509B, etc. by a diode. An engineer may be placed. Also, connect the transistors 1501 and 1501B to the transistor in FIG. By changing it like Gista 3401, the inverter circuit in Fig. 8 can be expanded and transferred. An arc gate circuit may be configured.
0112The operation of the circuit in FIG. 15 is the same as that described in the first to third embodiments. Therefore, it is omitted.
0113In addition, in FIGS. 10, 12, 14, and 15, the N-channel type transistor was used. Not limited to this. All transistors in the circuits shown in Figures 10, 12, 14 and 15 are P-channel type. If this is the case, the potentials of VDD and GND may be exchanged.
0114In this embodiment, when applied to various circuits such as NAND circuits, As described above, the applicable circuit is not limited to the circuit described in this embodiment. Various It can be applied to various circuits.
0115In this embodiment, an extension of the circuit described in the first to third embodiments will be described. I'm sorry. Therefore, the contents described in the first to third embodiments are also suitable for the present embodiment. It is possible to use.
0116(Embodiment 5) In the first embodiment, in the inverter circuit of FIG. 2, the output terminal is not only the terminal 108 but also the terminal 108. It has been described that terminal 107 may be used. Therefore, in the present embodiment, the output terminal 107 is output. An example of constructing various circuits by using force will be described. That is, the signal from terminal 108 The inverter circuit that outputs the number is operated as a level correction circuit, and various circuits are operated. An example of the case of making it is shown.
0117First, FIG. 16 shows the configuration when applied to an inverter circuit. In FIG. 16, in FIG. The inverter circuit is used as the level correction circuit, and the terminal 107 is used as the output terminal, and another time. It is connected to the input terminal of the road (inverter circuit in this case). And the level correction circuit 1601 The circuit (inverter circuit in this case) is operated normally by using the signal output from.
0118The input terminal 1603 and the input terminal 1604 of the level correction circuit 1601 are in contact with the terminal 105 and the terminal 1206, respectively. It is being continued. The output terminal 1605 of the level correction circuit 1601 is connected to the terminal 107, and the output terminal 160 6 is connected to terminal 106.
0119Signals inverted from each other are input to the input terminal 1603 and the input terminal 1604. Then, the output end The signal of the input terminal 1604 is output to the child 1606 as it is, while the input terminal is output to the output terminal 1605. The potential of the signal of the child 1603 is adjusted and output. Specifically, in the case of H signal, it is higher The potential is output.
0120Therefore, the output terminal 1605 has a P-channel type transition when it is configured as a CMOS type. The transistor of the part that uses the data may be connected. Then, the amplitude of the output signal becomes smaller. It is possible to prevent it from happening.
0121In FIG. 16, the output terminal 1605 of the level correction circuit 1601 is connected to the gate terminal of the transistor 1608. The output terminal 1606 is connected to the gate terminal of the transistor 1609. The conclusion As a result, a signal is output to the output terminal 1607 without reducing the amplitude value.
0122In this way, when configuring with CMOS type, the part that uses P channel type transistor A signal is input from the output terminal 1605 to the gate terminal of the Langista. As a result, the circuit is positive It will always work.
0123The level correction circuit is not limited to the configuration shown in FIG. Embodiments 1 to 3 The circuit described above can be used arbitrarily.
0124Here, assuming that the circuit of FIG. 16 is represented by the graphic symbol 301 representing the inverter circuit shown in FIG. 3, the terminals 1604 corresponds to terminal 303, terminal 1603 corresponds to terminal 304, and terminal 1607 corresponds to terminal 302. It becomes.
0125Similarly, FIG. 17 shows the configuration when applied to a clocked inverter circuit. level Using the correction circuit 1601C, the transistors 1702 and 1705 are turned on and off at the same time, and the level correction times. Transistors 1703 and 1704 are controlled using the path 1601A.
0126Since a high potential can be applied to the gate terminals of transistors 1702 and 1703, the output signal It is possible to prevent the amplitude of the number from becoming small.
0127Here, if the circuit of FIG. 17 is represented by the graphic symbol 1101 representing the clocked inverter circuit shown in FIG. Then, terminal 1604A corresponds to terminal 1103, terminal 1603A corresponds to terminal 1104, and terminal 1604C corresponds to the end. It corresponds to the child 1106, the terminal 1603C corresponds to the terminal 1105, and the terminal 1706 corresponds to the terminal 1102. Become.
0128Similarly, FIG. 18 shows the configuration when applied to a NAND circuit. Level correction circuit 1601 B is used to control transistors 1802 and 1805, and level correction circuit 1601A is used to control transistors. Controls Gista 1803 and 1804.
0129Since a high potential can be applied to the gate terminals of transistors 1802 and 1803, the output signal It is possible to prevent the amplitude of the number from becoming small.
0130Here, assuming that the circuit of FIG. 18 is represented by the graphic symbol 1301 representing the NAND circuit shown in FIG. 13, the terminal 1604A corresponds to terminal 1303, terminal 1603A corresponds to terminal 1304, terminal 1604B corresponds to terminal 1105 However, terminal 1603B corresponds to terminal 1306, and terminal 1806 corresponds to terminal 1302.
0131Similarly, FIG. 19 shows the configuration when applied to a NOR circuit. Level correction circuit 1601B The transistors 1902 and 1905 are controlled using, and the level correction circuit 1601A is used for the transition. Controls the stars 1903 and 1904.
0132Since a high potential can be applied to the gate terminals of transistors 1902 and 1903, the output end It is possible to prevent the amplitude of the output signal of the child 1906 from becoming small.
0133Similarly, FIG. 20 shows the configuration when applied to a transfer gate circuit. level Transistor 2003 is controlled using the correction circuit 1601A.
0134Since a high potential can be applied to the gate terminal of the transistor 2002, the input / output terminal 20 It is possible to prevent the amplitude of the signals of 03 and 2004 from becoming small.
0135So far, as shown in FIGS. 16 to 20, the case where there is one output terminal has been described. But that When another circuit is connected to the end of the circuit, an inverting signal is often required. There Next, a case where there are two output terminals and an inverted signal is also output will be described.
0136FIG. 21 shows a configuration when applied to an inverter. One inn with transistors 2103 and 2104 A burter circuit is configured, and one inverter circuit is composed of transistors 2103B and 2104B. .. If an inverted signal is input to each inverter circuit, two signals inverted from each other are output. I can help.
0137However, the gate terminals of transistor 2103 and transistor 2103B have higher electricity than VDD. You must be able to enter the place. And transistor 2103 and transistor 2103 Signals that are inverted from each other must be input to the gate terminal of B. Therefore, two Level correction circuits 1601A and 1601B are required.
0138Here, the case where the circuit of FIG. 21 is represented by the symbol 2201 is shown in FIG. The signal of input terminal 2203 is anti It is turned and output to the output terminal 2202. The input terminal 2204 has a signal inverted from that of the input terminal 2203. Is input, and a signal inverted from that of the output terminal 2202 is output to the output terminal 2207. Then Terminal 1604A corresponds to terminal 2203, terminal 1603A corresponds to terminal 2204, and terminal 2106 corresponds to terminal 2202. At the same time, terminal 2106B corresponds to terminal 2207.
0139Similarly, FIG. 23 shows a configuration when applied to a clocked inverter. Transistor 2302 , 2303, 2304, 2305 make up one clocked inverter circuit, and transistors 2302B, 2 The 303B, 2304B, and 2305B make up one clocked inverter circuit. Each clock If an inverted signal is input to the inverter circuit, two signals inverted from each other are output. Can be done.
0140However, the gate terminals of transistor 2303 and transistor 2303B have higher electricity than VDD. You must be able to enter the place. And transistor 2303 and transistor 2303 Signals that are inverted from each other must be input to the gate terminal of B. Therefore, two Level correction circuits 1601A and 1601B are required.
0141Also, the gate terminals of transistor 2302 and transistor 2302B have higher potentials than VDD. Must be able to be entered. However, transistor 2302 and transistor 2302 The same signal may be input to the gate terminal of B. Therefore, one level correction circuit 160 1C is required.
0142Here, FIG. 24 shows a case where the circuit of FIG. 23 is represented by the symbol 2401. H signal is input to terminal 2405 At that time, the signal of the input terminal 2403 is inverted and output to the output terminal 2402. Input terminal 24 A signal inverted from the input terminal 2403 is input to 04, and an input terminal 2405 is input to the input terminal 2406. The inverted signal is input, and the signal inverted from the output terminal 2402 is output to the output terminal 2407. Is done. Then, terminal 1603C corresponds to terminal 2405, terminal 1604C corresponds to terminal 2406, and terminal 1604. A corresponds to terminal 2403, terminal 1603A corresponds to terminal 2404, terminal 2306 corresponds to terminal 2402, and the end The child 2306B corresponds to the terminal 2407.
0143Similarly, FIG. 25 shows a configuration when applied to a NAND circuit. Transistors 2502, 2503, 2504, 2505 make up one NAND circuit, and transistors 2502B, 2503B, 2504B, 2505B It constitutes one NAND circuit. If you input an inverted signal to each NAND circuit , It is possible to output two signals that are inverted from each other.
0144However, the gate terminals of transistors 2502, 2503, 2502B, 2503B have higher electricity than VDD. You must be able to enter the place. And transistor 2502 and transistor 2502 The gate terminal of B, or the gate terminal of transistor 2503 and transistor 2503B, is connected to each other. The inverted signal must be input. Therefore, four level correction circuits 1601A, 1 601B, 1601D, 1601E are required.
0145Here, FIG. 26 shows a case where the circuit of FIG. 25 is represented by the symbol 2601. Signals of input terminals 2603 and 2605 Is output to the output terminal 2602. A signal inverted from the input terminal 2603 is input to the input terminal 2604. The signal is input to the input terminal 2606, which is the reverse of the input terminal 2605, and is input to the output terminal 2607. Outputs a signal inverted from the output terminal 2602. Then, terminal 1604B corresponds to terminal 2603. However, terminal 1604A corresponds to terminal 2605, terminal 1603B corresponds to terminal 2604, and terminal 1603A corresponds to terminal 260. It corresponds to 6, terminal 2506 corresponds to terminal 2602, and terminal 2506B corresponds to terminal 2607.
0146Similarly, it can be applied to NOR circuits.
0147In this embodiment, the potential level is adjusted by using the level correction circuit. Not limited to. For example, even if a signal with a large amplitude is directly input and operated. Good. For example, the signal of terminal 1605C in FIGS. 17 and 23 does not use the level correction circuit 1601C. , Directly input a signal with a large amplitude, specifically, a signal whose potential of the H signal is larger than VDD. You may. Similarly, the signals of terminals 1605A, 1606A, 1605B, 1606B in FIGS. 17 and 23 are A signal having a large amplitude may be directly input without using the level correction circuits 1601A and 1601B.
0148In this embodiment, first, the potential level is adjusted by using the level correction circuit, and then the potential level is adjusted. The signal was input to the circuit to be operated, but it is not limited to this. On the contrary, first of all, it works You can operate it in the circuit you want to set up and then adjust the level of its potential. I. FIG. 27 shows a configuration when applied to an inverter circuit. Transistor 2708, Two sets of inverter circuits are constructed using 2709, 2710, and 2711. Two sets will be provided in the latter stage This is because the level correction circuit 2701 of the above also requires an inverting signal. And input terminal 27 Input a signal from the input terminal 2704 that receives 03 and its inverted signal, and level with the level correction circuit 2701. Is adjusted, and the signal is output from the output terminal 2707. In addition to the inverter, other circuits It can also be applied in.
0149As described above, in the present embodiment, the clocked inverter circuit, the NAND circuit, etc. The case where it is applied to various circuits has been described, but the applicable circuits are described in the present embodiment. It is not limited to the circuit. It can be applied to various circuits.
0150In this embodiment, the circuit using the circuits described in the first to fourth embodiments will be described. I'm sorry. Therefore, the contents described in the first to fourth embodiments are also suitable for the present embodiment. It is possible to use it, and by using a semiconductor device having these circuit configurations, it is accurate. It is possible to manufacture a semiconductor device that performs various operations at low cost.
<p num="0151"> In this embodiment, the configuration and operation of the display device, the signal line drive circuit, and the like will be described. I will reveal. A part of the signal line drive circuit and a part of the gate line drive circuit are shown in the first to fifth embodiments. The circuit configuration can be applied.</p><p num="0152"> As shown in FIG. 28, the display device includes a pixel 2801, a gate line drive circuit 2802, and a signal line drive circuit 28. Have 10. The gate line drive circuit 2802 sequentially outputs a selection signal to the pixel 2801. Signal line The drive circuit 2810 sequentially outputs a video signal to the pixel 2801. Pixel 2801 follows the video signal Therefore, the image is displayed by controlling the state of light. Signal line drive circuit 2810 to pixel 28 The video signal input to 01 is often a voltage. That is, the display elements arranged in the pixels And the element that controls the display element is the video signal (voltage) input from the signal line drive circuit 2810. Therefore, it often changes the state. In rare cases, the video message input to pixel 2801 The number may be an electric current. Examples of display elements arranged in pixels include liquid crystal (LCD) and Elements for organic EL and FED (field emission display), DMD (digital) Mirror device) etc.</p><p num="0153"> A plurality of gate line drive circuits 2802 and signal line drive circuits 2810 may be arranged.</p><p num="0154"> The signal line drive circuit 2810 can be divided into a plurality of parts. Roughly speaking, as an example 2803, 1st latch circuit (LAT1) 2804, 2nd latch circuit (LAT2) 2805, Digita It is divided into the analog conversion circuit 2806 and so on.</p><p num="0155"> Therefore, the operation of the signal line drive circuit 2810 will be briefly described. The shift register 2803 is flickering It is composed of multiple rows of desktop circuits (FF) and latch circuits, and has a clock signal (S-CLK) 2 812, start pulse (SP) 2813, clock inversion signal (S-CLKb) 2811 are input, these Sampling pulses are output sequentially according to the timing of the signal of.</p><p num="0156"> The sampling pulse output from the shift register 2803 is input to the first latch circuit 2804. Will be done. A video signal is input to the first latch circuit 2804 from the video signal line 2808. , Holds the video signal in each column according to the timing of the sampling pulse input Ku. If the digital-to-analog conversion circuit 2806 is installed, the video signal will be digital. The value.</p><p num="0157"> In the first latch circuit 2804, when the holding of the video signal up to the last row is completed, the horizontal return period In the meantime, a latch pulse is input from the latch control line 2809, and the first latch is performed. The video signals held on the road 2804 are transferred to the second latch circuit 2805 all at once. afterwards , The video signal held in the second latch circuit 2805 is digital / analog for one line at the same time. It is input to the conversion circuit 2806. And it is output from the digital-to-analog conversion circuit 2806. As for the signal, the signal is input to the pixel 2801.</p><p num="0158"> The video signal held in the second latch circuit 2805 goes through various circuits to the pixel 2801. While being input to, the shift register 2803 outputs a sampling pulse again. To. That is, two operations are performed at the same time. As a result, line sequential drive becomes possible. After that , Repeat this operation.</p><p num="0159"> The first latch circuit 2804 and the second latch circuit 2805 are circuits that can store analog values. In many cases, the digital-to-analog conversion circuit 2806 can be omitted. Also, on pixel 2801 If the data to be output is binary, that is, a digital value, a digital-to-analog conversion circuit 2806 can often be omitted. In addition, the signal line drive circuit 2810 has a level shift circuit and a gun. In some cases, a correction circuit, a voltage-current conversion circuit, an amplifier circuit, etc. are built-in.</p><p num="0160"> In addition, there is no first latch circuit 2804 or second latch circuit 2805, and the video signal line 2808 and pixels 2801 is connected via a transfer gate circuit (analog switch circuit) In some cases. In that case, the sampling pulse output from the shift register 2803 is Controls the transfer gate circuit.</p><p num="0161"> As described above, the configuration of the signal line drive circuit 2810 is not limited to FIG. 28, and there are various configurations.</p><p num="0162"> On the other hand, the gate line drive circuit 2802 may only sequentially output the selection signal to the pixel 2801. Since there are many, a shift register having the same configuration as the shift register 2803 of the signal line drive circuit 2810. It is often composed of a level shift circuit, an amplifier circuit, etc. However, a gate wire drive The configuration of the dynamic circuit 2802 is not limited to this, and there are various configurations.</p><p num="0163"> The circuit configurations of the first to fifth embodiments are described in the signal line drive circuit 2810, the gate line drive circuit 2802, and the like. Shift register, 1st latch circuit (LAT1) 2804 and 2nd latch of signal line drive circuit 2810 It can be applied to various parts that make up a circuit, such as circuit 2805.</p><p num="0164"> Therefore, it is used in the shift register, the first latch circuit (LAT1) 2804, the second latch circuit 2805, etc. The DFF circuit (delay flip-flop circuit) that can be used is shown in FIGS. 29 and 30.</p><p num="0165">In the DFF circuit 2901 of FIG. 29, a signal is input to the input terminal 2904 and input to the terminals 2906 and 2907. The operation is controlled by the synchronization signal. Then, a signal is output to the output terminal 2902. end Signals inverted to each other are input to the child 2904 and terminal 2905, and the terminals 2906 and 2907 also receive each other. The inverted signal is input to. And as an output, terminals 2902 and 2903 are opposite to each other. The converted signal is output. Similarly, in the DFF circuit 3001 of FIG. 30, at terminals 300 to 3007, Signals are exchanged.</p><p num="0166"> In FIG. 29, a circuit that also outputs an inverted signal is used. On the other hand, in FIG. 30, A circuit that does not output an inverted signal is used. Therefore, in order to create an inverted signal, The circuits of each part are arranged in parallel.</p><p num="0167"> Next, FIG. 31 shows a part of the shift register configured by using the DFF circuit or the like. DFF times It is composed of roads 2901A to 2901D. As a DFF circuit, even the circuit shown in Fig. 29 The circuit shown in FIG. 30 may be used. Clock signal (S-CLK) 2812, clock inversion signal (S-CLKb) , Is input to the part corresponding to terminals 2906, 2907 (or terminals 3006, 3007) and synchronizes with that signal. Then, the shift register operates.</p><p num="0168">When configuring the first latch circuit (LAT1) 2804 using a DFF circuit, etc., terminals 2906 and 2907 From the shift register to the part corresponding to (or terminals 3006, 3007) The output sampling pulse is input. In addition, the second latch using a DFF circuit or the like When configuring circuit (LAT2) 2805, it corresponds to terminals 2906, 2907 (or terminals 3006, 3007). A latch pulse is input from the latch control line 2809 to the portion.</p><p num="0169"> In the DFF circuit in the shift register, as a clocked inverter circuit , When using the circuits shown in Fig. 17 and Fig. 23, the clock signal (S-CLK) 2812 and the clock inversion signal ( If the signal amplitude of S-CLKb) is made larger than the amplitude of the power supply voltage, the circuit shown in Fig. 17 or Fig. 23 should be used. It is possible to omit the level correction circuit 1601C. Similarly, the first latch circuit (LAT1) ) Clocked Invar in the DFF circuit in 2804 and 2nd latch circuit (LAT2) 2805 When a circuit such as Fig. 17 or Fig. 23 is used as the data circuit, the data input from the video signal line 2808 Signal amplitude of deo signal and latch pulse input from latch control line 2809 Is larger than the amplitude of the power supply voltage, the level correction circuit in the circuits shown in FIGS. 17 and 23. It is possible to omit some of.</p><p num="0170">As already described, what type of transistor is the transistor in the present invention. It may be a gista or may be formed on any substrate. Therefore, as shown in FIG. Such circuits may be all formed on a glass substrate or formed on a plastic substrate. It may be formed, it may be formed on a single crystal substrate, or it may be formed on an SOI substrate. It may be formed on any substrate. Alternatively, the times in Figure 28 Part of the path is formed on one board and another part of the circuit in FIG. 28 is on another board. It may be formed. That is, all the circuits in FIG. 28 are formed on the same substrate. It does not have to be. For example, in FIG. 28, the pixel 2801 and the gate line drive circuit 2802 are , Formed on a glass substrate using TFT, the signal line drive circuit 2810 (or part of it) , Formed on a single crystal substrate, and the IC chip is connected by COG (Chip On Glass) on the glass substrate. It may be arranged. Alternatively, use the IC chip with TAB (Tape Auto Bonding) or a printed circuit board. It may be connected to a glass substrate.</p><p num="0171"> As described above, the display device is a semiconductor device having the circuit configuration described in the first to fifth embodiments. It is possible to use a device.</p>
<p num="0172"> A video camera as an electronic device having a display device using the semiconductor device of the present invention on the display unit. , Digital camera, goggle type display (head mounted display), navigation System, sound reproduction device (car audio, audio component, etc.), notebook type par Sonal computers, game machines, personal digital assistants (mobile computers, mobile phones, mobile phones) An image playback device (specifically, Digital) equipped with a band-type game machine or electronic book, etc., and a recording medium. A display that can play back recording media such as Versatile Disc (DVD) and display the image. (Equipped device) and the like. A specific example of these electronic devices is shown in FIG.</p><p num="0173"> FIG. 32 (A) shows the light emitting device, which includes the housing 13001, the support base 1302, and the display unit 13003. , Speaker section 13004, video input terminal 13005, etc. are included. Here, the semi-leading of the present invention A display device using the body device can be used for the display unit 13003. Also according to the present invention , The light emitting device shown in FIG. 32 (A) is completed. Since the light emitting device is a self-luminous type, it is a backlight. Is not required, and the display unit can be thinner than the liquid crystal display. The light emitting device Includes all information display devices for personal computers, TV broadcast reception, advertisement display, etc. ..</p><p num="0174"> Figure 32 (B) shows a digital still camera, which includes the main body 13101, display unit 13102, and image receiver. Part 13103, operation key 13104, external connection port 13105, shutter 13106 Etc. are included. Here, the display device using the semiconductor device of the present invention is used for the display unit 13102. be able to. Further, according to the present invention, the digital still camera shown in FIG. 32 (B) is completed. ..</p><p num="0175"> Figure 32 (C) shows a notebook personal computer with a main body 13201 and a housing 1320. 2, Display 13203, Keyboard 13204, External connection port 13205, Pointy Includes Ngmouth 13206 and the like. Here, the display device using the semiconductor device of the present invention is a display device. It can be used in part 13203. Further, according to the present invention, the light emitting device shown in FIG. 32 (C) is completed. Made.</p><p num="0176"> Figure 32 (D) shows a mobile computer, which includes the main unit 13301, display unit 13302, and Sui. Includes switch 13303, operation keys 13304, infrared port 13305, etc. Here, the main departure A display device using a bright semiconductor device can be used for the display unit 13302. In addition, the main departure Ming completes the mobile computer shown in Figure 32 (D).</p><p num="0177"> Figure 32 (E) shows a portable image playback device (specifically, a DVD playback device) equipped with a recording medium. Yes, main body 13401, housing 13402, display unit A13403, display unit B13404, note Recording medium (DVD, etc.) Reading unit 13405, operation keys 13406, speaker unit 1340 Including 7 mag. The display unit A13403 mainly displays image information, and the display unit B13404 mainly displays image information. However, in the display device using the semiconductor device of the present invention, the display units A and B1 are displayed. It can be used for 3403 and 13404. For image playback devices equipped with a recording medium It also includes home video game machines. Further, according to the present invention, the DVD playback device shown in FIG. 32 (E). Is completed.</p><p num="0178"> Figure 32 (F) shows a goggle-type display (head-mounted display), which is the main body 1. Includes 3501, display 13502, and arm 13503. Here, the semiconductor device of the present invention The display device using the above can be used for the display unit 13502. Further, according to the present invention, FIG. 32 The goggle type display shown in (F) is completed.</p><p num="0179"> Figure 32 (G) shows a video camera, which is the main body 13601, display 13602, and housing 1360. 3, external connection port 13604, remote control receiver 13605, image receiver 13606, batte Includes Lee 13607, voice input unit 13608, operation keys 13609, etc. Here, the present invention A display device using the semiconductor device of the above can be used for the display unit 13602. The present invention Completes the video camera shown in FIG. 32 (G).</p><p num="0180"> Figure 32 (H) shows a mobile phone, which includes the main body 13701, the housing 13702, and the display unit 13703. Audio input unit 13704, audio output unit 13705, operation key 13706, external connection port 1 Includes 3707, antenna 13708, etc. Here, a display device using the semiconductor device of the present invention. Can be used for the display unit 13703. The display unit 13703 is white on a black background. By displaying colored characters, the current consumption of the mobile phone can be suppressed. Also according to the present invention , The mobile phone shown in Fig. 32 (H) is completed.</p><p num="0181"> If the emission brightness of the light emitting material becomes high in the future, the light including the output image information will be lensed. It is also possible to use it for front type or rear type projectors by enlarging and projecting with etc. ..</p><p num="0182"> In addition, the above electronic devices are used for electronic communication such as the Internet and CATV (cable TV). More often the information delivered through the line is displayed, especially the opportunity to display video information I'm doing it. Since the response speed of the light emitting material is very high, the light emitting device is preferable for moving image display.</p><p num="0183"> In addition, since the light emitting part of the light emitting device consumes power, the light emitting part is reduced as much as possible. It is desirable to display the information as such. Therefore, mobile information terminals, especially mobile phones and sound reproduction When a light emitting device is used for a display unit that mainly uses character information such as a device, the non-light emitting portion is used as the background. It is desirable to drive the character information so as to be formed by the light emitting portion.</p><p num="0184"> As described above, the scope of application of the present invention is extremely wide, and it is used for the display unit of electronic devices in all fields. It is possible. Further, the electronic device of this embodiment is any of the electronic devices shown in the first to fifth embodiments. A display device using a semiconductor device having a circuit configuration may be provided.</p>
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Every citation, both ways
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| JP58151719A | Cites | Japan |
67 members in 5 offices
Priority claims2
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| 2002374098 | Japan | A |
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Numbers
- Publication
- 5777769
- Application
- 104863
Titles2
- Japanese
- 半導体装置、表示装置及び電子機器
- English
- Semiconductor devices, display devices and electronic devices
Classification
- CPC, 13
- H03K19/018507
- G09G5/003
- G09G3/20
- G09G2310/0267
- G09G2310/0275
- G09G2310/0286
- G09G2310/0291
- G09G3/36
- H10D86/60
- H10D86/441
- H10D86/481
- G09G2310/0289
- G09G2330/021
- IPC, 12
- H03K19 094
- H03K3 356
- G09F9 30
- G09G3 00
- G09G3 20
- H03F3 16
- H03K17 00
- H03K17 06
- H03K17 687
- H03K19 096
- H10D30 67
- H10D84 03
