Image decoding apparatus, image decoding method, image coding apparatus, and image coding method

The present invention relates to an image decoding device and an image coding device that decode and encode moving image information, and more particularly to an image decoding device and an image coding device that perform decoding and coding by parallel processing. ..

MPEG (Motion Pictures Experts Group) coding method using inter-frame difference is often used as a technique for compressing and coding (hereinafter, simply referred to as "coding") moving image information. As an MPEG coding method, in addition to the conventionally used MPEG-2 (ISO / IEC13818-2) and MPEG-4 (ISO / IEC14496-2), in recent years H.264 / MPEG-4 AVC (ISO) New coding methods such as / IEC14496-10) (hereinafter simply referred to as "H.264") and VC-1 (SMPTE 421M) are being used.

In such a coding method, one screen (picture) is divided into blocks (luminance component: 16 pixels × 16 pixels) having a predetermined number of pixels, and decoding processing or coding processing is performed for each block. This block is called a macroblock.

FIG. 18 is a diagram showing the dependency of adjacent macroblocks of H.264. In the new coding method represented by H.264, when encoding a macroblock, the compression efficiency is improved by utilizing the correlation between the macroblock to be encoded and the macroblocks around it. Therefore, in order to decode or encode an arbitrary macroblock MB10, as shown in FIG. 18, the left adjacent macroblock MB11 adjacent to the macroblock MB10, the upper left adjacent macroblock MB12, the upper upper adjacent macroblock MB13, and the upper right It is necessary to refer to the processing results of the four adjacent macroblocks of the adjacent macroblock MB14, and these adjacent macroblocks MB11 to MB14 must be decoded or encoded in advance.

Further, in order to perform the decoding process or the coding process at high speed, a plurality of decoding units for decoding macroblocks or coding units for coding (hereinafter, simply referred to as "macroblock processing units") are used. An image decoding device or an image coding device that executes a decoding process or a coding process in parallel has been proposed. In such an image decoding device or an image coding device, the above-mentioned dependency of adjacent macroblocks is not solved by individual macroblock processing units, but is linked by a plurality of macroblock processing units that operate in parallel. However, it needs to be resolved. Therefore, conventionally, a method for resolving this dependency has been proposed (see, for example, Patent Document 1).

FIG. 19 is a diagram showing a processing procedure of the image decoding device and the image coding device described in Patent Document 1. In FIG. 19, the numbers assigned to the macroblock MB indicate the processing order of the macroblock MB in the picture Pic, and the macroblock MBs having the same number are processed in parallel. As shown in FIG. 19, the image decoding device and the image coding device start processing from the macro block MB on the upper left of the picture Pic, and when processing an arbitrary macro block MB, the macro block MB and its By processing the macroblock MB located on the left side of the row two columns one row below the macroblock MB in parallel, the above-mentioned dependency of the adjacent macroblock is solved.

That is, in order to process (decode or encode) the macroblock MB due to the above-mentioned dependency, the processing result of the adjacent macroblock MB adjacent to the left, upper left, upper, and upper right of the processing target macroblock MB. Information is needed to indicate. However, when processing each row (macroblock line) of the picture Pic in parallel, if you simply try to process the macroblock MB located in the same column in each row in parallel, it is necessary for each processing target macroblock MB. Information on the adjacent macroblock MB that is said to be cannot be obtained. Therefore, such parallel processing cannot be realized. Therefore, in the image decoding device and the image coding device of Patent Document 1, each row of the picture Pic is processed in parallel by different columns in which the processing target macroblock MB is located in each row.

In this way, by setting the position (column) of the macroblock to be processed for the macroblock processing unit to be operated in parallel, the processing of each adjacent macroblock of the macroblock MB to be processed is always completed in advance. Therefore, the above-mentioned dependency of the adjacent macroblock is resolved, and parallel processing for each line of the picture Pic can be realized.

<p num="0009"><patcit num="1"><text>JP-A-2007-251865</text></patcit></p>

<p num="0010"> However, in the image decoding device and the image coding device described in Patent Document 1, frequent communication between macroblock processing units is required in order to resolve the above dependency, and decoding or coding is required. There is a problem that the overhead of is large and the efficiency of parallelization is low. That is, every time the macroblock processing unit processes a macroblock, the processing result must be transferred to another macroblock processing unit, which increases the processing overhead and the difficulty of feasibility. Further, a macroblock processing unit is required for each line of the macroblock, and each macroblock processing unit requires a memory for accumulating and transferring the processing result. As a result, there is also a problem that the circuit cost increases because the capacity of the memory for holding the information of the adjacent macroblock which is the processing result increases in the entire image decoding device or the image coding device.</p><p num="0011"> Therefore, the present invention has been made in view of such a problem, and parallel processing is performed while solving the dependency on the information of the peripheral macroblock existing in the new coding method represented by H.264. It is an object of the present invention to provide an image decoding device, an image coding device, an image decoding method, and an image coding method in which the overhead of the above is suppressed, the parallelization efficiency is improved, and the circuit cost is reduced.</p>

<p num="0012"> In order to achieve the above object, the image coding device according to the present invention is an image coding device that encodes the picture for each block constituting the picture, and is included in the picture including the coded block. The coded block is encoded by referring to the block information of the blocks around the coded block that has already been generated by another coding unit as peripheral information. By repeating the above, a plurality of coding units for encoding the image regions of different regions associated with the respective in the picture are provided, and each of the plurality of coding units is referred to at the time of coding. A storage unit for holding the peripheral information is provided, and each storage unit of the plurality of coding units holds peripheral information of a number of blocks smaller than the number of blocks in the horizontal direction of the picture.</p><p num="0013"> Further, in order to achieve the above object, the image decoding device according to the present invention is an image decoding device that decodes the coded picture for each block constituting the coded picture, and is a decoding target block. It includes a division unit that divides a coded picture based on a block address indicating a spatial position in the picture, and a decoding unit that decodes the coded picture divided by the division unit.</p><p num="0014"> Further, in order to achieve the above object, the image decoding device according to the present invention is an image decoding device that decodes the coded picture for each block constituting the coded picture, and is a decoding target block. By repeating decoding of the decoding target block by referring to the information of the already decoded blocks in the periphery as peripheral information, the images of the regions associated with each in the encoded picture are arranged in parallel. Each of the plurality of decoding units to be decoded and the decoding unit included in the plurality of decoding units is referred to by the decoding unit, and the peripheral information generated by the other decoding units is transferred to the peripheral area to be transferred. As information, the transfer unit to be transferred from the other decoding unit to the decoding unit and the decoding target block at the end of the region associated with the decoding unit for each decoding unit are decoded. The transfer target peripheral information referred to in the above is provided with a detection unit for detecting whether or not the transfer target peripheral information has been transferred to the decoding unit, and each of the plurality of decoding units has the transfer target peripheral information transferred to the decoding unit. When the transfer is detected by the detection unit, the decoding target block at the end of the region associated with the decoding unit is decoded, and the boundary line between the regions is a block adjacent to each other. Is orthogonal to the decoding direction in the order in which they are subsequently decoded. For example, the decoding direction is the horizontal direction, and the decoding unit of any one of the plurality of decoding units is one of the two regions arranged horizontally in the coded picture. The image is decoded, and the other decoding unit of the plurality of decoding units decodes the other image of the two regions.</p><p num="0015"> As a result, since the boundary line between the regions is orthogonal to the decoding direction, in parallel decoding of the image in each region, the transfer target peripheral information is sequentially decoded every time all the blocks in the coded picture are sequentially decoded. However, it is not purposely generated and transferred, and the transfer target peripheral information is generated and transferred only when the block including a part of the boundary line is decoded. That is, each time each of the decoding units decodes all the blocks in the area associated with the decoding unit, all the peripheral information generated by the decoding of the blocks is referred to as the transfer target peripheral information. Only when the block including a part of the boundary line in the area is decoded, the peripheral information generated by the decoding may be used as the transfer target peripheral information. Therefore, unlike the conventional case, peripheral information is not frequently transferred, and the transfer frequency can be suppressed. As a result, even with an encoding method such as H.264 that requires peripheral information to decode macroblocks, parallel processing overhead is suppressed and parallelization efficiency is improved while eliminating the dependency of adjacent macroblocks. Can be improved. Further, conventionally, as many decoding units as the number of macroblock lines are required, and as many memories as the number of decoding units are required to store peripheral information generated by the decoding units, a large amount of memory capacity is required. It takes. However, in the present invention, the number of decoding units can be suppressed to reduce the memory capacity used for the entire device. As a result, the circuit cost can be reduced, the performance can be improved, and the cost can be reduced.</p><p num="0016"> It should be noted that the present invention can not only be realized by such an image decoding device, but also an image coding device, a method of processing operation in those devices, a program for causing those devices to perform processing operation, and a program thereof. It can also be realized as a storage medium for storing.</p>

<p num="0017"> The image decoding device and the image coding device of the present invention transfer information with few dependencies on the information of the peripheral macroblocks in a coding method in which the compression efficiency is improved by utilizing the correlation with the peripheral macroblocks. High performance and low cost can be realized by efficiently operating a plurality of decoding units or coding units in parallel while solving the problem in terms of quantity.</p>

<figref num="1">FIG. 1 is a block diagram showing a configuration of a moving image decoding apparatus according to the first embodiment of the present invention.</figref><figref num="2">FIG. 2 is an explanatory diagram for explaining the operation of the image decoding apparatus of the above.</figref><figref num="3">FIG. 3 is an explanatory diagram for explaining the adjacent macroblock and peripheral information of the above.</figref><figref num="4A">FIG. 4A is a diagram showing an adjacent macroblock when the same decoding target macroblock is the rightmost decoding target block.</figref><figref num="4B">FIG. 4B is a diagram showing an adjacent macroblock when the same decoding target macroblock is the leftmost decoding target block.</figref><figref num="5">FIG. 5 is a diagram showing an example of the processing timing of the first decoding circuit and the second decoding circuit of the same as above.</figref><figref num="6">FIG. 6 is a flowchart showing the operation when the first decoding circuit of the same above decodes the macroblock line.</figref><figref num="7">FIG. 7 is a flowchart showing the operation when the second decoding circuit of the same above decodes the macroblock line.</figref><figref num="8">FIG. 8 is a block diagram showing a configuration of an image decoding device according to the first modification of the above.</figref><figref num="9">FIG. 9 is a block diagram showing a configuration of an image decoding device according to the second modification of the above.</figref><figref num="10A">FIG. 10A is a diagram showing a configuration of a coded stream according to the second modification of the above.</figref><figref num="10B">FIG. 10B is a diagram showing a configuration of a machining stream according to the second modification of the above.</figref><figref num="10C">FIG. 10C is a diagram showing a configuration of a selection stream according to the second modification of the above.</figref><figref num="11A">FIG. 11A is a diagram showing the decoding order of macroblocks when the coded picture according to the third modification of the above is composed of MBAFF.</figref><figref num="11B">FIG. 11B is an explanatory diagram for explaining peripheral information when the coded picture according to the third modification of the above is composed of MBAFF.</figref><figref num="12">FIG. 12 is a block diagram showing the configuration of the moving image coding device according to the second embodiment of the present invention.</figref><figref num="13">FIG. 13 is an explanatory diagram for explaining the operation of the same image coding apparatus.</figref><figref num="14">FIG. 14 is a diagram showing an example of the processing timing of the first coding circuit and the second coding circuit of the same as above.</figref><figref num="15">FIG. 15 is a flowchart showing the operation when the first coding circuit of the same above encodes the macroblock line.</figref><figref num="16">FIG. 16 is a flowchart showing the operation when the second coding circuit of the same above encodes the macroblock line.</figref><figref num="17">FIG. 17 is a block diagram of an AV processing unit that realizes the H.264 recorder according to the third embodiment of the present invention.</figref><figref num="18">FIG. 18 is a diagram showing the dependency of adjacent macroblocks of H.264.</figref><figref num="19">FIG. 19 is a diagram showing a processing procedure of the image decoding device and the image coding device described in Patent Document 1.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of an image decoding apparatus according to the first embodiment of the present invention.

The image decoding device 100 in the present embodiment divides the coded stream Str in which the data indicating the moving image is encoded by H.264 and outputs the divided coded streams Str1 and Str2, while the dividing unit 130. The first decoding circuit 101 that decodes the divided coded stream Str1 and the second decoding that decodes the other divided coded stream Str2 in parallel with the decoding process by the first decoding circuit 101. Information transferred between the circuit 102, the information transfer bus (data bus) 103 for transferring information between the first and second decoding circuits 101, 102, and the first and second decoding circuits 101, 102. It includes first and second transfer completion detection units 104 and 105 for detecting that the transfer has been completed.

As shown in the dotted frame in FIG. 1, the first decoding circuit 101 and the first transfer completion detection unit 104 are integrated circuits such as LSI (Large Scale Integration). Similarly, the second decoding circuit 102 and the second transfer completion detection unit 105 may also be configured as one integrated circuit such as an LSI. Further, in the present embodiment, each of the first decoding circuit 101 and the second decoding circuit 102 is subjected to the left peripheral information or the right peripheral to be described later in the other decoding circuit via the information transfer bus 103. A transfer unit for transferring information (information on the surrounding area to be transferred) is provided.

In the split unit 130, the left part (left split coded picture) of each coded picture in the coded stream Str is included in the split coded stream Str1, and the remaining right part (right split coded picture) is split. Split the coded stream Str so that it is included in the coded stream Str2. The division unit 130 divides the coded stream Str based on the macroblock (MB) address of the macroblock included in each coded picture.

The first decoding circuit 101 acquires the divided coded stream Str1 from the divided unit 130 and decodes it. Specifically, the first decoding circuit 101 sequentially decodes the left-divided coded picture included in the divided-coded stream Str1. At this time, the first decoding circuit 101 decodes the left-divided coded picture for each macroblock line from the macroblock line at the upper end to the lower side of the left-divided coded picture. The macro block line is a group composed of a plurality of macro blocks arranged in the horizontal direction in the left-divided coded picture. Further, when decoding the macroblock line, the first decoding circuit 101 sequentially decodes the macroblocks from the leftmost macroblock toward the right side, that is, in the horizontal direction. Then, the first decoding circuit 101 outputs the decoded image data 120 generated by the decoding as described above.

Further, when the first decoding circuit 101 decodes the macroblock at the right end of the left-divided coded picture so that the dependency of the adjacent macroblock is satisfied in the decoding process by the second decoding circuit 102. , The left peripheral information generated by the decoding is transferred to the second decoding circuit 102 via the information transfer bus 103.

The adjacent macroblock is a left adjacent macroblock adjacent to the left, an upper left adjacent macroblock adjacent to the upper left, an upper adjacent macroblock adjacent to the upper, and an upper right adjacent macroblock adjacent to the upper right with respect to the macroblock to be decoded. It is one of the macroblocks. Further, the dependency of the adjacent macroblock is that if the adjacent macroblock exists in the encoded picture, the decoding target macroblock is decoded (motion vector) by referring to the peripheral information indicating the decoding result of the adjacent macroblock. A relationship that is predicted (predicted, in-screen predicted, or deblocked filtered). The above four adjacent macroblocks are the maximum range of peripheral information that can be referred to, and not all peripheral information may be referred to. Further, the peripheral information is the decoded motion vector and pixel value of the adjacent macroblock when the macroblock to be decoded is interscreen prediction coding, and the decoding target macroblock is the in-screen prediction code. If it is, it is the pixel value of the adjacent macroblock. Further, the left peripheral information is the peripheral information of the left adjacent macroblock in the left-divided coded picture when the decoding target macroblock is at the upper left end of the right-divided coded picture, and is the decoding target macroblock. Is the peripheral information of the left adjacent macroblock and the upper left adjacent macroblock in the left divided coded picture when is located at the left end excluding the upper end of the right divided coded picture.

The second decoding circuit 102 acquires the divided coded stream Str2 from the divided unit 130 and decodes it. Specifically, the second decoding circuit 102 sequentially decodes the right-divided coded picture included in the divided coded stream Str2. At this time, the second decoding circuit 102 decodes the right-divided coded picture for each macroblock line from the macroblock line at the upper end to the lower side of the right-divided coded picture. The macro block line is a group composed of a plurality of macro blocks arranged in the horizontal direction in the right-divided coded picture. Further, when decoding the macroblock line, the second decoding circuit 102 sequentially decodes the macroblocks from the leftmost macroblock toward the right side, that is, in the horizontal direction. Then, the second decoding circuit 102 outputs the decoded image data 121 generated by the decoding as described above.

Further, when the second decoding circuit 102 decodes the macroblock at the left end of the right-divided coded picture so that the dependency of the adjacent macroblock is satisfied in the decoding process by the first decoding circuit 101. , The right peripheral information generated by the decoding is transferred to the first decoding circuit 101 via the information transfer bus 103. The right peripheral information is peripheral information of the upper right adjacent macroblock in the right-divided coded picture when the decoding target macroblock is at the right end excluding the upper end of the left-divided coded picture.

The first transfer completion detection unit 104 detects that the right peripheral information required for the decoding process by the first decoding circuit 101 has been transferred from the second decoding circuit 102 to the first decoding circuit 101. Then, the first decoding circuit 101 is notified of this. When the first decoding circuit 101 decodes the macro block at the right end of the left-divided coded picture (right end decoding target block), the macro block adjacent to the upper right of the right end decoding target block (upper right adjacent macro block). If) is in the right-split coded picture, the right peripheral information of the macroblock adjacent to the upper right is required. Therefore, when the first transfer completion detection unit 104 detects that the right peripheral information of the upper right adjacent macroblock has been transferred, it notifies the first decoding circuit 101 of that fact, and the rightmost decoding target block Start decryption. In other words, when decoding the rightmost decoding target block, the first decoding circuit 101 waits without performing the decoding unless there is a notification from the first transfer completion detection unit 104, and the notification is given. When it receives, its decryption starts.

The second transfer completion detection unit 105 detects that the left peripheral information required for the decoding process by the second decoding circuit 102 has been transferred from the first decoding circuit 101 to the second decoding circuit 102. Then, the second decoding circuit 102 is notified of this. When the second decoding circuit 102 decodes the macroblock (leftmost decoding target block) at the left end of the right-divided coded picture, the macroblock adjacent to the upper left of the leftmost decoding target block (upper left adjacent macroblock). ), And if there is a macroblock adjacent to the left (left adjacent macroblock) in the left-partitioned coded picture, the left peripheral information of the upper left adjacent macroblock and the left adjacent macroblock is required. Further, if there is no upper left adjacent macroblock and only the left adjacent macroblock is in the left split coded picture, the left peripheral information of the left adjacent macroblock is required. Therefore, when the second transfer completion detection unit 105 detects that the left peripheral information of the upper left adjacent macroblock and the left adjacent macroblock has been transferred, or that only the left peripheral information of the left adjacent macroblock has been transferred, it determines. This is notified to the second decoding circuit 102, and the decoding of the leftmost decoding target block is started. In other words, when decoding the leftmost decoding target block, the second decoding circuit 102 waits without decoding unless notified by the second transfer completion detection unit 105, and the notification thereof. When it receives, its decryption starts.

In such an image decoding device 100, when the first decoding circuit 101 decodes a macroblock, the information obtained by the decoding is used as peripheral information necessary for decoding another macroblock. It is stored in the memory provided in the decoding circuit 101 of 1. Then, when the first decoding circuit 101 decodes the macroblock, the four adjacent macroblocks (left adjacent macroblock, upper left adjacent macroblock, upper adjacent macroblock, and upper right adjacent macroblock) adjacent to the macroblock are decoded. If any of the macroblocks) is in the coded picture, the macroblock to be decoded is decoded by referring to the peripheral information obtained by decoding the adjacent macroblock and stored in the memory. However, if the first decoding circuit 101 has not decoded the adjacent macroblock in the coded picture and the second decoding circuit 102 has decoded the adjacent macroblock, the adjacent macroblock has been decoded. Peripheral information is not stored in the memory of the first decoding circuit 101. Therefore, the first decoding circuit 101 acquires the peripheral information of the adjacent macroblock transferred from the second decoding circuit 102 as the right peripheral information and stores it in the memory, and all the adjacent information existing in the coded picture. When the peripheral information of the macroblock is prepared, the macroblock to be decoded is decoded by referring to all the peripheral information including the right peripheral information.

Similarly, when the macroblock is decoded, the second decoding circuit 102 sends the information obtained by the decoding to the second decoding circuit 102 as peripheral information necessary for decoding another macroblock. Store in the provided memory. Then, when the second decoding circuit 102 decodes the macroblock, if any of the four adjacent macroblocks adjacent to the macroblock is in the coded picture, the decoding of the adjacent macroblock causes the second decoding circuit 102 to decode the macroblock. The macroblock to be decoded is decoded by referring to the peripheral information obtained and stored in the memory. However, if the second decoding circuit 102 has not decoded the adjacent macroblock in the coded picture and the first decoding circuit 101 has decoded the adjacent macroblock, the adjacent macroblock has been decoded. Peripheral information is not stored in the memory of the second decoding circuit 102. Therefore, the second decoding circuit 102 acquires the peripheral information of the adjacent macroblock transferred from the first decoding circuit 101 as the left peripheral information and stores it in the memory, and all the adjacent information existing in the encoded picture. When the peripheral information of the macroblock is prepared, the macroblock to be decoded is decoded by referring to all the peripheral information including the left peripheral information.

As described above, in the image decoding apparatus 100 of the present embodiment, the left peripheral information and the right peripheral information are transferred between the first and second decoding circuits 101 and 102, so that the decoding result of the adjacent macroblock is obtained. It is possible to realize the decoding of macroblocks according to H.264 using.

FIG. 2 is an explanatory diagram for explaining the operation of the image decoding apparatus 100 according to the present embodiment.

The division unit 130 generates a left division coded picture Pic1 and a right division coded picture Pic2 by dividing the coded picture Pic into two left and right parts.

Here, the coded picture Pic is composed of a plurality of macroblock MBs arranged in the horizontal direction and the vertical direction. Further, the first and second decoding circuits 101 and 102 sequentially decode a plurality of macroblocks in the horizontal direction when decoding the macroblock line of the coded picture Pic. The numbers 1 to 2N + 2 (N is an integer of 2 or more) shown in each macroblock MB in FIG. 2 indicate the approximate order in which the macroblocks are decoded. Therefore, the division unit 130 divides the coded picture Pic in the direction orthogonal to the decoding direction of the macroblock by the first and second decoding circuits 101 and 102. That is, the division unit 130 divides the coded picture Pic so that the boundary line between the left divided coded picture Pic1 and the right divided coded picture Pic2 is orthogonal to the above-mentioned decoding direction.

The division unit 130 in the present embodiment divides the coded picture Pic so that the left-divided coded picture Pic1 and the right-divided coded picture Pic2 have the same size. As a result, the number of macroblocks included in each macroblock line of the left-split coded picture Pic1 and the right-split coded picture Pic2 is N.

The first decoding circuit 101 decodes the left-divided coded picture Pic1 and the second decoding circuit 102 decodes the right-divided coded picture Pic2.

Specifically, first, the first decoding circuit 101 is the macroblock line at the upper end of the left-divided coded picture Pic1, that is, the macroblock MB (1st) at the upper left end to the macroblock MB (Nth) at the upper right end. ) Sequentially decodes each macroblock MB. Since the Nth macroblock MB is at the right end in the left split coded picture Pic1, the first decoding circuit 101 decodes the left peripheral information obtained by decoding the Nth macroblock MB into the second decoding. Transfer to the conversion circuit 102.

Next, the first decoding circuit 101 is the second macroblock line from the top of the left split coded picture Pic1, that is, each macroblock MB from the N + 1th macroblock MB to the 2Nth macroblock MB. Are sequentially decoded. At this time, the second decoding circuit 102 is from the macroblock line at the upper end of the right-divided coded picture Pic2, that is, from the macroblock MB (N + 1th) at the upper left end to the macroblock MB (2Nth) at the upper right end. Decrypt each macroblock MB of. That is, the first and second decoding circuits 101 and 102 decode the second macroblock line from the top of the left-divided coded picture Pic1 and the macroblock line at the upper end of the right-partitioned coded picture Pic2. Is executed in parallel.

Here, when the second decoding circuit 102 decodes the N + 1th macroblock MB of the right-divided coded picture Pic2, since the macroblock MB is the leftmost decoding target block, the leftmost decoding is performed. Left peripheral information is required to decrypt the block MB to be converted. In the coded picture Pic, the Nth macroblock MB of the left split coded picture Pic1 is adjacent to the leftmost decoding target block MB (N + 1th) as a left adjacent macroblock. Therefore, the second decoding circuit 102 needs left peripheral information indicating the decoding result of the left adjacent macroblock in order to decode the N + 1th left end decoding target block described above. Therefore, the second decoding circuit 102 does not decode the leftmost decoding target block until it is notified that the left peripheral information of the left adjacent macroblock has been transferred from the first decoding circuit 101. Waits for, and decrypts after being notified.

Further, when the first decoding circuit 101 decodes the 2Nth macroblock MB of the left split coded picture Pic1, the macroblock MB is the rightmost decoding target block, so the leftmost decoding target block. Requires right peripheral information to decode. In the coded picture Pic, the N + 1th macroblock MB of the right-partitioned coded picture Pic2 is adjacent to the rightmost decoding target block MB (2Nth) as an upper right adjacent macroblock. Therefore, the first decoding circuit 101 needs right peripheral information indicating the decoding result of the upper right adjacent macroblock in order to decode the 2Nth right end decoding target block described above. Therefore, the first decoding circuit 101 does not decode the rightmost decoding target block until it is notified that the right peripheral information of the upper right adjacent macroblock has been transferred from the second decoding circuit 102. Waits for, and decrypts after being notified.

Next, the first decoding circuit 101 is the third macroblock line from the top of the left split coded picture Pic1, that is, each macroblock MB from the 2N + 1st macroblock MB to the 3Nth macroblock MB. Are sequentially decoded. At this time, the second decoding circuit 102 is the second macroblock line from the top of the right-split coded picture Pic2, that is, each macroblock MB from the 2N + 1st macroblock MB to the 3Nth macroblock MB. Are sequentially decoded. As a result, the first and second decoding circuits 101 and 102 decode the third macroblock line from the top of the left split coded picture Pic1 and the second macroblock line from the top of the right split coded picture Pic2. Decrypt and perform in parallel.

Here, when the second decoding circuit 102 decodes the 2N + 1st macroblock MB of the right-divided coded picture Pic2, the macroblock MB is the leftmost decoding target block, so that the leftmost decoding is performed. Left peripheral information is required to decrypt the block MB to be converted. In the coded picture Pic, the Nth macroblock MB of the left-divided coded picture Pic1 is adjacent to the leftmost decoding target block MB (2N + 1th) as the upper left adjacent macroblock, and the left division is performed. The 2Nth macroblock MB of the coded picture Pic1 is adjacent as a left adjacent macroblock. Therefore, the second decoding circuit 102 obtains the left peripheral information indicating the decoding result of the left adjacent macroblock and the upper left adjacent macroblock in order to decode the above-mentioned 2N + 1th leftmost decoding target block. It takes. Therefore, the second decoding circuit 102 is the leftmost decoding target block until it is notified that the left peripheral information of the left adjacent macroblock and the upper left adjacent macroblock has been transferred from the first decoding circuit 101. It waits without decrypting, and decrypts after being notified.

FIG. 3 is an explanatory diagram for explaining adjacent macroblocks and peripheral information.

The first decoding circuit 101 decodes, for example, the macroblock MBa of the left-divided coded picture Pic1. At this time, the first decoding circuit 101 includes peripheral information indicating the decoding results of the macro blocks Bam to Bak included in the macro block line LL3 having the macro block MBa to be decoded, and peripheral information indicating the decoding results of the macro block line LL3. Peripheral information indicating the decoding result of macroblocks Ba1 to Ban included in the macroblock line LL2 immediately above is stored in the memory. That is, the first decoding circuit 101 includes each macro block from the upper left adjacent macro block to the right end included in the macro block line immediately above the macro block to be decoded, and a macro block having the macro block to be decoded. When each macroblock from the left end to the left adjacent macroblock included in the line has already been decoded, at least the decoding result of those macroblocks is stored in the memory as peripheral information. Therefore, the memory provided in the first decoding circuit 101 includes at least the peripheral information generated by the first decoding circuit 101 (1 macroblock line + 1 macroblock) and the second decoding. It has a capacity for storing peripheral information for one macroblock received from the conversion circuit 102.

Then, the first decoding circuit 101 refers to the peripheral information of the left adjacent macroblock Bak, the upper left adjacent macroblock Ba1, the upper upper adjacent macroblock Ba2, and the upper right adjacent macroblock Ba3 stored in the memory. Decrypt block MBa. That is, in the first decoding circuit 101, if the left adjacent macroblock, the upper left adjacent macroblock, the upper upper adjacent macroblock, and the upper right adjacent macroblock each exist as adjacent macroblocks in the left split coded picture Pic1, they are present. Decrypts the macroblock to be decoded by referring to the peripheral information of the adjacent macroblock of.

Similar to the above, the second decoding circuit 102 decodes, for example, the macroblock MBb of the right-partitioned coded picture Pic2. At this time, the second decoding circuit 102 includes peripheral information indicating the decoding results of the macro blocks Bbm to Bbk included in the macro block line RL2 having the macro block MBb to be decoded, and peripheral information indicating the decoding results of the macro block line RL2. Peripheral information indicating the decoding result of macroblocks Bb1 to Bbn included in the macroblock line RL1 immediately above is stored in the memory. That is, the second decoding circuit 102 includes each macro block from the upper left adjacent macro block to the right end included in the macro block line immediately above the macro block to be decoded, and a macro block having the macro block to be decoded. When each macroblock from the left end to the left adjacent macroblock included in the line has already been decoded, at least the decoding result of those macroblocks is stored in the memory as peripheral information. Therefore, the memory provided in the second decoding circuit 102 includes at least the peripheral information generated by the second decoding circuit 102 (1 macroblock line + 1 macroblock) and the first decoding. It has a capacity for storing peripheral information for one macroblock received from the conversion circuit 101.

Then, the second decoding circuit 102 refers to the peripheral information of the left adjacent macroblock Bbk, the upper left adjacent macroblock Bb1, the upper upper adjacent macroblock Bb2, and the upper right adjacent macroblock Bb3 stored in the memory. Decrypt block MBb. That is, in the second decoding circuit 102, if the left adjacent macroblock, the upper left adjacent macroblock, the upper upper adjacent macroblock, and the upper right adjacent macroblock each exist as adjacent macroblocks in the right-divided coded picture Pic2, they are present. Decrypts the macroblock to be decoded by referring to the peripheral information of the adjacent macroblock of.

FIG. 4A is a diagram showing adjacent macroblocks when the decoding target macroblock is the rightmost decoding target block.

For example, if the decoding target macroblock MBa is the rightmost decoding target block in the left split coded picture Pic1, the macroblock MB1 adjacent to the upper right of the decoding target macroblock MBa may exist in the right split coded picture Pic2. is there. In such a case, the right peripheral information of the upper right adjacent macroblock MB1 included in the right-divided coded picture Pic2 is not stored in the memory of the first decoding circuit 101, and is stored in the memory of the second decoding circuit 102. It is stored in memory. Therefore, the first decoding circuit 101 acquires the right peripheral information of the upper right adjacent macroblock MB1 included in the right-divided coded picture Pic2 from the second decoding circuit 102, and refers to the right peripheral information. Decrypts the macroblock MBa to be decrypted.

When the macroblock MBa to be decoded is at the upper right corner of the left-divided coded picture Pic1, the upper right adjacent macroblock does not exist in the right-divided coded picture Pic2. In this case, the first decoding circuit 101 decodes the macroblock to be decoded without referring to the right peripheral information.

FIG. 4B is a diagram showing adjacent macroblocks when the decoding target macroblock is the leftmost decoding target block.

For example, in the right-divided coded picture Pic2, when the decoding target macroblock MBb is the leftmost decoding target block, the upper left adjacent macroblock MB2 and the left adjacent macroblock MB3 of the decoding target macroblock MBb are left-divided encoded pictures. May be present in Pic1. In such a case, the left peripheral information of each of the upper left adjacent macroblock MB2 and the left adjacent macroblock MB3 included in the left split coded picture Pic1 is not stored in the memory of the second decoding circuit 102. It is stored in the memory of the first decoding circuit 101. Therefore, the second decoding circuit 102 acquires the left peripheral information of each of the upper left adjacent macroblock MB2 and the left adjacent macroblock MB3 included in the left split coded picture Pic1 from the first decoding circuit 101. The macroblock MBb to be decoded is decoded by referring to the information around the left side of the block.

When the macroblock MBb to be decoded is at the upper left corner of the right-divided coded picture Pic2, the upper left adjacent macroblock does not exist in the left-divided coded picture Pic1. In this case, the second decoding circuit 102 decodes the macroblock to be decoded by referring to the left peripheral information of the left adjacent macroblock without referring to the left peripheral information of the upper left adjacent macroblock.

FIG. 5 is a diagram showing an example of the processing timing of the first decoding circuit 101 and the second decoding circuit 102. The timing shown in FIG. 5 is an example for showing the processing operations of the first and second decoding circuits 101 and 102 in an easy-to-understand manner.

First, the first decoding circuit 101 starts decoding the macroblock line L1 at the upper end of the left-divided coded picture Pic1 at time t0. When the decoding of the macroblock line L1 is completed at time t1, the first decoding circuit 101 transfers the left peripheral information indicating the decoding result of the rightmost decoding target block to the second decoding circuit 102. Further, the first decoding circuit 101 starts decoding of the second macroblock line L2 from the top of the left split coded picture Pic1. Further, when the second decoding circuit 102 acquires the left peripheral information transferred from the first decoding circuit 101 at time t2, the second decoding circuit 102 refers to the left peripheral information and refers to the upper end of the right-divided coded picture Pic2. Start decoding the macroblock line R1 of.

Here, when the first decoding circuit 101 decodes the second macro block from the right end of the macro block line L2, it is necessary for decoding the next macro block to be decoded (the right end decoding target block). Since there is no right peripheral information, the decoding process is stopped from time t3 and the standby state is entered. On the other hand, when the decoding of the leftmost decoding target block of the macroblock line R1 is completed at time t4, the second decoding circuit 102 provides the right peripheral information indicating the decoding result to the first decoding circuit 101. Transfer to.

The first transfer is that the first decoding circuit 101 acquires the right peripheral information from the second decoding circuit 102 at time t5 and the right peripheral information is transferred to the first decoding circuit 101. When notified from the completion detection unit 104, the standby state is released, and the rightmost decoding target block of the macro block line L2 is decoded with reference to the right peripheral information. On the other hand, the second decoding circuit 102 completes the decoding of the macroblock line R1 at time t5, and tries to start the decoding of the next macroblock line R2. However, since the second decoding circuit 102 does not have the left peripheral information necessary for decoding the leftmost decoding target block of the macroblock line R2, the decoding process is stopped from time t5 and enters a standby state.

When the first decoding circuit 101 completes the decoding of the right end decoding target block of the macroblock line L2 at time t6, the left peripheral information indicating the decoding result is transferred to the second decoding circuit 102. To do. Further, the first decoding circuit 102 starts decoding of the next macroblock line L3. On the other hand, the second decoding circuit 102 acquires the left peripheral information from the first decoding circuit 101 at time t7, and the left peripheral information is transferred to the second decoding circuit 102. When notified from the transfer completion detection unit 105 of the above, the standby state is released, the decoding of the macroblock line R2 is started with reference to the information around the left side thereof, and the leftmost decoding target block is decoded.

Then, when the first decoding circuit 101 decodes the second macro block from the right end of the macro block line L3, it is necessary for decoding the next macro block to be decoded (the right end decoding target block). Since there is no right peripheral information, the decryption process is stopped from time t8 and the standby state is entered.

FIG. 6 is a flowchart showing an operation when the first decoding circuit 101 decodes the macroblock line.

First, the first decoding circuit 101 determines whether or not all the peripheral information necessary for decoding the macroblock to be decoded is prepared (step S100). For example, in the first decoding circuit 101, when the decoding target macroblock is the rightmost decoding target block, whether or not the first transfer completion detection unit 104 has notified that the right peripheral information has been transferred. To determine. Here, when the first decoding circuit 101 determines that they are aligned (Yes in step S100), the first decoding circuit 101 decodes the macroblock to be decoded by referring to the peripheral information (step S102). On the other hand, if the first decoding circuit 101 determines that they are not aligned (No in step S100), the first decoding circuit 101 waits because the macroblock to be decoded cannot be decoded.

When the macroblock to be decoded is decoded in step S102, the first decoding circuit 101 determines whether or not the decoded macroblock is at the right end of the macroblock line (step S104). Here, when the first decoding circuit 101 determines that it is at the right end (Yes in step S104), the second decoding circuit 102 displays the left peripheral information indicating the result of decoding the macroblock at the right end. Transfer to (step S106). On the other hand, when the first decoding circuit 101 determines that it is not at the right end (No in step S104), the macro block to the right of the decoded macro block is set as the next decoding target macro block from step S100. Repeat the process of. As a result, the macro block line is decoded, and by repeating the decoding of such a macro block line, the left-divided coded picture Pic1 of the coded picture Pic is decoded.

FIG. 7 is a flowchart showing an operation when the second decoding circuit 102 decodes the macroblock line.

First, the second decoding circuit 102 determines whether or not all the peripheral information necessary for decoding the macroblock to be decoded is available (step S200). For example, in the second decoding circuit 102, when the decoding target macroblock is the leftmost decoding target block, whether or not the second transfer completion detection unit 105 has notified that the left peripheral information has been transferred. To determine. Here, when the second decoding circuit 102 determines that they are aligned (Yes in step S200), it decodes the macroblock to be decoded by referring to the peripheral information (step S202). On the other hand, if the second decoding circuit 102 determines that they are not aligned (No in step S200), the second decoding circuit 102 waits because the macroblock to be decoded cannot be decoded.

When the macroblock to be decoded is decoded in step S202, the second decoding circuit 102 determines whether or not the decoded macroblock is at the left end of the macroblock line (step S204). Here, when the second decoding circuit 102 determines that it is at the left end (Yes in step S204), the first decoding circuit 101 obtains the right peripheral information indicating the result of decoding the macroblock at the left end. Transfer to (step S206). On the other hand, when the second decoding circuit 102 determines that it is not at the left end (No in step S204), it further determines whether or not the decoded macroblock is at the right end of the macroblock line (step S208). ). Here, when the first decoding circuit 101 determines that it is at the right end (Yes in step S208), it finishes the decoding process of the macroblock line, and determines that it is not at the right end (No in step S208). The process from step S200 is repeatedly executed with the macroblock to the right of the decoded macroblock as the next macroblock to be decoded. As a result, the macro block line is decoded, and by repeating the decoding of the macro block line, the right-divided coded picture Pic2 of the coded picture Pic is decoded.

As described above, in the present embodiment, since the boundary line between the regions (left-divided coded picture Pic1 and right-divided coded picture Pic2) is orthogonal to the decoding direction, parallel decoding for the image in each region is performed. In the conversion, the peripheral information is not transferred every time all the macroblocks in the coded picture Pic are sequentially decoded, and only when the macroblock including a part of the boundary line is decoded. Peripheral information is transferred as left peripheral information or right peripheral information. Therefore, unlike the conventional case, peripheral information is not frequently transferred, and the transfer frequency can be suppressed. As a result, even with an encoding method such as H.264 that requires peripheral information to decode macroblocks, parallel processing overhead is suppressed and parallelization efficiency is improved while eliminating the dependency of adjacent macroblocks. Can be improved. Further, conventionally, as many decoding units as the number of macroblock lines are required, and as many memories as the number of decoding units are required to store peripheral information generated by the decoding units, a large amount of memory capacity is required. It takes. However, in the present embodiment, the number of decoding units can be suppressed to reduce the memory capacity used for the entire device. As a result, the circuit cost can be reduced, the performance can be improved, and the cost can be reduced.

(Modification example 1) Here, a first modification of the present embodiment will be described. In the image decoding apparatus according to the present modification, the method of passing the left peripheral information and the right peripheral information between the first decoding circuit 101 and the second decoding circuit 102 is the image decoding of the first embodiment. Different from device 100.

FIG. 8 is a block diagram showing a configuration of an image decoding device according to this modification.

The image decoding device 100a according to this modification includes the division unit 130, the first decoding circuit 101, the second decoding circuit 102, the first transfer completion detection unit 104, and the second transfer completion. It includes a detection unit 105, a first memory bank 141, and a second memory bank 142.

In FIG. 8, the components having the same functions and configurations as the components of the image decoding device 100 of the first embodiment are designated by the same reference numerals as the components of the image decoding device 100 for details. Explanation is omitted.

In the image decoding device 100a according to this modification, the first decoding circuit 101 and the second decoding circuit 102 do not transmit and receive left peripheral information and right peripheral information via the information transfer bus 103. By accessing the first and second memory banks 141 and 142, the left peripheral information and the right peripheral information are passed. In other words, the left peripheral information and the right peripheral information are shared by the first and second decoding circuits 101 and 102 by bank switching of the first and second memory banks 141 and 142.

The first memory bank 141 has an area for storing peripheral information generated by the first decoding circuit 101, and is accessed by the first decoding circuit 101 and the second decoding circuit 102. ..

The second memory bank 142 has an area for storing peripheral information generated by the second decoding circuit 102, and is accessed by the first decoding circuit 101 and the second decoding circuit 102. ..

Each time the macro block of the left-divided coded picture Pic1 is decoded, the first decoding circuit 101 stores the peripheral information generated by the decoding in the first memory bank 141. Further, when decoding the macroblock, the first decoding circuit 101 reads the peripheral information of the adjacent macroblock if the peripheral information of the adjacent macroblock is stored in the first memory bank 141, and reads the peripheral information. Refer to and decode the macroblock.

The second decoding circuit 102 stores the peripheral information generated by the decoding every time the macro block of the right-divided coded picture Pic2 is decoded in the second memory bank 142. Further, when decoding the macroblock, the second decoding circuit 102 reads the peripheral information of the adjacent macroblock if the peripheral information of the adjacent macroblock is stored in the second memory bank 142, and reads the peripheral information. Refer to and decode the macroblock.

Here, in the left-divided coded picture Pic1, if the decoding target macroblock is the right-end decoding target block and is not at the upper end of the left-divided coded picture Pic1, the right-end decoding target block is decoded. The necessary peripheral information of the upper right adjacent macroblock is not stored in the first memory bank 141. That is, since the upper right adjacent macroblock is in the right split coded picture Pic2, it is decoded by the second decoding circuit 102, and the peripheral information of the upper right adjacent macroblock is stored in the second memory bank 142. ing.

Therefore, when the first decoding circuit 101 decodes the right-end decoding target block that is not at the upper end of the left-divided coded picture Pic1, the peripheral information of the upper right adjacent macroblock stored in the second memory bank 142. Is acquired as the right peripheral information, and the rightmost decoding target block is decoded with reference to the right peripheral information.

Similar to the above, in the right-partitioned coded picture Pic2, when the decoding target macroblock is the leftmost decoding target block, the left adjacent macroblock (and the upper left adjacent macroblock) required for decoding the leftmost decoding target block. Peripheral information of block) is not stored in the second memory bank 142. That is, the left adjacent macroblock (and the upper left adjacent macroblock) is decoded by the first decoding circuit 101 because it is in the left split coded picture Pic1, and the left adjacent macroblock (and the upper left adjacent macroblock) is decoded. ) Peripheral information is stored in the first memory bank 141.

Therefore, when the second decoding circuit 102 decodes the leftmost decoding target block of the right-divided coded picture Pic2, the left adjacent macroblock (and the upper left adjacent macroblock) stored in the first memory bank 141 is used. ) Peripheral information is acquired as the left peripheral information, and the leftmost decoding target block is decoded with reference to the left peripheral information.

The first transfer completion detection unit 104 determines whether or not the right peripheral information necessary for decoding the rightmost decoding target block has been transferred to the first decoding circuit 101, that is, the right peripheral information is the second memory bank 142. It is determined whether or not the information is stored in the first decoding circuit 101, and when it is determined that the information is stored in the first decoding circuit 101, the right peripheral information is transferred.

The second transfer completion detection unit 105 determines whether or not the left peripheral information necessary for decoding the leftmost decoding target block has been transferred to the second decoding circuit 102, that is, the left peripheral information is the first memory bank 141. It is determined whether or not the information is stored in the second decoding circuit 102, and when it is determined that the information is stored in the second decoding circuit 102, the left peripheral information is transferred.

In this modification, the first and second decoding circuits 101 and 102 store all peripheral information in the first and second memory banks 141 and 142, but only the left peripheral information and the right peripheral information are stored in the first and first peripheral information. It may be stored in the memory banks 141 and 142 of 2.

(Modification example 2) Here, a second modification of the present embodiment will be described. In the image decoding apparatus according to the present modification, as in the first modification, the method of passing the left peripheral information and the right peripheral information between the first decoding circuit 101 and the second decoding circuit 102 is described above. It is different from the image decoding apparatus 100 of the first embodiment.

FIG. 9 is a block diagram showing a configuration of an image decoding device according to this modification.

The image decoding device 100b according to this modification includes a first decoding circuit 101, a second decoding circuit 102, a first transfer completion detection unit 104, a second transfer completion detection unit 105, and the like. It is equipped with a selector 151. That is, the image decoding device 100b according to the present modification does not include the division unit 130 and the information transfer bus 103 unlike the image decoding device 100 of the first embodiment, and uses the selector 151 to use the first and first image decoding devices 100b. Each of the decoding circuits in 2 is characterized in that it processes a stream in which right peripheral information or left peripheral information is mixed.

In FIG. 9, the components having the same functions and configurations as the components of the image decoding device 100 of the first embodiment are designated by the same reference numerals as the components of the image decoding device 100 for details. Explanation is omitted.

The selector 151 acquires the coded stream Str and outputs it to the first decoding circuit 101. Further, when the selector 151 acquires the right peripheral information Inf2 from the second decoding circuit 102 while acquiring the encoded stream Str, the selector 151 stops the output of the encoded stream Str and obtains the right peripheral information Inf2. Output. Then, when the output of the right peripheral information Inf2 is completed, the selector 151 resumes the output of the coded stream Str. In this way, the selector 151 selects the coded stream Str or the right peripheral information Inf2 and outputs it to the first decoding circuit 101. As a result, the selector 151 outputs the selection stream Stra in which the right peripheral information Inf2 is mixed in the middle of the coded stream Str to the first decoding circuit 101.

When the first transfer completion detection unit 104 detects that the right peripheral information Inf2 has been transferred from the selector 151 to the first decoding circuit 101, it notifies the first decoding circuit 101 of that fact.

When the first decoding circuit 101 acquires the selected stream Stra from the selector 151, the first decoding circuit 101 extracts and decodes the portion belonging to the left-divided coded picture Pic1 from the selected stream Stra. At this time, when the first transfer completion detection unit 104 notifies that the right peripheral information Inf2 has been transferred, the first decoding circuit 101 refers to the right peripheral information Inf2 and performs left division coding. Decodes the rightmost decoding target block of picture Pic1.

Further, the first decoding circuit 101 extracts a portion belonging to the right-divided coded picture Pic2 from the selected stream Stra, and adds the left peripheral information obtained by the above-described decoding to the portion. Then, the first decoding circuit 101 outputs a set in which the left peripheral information is added to the portion belonging to the right-divided coded picture Pic2 as a processing stream Strb to the second decoding circuit 102.

When the second transfer completion detection unit 105 detects that the left peripheral information has been transferred from the first decoding circuit 101 to the second decoding circuit 102, the second transfer completion detection unit 105 notifies the second decoding circuit 102 of that fact. To do.

When the second decoding circuit 102 acquires the processing stream Strb from the first decoding circuit 101, the second decoding circuit 102 decodes the portion belonging to the right-divided coded picture Pic2 included in the processing stream Strb. At this time, when the second transfer completion detection unit 105 notifies that the left peripheral information has been transferred, the second decoding circuit 102 refers to the left peripheral information and refers to the right-divided coded picture Pic2. Decrypts the block to be decoded at the left end of. Further, the second decoding circuit 102 outputs the right peripheral information Inf2 generated by the decoding to the first decoding circuit 101.

FIG. 10A is a diagram showing the configuration of a coded stream.

The coded stream Str is composed of a partial stream Str1 corresponding to the macro block line of the left split coded picture Pic1 and a partial stream Str2 corresponding to the macro block line of the right split coded picture Pic2 arranged alternately. There is.

FIG. 10B is a diagram showing the configuration of the machining stream Strb.

The processing stream Strb is configured by alternately arranging the left peripheral information Inf1 and the partial stream Str2 corresponding to the macro block line of the right-divided coded picture Pic2.

FIG. 10C is a diagram showing the configuration of the selected stream Stra.

The selection stream Stra is configured by alternately arranging the partial stream Str1 and the partial stream Str2 included in the coded stream Str and the right peripheral information Inf2.

As described above, in this modification, peripheral information is added to the stream including all or a part of the coded picture Pic and input to the first and second decoding circuits 101 and 102, respectively.

(Modification example 3) Here, a third modification of the present embodiment will be described. The image decoding device 100 according to this modification is characterized in that it is compatible with MBAFF (Macro Block Adaptive Frame Field).

FIG. 11A is a diagram showing the decoding order of macroblocks when the coded picture Pic is composed of MBAFF. The numbers shown in each macroblock MB in FIG. 11A (N is an integer of 2 or more) indicate the order in which the macroblocks are decoded.

If the coded picture Pic is composed of MBAFF, the coded picture Pic must be decoded every 2 macroblock lines. That is, when the first macroblock MB is decoded, the second macroblock adjacent below it is decoded, then the third macroblock adjacent to the upper right of it is decoded, and then adjacent below it. The fourth macroblock must be decrypted.

Therefore, the first and second decoding circuits 101 and 102 of the image decoding apparatus 100 according to the present modification are macroblocks in the left-divided coded picture Pic1 or the right-divided coded picture Pic2, respectively, in the order shown in FIG. 11A. Decrypt the block.

FIG. 11B is an explanatory diagram for explaining peripheral information when the coded picture Pic is composed of MBAFF.

The first and second decoding circuits 101 and 102 decode, for example, the macroblock pair MBp1 composed of the vertically adjacent macroblocks MBpa and MBpb, respectively. At this time, the first and second decoding circuits 101 and 102 refer to peripheral information indicating the decoding results of the four macroblock pairs MBp2 to MBp5 adjacent to the macroblock pair MBp1, respectively. Here, the macroblock pair MBp2 consists of macroblocks MBpc and MBpd, and is adjacent to the left of the macroblock pair MBp1. The macroblock pair MBp3 consists of macroblocks MBpe and MBpf, and is adjacent to the upper left of the macroblock pair MBp1. The macroblock pair MBp4 consists of macroblocks MBpg and MBph, and is adjacent to the macroblock pair MBp1. The macroblock pair MBp5 consists of macroblocks MBpi and MBpj, and is adjacent to the upper right of the macroblock pair MBp1.

That is, when the coded picture is composed of MBAFF, the image decoding apparatus 100 according to the present modification treats two macroblocks adjacent to each other as one macroblock in the above-described embodiment. The same effect as

(Embodiment 2) The image coding device according to the present embodiment is a device that encodes a picture for each macroblock according to H.264, and has the same characteristics as the image coding device according to the first embodiment. The only difference between the image coding device in the present embodiment and the image coding device in the first embodiment is whether to encode or decode the macroblock. It will be described in detail using.

FIG. 12 is a block diagram showing a configuration of an image coding device according to a second embodiment of the present invention.

The image coding device 200 according to the present embodiment has a division unit 230 that divides the moving image data Pin and outputs the divided moving image data Pin1 and Pin2, and a first reference numeral that encodes one of the divided moving image data Pin1. The conversion circuit 201, the second coding circuit 202 that encodes the other divided moving image data Pin2 in parallel with the coding process by the first coding circuit 201, and the first and second coding circuits 201, 202. The first and second transfer completion detectors that detect that the transfer of information performed between the information transfer bus 203 for transferring information between the first and second coding circuits 201 and 202 is completed. It has 204 and 205.

The first coding circuit 201 and the first transfer completion detection unit 204 are integrated circuits such as LSI (Large Scale Integration), as shown by the dotted line frame in FIG. Similarly, the second coding circuit 202 and the second transfer completion detection unit 205 may also be configured as one integrated circuit such as an LSI. In addition, the coding by the first and second coding circuits 201 and 202 in the present embodiment also includes local decoding in which the coded image is decoded for coding of another image. Further, in the present embodiment, the first coding circuit 201 and the second coding circuit 202 each have left peripheral information or right peripheral information (left peripheral information or right peripheral information) in the other coding circuit via the information transfer bus 203. A transfer unit for transferring (transfer target peripheral information) is provided.

In the split unit 230, the left part (left split picture) of each picture in the moving image data Pin is included in the split moving image data Pin1, and the remaining right part (right split picture) is included in the split moving image data Pin2. The moving image data Pin is divided so as to be obtained. The division unit 230 divides the moving image data Pin based on the macroblock (MB) address of the macroblock included in each picture.

The first coding circuit 201 acquires the divided moving image data Pin1 from the dividing unit 230 and encodes it. Specifically, the first coding circuit 201 sequentially encodes the left-divided picture included in the divided moving image data Pin1. At this time, the first coding circuit 201 encodes the left-divided picture for each macro block line from the macro block line at the upper end to the lower side in the left-divided picture. Further, when encoding the macroblock line, the first coding circuit 201 sequentially encodes the macroblocks from the leftmost macroblock toward the right side, that is, in the horizontal direction. Then, the first coding circuit 201 outputs the output data 220 composed of the divided coded stream or the locally decoded image data generated by the coding as described above.

Further, when the first coding circuit 201 encodes the macro block at the right end of the left split picture so that the dependency of the adjacent macro block is satisfied in the coding process by the second coding circuit 202, the first coding circuit 201 encodes the macro block. The left peripheral information generated by coding is transferred to the second coding circuit 202 via the information transfer bus 203.

The adjacent macroblock is a left adjacent macroblock adjacent to the left, an upper left adjacent macroblock adjacent to the upper left, an upper adjacent macroblock adjacent to the upper, and an upper right adjacent macroblock adjacent to the upper right with respect to the macro block to be encoded. It is one of the macroblocks. In addition, the dependency of the adjacent macroblock is that if the adjacent macroblock exists in the picture, the encoded macroblock is coded (motion vector prediction code) by referring to the peripheral information indicating the coding result of the adjacent macroblock. It refers to the relationship that is coded, predictively coded in the screen, or deblocked. The above four adjacent macroblocks are the maximum range of peripheral information that can be referred to, and not all peripheral information may be referred to. Further, the peripheral information is the motion vector of the adjacent macroblock and the encoded and decoded pixel values when the coded macroblock is predictively coded between screens, and the coded macroblock is In the case of in-screen predictive coding, it is the encoded and decoded pixel value of the adjacent macroblock. Further, the left peripheral information is the peripheral information of the left adjacent macroblock in the left divided picture when the coded macroblock is at the upper left end of the right divided picture, and the coded macroblock is the right divided picture. When it is at the left end excluding the upper end of, it is the peripheral information of the left adjacent macroblock and the upper left adjacent macroblock in the left split picture.

In the present embodiment, the peripheral information is not limited to the information defined by the coding method such as H.264, and may include other information. For example, the peripheral information may include data extracted from the amount of used bits for controlling the coded stream, the characteristics of the pattern of the adjacent macroblock, and the like.

The second coding circuit 202 acquires the divided moving image data Pin2 from the dividing unit 230 and encodes it. Specifically, the second coding circuit 202 sequentially encodes the right-divided picture included in the divided moving image data Pin2. At this time, the second coding circuit 202 encodes the right-divided picture for each macro block line from the macro block line at the upper end to the lower side in the right-divided picture. The macroblock line is a group composed of a plurality of macroblocks arranged in the horizontal direction in the right-divided picture. Further, when encoding the macroblock line, the second coding circuit 202 sequentially encodes the macroblocks from the leftmost macroblock toward the right side, that is, in the horizontal direction. Then, the second coding circuit 202 outputs the output data 221 composed of the divided coded stream or the locally decoded image data generated by the coding as described above.

Further, when the second coding circuit 202 encodes the macro block at the left end of the right-divided picture so that the dependency of the adjacent macro block is satisfied in the coding process by the first coding circuit 201, the second coding circuit 202 encodes the macro block. The right peripheral information generated by coding is transferred to the first coding circuit 201 via the information transfer bus 203. The right peripheral information is peripheral information of the upper right adjacent macroblock in the right divided picture when the coded target macroblock is at the right end excluding the upper end of the left divided picture.

The first transfer completion detection unit 204 detects that the right peripheral information required for the coding process by the first coding circuit 201 has been transferred from the second coding circuit 202 to the first coding circuit 201. Then, the first coding circuit 201 is notified of this. When the first coding circuit 201 encodes the macro block (rightmost coded block) at the right end of the left split picture, the macroblock adjacent to the upper right of the rightmost coded block (upper right adjacent macroblock) If it is in a right-split picture, the right peripheral information of the macroblock adjacent to the upper right is required. Therefore, when the first transfer completion detection unit 204 detects that the right peripheral information of the upper right adjacent macroblock has been transferred, it notifies the first coding circuit 201 of that fact, and the rightmost coded target block Start coding. In other words, when encoding the rightmost coded target block, the first coding circuit 201 waits without encoding unless notified by the first transfer completion detection unit 204, and the notification is given. When it receives, it starts its coding.

The second transfer completion detection unit 205 detects that the left peripheral information required for the coding process by the second coding circuit 202 has been transferred from the first coding circuit 201 to the second coding circuit 202. Then, the second coding circuit 202 is notified of this. When the second coding circuit 202 encodes the macro block at the left end of the right-divided picture (left-end coding target block), the macro block adjacent to the upper left of the left-end coding target block (upper left adjacent macro block), And if there is a macroblock adjacent to the left (left adjacent macroblock) in the left split picture, the left peripheral information of the upper left adjacent macroblock and the left adjacent macroblock is required. Further, if there is no upper left adjacent macroblock and only the left adjacent macroblock is in the left split picture, the left peripheral information of the left adjacent macroblock is required. Therefore, when the second transfer completion detection unit 205 detects that the left peripheral information of the upper left adjacent macroblock and the left adjacent macroblock has been transferred, or that only the left peripheral information of the left adjacent macroblock has been transferred, it determines. This is notified to the second coding circuit 202, and the coding of the leftmost coded target block is started. In other words, when encoding the leftmost coded target block, the second coding circuit 202 waits without encoding unless notified by the second transfer completion detection unit 205, and the notification is given. When it receives, its coding is started.

In such an image coding device 200, when the first coding circuit 201 encodes a macro block, the information obtained by the coding is used as peripheral information necessary for coding another macro block. It is stored in the memory provided in the coding circuit 201 of 1. Then, when the first coding circuit 201 encodes a macroblock, four adjacent macroblocks (left adjacent macroblock, upper left adjacent macroblock, upper adjacent macroblock, and upper right adjacent macroblock) adjacent to the macroblock are encoded. If any of the macroblocks) is in the picture, the macroblock to be encoded is encoded by referring to the peripheral information obtained by encoding the adjacent macroblock and stored in the memory. However, if the first coding circuit 201 does not encode the adjacent macroblock in the picture and the second coding circuit 202 encodes the adjacent macroblock, then the periphery of the adjacent macroblock. The information is not stored in the memory of the first coding circuit 201. Therefore, the first coding circuit 201 acquires the peripheral information of the adjacent macroblock transferred from the second coding circuit 202 as the right peripheral information and stores it in the memory, and all the adjacent macroblocks existing in the picture. When all the peripheral information of the above is prepared, the macroblock to be encoded is encoded by referring to all the peripheral information including the right peripheral information.

Similarly, when the macro block is encoded, the second coding circuit 202 sends the information obtained by the coding to the second coding circuit 202 as peripheral information necessary for coding the other macro blocks. Store in the provided memory. Then, when the second coding circuit 202 encodes the macroblock, the four adjacent macroblocks (left adjacent macroblock, upper left adjacent macroblock, upper adjacent macroblock, and upper right adjacent macroblock) adjacent to the macroblock are encoded. If any of the macroblocks) is in the picture, the macroblock to be encoded is encoded by referring to the peripheral information obtained by encoding the adjacent macroblock and stored in the memory. However, if the second coding circuit 202 does not encode the adjacent macroblock in the picture and the first coding circuit 201 encodes the adjacent macroblock, then the periphery of the adjacent macroblock. The information is not stored in the memory of the second coding circuit 202. Therefore, the second coding circuit 202 acquires the peripheral information of the adjacent macroblock transferred from the first coding circuit 201 as the left peripheral information and stores it in the memory, and all the adjacent macroblocks existing in the picture. When all the peripheral information of the above is prepared, the macroblock to be encoded is encoded by referring to all the peripheral information including the left peripheral information.

As described above, in the image coding apparatus 200 according to the present embodiment, the left peripheral information and the right peripheral information are transferred between the first and second coding circuits 201 and 202, so that the coding result of the adjacent macroblock is obtained. It is possible to realize macroblock coding according to H.264 using.

FIG. 13 is an explanatory diagram for explaining the operation of the image coding device 200 according to the present embodiment.

The division unit 230 generates a left division picture Pic1 and a right division picture Pic2 by dividing the picture Pic into two left and right.

Here, the picture Pic is composed of a plurality of macroblock MBs arranged in the horizontal direction and the vertical direction. Further, when the first and second coding circuits 201 and 202 encode the macro block line of the picture Pic, the first and second coding circuits 201 and 202 sequentially encode a plurality of macro blocks in the horizontal direction. The numbers 1 to 2N + 2 (N is an integer of 2 or more) shown in each macroblock MB in FIG. 13 indicate the approximate order in which the macroblocks are encoded. Therefore, the division unit 230 divides the picture Pic in the direction orthogonal to the coding direction of the macroblock by the first and second coding circuits 201 and 202. That is, the dividing unit 230 divides the picture Pic so that the boundary line between the left-divided picture Pic1 and the right-divided picture Pic2 is orthogonal to the above-mentioned coding direction.

The division unit 230 in the present embodiment divides the picture Pic so that the left-divided picture Pic1 and the right-divided picture Pic2 have the same size. As a result, the number of macroblocks included in each macroblock line of the left-split picture Pic1 and the right-split picture Pic2 is N.

The first coding circuit 201 encodes the left split picture Pic1 and the second coding circuit 202 encodes the right split picture Pic2.

Specifically, first, the first coding circuit 201 starts from the macroblock line at the upper end of the left split picture Pic1, that is, from the macroblock MB (1st) at the upper left end to the macroblock MB (Nth) at the upper right end. Each macroblock MB of is encoded sequentially. Since the Nth macroblock MB is at the right end in the left split picture Pic1, the first coding circuit 201 uses the left peripheral information obtained by encoding the Nth macroblock MB as the second coding circuit. Transfer to 202.

Next, the first coding circuit 201 sequentially performs the second macroblock line from the top of the left split picture Pic1, that is, each macroblock MB from the N + 1th macroblock MB to the 2Nth macroblock MB. Encode. At this time, the second coding circuit 202 is the macro block line at the upper end of the right split picture Pic2, that is, the macro block MB (N + 1th) at the upper left end to the macro block MB (2Nth) at the upper right end. Encode the macroblock MB sequentially. That is, the first and second coding circuits 201 and 202 execute the coding of the second macroblock line from the top of the left split picture Pic1 and the coding of the macroblock line at the upper end of the right split picture Pic2 in parallel. To do.

Here, when the second coding circuit 202 encodes the N + 1th macroblock MB of the right-divided picture Pic2, the macroblock MB is the leftmost coding target block, and therefore the leftmost coding target. Requires left peripheral information to encode the block MB. In the picture Pic, the Nth macroblock MB of the left split picture Pic1 is adjacent to the leftmost coded target block MB (N + 1th) as a left adjacent macroblock. Therefore, the second coding circuit 202 needs left peripheral information indicating the coding result of the left adjacent macroblock in order to encode the N + 1th leftmost coded target block described above. Therefore, the second coding circuit 202 does not encode the leftmost coded target block until it is notified that the left peripheral information of the left adjacent macroblock has been transferred from the first coding circuit 201. Waits for, and encodes after being notified.

Further, when the first coding circuit 201 encodes the 2Nth macroblock MB of the left split picture Pic1, since the macroblock MB is the rightmost coded target block, the rightmost coded block is coded. It requires information on the right periphery to be converted. In the picture Pic, the N + 1th macroblock MB of the right-split picture Pic2 is adjacent to the rightmost coded block MB (2Nth) as an upper right adjacent macroblock. Therefore, the first coding circuit 201 needs right peripheral information indicating the coding result of the upper right adjacent macroblock in order to encode the 2Nth right end coded target block described above. Therefore, the first coding circuit 201 does not encode the rightmost coded block until it is notified that the right peripheral information of the upper right adjacent macroblock has been transferred from the second coding circuit 202. Waits for, and encodes after being notified.

Next, the first coding circuit 201 sequentially performs the third macroblock line from the top of the left split picture Pic1, that is, each macroblock MB from the 2N + 1st macroblock MB to the 3Nth macroblock MB. Encode. At this time, the second coding circuit 202 sequentially performs the second macroblock line from the top of the right-split picture Pic2, that is, each macroblock MB from the 2N + 1st macroblock MB to the 3Nth macroblock MB. Encode. As a result, the first and second coding circuits 201 and 202 encode the third macroblock line from the top of the left split picture Pic1 and the second macroblock line from the top of the right split picture Pic2. Is executed in parallel.

Here, when the second coding circuit 202 encodes the 2N + 1st macroblock MB of the right-divided picture Pic2, the macroblock MB is the leftmost coding target block, and therefore the leftmost coding target. Requires left peripheral information to encode the block MB. In the picture Pic, the Nth macroblock MB of the left split picture Pic1 is adjacent as the upper left adjacent macroblock to the leftmost coded block MB (2N + 1th), and the 2N of the left split picture Pic1. The second macroblock MB is adjacent as a left-adjacent macroblock. Therefore, in order to encode the 2N + 1th leftmost coded target block described above, the second coding circuit 202 provides left peripheral information indicating the coding results of the left adjacent macroblock and the upper left adjacent macroblock. It takes. Therefore, the second coding circuit 202 is the leftmost coded block until it is notified that the left peripheral information of the left adjacent macroblock and the upper left adjacent macroblock has been transferred from the first coding circuit 201. It waits without encoding, and encodes after being notified.

FIG. 14 is a diagram showing an example of the processing timing of the first coding circuit 201 and the second coding circuit 202. The timing shown in FIG. 14 is an example for showing the processing operations of the first and second coding circuits 201 and 202 in an easy-to-understand manner.

First, the first coding circuit 201 starts coding the first macroblock line L1 from the top of the left split picture Pic1 at time t0. When the coding of the macro block line L1 is completed at time t1, the first coding circuit 201 transfers the left peripheral information indicating the coding result of the rightmost coded block to the second coding circuit 202. Further, the first coding circuit 201 starts coding the second macroblock line L2 from the top of the left split picture Pic1. Further, when the second coding circuit 202 acquires the left peripheral information transferred from the first coding circuit 201 at time t2, the second coding circuit 202 refers to the left peripheral information and macroblocks the upper end of the right split picture Pic2. Start coding the block line R1.

Here, when the first coding circuit 201 encodes the second macro block from the right end of the macro block line L2, it is necessary for coding the macro block to be coded next (the right end coding target block). Since there is no right peripheral information, the coding process is stopped from time t3 and the system enters a standby state. On the other hand, in the second coding circuit 202, when the coding of the leftmost coded target block of the macroblock line R1 is completed at time t4, the right peripheral information indicating the coding result is transmitted to the first coding circuit 201. Transfer to.

The first transfer is that the first coding circuit 201 acquires the right peripheral information from the second coding circuit 202 at time t5 and the right peripheral information is transferred from the first coding circuit 201. When notified from the completion detection unit 204, the standby state is released, and the rightmost coded target block of the macro block line L2 is encoded with reference to the information on the right periphery thereof. On the other hand, the second coding circuit 202 completes the coding of the macroblock line R1 at time t5, and tries to start the coding of the next macroblock line R2. However, since the second coding circuit 202 does not have the left peripheral information necessary for coding the leftmost coded block of the macroblock line R2, the second coding circuit 202 stops the coding process from time t5 and goes into a standby state.

When the first coding circuit 201 completes the coding of the rightmost coded target block of the macroblock line L2 at time t6, the left peripheral information indicating the coding result is transferred to the second coding circuit 202. To do. Further, the first coding circuit 201 starts coding the next macroblock line L3. On the other hand, the second coding circuit 202 acquires the left peripheral information from the first coding circuit 201 at time t7, and the left peripheral information is transferred to the second coding circuit 202. When notified from the transfer completion detection unit 205 of the above, the standby state is released, the coding of the macroblock line R2 is started with reference to the information on the left periphery thereof, and the leftmost coded target block is encoded.

Then, when the first coding circuit 201 encodes the second macro block from the right end of the macro block line L3, it is necessary for coding the next macro block to be coded (the right end coding target block). Since there is no right peripheral information, the coding process is stopped from time t8 and the system enters a standby state.

FIG. 15 is a flowchart showing the operation when the first coding circuit 201 encodes the macroblock line.

First, the first coding circuit 201 determines whether or not all the peripheral information necessary for coding the macroblock to be coded is prepared (step S300). For example, in the first coding circuit 201, when the coding target macroblock is the rightmost coding target block, whether or not the first transfer completion detection unit 204 has notified that the right peripheral information has been transferred. To determine. Here, when the first coding circuit 201 determines that they are aligned (Yes in step S300), the first coding circuit 201 encodes the macroblock to be coded with reference to the peripheral information (step S302). On the other hand, if the first coding circuit 201 determines that they are not aligned (No in step S300), the first coding circuit 201 waits because the macroblock to be coded cannot be coded.

When the coded macroblock is encoded in step S302, the first coding circuit 201 determines whether or not the coded macroblock is at the right end of the macroblock line (step S304). Here, when the first coding circuit 201 determines that it is at the right end (Yes in step S304), the second coding circuit 202 provides the left peripheral information indicating the result of encoding the macro block at the right end. Transfer to (step S306). On the other hand, when the first coding circuit 201 determines that it is not at the right end (No in step S304), the macro block to the right of the coded macro block is set as the next coded target macro block from step S300. Repeat the process of. As a result, the macro block line is encoded, and by repeating the coding of the macro block line, the left-divided picture Pic1 of the picture Pic is encoded.

FIG. 16 is a flowchart showing the operation when the second coding circuit 202 encodes the macroblock line.

First, the second coding circuit 202 determines whether or not all the peripheral information necessary for coding the macroblock to be coded is prepared (step S400). For example, in the second coding circuit 202, when the coding target macroblock is the leftmost coding target block, whether or not the second transfer completion detection unit 205 has notified that the left peripheral information has been transferred. To determine. Here, when the second coding circuit 202 determines that they are aligned (Yes in step S400), the second coding circuit 202 encodes the macroblock to be coded with reference to the peripheral information (step S402). On the other hand, if it is determined that the second coding circuit 202 is not aligned (No in step S400), the second coding circuit 202 waits because the macroblock to be coded cannot be coded.

When the coded macroblock is encoded in step S402, the second coding circuit 202 determines whether or not the coded macroblock is at the left end of the macroblock line (step S404). Here, when the second coding circuit 202 determines that it is at the left end (Yes in step S404), the first coding circuit 201 provides the right peripheral information indicating the result of encoding the macro block at the left end. Transfer to (step S406). On the other hand, when the second coding circuit 202 determines that it is not at the left end (No in step S404), it further determines whether or not the coded macroblock is at the right end of the macroblock line (step S408). ). Here, when the first coding circuit 201 determines that it is at the right end (Yes in step S408), it finishes the coding process of the macroblock line, and determines that it is not at the right end (No in step S408). The process from step S400 is repeatedly executed with the macroblock to the right of the coded macroblock as the next coded macroblock. As a result, the macro block line is encoded, and by repeating the coding of the macro block line, the right-split picture Pic2 of the picture Pic is encoded.

As described above, in the present embodiment, since the boundary line between the regions (left-divided picture Pic1 and right-divided picture Pic2) is orthogonal to the coding direction, the picture is used in parallel coding for the image in each region. Peripheral information is not transferred every time all macroblocks in Pic are sequentially encoded, and peripheral information is left peripheral information only when the macroblock including a part of the boundary line is encoded. Or it is transferred as right peripheral information. Therefore, unlike the conventional case, peripheral information is not frequently transferred, and the transfer frequency can be suppressed. As a result, even with a coding method such as H.264 that requires peripheral information for macroblock coding, parallel processing overhead is suppressed and parallelization efficiency is improved while eliminating the dependency of adjacent macroblocks. Can be improved. Further, conventionally, as many coding units as the number of macroblock lines are required, and as many memories as the number of coding units are required to store peripheral information generated by the coding units, a large amount of memory capacity is required. It takes. However, in the present embodiment, the number of coding units can be suppressed to reduce the memory capacity used for the entire device. As a result, the circuit cost can be reduced, the performance can be improved, and the cost can be reduced.

(Embodiment 3) This embodiment is an application example of the image decoding apparatus of the first embodiment and the image coding apparatus of the second embodiment, and is an AV processing unit that realizes an H.264 recorder.

FIG. 17 is a block diagram of the AV processing unit.

The AV processing unit 300 in the present embodiment is an AV processing unit such as a DVD recorder or a hard disk recorder that reproduces digitally compressed audio and images, and is configured as an integrated circuit such as an LSI. The AV processing unit 300 includes an image coding / decoding unit 301, a voice coding / decoding unit 302, and an image input that have the functions and configurations of the image decoding device and the image coding device of the first and second embodiments. The output unit 303, the image processing unit 304, the audio input / output unit 305, the audio processing unit 306, the bus 307, the AV control unit 308, the memory input / output unit 309, and the stream input / output unit 311 are provided. There is.

The memory 310 has an area for storing data such as stream data, coded data, and decoded data, and is connected to the memory input / output unit 309.

The bus 307 transfers data such as stream data Strd indicating audio and image and decrypted audio / image data. The stream input / output unit 311 acquires the stream data Strd and connects to the bus 307.

The image coding / decoding unit 301 encodes and decodes the image and connects to the bus 307.

Here, the image coding / decoding unit 301 includes the image decoding device 100, 100a or 100b of the first embodiment and the image coding device 200 of the second embodiment. The stream data Strd includes the coded stream Str shown in FIG. 1 and the output data 220,221 of FIG. Further, the signal between the memory 310 and the AV processing unit 300 includes the decoded image data 120 and 121 also shown in FIG. 1 and the moving image data Pin of FIG. 12. The decoded image data 120, 121 and the moving image data Pin of FIG. 12 may be included in the image signal VSig input to the image input / output unit 303.

The image processing unit 304 performs pre-processing and post-processing on the image signal VSig and connects to the bus 307. The image input / output unit 303 outputs an image signal VSig that has been processed by the image processing unit 304 or passed through without being processed by the image processing unit 304 to the outside. Alternatively, the image input / output unit 303 captures the image signal VSig from the outside.

The voice processing unit 306 performs pre-processing and post-processing on the voice signal ASig and connects to the bus 307. The voice input / output unit 305 outputs the voice signal ASig processed by the voice processing unit 306 or passed through without being processed by the voice processing unit 306 to the outside. Alternatively, the audio input / output unit 305 captures the audio signal ASig from the outside. In addition, the AV control unit 308 controls the entire AV processing unit 300.

In the coding process, the image signal VSig is first input to the image input / output unit 303, and the audio signal ASig is input to the audio input / output unit 305.

In the recording process, the image signal VSig input to the image input / output unit 303 is used, and the image processing unit 304 performs filter processing, feature extraction for coding, and the like. Then, the image signal VSig is stored as the original image in the memory 310 via the memory input / output unit 309. Next, the original image data and the reference image data are transferred from the memory 310 to the image coding / decoding unit 301 again via the memory input / output unit 309. On the contrary, the divided coded stream encoded by the image coding / decoding unit 301 and the locally decoded image data are transferred from the image coding / decoding unit 301 to the memory 310.

On the other hand, using the voice signal ASig input to the voice input / output unit 305, the voice processing unit 306 performs filtering and feature quantity extraction for coding. Then, the voice signal ASig is stored in the memory 310 as the original voice data via the memory input / output unit 309. Next, the original audio data is taken out from the memory 310 again via the memory input / output unit 309, encoded, and stored in the memory 310 again as audio stream data.

At the end of the coding process, the image stream, the audio stream, and other stream information are processed as one stream data, and the stream data Strd is output via the stream input / output unit 311. Then, a process of writing to a large-capacity storage device such as an optical disk (for example, DVD) or a hard disk (HDD) is performed.

Next, in the decoding process, the following operations are performed. First, the data stored in the recording process is read from a large-capacity storage device such as an optical disk, a hard disk, or a semiconductor memory. As a result, audio and image signals are input as stream data Strd via the stream input / output unit 311. From the stream data Strd, the image stream is input to the image coding / decoding unit 301, and the audio stream is input to the audio coding / decoding unit 302.

The image data decoded by the image coding decoding unit 301 is stored in the temporary memory 310 via the memory input / output unit 309. The image processing unit 304 performs processing such as noise removal on the data stored in the memory 310. Further, the image data stored in the memory 310 may be used again in the image coding / decoding unit 301 as a reference picture for the inter-screen motion compensation prediction.

Further, the voice data decoded by the voice coding / decoding unit 302 is stored in the temporary memory 310 via the memory input / output unit 309. The voice processing unit 306 performs processing such as sound on the data stored in the memory 310.

Finally, the data processed by the image processing unit 304 is output as an image signal VSig via the image input / output unit 303 while synchronizing the sound and the image in time, and is displayed on a television screen or the like. The data processed by the voice processing unit 306 is output as a voice signal ASig via the voice input / output unit 305, and is output from a speaker or the like.

In the present embodiment, the AV processing unit 300 is configured as one LSI, but it may be configured as a plurality of LSIs. In this case, the first decoding circuit 101, the second decoding circuit 102, the first coding circuit 201, or the second coding circuit 202 in the above-described first and second embodiments are individually provided for each of the LSIs. You may prepare for.

Although the image decoding device and the image coding device according to the present invention have been described above with reference to the above-described first and second embodiments and modifications thereof, the present invention is not limited thereto.

In the following, the first and second decoding circuits and the first and second coding circuits are collectively referred to as the first and second processing circuits (or simply processing circuits), and the decoding and coding are performed. All of these are collectively called codec processing. When it is not necessary to distinguish the coded picture from the picture of the original image, the coded picture is simply referred to as a picture.

For example, in the above-described first and second embodiments and their modifications, when each processing circuit codec-processes the macroblock in parallel, each processing circuit sequentially codec-processes the macroblock along the horizontal direction in a raster scan manner. , Macroblocks may be codeced sequentially along the vertical direction. In this case, the division unit divides the picture so that the boundary line of the division is along the horizontal direction. As a result, for example, the two divided pictures generated by dividing the picture are arranged vertically in the vertical direction, and the upper divided picture and the lower divided picture are codec-processed in parallel.

Further, the dividing unit may adaptively switch the direction of division, that is, the direction of the boundary line, according to the direction along the order of the macroblocks codec-processed by the processing circuit. Further, in the above-described first and second embodiments and the modified example thereof, the divided portion divides the picture so that the size of the left region and the right region are equal, but the sizes of the regions are different. May be good. For example, the division unit determines the size of the left area and the right area according to the content of the picture so that the first processing circuit and the second processing circuit have the same time to decode the area allocated to each. Make it different from the size of. Further, the division unit may replace the areas allocated to the first processing circuit and the second processing circuit according to the content of the picture. For example, in the split section, the left split coded picture is decoded by the first decoding circuit, and the right split coded picture is decoded by the second decoding circuit. It is decoded by the second decoding circuit, and the right-divided coded picture is switched to the state where it is decoded by the first decoding circuit. Further, each of the image decoding device and the image coding device may not be provided with a division unit, and each processing circuit may extract a region associated with itself from the picture and decode it. In this case, the image decoding device or the image coding device may be provided with a control unit that instructs each processing circuit to extract the region to be extracted.

Further, in the above-described first and second embodiments and the modified example thereof, the picture is divided into two and codec-processed, but the picture may be divided into three or more and the areas thereof may be codec-processed in parallel. In this case, the image decoding device or the image coding device includes three or more processing circuits.

Further, in the above-described first and second embodiments and the modified example thereof, the picture is codec-processed according to the coding method of H.264, but the codec processing is performed by referring to the information of the adjacent macroblock, not limited to this coding method. Any coding method may be used as long as it is a coding method.

Further, in the above-described first and second embodiments, the information transfer bus is configured as one bus capable of bidirectionally transferring information such as left peripheral information or right peripheral information between processing circuits, but each is unidirectional. It may consist of a plurality of buses that can be transferred to. Further, the means for passing the left peripheral information or the right peripheral information between the processing circuits is not limited to such an information transfer bus, but may be applied to a plurality of processing circuits as in the first and second modifications of the first embodiment. It may be a plurality of shared memory banks, a means for processing the stream by adding left peripheral information or right peripheral information to all or a part of the stream, and the information can be passed between the processing circuits. Any means or configuration may be used as long as it is used.

Further, in the first and second embodiments, the image decoding device and the image coding device are each an integrated circuit (for example, LSI) including a first processing circuit and a first transfer completion detection unit, and a first integrated circuit. Although it was provided with one integrated circuit including two processing circuits and a second transfer completion detection unit, each of the processing circuit and the transfer completion detection unit may be individually integrated into one chip and is included in the device. All or some of the components may be integrated into one chip so as to include all or some of the components. When all are integrated into one chip, the image decoding device and the image coding device are realized as, for example, a system integrated in a single LSI. Further, among each component, only the means for storing the data to be coded or decoded may be made into a separate structure without being made into one chip.

In addition, although an integrated circuit is used as an LSI here, the integrated circuit may be called an IC (Integrated Circuit), a system LSI, a super LSI, or an ultra LSI depending on the degree of integration. In addition, the method of making an integrated circuit is not limited to LSI, but a dedicated circuit. Alternatively, it may be realized by a general-purpose processor. After manufacturing the LSI, you can connect and set the FPGA (Field Programmable Gate Array) that can be programmed and the circuit cells inside the LSI. A reconfigurable reconfigurable processor may be used. Furthermore, if an integrated circuit technology that replaces an LSI appears due to advances in semiconductor technology or another technology derived from it, it is naturally possible to integrate functional blocks using that technology. There is a possibility of adaptation of biotechnology.

Further, the image decoding device and the image coding device of the present invention are not limited to the above-described first and second embodiments and modifications thereof. As long as the gist of the present invention is not deviated, the present invention also includes a form in which various modifications that can be conceived by those skilled in the art are applied to the present embodiment, and a form constructed by combining components or processing methods in different embodiments and modifications. Is included in the range of.

It should be noted that the present invention can be realized not only as a device, but also as a method in which processing by the components constituting the device is a step, or as a program for causing a computer to execute those steps, and the program is recorded. It can be realized as a recording medium such as a computer-readable CD-ROM, or as information, data or a signal indicating the program. Then, those programs, information, data and signals may be distributed via a communication network such as the Internet.

The image decoding device and the image coding device according to the present invention have an effect that the overhead of parallel processing can be suppressed, the parallelization efficiency can be improved, and the circuit cost can be reduced. For example, a shooting and image reproduction function can be achieved. It can be applied to mobile phones, personal computers, image recording / playback devices, etc.

100 Image Decoder 101 First decoding circuit 102 Second decoding circuit 103 Information transfer bus 104 1st transfer completion detector 105 Second transfer completion detector 120, 121 Decrypted image data 130 division 201 First coding circuit 202 Second coding circuit 203 Information transfer bus 204 1st transfer completion detector 205 Second transfer completion detector 230 split