Semiconductor device and method of manufacturing the semiconductor device

0001The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

0002For example, Patent Document 1 discloses a magnetoresistive element (MRAM: Magnetoresistive Random Access Memory) that utilizes a current-driven domain wall transport phenomenon.

0003FIG. 12 shows the configuration of the MRAM disclosed in Patent Document 1. The MRAM is composed of a first magnetization fixing layer 5a and 5b, a second magnetization fixing layer 6, a non-magnetic layer 4, and a magnetization free layer. The magnetization free layer includes magnetization fixing portions 1a and 1b, domain wall moving portions 3, and domain wall pin sites 2a and 2b. The second magnetization fixing layer 6 is provided so as to overlap with at least a part of the domain wall moving portion 3. The magnetization free layer, the first magnetization fixing layers 5a and 5b, and the second magnetization fixing layer 6 are all composed of ferromagnets and show the magnetization indicated by the direction of the arrow. That is, the first magnetization-fixed layers 5a and 5b have fixed magnetizations that are antiparallel to each other, and the second magnetization-fixed layer 6 has a fixed magnetization parallel to either the first magnetization-fixed layers 5a or 5b. Have.

0004Further, the domain wall moving portion 3 of the magnetization free layer can arbitrarily invert the magnetization according to the current writing, and is responsible for writing information. The first magnetization fixing layers 5a and 5b are provided adjacent to the magnetization fixing portions 1a and 1b of the magnetization free layer, whereby the magnetization fixing portions 1a and 1b have magnetizations antiparallel to each other.

0005Further, a domain wall is formed at either the domain wall pin site 2a or 2b depending on the direction of magnetization of the domain wall moving portion. The domain wall pin sight has a function of stably fixing the domain wall when a magnetic field or an electric current is not applied. It has been theoretically found that the domain wall pin sites 2a and 2b in the magnetized free layer can naturally fix the domain wall without providing a special structure.

0006Patent Document 2 discloses a structure of a magnetoresistive element suitable for miniaturization and integration.

0007This magnetic resistance element is formed in a cylindrical first magnetic material having a variable magnetization direction and one end open and in the cylinder of the first magnetic material via an insulating layer, and has one magnetization direction. It is provided with a columnar second magnetic material fixed in the circumferential direction, and a rotating magnetic field is generated by passing a tunnel current between the first and second magnetic materials to change the magnetization direction of the first magnetic material. It is set in one or the other circumferential direction, and the change in magnetic resistance due to the magnetization direction of the first magnetic material with respect to the magnetization direction of the second magnetic material is used as a binary signal.

0008Patent Document 3 discloses a magnetic storage device having a magnetoresistive element and a method for manufacturing the same.

0009Specifically, in a magnetic resistance effect element including a magnetized fixed layer, a non-magnetic spacer layer formed on the magnetized fixed layer, and a magnetized free layer formed on the non-magnetic spacer layer, the magnetized fixed layer In the element region excluding the peripheral portion of, the magnetized fixed layer and the magnetized free layer are close to each other with the non-magnetic spacer layer in between, and on the peripheral portion of the magnetized fixed layer, the magnetized fixed layer and the magnetized free layer are located. Disclosed structures that are separated.

<p num="0010"><patcit num="1"><text>International Publication No. 2009/001706</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2003-174149</text></patcit><patcit num="3"><text>JP 2009-224477</text></patcit></p>

<p num="0011"> In recent years, the development of Foundry in advanced LSI production has been accelerating, and it is required to realize mixed MRAM on a common logic IP (Intellectual Property). When MRAM is formed in the wiring layer, it is necessary that the multilayer wiring forming process of the LSI does not cause the characteristic fluctuation of the MRAM, and that the MRAM forming process does not cause the characteristic fluctuation of the multilayer wiring.</p><p num="0012"> Here, FIG. 13 shows a diagram disclosed in Patent Document 1. The figure shows an example in which the MRAM disclosed in FIG. 12 is formed in the multilayer wiring layer. Specifically, the MRAM is formed on the contact 8 formed on the lower layer wiring 9. In the case of the embodiment shown in the figure, the contact 7 in the region where the MRAM is not located in the layer in which the MRAM is introduced is higher than the contacts in the other layers. That is, the presence of MRAM affects the multi-layer wiring structure.</p><p num="0013"> If the height of the contact 7 is high, it becomes difficult to embed the metal material to be filled, and the resistance / capacitance parameters of the wiring differ from the normal logic IP, so a new design environment construction is required. Problems such as</p><p num="0014"> The techniques described in Patent Documents 2 and 3 relate to a magnetoresistive element having an element structure different from that of a domain wall moving type magnetoresistive element.</p>

<p num="0015"> According to the present invention, the multilayer wiring layer formed on the substrate is provided, and the first layer contained in the multilayer wiring layer is embedded in the first interlayer insulating film and the first interlayer insulating film. A plurality of first vias and a plurality of first wirings embedded in the first interlayer insulating film, connected to the first via, and whose surface is exposed from the first interlayer insulating film. In the first region of the second layer, which is included in the multilayer wiring layer and is located directly above the first layer, at least two which are in contact with the first wiring and are insulated from each other. The first magnetized fixed layer, the magnetized free layer that overlaps the two first magnetized fixed layers in a plan view and is connected to the first magnetized fixed layer, and the magnetized free layer located on the magnetized free layer. An MRAM having a non-magnetic layer and a second magnetization fixing layer located on the non-magnetic layer, a second interlayer insulating film covering the MRAM, and an embedded in the second interlayer insulating film. , The second via connected to the second magnetization fixing layer, embedded in the second interlayer insulating film, connected to the second via, and the surface exposed from the second interlayer insulating film. A second wiring, and a semiconductor device including, is provided.</p><p num="0016"> Further, according to the present invention, after forming the first interlayer insulating film on the substrate, a plurality of first vias and the first wiring are exposed on the first interlayer insulating film, and the first wiring is exposed. At least two electrically insulated from each other on the first wiring in the first step of forming the first layer and in the first region above the first layer by embedding in such a manner. The second step of forming the first magnetized fixed layer and the magnetized free layer that overlaps the two first magnetized fixed layers in a plan view and is electrically connected to the first magnetized fixed layer. A third step of completing the MRAM by forming a non-magnetic layer located on the magnetized free layer and a second magnetized fixed layer located on the non-magnetic layer, and a second step of covering the MRAM. The fourth step of forming the interlayer insulating film, the second via connected to the second magnetization fixing layer, and the second wiring connected to the second via to the second interlayer insulating film. A method for manufacturing a semiconductor device having a fifth step of embedding a magnet is provided.</p><p num="0017"> In the present invention, the MRAM is formed in contact with the wiring of the lower layer. That is, in the present invention, unlike the conventional technique shown in FIG. 13, no contact (or via) is located between the lower layer wiring and the MRAM. According to the present invention as described above, the thickness of the layer on which MRAM is formed can be reduced by the amount not through the contact (or via), so that the height of the layer can be set to the height of the layer on which MRAM is not formed. It can be the same as the height. In this case, the heights of the wiring and vias formed in each layer can be the same. As a result, it is possible to avoid the inconvenience that the multi-layer wiring structure on the logic side is changed by the MRAM formed in the multi-layer wiring layer.</p>

<p num="0018"> According to the present invention, in the logic mixed MRAM, it is possible to reduce the inconvenience that the multilayer wiring forming process of the LSI causes the characteristic variation of the MRAM and the inconvenience that the MRAM forming process causes the characteristic variation of the multilayer wiring.</p>

0019<figref num="1">It is an example of the sectional view of the semiconductor device of this embodiment.</figref><figref num="2">It is an example of the sectional view of the semiconductor device of this embodiment.</figref><figref num="3">This is an example of a manufacturing flow chart of the semiconductor device of this embodiment.</figref><figref num="4">This is an example of a manufacturing flow chart of the semiconductor device of this embodiment.</figref><figref num="5">This is an example of a manufacturing flow chart of the semiconductor device of this embodiment.</figref><figref num="6">This is an example of a manufacturing flow chart of the semiconductor device of this embodiment.</figref><figref num="7">It is an example of the sectional view of the semiconductor device of this embodiment.</figref><figref num="8">This is an example of a manufacturing flow chart of the semiconductor device of this embodiment.</figref><figref num="9">It is a figure for demonstrating the action effect of the semiconductor device of this embodiment.</figref><figref num="10">It is a figure for demonstrating the action effect of the semiconductor device of this embodiment.</figref><figref num="11">It is a schematic diagram of the magnetic field writing type MRAM, and the schematic diagram of the domain wall moving type MRAM.</figref><figref num="12">This is an example of a cross-sectional view of a conventional semiconductor device.</figref><figref num="13">This is an example of a cross-sectional view of a conventional semiconductor device.</figref>

0020Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all drawings, similar components are designated by the same reference numerals, and description thereof will be omitted as appropriate.

0021&lt;&lt; First Embodiment &gt;&gt; The present inventor should consider in order to realize a logic-mixed MRAM that satisfies that the multilayer wiring formation process of the LSI does not cause the characteristic fluctuation of the MRAM and that the MRAM formation process does not cause the characteristic fluctuation of the multilayer wiring. The following points were found as points.

0022(1) Matching logic IP and device parameters That is, the multi-layer wiring structure on the logic side, for example, the height of the wiring layer, the height of the wiring and vias, and the material configuration thereof must not change due to the MRAM formed in the multi-layer wiring. The device parameter is, for example, a resistance or capacitance value in the wiring layer. In circuit design, the design is generally based on the device parameters provided by the device side, but when the via depth becomes deeper, the distance between the upper and lower wirings changes, so the capacitance value between the upper and lower wirings changes. And there is concern about the effect on the via resistance value. If the resistance or capacitance shifts, the signal timing shifts, which may interfere with circuit operation.

0023(2) Necessity of barrier coating on MRAM Moisture in the Cu or BEOL process, which is a wiring material, diffuses and mixes into the MRAM region, causing deterioration of the characteristics of the MRAM, and deterioration of the logic characteristics due to the diffusion of the metal elements that make up the MRAM. Sometimes. Therefore, in the present embodiment, the inconvenience is eliminated by covering the MRAM with a barrier coating. Naturally, it is necessary to prevent the multi-layer wiring structure and material configuration on the logic side from changing due to this barrier coating.

0024Hereinafter, the present embodiment that satisfies the above points will be described.

0025&lt;Semiconductor device configuration&gt; FIG. 1 shows an example of a cross-sectional view of the semiconductor device 100 of the present embodiment. The illustrated semiconductor device 100 has a CMOS logic region (second region) 101 and an MRAM cell region (first region) 102. This figure is an example in which MRAM103 is formed on the wiring layer A (second layer). In the present embodiment, the height of the wiring layer A on which the MRAM 103 is formed and the height of the wiring layer B (first layer) on which the MRAM 103 is not formed are the same. Therefore, in the CMOS logic region 101, the heights of the wiring (third wiring) 104a and via (third via) 105a formed in the wiring layer A and the wiring (first wiring) formed in the wiring layer B. ) 104b and via (first via) 105b are the same height. The same as used here means that there is no difference beyond the range of variation in the manufacturing margin. The same premise applies to the following.

0026Next, FIGS. 2 (A) and 2 (B) show enlarged cross-sectional views of the wiring layer A and the main parts of the wiring layer B. FIG. 2 (A) shows the MRAM cell area 102, and FIG. 2 (B) shows the CMOS logic area 101.

0027As shown in FIG. 2A, the wiring layer A of the MRAM cell region 102 includes at least two first magnetization fixing layers 50a and 50b that are in contact with the wiring 104b of the wiring layer B and are insulated from each other. It overlaps with the first magnetization fixing layers 50a and 50b in a plan view (for example, contains the first magnetization fixing layers 50a and 50b), and is electrically connected to the first magnetization fixing layers 50a and 50b. An MRAM including a magnetized free layer 10, a non-magnetic layer 40 located on the magnetized free layer 10, and a second magnetized fixed layer 60 located on the non-magnetic layer is formed. The side surface and the upper surface of the MRAM are covered with the protective film 70. The wiring 104b in contact with the first magnetization fixed layers 50a and 50b is connected to an external circuit.

0028For the first magnetization-fixed layers 50a and 50b, for example, an alloy of Pt and Co, or a laminated film in which Pt and Co are alternately laminated is used. The ferromagnet used here is not limited to these, and may be any ferromagnet capable of having magnetization in the vertical direction. Further, it is desirable to provide conductive films 51a and 51b containing Ta or Ti as a barrier film for suppressing diffusion prevention of the ferromagnet material in the lowermost layer of the ferromagnet. The barrier film can be regarded as a part of the first magnetization fixing layer.

0029For the magnetization free layer 10, for example, an alloy of Co and Ni, or a film in which Co and Ni are alternately laminated is used. The ferromagnet used here is not limited to these, and may be any ferromagnet capable of having magnetization in the vertical direction. Further, between the magnetization free layer 10 and the first magnetization fixed layers 50a and 50b, a coupling layer that secures conductivity and combines the magnetization of the first magnetization fixed layers 50a and 50b with the magnetization free layer 10. Need to insert (not shown). This coupling layer is an alloy layer containing at least two or more elements of Pt, Co, Fe, Ni and Ta, or an amorphous magnetic film such as CoNiB, CoFeB, CoFeZr, CoNiZr, NiFB and NiFeZr. , These laminated films are used.

0030As the non-magnetic layer 40, an insulator, a semiconductor, a metal or the like can be used, but it is preferable to use a metal oxide such as MgO or AlO.

0031As the second magnetization fixing layer 60, for example, an alloy of Pt, Co, Ru, or a laminated film in which Pt, Co, Ru are arbitrarily laminated is used. The ferromagnet used here is not limited to these, and may be any ferromagnet capable of having magnetization in the vertical direction.

0032The protective film 70 is SiN, SiCN, or a laminated film thereof. The protective film 70 preferably covers the side surface and the upper surface of the MRAM as shown in FIG. 2 (A), but a certain effect can be obtained by covering at least a part of the side surface and the upper surface of the MRAM.

0033The configuration of the MRAM of this embodiment is the same as the configuration of the MRAM described in Patent Document 1. Therefore, detailed description of the functions, actions, effects, etc. of the MRAM of the present embodiment will be omitted.

0034As shown in FIG. 2B, in the CMOS logic region 101, the heights of the wiring 104a and the via 105a formed in the wiring layer A and the heights of the wiring 104b and the via 105b formed in the wiring layer B are the same. is there.

0035&lt;Manufacturing method of semiconductor devices&gt; Next, examples of the manufacturing method of the semiconductor device 100 of the present embodiment as described above are shown in FIGS. 3 (A) to (F), 4 (G) to (L), and 5 (M) to (P). , FIGS. 6 (Q) to 6 (S) will be described. These figures are cross-sectional views showing the manufacturing flow of the semiconductor device 100 of the present embodiment, in which the MRAM cell area 102 is formed on the left side of the figure and the CMOS logic area 101 is formed on the right side of the figure.

0036First, as shown in FIG. 3 (A), vias are formed in the first interlayer insulating film 106 formed on the substrate (not shown) by using a normal multilayer wiring formation (dual damascene) process. Form (first via) 105b and wiring (first wiring) 104b. The figure shows a state after embedding Cu as a via (first via) 105b and wiring (first wiring) 104b in the first interlayer insulating film 106 and then flattening by CMP. ..

0037Next, as shown in FIG. 3B, a laminated cap film 107 is formed on the surface of the first interlayer insulating film 106 in which Cu is embedded. The laminated cap film 107 is, for example, a SiN (or SiCN) film 107c / SiO in order from the top.₂It consists of membrane 107b / SiCN membrane 107a. Then, as shown in FIG. 3C, the laminated cap film 107 of the MRAM cell region 102 is removed by photolithography and dry etching to expose the wiring (first wiring) 104b formed in the MRAM cell region 102. Let me.

0038Next, as shown in FIG. 3D, the first first magnetization fixed layer 50a is formed on the entire surface of the substrate by the sputtering method. For example, as the first magnetization fixing layer 50a, an alloy of Pt and Co or a laminated film in which Pt and Co are alternately laminated is formed.

0039Next, as shown in FIG. 3 (E), the SiN protective film 108 and SiO are placed on the first magnetization fixing layer 50a.₂The hard mask 109 is formed in this order, and the resist pattern 110 covering the portion where the first magnetization fixing layer 50a is left is formed on the hard mask 109. After that, using the resist pattern 110 as a mask, SiO₂The hard mask 109, the SiN protective film 108, and the first magnetization fixing layer 50a are dry-etched. Then, the resist pattern 110 and SiO remaining after dry etching₂When the hard mask 109 is removed, the state shown in FIG. 3 (F) is obtained. At this time, the CMOS logic region 101 is covered with a SiN (or SiCN) film 107c / SiO.₂The laminated cap film 107 composed of the film 107b / SiCN film 107a remains.

0040Next, as shown in FIG. 4 (G), the second first magnetization fixed layer 50b is formed on the entire surface of the substrate by the sputtering method. For example, as the first magnetization fixing layer 50b, an alloy of Pt and Co or a laminated film in which Pt and Co are alternately laminated is formed similarly to the first first magnetization fixation layer 50a. It is necessary to make a difference in the magnetization holding force in order to finally reverse the magnetization direction from the first first magnetization fixed layer 50a, but the magnetization is retained by changing the film thickness and film formation conditions. It is possible to make a difference in force.

0041Next, as shown in FIG. 4 (H), the SiN protective film 111 and SiO are placed on the first magnetization fixing layer 50b.₂The hard mask 112 is formed in this order, and the resist pattern 113 covering the portion where the first magnetization fixing layer 50b is left is formed on the hard mask 112. After that, using the resist pattern 113 as a mask, SiO₂The hard mask 112, the SiN protective film 111, and the first magnetization fixing layer 50b are dry-etched. Then, the resist pattern 113 and SiO remaining after dry etching₂When the hard mask 112 is removed, the state shown in FIG. 4 (I) is obtained. At this time, the CMOS logic region 101 is covered with a SiN (or SiCN) film 107c / SiO.₂The laminated cap film 107 composed of the film 107b / SiCN film 107a remains.

0042Next, SiN and SiO are applied to the entire surface of the substrate in the state shown in FIG. 4 (I).₂After forming the laminated film 114 of the above, dry etching with CMP exposes the first magnetization fixing layers 50a and 50b as shown in FIG. 4 (J). By this treatment, the SiN (or SiCN) film 107c of the laminated cap film 107 is also removed. At this time, an ultrathin SiN film may be left on the surface. In this case, the ultrathin SiN film remaining by Ar sputtering or the like can be removed in the sputtering chamber before the subsequent formation of the magnetization free layer.

0043Next, as shown in FIG. 4 (K), the magnetization free layer 10, the non-magnetic layer (tunnel barrier layer) 40, and the second magnetization fixing layer 60 are formed on the entire surface of the substrate in this order by the sputtering method. Next, from above, SiN protective film 115, SiO₂A hard mask is formed in this order, and a desired resist pattern is further formed on the hard mask. Then, using the resist pattern as a mask, SiO₂The hard mask, SiN protective film 115, second magnetization fixing layer 60, non-magnetic layer (tunnel barrier layer) 40, magnetization free layer 10, and laminated film 114 are dry-etched. Then, the resist pattern and SiO remaining after dry etching₂When the hard mask is removed, the state shown in Fig. 4 (L) is obtained. At this time, the CMOS logic area 101 is filled with SiO.₂The laminated cap film 107 composed of the film 107b / SiCN film 107a remains.

0044Next, the SiN film 116 and SiO are applied to the entire surface of the substrate in the state shown in FIG. 4 (L).₂After forming the film 117 in this order, the film 117 is flattened by CMP to obtain the state shown in FIG. 5 (M). Then SiO₂A resist pattern is formed on the film 117 so as to cover the portion where the second magnetization fixing layer 60 is left. Next, using the resist pattern as a mask, SiO₂Membrane 117, SiN film 116, SiN protective film 115, second magnetization fixing layer 60, and SiO₂The film 107b is dry etched. The dry etching is adjusted so that the non-magnetic layer (tunnel barrier layer) 40 stops etching and the magnetization free layer 10 is not exposed. Then, the resist pattern and SiO remaining after dry etching₂When the film 117 is removed, the state shown in FIG. 5 (N) is obtained. At this time, the laminated cap film 107 made of the SiCN film 107a remains in the CMOS logic region 101.

0045Next, as shown in FIG. 5 (O), a protective film 70 made of, for example, a SiCN film is formed on the entire surface of the substrate, and then a second interlayer insulating film 118 is formed on the protective film 70. Then, when the second interlayer insulating film 118 is flattened by CMP, the state shown in FIG. 5 (P) is obtained. The thickness of the second interlayer insulating film 118 after flattening is adjusted to be the same as that of the first interlayer insulating film 106.

0046Next, as shown in FIGS. 6 (Q) and 6 (R), SiO is placed on the second interlayer insulating film 118.₂After forming the hard mask 119, via hole processing and wiring groove processing are performed according to a normal wiring processing process. Here, an example of a via-first processing process for processing a via hole first is shown, but the processing method is not limited to via-first, and a trench-first process for processing a wiring groove pattern first can also be used. Is.

0047Next, by embedding the barrier metal and Cu in the wiring groove and via hole and removing the excess Cu and barrier metal by CMP, as shown in FIG. 6 (S), the logic matching wiring layer in which the MRAM is formed is formed. It is formed. According to this step, the via (second via) 105a electrically connected to the second magnetizing fixed layer 60 in the MRAM cell region 102 and the wiring electrically connected to the via (second wiring). In addition to being able to form 105b, via the same process, the via (third via) 105a that electrically connects to the wiring (first wiring) 104b in the CMOS logic area 101, and the wiring that electrically connects to the via (third via) ( Third wiring) 105b can be formed.

0048&lt;Action effect&gt; In this embodiment, the MRAM is formed in contact with the lower layer wiring. That is, in this embodiment, unlike the conventional technique shown in FIG. 13, the contact 8 (or via) is not located between the lower layer wiring and the MRAM. According to this embodiment, the thickness of the layer on which the MRAM is formed can be reduced by the amount that the contact 8 (or via) is not interposed, so that the height of the layer is not set to the MRAM. It can be the same as the height of the layer. In this case, the heights of the wiring and vias formed in each layer can be the same. As a result, it is possible to avoid the inconvenience that the multi-layer wiring structure on the logic side is changed by the MRAM formed in the multi-layer wiring layer.

0049Normally, it is considered that a contact 8 (or via) is interposed between the lower layer wiring and the MRAM for the reason of suppressing corrosion of the lower layer wiring when forming the MRAM element. If the contact 8 (or via) is not located between the lower layer wiring and the MRAM, inconveniences such as Cu corrosion on the lower layer wiring surface may occur. However, in this embodiment, the laminated cap film 107 is used. The inconvenience is avoided by covering the lower layer wiring surface of the logic area with.

0050Further, according to the present embodiment, the material configuration of the multi-layer wiring on the logic side does not change due to the MRAM formed in the multi-layer wiring layer.

0051Further, according to this embodiment, water resistant upper surface and the side surface of the MRAM, SiCN having a resistance to Cu diffusion resistance, SiN, or because it covered with a film consisting of the laminated structure, to improve the stability of the MRAM that ..

0052&lt;&lt; Second Embodiment &gt;&gt; &lt;Semiconductor device configuration&gt; 7 (A) and 7 (B) show enlarged cross-sectional views of the main parts of the wiring layer A and the wiring layer B of the semiconductor device of the present embodiment. FIG. 7 (A) shows the MRAM cell area, and FIG. 7 (B) shows the CMOS logic area.

0053The semiconductor device of the present embodiment is different from the first embodiment in that the metal cap films 120 and 121 are provided on the surfaces of the wirings 104a and 104b. Other configurations of the semiconductor device of this embodiment are the same as those of the first embodiment.

0054According to the semiconductor device of the present embodiment as described above, the metal cap film 120 is located between the wiring 104b and the first magnetization fixing layers 50a and 50b. The metal cap film 120 can be, for example, a film containing Co, a film containing W, or a film containing Ru. The thickness of the metal cap film 120 can be, for example, 5 nm. The metal cap film 120 can function as a part of the first magnetization fixing layers 50a and 50b.

0055&lt;Manufacturing method of semiconductor devices&gt; Next, an example of the method for manufacturing the semiconductor device of the present embodiment as described above will be described with reference to FIGS. 8A to 8C. These figures are cross-sectional views showing the manufacturing flow of the semiconductor device of the present embodiment, in which the MRAM cell region 102 is formed on the left side of the figure and the CMOS logic region 101 is formed on the right side of the figure.

0056First, as shown in FIG. 8 (A), via 105b and wiring 104b are formed in the first interlayer insulating film 106 formed on the substrate (not shown) by a normal multilayer wiring formation (dual damascene) process. To form. The figure shows a state after embedding Cu as a via 105b and a wiring 104b in the first interlayer insulating film 106 and then flattening it by CMP. Next, as shown in FIG. 8B, the metal cap film 120 is selectively formed on the wiring 104b by electroless plating or selective CVD.

0057After that, the state shown in FIG. 8C can be obtained by performing the same processing as that described in the first embodiment. Then, the metal cap film 120 (not shown) is selectively formed on the wiring 104a by electroless plating or selective CVD.

0058&lt;Action effect&gt; According to the present embodiment, in addition to the action and effect of the first embodiment, the following action and effect can be realized.

0059(1) According to the present embodiment, when the wiring 104b of the MRAM cell region 102 is exposed by dry etching, the surface of the wiring 104b is covered with the metal cap film 120, so that the etching gas, the release liquid, or the like is used. Corrosion of wiring 104b can be suppressed.

0060(2) Further, according to the present embodiment, by forming the metal cap films 120 and 121 on the wirings 104a and 104b, the electromigration (EM) resistance of the wirings 104a and 104b can be significantly improved.

0061FIG. 9 shows the cumulative failure probability of disconnection failure of the copper-containing wiring directly under the via hole due to EM for the reference condition in which the metal cap films 120 and 121 are not used and the condition in which the metal cap films 120 and 121 are used. It is a figure. As can be seen from the figure, the use of the metal cap films 120 and 121 improves the EM resistance by about 6000 times.

0062In the MRAM, the current at the time of writing causes the wiring to be broken by the EM, which may limit the number of times of writing to the MRAM. According to the present embodiment, by forming the metal cap films 120 and 121 on the wirings 104a and 104b, the EM resistance of the wirings can be improved, and as a result, the limitation on the number of writes can be removed.

0063(3) Further, according to the present embodiment, the EM resistance of the wirings 104a and 104b is significantly improved, the formation of voids in the wiring due to the write current can be suppressed, and RAM operation becomes possible.

0064FIGS. 10 (A) to 10 (C) show the effect when the metal cap films 120 and 121 are applied to the writing wiring of the MRAM. FIG. 11 (A) shows a schematic diagram of a magnetic field writing type, and FIG. 11 (B) shows a schematic diagram of a domain wall moving type. The magnetic field writing type, which reverses the spin of the MTJ (Magnetic Tunnel Junction) element depending on the magnetic field direction, requires a larger current than the domain wall moving type.

0065Fig. 10 (A) shows the operating temperature dependence of the number of writable times by EM rate-determining in the write wiring when a write current of 1 mA and 30 nsec is applied, assuming a magnetic field write type, with and without a metal cap. Each is shown. In the figure, "reference" is the data corresponding to no metal cap. The same assumption applies to FIGS. 10 (B) and 10 (C).

0066Fig. 10 (B) shows the operating temperature dependence of the number of writable times when a write current of 0.2 mA and 4 nsec is applied, assuming a domain wall moving type, with and without a metal cap. FIG. 10 (C) shows the number of writable times at 210 ° C for each of the magnetic field writing type and the domain wall moving type.

0067As can be seen from FIGS. 10A and 10C, in the magnetic field writing type having a large writing current, the number of DRAM writes is 1 × E under the condition that the metal cap is not used.¹⁶Cannot achieve times. However, when a metal cap is used, as shown in Fig. 10 (A), the number of DRAM writes is 1 × E.¹⁶Can achieve times. In addition, when a metal cap is used, as shown in Fig. 10 (C), the number of DRAM writes is 1 x E even in a high temperature environment of 210 ° C.¹⁶Can achieve times.

0068As can be seen from FIGS. 10 (B) and 10 (C), in the domain wall moving type, when the operating temperature exceeds around 100 ° C under the condition that the metal cap is not used, the number of DRAM writes is 1 × E.¹⁶Cannot achieve times. However, when a metal cap is used, as shown in Fig. 10 (B), the number of DRAM writes is 1 × E.¹⁶Can achieve times. In addition, when a metal cap is used, as shown in Fig. 10 (C), the number of DRAM writes is 1 x E even in a high temperature environment of 210 ° C.¹⁶Can achieve times.

0069In this way, by applying the metal cap to the write wiring, the limitation on the number of writes due to EM rate control is removed, RAM operation becomes possible even at a high temperature of 210 ° C, and it can be applied to high temperature environments such as in-vehicle microcomputers. You can expect it.

0070(4) Further, according to the method for manufacturing the semiconductor device of the present embodiment, it is possible to reduce the inconvenience caused by the low temperature of the wiring process.

0071That is, there is a risk that the interlayer insulating film easily absorbs water due to a decrease in density due to a decrease in the temperature of the wiring process, and the wiring is likely to be corroded. Inconvenience can be reduced.

0072&lt;&lt; Third Embodiment &gt;&gt; &lt;Semiconductor device configuration&gt; The configuration of the semiconductor device of the present embodiment is the first embodiment or the second embodiment except that the interlayer insulating film is a SiOCH film and the composition ratio represented by C / Si is 1 or more and 10 or less. It is the same as the embodiment.

0073&lt;Manufacturing method of semiconductor devices&gt; The method for manufacturing a semiconductor device of the present embodiment is the first embodiment or the method of manufacturing the semiconductor device, except that the interlayer insulating film is formed by a plasma polymerization reaction using a raw material having a cyclic organic silica structure represented by the following formula (1). It is the same as the second embodiment.

0074<chemistry num="1"><img id="000002" he="107" wi="153" file="JP5695453B2_D0001.tif" img-format="tif" img-content="drawing" /></chemistry> (1)

0075&lt;Action effect&gt; As a means for forming the low-k insulating layer, a means for forming a porous insulating layer by vaporizing the substance embedded in the insulating layer by heating and forming pores in the insulating layer can be considered. However, in the case of such means, a temperature of 400 ° C. or higher is required for the above heating. Since the heat resistance of MRAM is 350 ° C or less, if this means is adopted, the characteristics of MRAM may deteriorate.

0076According to the configuration of the present embodiment, since the low-k insulating layer can be formed at 300 ° C or lower, the inconvenience that MRAM is exposed to a temperature of 350 ° C or higher in the manufacturing process and the deterioration of characteristics due to thermal history As a result, the stability of MRAM is improved.

0077Further, according to the present embodiment, the average pore diameter of the interlayer insulating film is as fine as 0.3 nm or more and 0.7 nm or less, and the individual pores tend to have an independent structure. Diffusion of water, metals, etc. is suppressed. Therefore, highly reliable multi-layer wiring and MRAM are realized.

0078Further, according to the present embodiment, the composition ratio represented by C / Si of the interlayer insulating film, which is a SiOCH film, is 1 or more, and the C concentration is high, so that high resistance to plasma treatment during the process is realized. , It is possible to achieve stable wiring performance and yield with little fluctuation in wiring capacity.<u style="single"> An example of the reference form is added below.</u><u style="single">1. It has a multi-layer wiring layer formed on the substrate,</u><u style="single"> The first layer contained in the multilayer wiring layer is</u><u style="single"> The first interlayer insulating film and</u><u style="single"> A plurality of first vias embedded in the first interlayer insulating film,</u><u style="single"> A plurality of first wires embedded in the first interlayer insulating film, connected to the first via, and whose surface is exposed from the first interlayer insulating film.</u><u style="single"> The first region of the second layer included in the multilayer wiring layer and located immediately above the first layer</u><u style="single"> With at least two first magnetization fixing layers that are in contact with the first wiring and are insulated from each other,</u><u style="single"> A magnetizing free layer that overlaps the two first magnetization fixing layers in a plan view and is connected to the first magnetization fixing layer.</u><u style="single"> The non-magnetic layer located on the magnetization free layer and</u><u style="single"> An MRAM (Magnetoresistive Random Access Memory) having a second magnetization-fixing layer located on the non-magnetic layer, and</u><u style="single"> A second interlayer insulating film covering the MRAM and</u><u style="single"> A second via embedded in the second interlayer insulating film and connected to the second magnetization fixing layer,</u><u style="single"> A semiconductor device including a second wiring embedded in the second interlayer insulating film, connected to the second via, and whose surface is exposed from the second interlayer insulating film.</u><u style="single">2. In the semiconductor device according to 1.</u><u style="single"> A semiconductor device in which the height of the first layer and the height of the second layer are the same.</u><u style="single">3. In the semiconductor device according to 1 or 2.</u><u style="single"> No MRAM is located in the second region of the second layer,</u><u style="single"> With the second interlayer insulating film formed on the first layer,</u><u style="single"> A third via embedded in the second interlayer insulating film and connected to the first wiring,</u><u style="single"> A semiconductor device in which a third wiring embedded in the second interlayer insulating film and connected to the third via is located.</u><u style="single">Four. In the semiconductor device according to any one of 1 to 3,</u><u style="single"> Further having a protective film covering the MRAM</u><u style="single"> The protective film is a semiconductor device that is a SiN film, a SiCN film, or a laminated film containing these.</u><u style="single">Five. In the semiconductor device described in 4,</u><u style="single"> The protective film is a semiconductor device that covers the upper surface and the side surface of the MRAM.</u><u style="single">6. In the semiconductor device according to 4 or 5, which is subordinate to 3.</u><u style="single"> A semiconductor device that extends to the second region of the second layer and is located between the first layer and the second interlayer insulating film.</u><u style="single">7. In the semiconductor device according to any one of 1 to 6,</u><u style="single"> A semiconductor device in which the exposed surfaces of the first and second wirings are covered with a metal cap film.</u><u style="single">8. 8. In the semiconductor device described in 7.</u><u style="single"> The metal cap film covering the first wiring is a semiconductor device that becomes a part of the MRAM.</u><u style="single">9. In the semiconductor device according to any one of 1 to 8.</u><u style="single"> The first and second interlayer insulating films are semiconductor devices made of SiCOH.</u><u style="single">Ten. In the semiconductor device described in 9.</u><u style="single"> The first and second interlayer insulating films made of SiCOH are semiconductor devices having a C / Si ratio of 1 or more and less than 10.</u><u style="single">11. 11. After forming the first interlayer insulating film on the substrate, a plurality of first vias and the first wiring are embedded in the first interlayer insulating film so that the first wiring is exposed. The first step of forming one layer and</u><u style="single"> In the first region above the first layer, a second step of forming at least two first magnetization-fixed layers electrically isolated from each other on the first wiring,</u><u style="single"> A magnetization free layer that overlaps the two first magnetization fixed layers in a plan view and is electrically connected to the first magnetization fixed layer, a non-magnetic layer located on the magnetization free layer, and the above. The third step of completing the MRAM by forming a second magnetization-fixed layer located on the non-magnetic layer, and</u><u style="single"> The fourth step of forming the second interlayer insulating film covering the MRAM, and</u><u style="single"> A semiconductor device having a second via that connects to the second magnetization fixing layer and a fifth step of embedding a second wiring that connects to the second via in the second interlayer insulating film. Production method.</u><u style="single">12. In the method for manufacturing a semiconductor device described in 11.</u><u style="single"> Manufacture of a semiconductor device further comprising a step of forming a SiN film, a SiCN film, or a protective film which is a laminated film containing these so as to cover the MRAM after the third step and before the fourth step. Method.</u><u style="single">13. In the method for manufacturing a semiconductor device according to 11 or 12,</u><u style="single"> In the fourth step, the second interlayer insulating film is formed on the second region above the first layer.</u><u style="single"> In the fifth step, a third via connected to the first wiring and the third via are connected to the second region by the same process as the formation of the second via and the second wiring. A method for manufacturing a semiconductor device in which a third wiring to be connected to a via is embedded in the second interlayer insulating film.</u><u style="single">14. In the method for manufacturing a semiconductor device according to any one of 11 to 13.</u><u style="single"> A method for manufacturing a semiconductor device in which the first and second interlayer insulating films are formed by a plasma polymerization reaction using a raw material having a cyclic organic silica structure represented by the following formula (1).</u><chemistry num="1"><img id="000003" he="107" wi="153" file="JP5695453B2_D0001.tif" img-format="tif" img-content="drawing" /></chemistry><u style="single"> (1)</u><u style="single">15. 15. In the method for manufacturing a semiconductor device according to any one of 11 to 14.</u><u style="single"> A method for manufacturing a semiconductor device, comprising a step of forming a mask film covering the first wiring exposed in a region where the MRAM is not formed, after the first step and before the second step.</u><u style="single">16. In the method for manufacturing a semiconductor device according to 15.</u><u style="single"> A method for manufacturing a semiconductor device, wherein the mask film is a laminated film in which a SiN film or a SiCN film, a SiO2 film, and a SiCN film are laminated in order from the top.</u>

007910 Magnetized free layer 40 Non-magnetic layer 50a 1st magnetized fixed layer 50b 1st magnetized fixed layer 51a Conductive film 51b Conductive film 60 Magnetized fixed layer 70 Protective film 100 semiconductor devices 101 CMOS logic area 102 MRAM cell area 103 MRAM 104a wiring 104b wiring 105a beer 105b beer 106 First interlayer insulating film 107 Laminated cap membrane 107a SiC N film 107b SiO₂film 107c SiN (or SiCN) membrane 108 SiN protective film 109 SiO₂Hard mask 110 resist pattern 111 SiN protective film 112 SiO₂Hard mask 113 resist pattern 114 Laminated film 115 SiN protective film 116 SiN membrane 117 SiO₂film 118 Second interlayer insulating film 119 SiO₂Hard mask 120 metal cap membrane 121 Metal cap membrane