Magnetic tunnel junction device

0001The present disclosure relates generally to magnetic tunnel junction devices.

0002Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetization to represent stored data. Usually, the MRAM has multiple magnetic cells in the array. Typically, each cell represents a bit of data. The cell comprises a magnetic element such as a magnetic tunnel junction (MTJ).

0003Typically, the MTJ's ferromagnetic plate comprises a free layer and a pinning layer separated by a thin tunnel barrier layer. This plate is associated with the direction of magnetization (or the orientation of the magnetic moment). The magnetization direction can rotate freely in the free layer. Antiferromagnetic layers can be used to fix the magnetization of the pinning layer in a particular direction. One bit is written to the MTJ by changing the magnetization direction of one of the ferromagnetic plates of the MTJ. The resistance of MTJ is determined by the orientation of the magnetic moments of the pinning layer and the free layer. By applying a switching current to the MTJ device, the magnetic polarization of the MTJ device can be changed from the logic "1" state to the logic "0" state and vice versa.

<p num="0004"> Embodiments herein describe methods and devices for forming magnetic tunnel junction (MTJ) devices. According to an exemplary embodiment, the MTJ device deposits a first free layer of magnetically permeable material on the tunnel barrier layer, a spacer layer on the first free layer, and on the spacer layer. It is formed by a step of depositing a second free layer and a step of depositing a spin torque strengthening layer on the second free layer. One or more materials and thicknesses of the spacer layer are selected so as to substantially suppress the exchange bond between the first free layer and the second free layer. However, the first free layer and the second free layer are strongly and electrostatically coupled. Therefore, the magnetic polarization between the first free layer and the second free layer is anti-parallel regardless of whether the device is switched to the logical "1" state or the logical "0" state.</p><p num="0005"> In certain embodiments, an MTJ device having a first free layer having a first thickness, a second free layer, and a spin torque strengthening layer is disclosed. The device also includes a spacer layer between the first free layer and the second free layer. The material and thickness of the spacer layer substantially suppresses the exchange bond between the first free layer and the second free layer. The first free layer is magnetically coupled to the second free layer. In other specific embodiments, it is possible to provide a spacer layer of a combination of materials having a total thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. The combination of materials can have two different non-magnetic materials, or two or more different non-magnetic materials. In other specific embodiments, the spacer layer can be multi-layered and has a layer thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. Is possible. The spacer layer can include two non-magnetic layers made of different materials, or two or more non-magnetic layers made of different materials.</p><p num="0006"> In other specific embodiments, methods of manufacturing MTJ devices are disclosed. This method involves depositing a first free layer on the tunnel barrier layer of the MTJ structure. The first free layer contains a magnetically permeable material and has a first thickness. The method also includes the step of depositing a spacer layer on the first free layer. The spacer layer contains substantially a non-magnetically permeable insulating material and has a thickness that substantially suppresses exchange coupling. This method further comprises the step of depositing a second free layer on the spacer layer. The second free layer contains a magnetically permeable material. This method further comprises the step of depositing a spin torque reinforcement layer on top of the second free layer.</p><p num="0007"> In other particular embodiments, a computer-readable tangible medium stores instructions that can be executed by a computer to facilitate the manufacture of MTJ devices. Stored instructions are computer-executable to control the deposition of the first free layer on the tunnel barrier layer of the MTJ structure, the first free layer containing a magnetically permeable material and a first thickness. Has Stored instructions can be executed by a computer to control the deposition of the spacer layer on the first free layer. The spacer layer comprises a substantially non-magnetically permeable insulating material having a thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. Stored instructions can be executed by a computer to control the deposition of the second free layer on the spacer layer. The second free layer contains a magnetically permeable material. Stored instructions can be executed by the computer to control the deposition of the spin torque reinforcement layer on the second free layer.</p><p num="0008"> In other specific embodiments, methods of designing MTJ devices are disclosed. This method involves receiving design information that indicates at least one physical property of the semiconductor device. The semiconductor device includes a first free layer having a first thickness, a second free layer having a second thickness, a spin torque strengthening layer, and a spacer layer between the first free layer and the second free layer. ,including. The spacer layer comprises one or more materials and has a thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. Also, the spacer layer contains two or more non-magnetic layers made from different materials and has a total thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. Can have. The first free layer is magnetically coupled to the second free layer. The method further comprises transforming the design information to fit the file format and generating a data file containing the transformed design information.</p><p num="0009"> In other specific embodiments, methods for positioning packaged MTJ devices are disclosed. This method involves receiving design information, including physical positioning information for the packaged semiconductor device on the circuit board. The packaged semiconductor device is a spacer between the first free layer having the first thickness, the second free layer having the second thickness, the spin torque strengthening layer, and the first free layer and the second free layer. Includes a layer and a semiconductor structure including. The first free layer is magnetically coupled to the second free layer. This method further includes the step of transforming the design information to generate a data file.</p><p num="0010"> In other specific embodiments, a method of manufacturing a circuit board that includes a packaged MTJ device is disclosed. The method comprises receiving a data file containing design information including physical positioning information of the packaged semiconductor device on the circuit board. This method further comprises the step of manufacturing a circuit board configured to accept the packaged semiconductor device according to the design information. The packaged semiconductor device is a spacer between the first free layer having the first thickness, the second free layer having the second thickness, the spin torque strengthening layer, and the first free layer and the second free layer. Including layers. The first free layer is magnetically coupled to the second free layer.</p>

<p num="0011"> One particular advantage provided by the disclosed embodiments is the low switching current that changes the state of the MTJ device. Other aspects, advantages, and features of the disclosure will become apparent after a full review of the present application, including the following items: a brief description of the drawings, embodiments for carrying out the invention, and claims. Let's go.</p>

0012<figref num="1">FIG. 5 is a cross-sectional view of an embodiment of a magnetic tunnel junction (MTJ) device in a first state and a second state.</figref><figref num="2">FIG. 5 is a cross-sectional view of the first embodiment of the double free layer of the embodiment of the MTJ device.</figref><figref num="3">It is sectional drawing of the 2nd embodiment and the 3rd embodiment of a part of a typical MTJ device.</figref><figref num="4">It is a graph which shows the switching current pair layer thickness of the embodiment of an MTJ device.</figref><figref num="5">It is a flowchart of embodiment of the formation method of MTJ device.</figref><figref num="6">It is a flowchart of another embodiment of the method of forming an MTJ device.</figref><figref num="7">It is a flowchart of the embodiment of the design and manufacturing process of the semiconductor device including the embodiment of the MTJ device.</figref>

0013FIG. 1 is a cross-sectional view of an embodiment of the MTJ device in the first state 120, (logic 1) and the second state 130, (logic 0). The embodiment of FIG. 1 has a multilayer on the substrate 101. The substrate 101 can be, for example, a semiconductor substrate containing silicon, germanium, or a compound semiconductor material. The first layer 102 on the substrate is the bottom layer that forms the electrodes and can contain Ta. Ta provides a good texture for the antiferromagnetic (AFM) pinning layer and provides a smooth surface for growing MTJs. The bottom layer can be composed of multiple layers of different materials. Layer 103 is an antiferromagnetic (AFM) pinning layer. The AFM pinning layer 103 functions to pin the magnetic moment between the layers 104 and 108. The AFM pinning layer 103 may contain anti-ferromagnetic materials such as MnPt, IrMn, FeMn, or NiO. An exemplary thickness of the AFM pinning layer 103 is 15 nm. Other thicknesses may be adopted for the AFM pinning layer 103.

0014Layers 104, 106 and 108 form a synthetic antiferromagnetic (SAF) layer. Layer 104 is pinned by layer 103 by an exchange coupling mechanism.

0015Layer 108 is pinned to layer 104 by exchange coupling via the spacer layer 106. The spacer-layer 106 can be Ru, Rh, or Cr, or any other material that does not substantially suppress exchange binding. Layers 104 and 108 are ferromagnetic and may contain Fe, Ni, Co, or B, or a combination of these elements, such as CoFeB. The magnetic moments at layers 104 and 108 are anti-parallel and thus form an anti-ferromagnetic layer. An exemplary thickness of the SAF layer is 2 nm (nanometers) in layer 104, 0.9 nm in layer 106, and 2 nm in layer 108. Other thicknesses may be adopted for the SAF layer.

0016Layer 110 is a tunnel barrier layer that can be formed from a dielectric such as MgO. An exemplary thickness of the tunnel barrier layer 110 is 1 nm. Other thicknesses may be adopted for the tunnel barrier layer.

0017Layer 112 is a first free layer that is magnetizable and has a first thickness. Layer 114 is a spacer layer with a thickness and material that substantially suppresses the exchange bond between the first free layer 112 and the second free layer 116. The spacer layer 114 may be composed of a number of materials such as alloys or multilayers. For example, the spacer layer may include one of AlCu, AlRu, and AlAg. As another example, the spacer layer may include two layers of Ta and MgO, Ta and Mg, and one of Ta and Ru. In certain embodiments, the spacer layer has a thickness of at least 4 angstroms (4 x 10).^-10Meters). Layer 116 is a second free layer that is magnetizable and can have a second thickness that is equal to or different from the thickness of the first free layer 112. In one embodiment, the thickness of the second free layer 116 is greater than the thickness of the first free layer 112. In certain embodiments, the thickness of the first free layer 112 is between 5 and 25 angstroms. In other embodiments, the thickness of the first free layer 112 is between 15 and 20 angstroms. In certain embodiments, the thickness of the second free layer 116 is between 10 and 60 angstroms. In other embodiments, the thickness of the second free layer 116 is between 30 and 50 angstroms. In certain embodiments, the capping layer 122 is deposited on the second free layer 116. Capping layer 122 is a non-magnetic layer, forming a spin barrier or top electrode, but not a pinning layer.

0018In the logical "0" state, the magnetic polarization of the two upper free layers 112, 116 is oriented as shown in 130, and in the logical "1" state, the magnetic polarization of the two upper free layers 112, 116, Oriented as shown in 120. The state of the MTJ device can be changed by applying a switching current across the device. Specifically, the current I applied in one direction through the MTJ device._writing-1 puts the device in the logical "1" state and the current I applied in the opposite direction_writing-2 puts the device in the logical "0" state. Therefore, there may be a magnetic tunnel junction device in a memory cell where the current applied across the magnetic tunnel junction device changes the data values stored in the cell. When the magnetic moment of the lower free layer 112 is aligned with the magnetic moment of the upper pinning layer 108 of the synthetic antiferromagnetic (SAF) layer, the resistance of the device is low and the device is in the logical 0 state. .. When the magnetic moment of the lower free layer 112 is aligned opposite to the magnetic moment of the upper pinning layer 108, the resistance of the device is high and the MTJ device is in the logical "1" state.

0019Figure 2 shows some of the typical MTJ devices with many free layers. Layer 212 is a first free layer that is magnetizable and has a first thickness. Layer 212 may contain an iron alloy such as CoFeB. Layer 214 is a spacer layer formed of a dielectric such as Ta or MgO that substantially suppresses the exchange bond between the first free layer 212 and the second free layer 216. Also, exchange coupling can be substantially suppressed by the thickness of the spacer layer 214. In certain embodiments, the spacer layer 214 has a thickness of at least 4 angstroms (4 × 10).^-10Meters). In other embodiments, the spacer layer has a thickness of at least 8 angstroms. Layer 216 is a second free layer that may contain an iron alloy such as NiFe. The second free layer 216 is magnetizable. Further, the layer 214 may be a large number of spacer layers formed of a large number of dielectrics such as Ta and MgO, Ta and Mg, Ta and Ru, etc., but is not limited to these materials.

0020As can be seen from FIGS. 1 and 2, the magnetic moments M3 in the first free layers 112 and 212 are anti-parallel to the magnetic moments M4 in the second free layers 116 and 216. Regardless of the state of the MTJ device, the magnetic moments in the first and second free layers are anti-parallel. As shown by the dotted line in FIG. 2, 208, the magnetic moments in the free layer are anti-parallel because they are statically coupled but not substantially exchange-coupled. The dotted line indicates H, a magnetic field that is circuitous and magnetically connects the first free layer and the second free layer.

0021Layer 212 is a first free layer that is magnetizable and has a first thickness. Layer 212 may contain an iron alloy such as CoFeB. The layer 214 is a spacer layer formed of a dielectric such as Ta or MgO, which substantially suppresses the exchange bond between the first free layer 212 and the second free layer 216. Also, exchange coupling can be substantially suppressed by the thickness of the spacer layer 214. In certain embodiments, the spacer layer 214 has a thickness of at least 4 angstroms (4 × 10).^-10Meters). In other embodiments, the spacer layer has a thickness of at least 8 angstroms. Layer 216 is a second free layer that may contain an iron alloy such as NiFe. The second free layer 216 is magnetizable. Further, the layer 214 may be a large number of spacer layers formed of a large number of dielectrics such as Ta and MgO, Ta and Mg, Ta and Ru, etc., but is not limited to these materials.

0022FIG. 3 shows a second embodiment and a third embodiment of a part of a typical MTJ device including two free layers 312 and 316 separated by a spacer layer 314. In some second embodiments of the MTJ device 324, a spin torque strengthening layer 320 is added above the second free layer 316. The spin torque strengthening layer 320 reduces the damping constant of the free layer. The spin torque reinforcement layer 320 may include MgO, SiN, TaO, or other suitable material. In some third embodiments of the MTJ device 326, a spin storage layer 318 is added between the second free layer 316 and the spin torque strengthening layer 320. In certain embodiments, the spin storage layer 318 has high conductivity and a long diffusion distance that can result in the accumulation of angular momentum. The spin storage layer may contain Mg, Cu, Al or other suitable material.

0023FIG. 4 is a graph 400 showing switching current vs. layer thickness for different MTJ device embodiments. Line 402 shows the switching current as a function of the thickness of the first free layer in the MTJ embodiment without the second free layer. Line 404 shows the switching current as a function of the thickness of the MTJ device embodiment including the first free layer and the second free layer. More specifically, the first free layer is 20 angstroms (20 x 10).^-10Includes CoFeB with a thickness of (meters). The second free layer contains NiFe. Line 406 shows the switching current as a function of the thickness of other embodiments of MTJ devices with two free layers. The first free layer contains CoFeB with a thickness of 15 angstroms and the second free layer contains NiFe.

0024With reference to FIG. 4, low switching currents can be achieved with large free layer thickness in MTJ devices with a second free layer above the spacer, as shown in FIGS. 1 and 2. is there. As a function of the thickness of the first free layer, the switching current increases more slowly. Specifically, the provision of a CoFeB first free layer having a thickness of 15 angstroms and a second free layer having a total thickness of 25 to 50 angstroms produces a switching current of about 300 micro-amperes. In MTJ devices without a second free layer, line 402 indicates that the switching current exceeds 400 micro-amps when the free layer, CoFeB thickness exceeds 25 angstroms. Therefore, in some situations, a low switching current is required to change the state of the device in the presence of the second free layer. In certain embodiments, the first free layer has a thickness in the range of 5-25 angstroms and the second free layer has a thickness in the range of 10-60 angstroms. In other embodiments, the first free layer has a thickness in the range of 15-20 angstroms and the second free layer has a thickness of 30-50 angstroms. In certain embodiments, the thickness of the spacer layer is in the range of .4 to 30 angstroms.

0025Therefore, the presence of a second free layer, which is electrostatically coupled to the first free layer but not substantially exchange-coupled to the first free layer, causes the low switching current of the MTJ device to change the state of the device. It is possible to provide the advantages of. Also, the presence of the second free layer increases the energy barrier to the movement of electrons away from the first free layer, resulting in great efficiency. The presence of the second free layer can reduce the magnetic-distortion in the first free layer, which can improve the switching uniformity of the MTJ device.

0026FIG. 5 is a flowchart 500 of an embodiment of a method for forming an MTJ device. Starting at 502, the first free layer containing the magnetically permeable material is deposited on the tunnel barrier layer of the MTJ structure. The first free layer has a first thickness. For example, a layer of CoFeB can be deposited on top of the tunnel barrier layer as shown in Figure 1 (Layer 112). Proceeding to 504, a substantially non-magnetically permeable spacer layer is deposited on the first free layer. The spacer layer is an insulating material having a thickness that substantially suppresses the exchange bond between the first free layer and the second free layer deposited on the spacer layer. For example, a layer of Ta or MgO can be deposited on top of the first free layer as shown in FIG. 1 (Layer 114). The spacer layer itself can be a multi-layer structure containing materials such as TaMg, TaRu, MgOTa, MgTa, or RuTa. Moving to 506, a second free layer containing a magnetically permeable material is deposited on the spacer layer. For example, a layer of NiFe can be deposited on top of the spacer layer, as shown in FIG. 1 (Layer 116). Proceeding to 508, a spin torque reinforcement layer is deposited on or on the second free layer.

0027Thus, certain embodiments include methods of manufacturing magnetic tunnel junction devices. This method involves depositing a first free layer on a tunnel barrier layer of a magnetic tunnel junction structure, the first free layer containing a magnetically permeable material and having a first thickness. This method also includes the step of depositing a spacer layer on the first free layer, the spacer layer containing a substantially non-magnetically permeable insulating material, between the first free layer and the second free layer. It has a second thickness that substantially suppresses the exchange bond of. The method also includes the step of depositing a second free layer on the spacer layer, the second free layer comprising a magnetically permeable material. The method also includes the step of depositing a spin torque reinforcement layer on or on the second free layer.

0028FIG. 6 is a flowchart 600 of an embodiment for another explanation of a method of forming an MTJ device. Starting at 602, an antiferromagnetic (AFM) pinning layer is deposited on the substrate (eg, substrate 101 in FIG. 1). As shown in FIG. 1, the bottom layer can be deposited on the substrate prior to the step of depositing the AFM layer. Proceeding to 604, a synthetic antiferromagnetic (SAF) layer is deposited on the AFM pinning layer. For example, SAF layers 104, 106 and 108 can be deposited on the AFM pinning layer 102, as shown in FIG. Moving to 606, a tunnel barrier layer is deposited on the SAF layer (eg, layer 110 in FIG. 1 can be deposited on layer 108). Following 608, a first free layer is deposited on the tunnel barrier layer and the first free layer has a first thickness (eg, layer 112 in FIG. 1). Proceeding to 610, a spacer layer is deposited on the first free layer, as shown in layer 114 of FIG. The spacer layer is composed of one material or a plurality of materials and has a thickness that substantially suppresses the exchange bond between the first free layer and the second free layer. Proceeding to 612, a second free layer (eg, layer 116 in FIG. 1) is deposited on the spacer layer. The presence of a second free layer, which is electrostatically coupled to the first free layer but not substantially interchangeable, results in a low switching current to change the state of the MTJ device. Proceeding to 614, a spin torque reinforcement layer is deposited on or on the second free layer. Moving to 616, the capping layer is deposited on the second free layer. The capping layer (eg, layer 122 in FIG. 1) forms the spin barrier or top electrode, but is not the pinning layer. Capping layer 122 can be formed from Ta, TaN, or Ru. An example thickness of the capping layer is 0.2-200 nm.

0029It should be noted here that any one or more layers described herein can be deposited using a vapor deposition process, a vacuum deposition process, or any other suitable deposition process.

0030MTJ devices such as those described herein can be located within each one of multiple memory cells forming an array of magnetic random access memory. In one embodiment, for the MTJ device to store a logical "1" value in each cell of the memory array, which is inside the cells of the spin-movement-torque magnetorandom access memory (STT-MRAM). It is placed in one state of, and the opposite state for storing a logical "0" value. By applying current across the MTJ devices that form the cell, the memory cell can be placed in one state or another.

0031The MTJs and memory devices and functionality disclosed above can be designed and configured in computer files (eg, RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all such files may be provided to the manufacturer assembling the device based on such files. The resulting product comprises a semiconductor wafer that is subsequently cut into semiconductor dies and packaged into semiconductor chips. The chip is then used for electronic devices.

0032FIG. 7 shows an embodiment for a particular description of the electronic device manufacturing process 700. The physical device information 702 is accepted by the manufacturing process 700, such as in the research computer 706. The physical device information 702 is designed to represent at least one physical property of a semiconductor device such as a memory device including a memory cell including an MTJ device with a double free layer as illustrated in FIGS. 1 and 2. May contain information. For example, the physical device information 702 may include physical parameters, material properties, and structural information input via user interface 704 coupled to research computer 706. The research computer 706 includes a processor 708, such as one or more processing cores, coupled with a computer-readable medium such as memory 710. Memory 710 may store computer-readable instructions that can be executed to cause processor 708 to convert physical device information 702 to fit the file format and generate library file 712.

0033In certain embodiments, the library file 712 includes at least one data file that contains the transformed design information. For example, a memory array in which library file 712 contains an MTJ device with a double free layer as shown in Figure 1 or Figure 2 provided for use with Electronic Design Automation (EDA) Tool 720. Alternatively, it may include a library of semiconductor devices, including MTJ devices.

0034The library file 712 can be used with the EDA tool 720 on a design computer 714 that includes a processor 716, such as one or more processing cores, coupled to memory 718. The EDA tool 720 is now in memory 718 so that users of design computer 714 can design circuits that use MTJ devices with the dual free layers of Figure 1 or Figure 2 of library file 712. It can be stored as a processor executable instruction. For example, a user of design computer 714 may enter circuit design information 722 through a user interface 724 coupled to design computer 714. The circuit design information 722 may include design information representing at least one physical property of the semiconductor device, such as the MTJ device of FIG. 1 or FIG. For illustration purposes, circuit design characteristics may include identification of relationships with other elements in a particular circuit and circuit design, location information, shape information, wiring information, or other information representing the physical characteristics of a semiconductor device.

0035The design computer 714 may be configured to convert the design information, including the circuit design information 722, to fit the file format. For illustration purposes, file formats may include database binary file formats that represent planar geometry, text labels, and other information about circuit layout in hierarchical formats such as the Graphic Data System (GDSII) file format. The design computer 714 may be configured to generate a data file containing the transformed design information, such as the GDS II file 726, which contains information representing the MTJ device with the dual free layers of Figure 1 or Figure 2. For illustration purposes, the information corresponding to a system-on-chip (SOC) in which the data file contains an MTJ device with the dual free layers of Figure 1 or Figure 2 and also contains additional electronics and components within the SOC. Can include.

0036The GDSII file 726 can be accepted in manufacturing process 728 to manufacture the MTJ device of Figure 1 or FIG. 2 according to the converted information in the GDSII file 726. For example, the device manufacturing process provides the mask manufacturer 730 with a GDS II file 726 to form one or more masks, such as those used in the photolithography process illustrated as the representative mask 732. Can include. A mask 732 is used during the manufacturing process to produce one or more wafers 734, and one or more wafers 734 can be inspected and separated into dies such as the representative die 736. The die 736 may include a circuit containing the MTJ device of FIG. 1 or FIG.

0037The die 736 may be provided in a packaging process 738 in which the die 736 is incorporated into a representative package 740. For example, package 740 may include a single die 736 or multiple dies, such as a system-in-package (SiP) configuration. Package 740 may be configured to comply with one or more standards or specifications, such as the JEDEC Standards.

0038Information about package 740 can be distributed to various product designers, such as through a component library stored in computer 746. Computer 746 may include processor 748, such as one or more processing cores coupled to memory 750. A printed circuit board (PCB) tool may be stored in memory 750 as a processor executable instruction to process PCB design information 742 accepted by users of computer 746 via user interface 744. The PCB design information 742 may include physical location information of the packaged semiconductor device on the circuit board. The packaged semiconductor device corresponds to Package 740, which includes the MTJ device with the double free layer of Figure 1 or Figure 2.

0039Computer 746 transforms PCB design information 742 to have GERBER file 752 with data including physical location information of the packaged semiconductor device on the circuit board and layout of electrical connections such as traces and vias. Etc. may be configured to generate data files such as, and the packaged semiconductor device corresponds to a package 740 containing an MTJ device with a double free layer of FIG. 1 or FIG. In other embodiments, the data file generated by the converted PCB design information may have a format other than the GERBER format.

0040The GERBER file 752 can be used to make a PCB such as a representative PCB 756 that is accepted in the board assembly process 754 and manufactured according to the design information stored in the GERBER file 752. For example, the GERBER file 752 can be uploaded to one or more machines to perform various steps in the PCB manufacturing process. The PCB 756 can be fitted with electronic components, including package 740, to form a typical printed circuit assembly (PCA) 758.

0041The PCA758 can be accepted in the product manufacturing process 760 and incorporated into one or more electronic devices such as the first representative electronic device 762 and the second representative electronic device 764. As a non-limiting example for illustration purposes, the first representative electronic device 762, the second representative electronic device 764, or both are set-top boxes, music players, video players, entertainment units, You can choose from a group of navigation devices, communication devices, personal digital assistants (PDAs), fixed position data units, and computers. For other purposes, as a non-limiting example, one or more of the electronic devices 762 and 764 may be a mobile phone, a remote unit such as a handheld personal communication system (PCS) unit, a personal digital assistant, etc. Portable data units, Global Positioning System (GPS) available devices, navigation devices, meter reading It can be a fixed position data unit such as equipment), or any other device that stores or retrieves data or computer instructions, or any combination thereof. The present disclosure is not limited to these exemplary units. The embodiments of the present disclosure can be suitably used for any device including active integrated circuits including memory.

0042Thus, the MTJ device of FIG. 1 or 2 can be manufactured, processed and incorporated into an electronic device as described in Process 700 for illustration. One or more embodiments of the embodiments disclosed with respect to FIGS. 1-2 are included in various processing steps, such as in library file 712, GDSII file 726, and GERBER file 752, and memory 710 of research computer 706. , Designed computer 714 memory 718, computer 746 memory 750, board assembly process 754, etc. stored in memory of one or more other computers or processors (not shown) and also masked. It can be incorporated into one or more other physical embodiments such as 732, die 736, package 740, PCA758, prototype circuit or device (not shown), or any combination thereof. Various typical manufacturing steps have been shown, from physical device design to final products, but in other embodiments, fewer steps may be used or additional steps may be included. Similarly, process 700 may be performed by a single entity, or by one or more entities performing various stages of process 700.

0043Logical blocks, configurations, modules, circuits, and algorithmic steps for various descriptions described in connection with the embodiments disclosed herein are performed as electronic hardware, computer software, or a combination thereof. Those skilled in the art can further understand this. The components, blocks, configurations, modules, circuits, and steps for various descriptions have been outlined above with respect to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design restrictions imposed on the entire system. One of ordinary skill in the art may implement the above functionality in a manner that varies with the particular application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

0044The steps of methods or algorithms described in connection with the embodiments disclosed herein can be embodied directly in hardware, software modules executed by a processor, or a combination thereof. Software modules include random access memory (RAM) including MRAM and STT-MRAM, flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable. It can reside in programmable read-only memory (EEPROM), registers, hard disks, removable disks, compact disk read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write the information to the storage medium. In an alternative example, the storage medium can be essential to the processor. Processors and storage media can reside in application specific integrated circuits (ASICs). The ASIC can be in the computing device or user terminal. In an alternative example, the processor and storage medium can exist as separate components in the computing device or user terminal.

0045The above description of the disclosed embodiments is provided to allow one of ordinary skill in the art to make or use the disclosed embodiments. Various modifications of these embodiments will be readily apparent to those of skill in the art and the principles defined herein can be applied to other embodiments without departing from the scope of the present disclosure. The disclosure is not intended to be limited to the embodiments set forth herein and is consistent with the widest possible range according to the principles and novel features defined by the appended claims.

0046101 board 102 Bottom layer 103 AFM pinning layer 104, 106, 108 SAF fixed layer 110 tunnel barrier 112 Free layer 114 spacer 116 Free layer 118 Capping layer 120 First state 130 Second state