Light emitting device and method of manufacturing the same

The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly to a light emitting device for increasing the luminous efficiency and brightness of a nitride semiconductor light emitting device and a method for manufacturing the same.

A light emitting device (LED) is an element that creates a small number of carriers (electrons or holes) injected using a semiconductor pn junction structure and emits predetermined light by recombination of these, GaAs, Various colors can be realized by changing the material of the compound semiconductor such as AlGaAs, GaN, InGaN, and AlGaInP to form the light emitting source. For example, a red light emitting element can be obtained by using GaAsP or the like, a green light emitting element can be obtained by using GaP, InGaN or the like, and a blue light emitting element can be obtained by using an InGaN / GaN double hetero structure. Further, the UV light emitting device can be obtained by using an AlGaN / GaN or an AlGaN / AlGaN structure.

In particular, GaN has a direct transition bandgap of 3.4 eV at room temperature, and can be combined with substances such as indium nitride (InN) and aluminum nitride (AlN) to produce 1.9 eV (InN) to 3.4 eV (in N). Since it has a direct energy bandgap up to GaN) and 6.2 eV (AlN) and a wide wavelength range from visible light to ultraviolet light can be obtained, it is considered to be a material with extremely high applicability of optical elements. There is. Since the wavelength can be adjusted in this way and full color by the red, green, and blue light emitting elements in the short wavelength region can be realized, the ripple effect on the general lighting market as well as the display region is expected to be extremely large.

Compared to existing light bulbs or fluorescent lamps, the light emitting element has the characteristics of low power consumption, long life, can be installed in a narrow space, and is resistant to vibration. This type of light emitting element is used as a display element and a backlight, but since it has excellent characteristics in terms of reduction of power consumption and durability, research for its adoption in lighting applications has been actively conducted in recent years. It's coming. In the future, its application is expected to expand to backlights for large LCD-TVs, headlights for automobiles, and general lighting, and it is expected that the luminous efficiency of light emitting elements will be improved, the heat dissipation problem will be solved, and the brightness of light emitting elements will be high. Higher output and higher output remain as solutions.

So far, many technologies have been developed to improve the performance of light emitting elements. There are various indicators of the performance of the light emitting element, such as luminous efficiency (lm / W), internal quantum efficiency (%), external quantum efficiency (%), and extraction efficiency (%). The extraction efficiency is injected into the light emitting element. It is determined by the ratio of the emitted electrons to the photons emitted outside the light emitting element, and the higher the extraction efficiency, the brighter the light emitting element. Since the extraction efficiency of the light emitting element is greatly affected by the shape and surface shape of the chip, the structure of the chip, and the packaging method, it is necessary to pay close attention when designing the light emitting element.

FIG. 1 is a cross-sectional view showing a conventional light emitting element having a horizontal structure. Referring to FIG. 1, the light emitting element includes a substrate 1, an N-type semiconductor layer 2 formed on the substrate 1, an active layer 3 formed on a part of the N-type semiconductor layer 2, and a P-type. It includes a semiconductor layer 4. In this method, an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially formed on the substrate 1, and then the P-type semiconductor layer 4 and the active layer 3 in a predetermined region are etched to form an N-type. This is for exposing a part of the semiconductor layer 2 and applying a predetermined voltage to the upper surface of the exposed N-type semiconductor layer 2 and the upper surface of the P-type semiconductor layer 2, respectively.

FIG. 2 is a cross-sectional view showing a light emitting element having a conventional flip-chip structure. Referring to FIG. 2, the light emitting element includes an N-type semiconductor layer 2 sequentially formed on the base substrate 1, an active layer 3 and a P-type semiconductor layer 4, and further uses metal bumps 8 and 9. A submount substrate 5 obtained by flip-chip bonding the base substrate 1 is provided. For this purpose, an N-type semiconductor layer 2, an active layer 3 and a P-type semiconductor layer 4 are sequentially formed on a predetermined substrate 1, and a part of the P-type semiconductor layer 4 and the active layer 3 is etched. The N-type semiconductor layer 2 is exposed to form a light emitting cell. Further, another submount substrate 5 is prepared to form the first and second electrodes 6 and 7, a P-shaped metal bump 8 is formed on the first electrode 6, and the second electrode 7 is formed. An N-shaped metal bump 9 is formed on the top. After that, the light emitting cell is bonded to the submount substrate 5, and a light emitting element is manufactured by bonding the P electrode of the light emitting cell to the P type metal bump 8 and the N electrode to the N type metal bump 9. Since such a conventional light-emitting element having a flip-chip structure has high heat dissipation efficiency and almost no light shielding, it has an effect that the light efficiency is increased by 50% or more as compared with the existing light-emitting element, and emits light. Since a gold wire for driving an element is not required, application to various small packages is also considered.

The light generated in the light emitting layer of the light emitting element is emitted from the entire surface of the chip, and the light extraction efficiency is usually determined by the critical angle of light. However, in the conventional light emitting device, when etching is performed to expose the N-type semiconductor layer, the side surfaces of the P-type semiconductor layer and the active layer are processed vertically, and a part of the light generated inside the light emitting device is generated. Is totally reflected on the etched surface processed vertically from the horizontal plane. In addition, a considerable amount of light that is totally reflected is extinguished inside the light emitting element without being emitted to the outside due to internal reflection. That is, there is a disadvantage that the luminous efficiency at which electrical energy is converted into light energy and escapes to the outside of the element is low.

<p num="0009">The present invention has been made in view of the above circumstances, and an object of the present invention is to emit high-luminous and high-luminance light by enhancing characteristics such as luminous efficiency, external quantum efficiency, and extraction efficiency and ensuring reliability. It is an object of the present invention to provide a light emitting element capable of the present invention and a method for manufacturing the same.</p>

<p num="0010">In order to achieve the above-mentioned object, the present invention comprises a large number of light emitting cells including an N-type semiconductor layer and a P-type semiconductor layer formed as a part of the N-type semiconductor layer on a substrate. The N-type semiconductor layer of the one light emitting cell and the P-type semiconductor layer of the other light emitting cell adjacent thereto are connected, and the side surface of the light emitting cell including the N-type semiconductor layer or the P-type semiconductor layer is 20 to 80 ° from the horizontal plane. Provided is a light emitting element characterized by having a gradient of. Wiring for connecting the N-type semiconductor layer of the one light emitting cell and the P-type semiconductor layer of the other light emitting cell adjacent thereto may be further provided. A transparent electrode layer may be further provided on the P-type semiconductor layer, and a P-type ohmic metal layer containing Cr or Au and an N-type ohmic metal layer are respectively provided on the P-type semiconductor layer and the N-type semiconductor layer. You may also prepare for it.</p><p num="0011">Further, the present invention comprises a substrate on which a large number of light emitting cells including an N-type semiconductor layer and a P-type semiconductor layer formed on the N-type semiconductor layer are formed, and a submount substrate in which the substrate is flip-chip bonded. The N-type semiconductor layer of the one light-emitting cell and the P-type semiconductor layer of the other light-emitting cell adjacent thereto are connected to each other, and the side surface of the light-emitting cell including at least the P-type semiconductor layer is 20 to 80 from the horizontal plane. Provided is a light emitting element characterized by having a gradient of °. Wiring for connecting the N-type semiconductor layer of the one light emitting cell and the P-type semiconductor layer of the other light emitting cell adjacent thereto may be further provided.</p><p num="0012">The present invention forms a step of sequentially forming an N-type semiconductor layer and a P-type semiconductor layer on a substrate, and an etching mask pattern on the P-type semiconductor layer whose side surfaces have a predetermined gradient rather than perpendicular to the horizontal plane. Provided is a method for manufacturing a light emitting device, which comprises a step of removing the P-type semiconductor layer exposed by the etching mask pattern and a step of removing the etching mask pattern.</p><p num="0013">A step of removing a part of the N-type semiconductor layer exposed by removing the P-type semiconductor layer to form a large number of light emitting cells, and an N-type semiconductor layer of one light emitting cell and its neighbors via conductive wiring. It may further include a step of connecting the P-type semiconductor layer of the other matching light emitting cell.</p><p num="0014">Further, after the step of removing the P-type semiconductor layer and the etching mask pattern, a step of flip-chip bonding the substrate to another submount substrate may be further included. Here, a step of removing a part of the N-type semiconductor layer exposed by removing the P-type semiconductor layer to form a large number of light emitting cells, and removing the P-type semiconductor layer and the etching mask pattern. Later, a step of connecting the N-type semiconductor layer of one light emitting cell and the P-type semiconductor layer of the other light emitting cell adjacent thereto via a conductive wiring may be further included.</p><p num="0015">The steps of forming the large number of light emitting cells include a step of forming an etching mask pattern on the P-type semiconductor layer whose side surfaces have a predetermined gradient rather than perpendicular to the horizontal plane, and a P-type exposed by the etching mask pattern. It may include a step of removing the semiconductor layer and the N-type semiconductor layer to form a large number of light emitting cells, and a step of removing the etching mask pattern.</p><p num="0016">The conductive wiring is characterized in that the N-type semiconductor layer of one light emitting cell and the P-type semiconductor layer of the other light emitting cell adjacent thereto are connected by a bridge step or a step covering step.</p><p num="0017">In the step of forming the etching mask pattern, a photosensitive film having a thickness of 3 to 50 μm may be used. The steps of forming the etching mask pattern include a step of applying the photosensitive film on the P-type semiconductor layer, a step of exposing the photosensitive film according to a predetermined mask pattern, and a baking step after the exposure. It may include a step of developing without performing. The steps for forming the etching mask pattern include a step of applying the photosensitive film on the P-type semiconductor layer, a step of exposing the photosensitive film according to a predetermined mask pattern, and a step of exposing the photosensitive film at 100 to 140 ° C. It may include a step of performing hard baking at a temperature and a step of performing development.</p><p num="0018">After the step of removing the P-type semiconductor layer and the etching mask pattern, a step of removing the back surface of the substrate by a predetermined thickness and an Al, Ti, Ag, W, Ta, Ni, Ru or It may further include a step of depositing these alloys.</p>

<p num="0019">According to the light emitting device and the manufacturing method thereof according to the present invention, the light emitted from the side surface of the semiconductor layer having a predetermined gradient rather than vertical from the horizontal plane is emitted to the outside of the light emitting device without being totally reflected. Characteristics such as high light extraction efficiency, external quantum efficiency, and luminous efficiency can be obtained.</p>

<figref num="1">Sectional drawing which shows the conventional light emitting element.</figref><figref num="2">Sectional drawing which shows the conventional light emitting element.</figref><figref num="3">The conceptual cross-sectional view for explaining the light emitting element of the horizontal structure by this invention.</figref><figref num="4">A and B are cross-sectional views for explaining the manufacturing process of the first embodiment according to the present invention.</figref><figref num="5">A to D are cross-sectional views for explaining the manufacturing process of the second embodiment according to the present invention.</figref><figref num="6">A to D are cross-sectional views for explaining the manufacturing process of the third embodiment according to the present invention.</figref><figref num="7">A to D are cross-sectional views for explaining the manufacturing process of the fourth embodiment according to the present invention.</figref><figref num="8">The conceptual cross-sectional view for demonstrating the light emitting element of the flip chip structure by this invention.</figref><figref num="9">A to E are cross-sectional views for explaining the manufacturing process of the fifth embodiment according to the present invention.</figref><figref num="10">A to E are cross-sectional views for explaining the manufacturing process of the sixth embodiment according to the present invention.</figref><figref num="11">FIG. 5 is a cross-sectional view showing a seventh embodiment according to the present invention.</figref><figref num="12">A and B are conceptual cross-sectional views for explaining the effects of the conventional technique and the light emitting element according to the present invention, respectively.</figref>

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, and can be realized in different forms, and these embodiments merely complete the disclosure of the present invention and are in the art. It is provided to fully inform those who have the usual knowledge of the invention of the scope of the invention.

FIG. 3 is a conceptual cross-sectional view for explaining a light emitting element having a horizontal structure according to the present invention. Referring to FIG. 3, the light emitting element includes a substrate 10, an N-type semiconductor layer 20 sequentially formed on the substrate 10, an active layer 30, and a P-type semiconductor layer 40. The side surfaces of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 in a predetermined portion have a gradient of 80 to 20 ° from the horizontal plane, and light can be easily emitted from this side surface by changing the critical angle of light. Since it can be taken out, the luminous efficiency of the light emitting element can be improved.

4A and 4B are cross-sectional views for explaining the manufacturing process of the first embodiment according to the present invention. Referring to FIG. 4A, an N-type semiconductor layer 20, an active layer 30, and a P-type semiconductor layer 40 are sequentially formed on the substrate 10.

The substrate 10 refers to a normal wafer for manufacturing a light emitting element, and is Al._２O_３, SiC, ZnO, Si, GaAs, GaP, LiAl_２O_３, BN, AlN and GaN, at least one of the substrates 10 is used. In this embodiment, a sapphire crystal growth substrate is used.

A buffer layer (not shown) for reducing lattice mismatch between the substrate 10 and the subsequent layer may be further formed on the substrate 10 when crystals are grown. The buffer layer may be formed by including GaN or AlN as a semiconductor material.

The N-type semiconductor layer 20 is a layer in which electrons are generated, and it is preferable to use gallium nitride (GaN) in which N-type impurities are injected, but the present invention is not limited to this, and various semiconductors are used. A material layer having properties can be adopted. In this embodiment, N-type Al_xGa_1-xThe N-type semiconductor layer 20 containing N (0 x 1) is formed. Further, the P-type semiconductor layer 40 is a layer in which holes are generated, and it is preferable to use gallium nitride (GaN) in which P-type impurities are injected, but the present invention is not limited thereto. Material layers having various semiconductor properties can be adopted. In this embodiment, P-type Al_xGa_1-xThe P-type semiconductor layer 40 containing N (0 x 1) is formed. In addition, InGaN may be used as the semiconductor layer. The N-type semiconductor layer 20 and the P-type semiconductor layer 40 may be multilayer films.

The active layer 30 has a predetermined band gap, is a region where a quantum well is formed and electrons and holes are recombinated, and may contain InGaN. The emission wavelength obtained by combining electrons and holes changes depending on the type of the substance constituting the active layer 30. Therefore, it is preferable to adjust the semiconductor material contained in the active layer 30 according to the target wavelength.

The above-mentioned material layer includes an organic metal chemical vapor deposition (MOCVD), a chemical vapor deposition (CVD), a plasma-enhanced molecular beam epitaxy (PCVD), and a plasma-enhanced molecular beam epitaxy. It is formed by various vapor deposition and growth methods such as a method (MBE: Molecular Beam Epitaxy), a hydride vapor phase growth method (HVPE: Hybrid Vapor Phase Epitaxy), and the like.

After that, a part of the P-type semiconductor layer 40 and the active layer 30 is removed by a predetermined etching step to expose a part of the N-type semiconductor layer 20. After forming an etching mask pattern on the P-type semiconductor layer 40, the P-type semiconductor layer 40 and the active layer 30 are removed by performing a dry or wet etching step to expose the N-type semiconductor layer 20.

Usually, in order to carry out the etching step, a photosensitive film having a thickness of 1 to 2 μm is applied to the upper surface of the P-type semiconductor layer, and then soft baking is performed at a temperature of 80 to 90 ° C. Next, an exposure step is performed in which a pattern formed on the mask is transferred to a photosensitive film coated by irradiating light in an ultraviolet (UV) region through a predetermined photomask. After that, hard baking is performed at a temperature of 100 to 120 ° C., and a developing step is performed in which the photosensitive film at a portion where the bond is relatively weakened by the exposure step is dissolved with a solvent. Through these processes, a predetermined etching mask pattern is formed on the P-type semiconductor layer 40.

However, in this embodiment, in forming the etching mask pattern, a photosensitive film is applied to a thickness of 3 to 50 μm, which is thicker than the conventional one, and an exposure step is performed through soft baking. After that, if it is developed immediately without performing hard baking, the developed side surface of the remaining photosensitive film forms a slope having a predetermined gradient rather than perpendicular (90 °) from the horizontal plane. Next, if the P-type semiconductor layer 40, the active layer 30, and the predetermined N-type semiconductor layer 20 in the exposed region are etched using the etching mask pattern having such a side slope, the etched P-type semiconductor layer is obtained. 40, the active layer 30, and the side surface of the predetermined N-type semiconductor layer 20 are similar to the above, and a slope is obtained so as to have a predetermined gradient rather than perpendicular (90 °) from the horizontal plane.

That is, after applying a thick photosensitive film to a thickness of 3 to 50 μm on the P-type semiconductor layer 40 shown in FIG. 4A and exposing it, an etching mask pattern developed immediately is formed without performing hard baking. The P-type semiconductor layer 40 and the active layer 30 exposed by the etching mask pattern are removed by inductively coupled plasma (ICP) or a dry etching step to expose the N-type semiconductor layer 20. A part of the exposed N-type semiconductor layer 20 may be further removed. After that, if the etching mask pattern is removed, as shown in FIG. 4B, the side surfaces of the P-type semiconductor layer 40, the active layer 30, and a part of the N-type semiconductor layer 20 are not perpendicular (90 °) from the horizontal plane but are predetermined. A light emitting element having a gradient can be manufactured.

Further, when hard baking is performed after applying a thick photosensitive film to a thickness of 3 to 50 μm on the P-type semiconductor layer 40 shown in FIG. 4A and then performing hard baking, the temperature of the hard baking is set to 100 to 140 ° C. When the development is performed after the hard baking, the side surface of the developed photosensitive film is etched so that the side surface has a gradient of 80 to 20 ° from the horizontal plane. For example, when hard baking is performed at a temperature of 100 ° C., an etching mask pattern having a gradient of about 80 ° from the horizontal plane is obtained, and this is used to obtain a P-type semiconductor layer 40, an active layer 30, and a part of N. The side surface of the type semiconductor layer 20 can have a gradient of about 80 ° from the horizontal plane. Further, when hard baking is performed at a temperature of 140 ° C., an etching mask pattern having a gradient of about 20 ° from the horizontal plane is obtained, and using this, a P-type semiconductor layer 40, an active layer 30, and a part of N The side surface of the type semiconductor layer 20 can have a gradient of about 20 ° from the horizontal plane.

The P-type semiconductor layer 40 etched by using an etching mask pattern developed after exposing a photosensitive film having a thickness of 3 to 50 μm in this way and then performing hard baking at a temperature of 100 to 140 ° C. , The side surface of the active layer 30 and the predetermined N-type semiconductor layer 20 is etched so as to have a gradient of 80 to 20 ° from the horizontal plane in the same manner as described above. Therefore, the light generated inside the light emitting layer escapes to the outside of the light emitting element without being totally reflected by the side surface etched so as to have various gradients. A transparent electrode layer may be further formed on the P-type semiconductor layer 40 for the purpose of reducing the resistance of the P-type semiconductor layer 40 and increasing the translucency, and the P-type semiconductor layer 40 or the exposed N-type semiconductor may be further formed. Another ohmic metal layer may be further provided to smoothly supply the current to the upper part of the layer 20. The transparent electrode layer includes ITO (Indium Tin). Oxide), ZnO or a transparent metal having conductivity can be used, and Cr and Au can be used as the ohmic metal layer. Further, for the purpose of applying a voltage, a P-type electrode may be further formed on the upper part of the type semiconductor layer 40, or an N-type electrode may be further formed on the upper part of the N-type semiconductor layer 20.

Further, in order to enhance the heat dissipation characteristics of the light emitting element, after removing the back surface of the substrate 10 by a predetermined thickness, Al, Ti, Ag, W, Ni, Ta, Ru or an alloy thereof is applied to the back surface of the substrate 10. It may be vapor-deposited.

As is clear from the drawings, a large number of light emitting elements may be manufactured on one substrate 10. In this case, individual light emitting elements are cut out from the large number of light emitting elements for future use. At this time, the part A in FIG. 4B is a cutout part for cutting out individual light emitting elements from these a large number of light emitting elements.

This makes it possible to manufacture a light emitting element in which a part of the side surface of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 has a predetermined gradient rather than perpendicular to the horizontal plane.

The manufacturing process of the light emitting element of the present invention described above is merely an example, and the present invention is not limited thereto, and various steps and manufacturing methods can be changed or added depending on the characteristics of the device and the convenience of the process. ..

5A to 5D are cross-sectional views for explaining the manufacturing process of the second embodiment according to the present invention. The second embodiment according to the present invention is almost the same as the first embodiment. If there is only a difference, the second embodiment connects a large number of light emitting cells in series, parallel or series-parallel at the wafer level to reduce the size of the device and drive it to an appropriate voltage and current. In addition to being able to be used as lighting, it also provides a light emitting element that can be driven by an AC power source. In the following, the description of the part that overlaps with the first embodiment described above will be omitted.

Referring to FIG. 5A, the N-type semiconductor layer 20 is placed on the substrate 10 by various vapor deposition methods such as an organic metal chemical vapor deposition method, a chemical vapor deposition method, a plasma chemical vapor deposition method, a molecular beam growth method, and a hydride vapor phase growth method. , The active layer 30 and the P-type semiconductor layer 40 are sequentially formed. A buffer layer for reducing lattice mismatch between the substrate 10 and the subsequent layer may be further formed on the substrate 10 when crystals are grown.

After that, a part of the P-type semiconductor layer 40 and the active layer 30 is removed by a predetermined etching step to expose a part of the N-type semiconductor layer 20. That is, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 40 shown in FIG. 5A for exposure, and then immediately developed without hard baking to form an etching mask pattern. .. The P-type semiconductor layer 40 and the active layer 30 exposed by the etching mask pattern are removed by inductively coupled plasma or a dry etching process to expose the N-type semiconductor layer 20. A part of the exposed N-type semiconductor layer 20 may be further removed. After that, if the etching mask pattern is removed, as shown in FIG. 5B, the side surfaces of the P-type semiconductor layer 40, the active layer 30, and the predetermined N-type semiconductor layer 20 are not perpendicular (90 °) to the horizontal plane but have a predetermined gradient. A slope is obtained that has.

Further, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 40 shown in FIG. 5A for exposure, and then hard-baked at a temperature of 100 to 140 ° C. and then developed. The etching mask pattern may be formed. After etching the P-type semiconductor layer 40 and the active layer 30 exposed by this etching mask pattern, the etching mask pattern is removed and the side surfaces of the etched P-type semiconductor layer 40 and the active layer 30 are variously formed at 80 to 20 °. May have a gradient of.

Next, a predetermined region of the N-type semiconductor layer 20 exposed to form a large number of light emitting cells on the substrate 10 is removed so that the substrate 10 is exposed. For this purpose, after forming a predetermined mask pattern in all the portions except the predetermined region where the substrate 10 is exposed, the N-type semiconductor layer 20 in the region exposed by the mask pattern is etched to show FIG. 5C. As shown in, a large number of light emitting cells are electrically insulated. At this time, by forming a mask pattern having a slope on the side surface by the above-mentioned step and etching, the side surface of the N-type semiconductor layer 20 from which a large number of light emitting cells are separated is not perpendicular to the horizontal plane but has various gradients. Can also be done.

Referring to FIG. 5D, the N-type semiconductor layer 20 and the P-type semiconductor layer 40 are connected between adjacent light emitting cells by a predetermined wiring forming step. That, dew one light emitting cells connected to P-type semiconductor layer 40 of the other light emitting cells with N-type semiconductor layer 20 issued adjacent thereto via the wire 60. At this time, a conductive wiring 60 that electrically connects the N-type semiconductor layer 20 and the P-type semiconductor layer 40 of adjacent light emitting cells is formed by a bridging step.

The above-mentioned bridging process is also called an air bridging process, and a photosensitive liquid is applied and developed between chips connected to each other by using a photo process to form a photosensitive film pattern, and a substance such as metal is first vacuum-deposited on the photosensitive film pattern. It is formed as a thin film by a method such as, and then a conductive substance containing gold is applied to a predetermined thickness by a method such as electroplating, electroless plating, or metal vapor deposition. After that, if the photosensitive film pattern is removed with a solution such as solvent, the lower part of the conductive substance is completely removed and only the bridge-shaped conductive substance is formed in the space.

As the wiring 60, in addition to metal, any substance having conductivity can be used. Of course, it is also possible to use a silicon compound doped with impurities.

Further, for the purpose of applying a voltage to the light emitting element from the outside, a P-type bonding pad 50 is formed on the P-type semiconductor layer 40 of the light emitting cell located on one peripheral edge, and the light emitting cell located on the other peripheral edge is exposed. The N-type bonding pad 55 is formed on the N-type semiconductor layer 20.

The manufacturing process of the light emitting device of the present invention described above is merely an example, and the present invention is not limited thereto, and various modifications and various material films can be further added. For example, in order to improve the heat dissipation characteristics of the light emitting element, the back surface of the substrate is removed by a predetermined thickness, and then Al, Ti, Ag, W, Ta, Ni, Ru or an alloy thereof is deposited on the back surface of the substrate. You may.

As a result, a light emitting device is manufactured in which a large number of light emitting cells are connected so that a part of the side surface of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 is not perpendicular to the horizontal plane but has a predetermined gradient. Can be done.

6A to 6D are cross-sectional views for explaining the manufacturing method of the third embodiment according to the present invention. The third embodiment according to the present invention is almost the same as the second embodiment. If there is a mere difference, in the second embodiment, first, the N-type semiconductor layer 20 is exposed, and then a part of the exposed N-type semiconductor layer 20 for separation between the light emitting cells is removed. However, in the third embodiment, first, a large number of light emitting cells are separated, and then a part of the N-type semiconductor layer 20 is exposed. In the following, the description overlapping with the second embodiment described above will be omitted.

Referring to FIG. 6A, a part of the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 sequentially formed on the substrate 10 is removed to form a large number of light emitting cells. For this purpose, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 40 for exposure, and then immediately developed without hard baking to form an etching mask pattern. The light emitting cell is separated by removing the P-type semiconductor layer 40, the active layer 30, the predetermined N-type semiconductor layer 20, and the etching mask pattern exposed by the etching mask pattern. Then, as shown in the drawing, a slope is obtained such that all the side surfaces of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 have a predetermined gradient from the horizontal plane to the horizontal plane rather than perpendicularly (90 °). .. Further, an etching mask pattern developed after applying a thick photosensitive film to a thickness of 3 to 50 μm on the P-type semiconductor layer 40 and exposing it, and then performing hard baking at a temperature of 100 to 140 ° C. is applied. By removing the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 using the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 on all sides of various 80 to 20 °. It can also have a gradient.

After that, as shown in FIG. 6B, a part of the P-type semiconductor layer 40 and the active layer 30 is removed by a predetermined etching step to expose a part of the N-type semiconductor layer 20.

Referring to FIG. 6C, the N-type semiconductor layer 20 and the P-type semiconductor layer 40 are connected between adjacent light emitting cells by a bridging step.

Further, in order to apply an external voltage to the light emitting element, a P-type bonding pad 50 is formed on the P-type semiconductor layer 40 of the light emitting cell located on one peripheral edge, and the exposed N of the light emitting cell located on the other peripheral edge is formed. The N-type bonding pad 55 is formed on the type semiconductor layer 20.

The manufacturing process of the light emitting device of the present invention described above is merely an example, and the present invention is not limited thereto, and various modifications and material films can be further added. For example, in order to improve the heat dissipation characteristics of the light emitting element, after removing the back surface of the substrate by a predetermined thickness, Al, Ti, Ag, W, Ta, Ni, Ru or an alloy thereof is vapor-deposited on the back surface of the substrate. You may.

Further, as shown in FIG. 6A, when a large number of light emitting cells are separated by etching so that the side surfaces have various gradients and then etched to expose the N-type semiconductor layer 20, light is emitted by the same etching process. The element can be manufactured. That is, as shown in FIG. 6D, the side surfaces of the P-type semiconductor layer 40 and the active layer 30 that are etched so that the N-type semiconductor layer 20 is exposed can have various gradients.

As a result, a light emitting element obtained by connecting a large number of light emitting cells such that all the side surfaces of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 have a predetermined gradient rather than perpendicular to the horizontal plane can be manufactured. Can be done.

7A to 7D are cross-sectional views for explaining the manufacturing method of the fourth embodiment according to the present invention. The fourth embodiment according to the present invention is almost the same as the third embodiment. If there is a mere difference, in the third embodiment, the conductive wiring for electrically connecting the N-type semiconductor layer and the P-type semiconductor layer of the adjacent light emitting cells is formed by the bridging step. In the embodiment of the above, the above-mentioned conductive wiring is formed by a step cover registration step. In the following, the description overlapping with the third embodiment described above will be omitted.

Referring to FIG. 7A, even when etching is performed so that the side surfaces have various gradients by the above-mentioned steps to separate a large number of light emitting cells and then etched to expose the N-type semiconductor layer 20, the N-type is also formed. The sides of the P-type semiconductor layer 40 and the active layer 30 that are etched so that the semiconductor layer 20 is exposed have various gradients. Further, a transparent electrode layer 85 may be further formed on the upper part of the P-type semiconductor layer 40 for the purpose of reducing the resistance of the P-type semiconductor layer 40 and increasing the translucency, and the P-type semiconductor layer 40 or is exposed. Another ohmic metal layer 87 may be further provided to smoothly supply the current to the upper part of the N-type semiconductor layer 20. As the transparent electrode layer 85, ITO, ZnO or a transparent metal having conductivity can be used, and as the ohmic metal layer 87, Cr and Au can be used.

Referring to FIG. 7B, a continuous insulating layer 70 is formed on the entire upper surface of the substrate 10 on which a large number of light emitting cells are formed. The insulating layer 70 covers the side surface and the upper surface of the light emitting cell, and covers the upper part of the substrate 10 in the region between the light emitting cells. The insulating layer 70 can be formed from, for example, a silicon oxide film by using chemical vapor deposition (CVD) technology.

Since the side surface of the light emitting cell is a slope, the insulating layer 70 can easily cover the side surface of the light emitting cell. Since the overall thickness of the N-type semiconductor layer 20 and the active layer 30 is thin and the space between the P-type semiconductor layers 40 is wide, the P-type semiconductor layer 40 adjacent to the exposed region of the N-type semiconductor layer 20 The sides of the are also easily covered by the insulating layer 70.

Referring to FIG. 7C, the insulating layer 70 is patterned by a predetermined etching step to form an opening on the exposed N-type semiconductor layer 20 and P-type semiconductor layer 40 of the light emitting cell. As shown in the figure, when the transparent electrode layer 85 and / or the ohmic metal layer 87 is formed, the transparent electrode layer 85 and / or the ohmic metal layer 87 is exposed by the opening.

With reference to FIG. 7D, the wiring 80 is formed on the insulating layer 70 having the opening. The wiring 80 is electrically connected to the N-type semiconductor layer 20 and the P-type semiconductor layer 40 through the opening, and electrically connects the N-type semiconductor layer 20 and the P-type semiconductor layer 40 of adjacent light emitting cells, respectively. Connecting.

The wiring 80 can be formed by plating technology. That is, the wiring 80 is formed by forming an etching mask pattern having an opening limiting the wiring 80 region on the insulating layer 70, plating the metal layer in the opening, and then removing the etching mask pattern. Can be formed.

Further, the wiring 80 may be formed by chemical vapor deposition or physical vapor deposition technology. That is, wiring can be formed by forming a metal layer by a vapor deposition technique such as electron beam deposition and then patterning the metal layer by using a photograph and an etching process. Since the side surface of the light emitting cell is a slope, the metal layer is continuously provided on the upper part of the side surface of the light emitting cell.

The light emitting element in which the wiring 80 is formed by such a method can prevent the wiring 80 from being short-circuited or short-circuited due to external pressure, and the conductive substance such as metal remaining during the formation of the wiring 80 is a light emitting cell. There is an advantage that it can be prevented from short-circuiting.

As a result, a light emitting element obtained by connecting a large number of light emitting cells such that all the side surfaces of the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 have a predetermined gradient rather than perpendicular to the horizontal plane can be manufactured. Can be done.

As described above, the light emitting device according to the present invention emits light as compared with the conventional light emitting device because some side surfaces of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer have a predetermined gradient rather than perpendicular to the horizontal plane. Efficiency can be increased. This is because photons that were reflected on a conventional flat surface escape to the outside without being reflected by the surfaces at various angles.

FIG. 8 is a conceptual cross-sectional view for explaining a light emitting element having a flip chip structure according to the present invention. Referring to FIG. 8, a light emitting layer sequentially formed on the base substrate 110, that is, an N-type semiconductor layer 120, an active layer 130, and a P-type semiconductor layer 140 are provided, and metal bumps 150 and 155 are further used. The submount substrate 200 is flip-chip bonded to the base substrate 110 on which the light emitting layer is formed. The side surface of the light emitting layer including the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 has a gradient of 20 to 80 ° from the horizontal plane, and light can be easily extracted from this side surface by changing the critical angle of light. It is possible to improve the luminous efficiency of the light emitting element.

9A to 9E are cross-sectional views for explaining the manufacturing process of the fifth embodiment according to the present invention. Referring to FIG. 9A, the N-type semiconductor layer 120, the active layer 130, and the P-type semiconductor layer 140 are sequentially formed on the base substrate 110. The base substrate 110 refers to a normal wafer for manufacturing a light emitting element, and is Al._２O_３, ZnO, LiAl_２O_３Use a transparent substrate such as. In this embodiment, a transparent crystal growth substrate made of sapphire is used.

The N-type semiconductor layer 120, the active layer 130, and the base substrate 110 are subjected to various vapor deposition methods such as an organic metal chemical vapor deposition method, a chemical vapor deposition method, a plasma chemical vapor deposition method, a molecular beam growth method, and a hydride vapor phase growth method. The P-type semiconductor layer 140 is sequentially formed. A buffer layer for reducing the lattice mismatch between the substrate 110 and the subsequent layer may be further formed on the substrate 110 when the crystal is grown. Since this is as described above, overlapping explanations will be omitted below.

After that, a part of the P-type semiconductor layer 140 and the active layer 130 is removed by a predetermined etching step to expose a part of the N-type semiconductor layer 120. This is done in the same manner as in the above-described embodiment.

That is, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 140 shown in FIG. 9A for exposure, and then immediately developed without hard baking to form an etching mask pattern. .. The P-type semiconductor layer 140 and the active layer 130 exposed by the etching mask pattern are removed by an inductively coupled plasma or a dry etching process to expose the N-type semiconductor layer 120. After that, if the etching mask pattern is removed, as shown in FIG. 9B, a slope is obtained in which the side surfaces of the P-type semiconductor layer 140 and the active layer 130 are not vertical (90 °) but have a predetermined gradient.

Further, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 140 shown in FIG. 9A for exposure, and then hard-baked at a temperature of 100 to 140 ° C. and then developed. The etching mask pattern may be formed. After etching the P-type semiconductor layer 140 and the active layer 130 exposed by such an etching mask pattern, the side surfaces of the P-type semiconductor layer 140 and the active layer 130 etched by removing the etching mask pattern are 80 to 80 to the horizontal plane. It can also have various gradients of 20 °.

A reflective layer for reflecting light may be further formed on the upper part of the P-type semiconductor layer 140, and the current is smoothly supplied to the upper part of the P-type semiconductor layer 140 or the exposed N-type semiconductor layer 120. Another ohmic metal layer for the purpose may be further provided. Cr and Au can be used as the ohmic metal layer.

Further, as shown in FIG. 9C, a P-type metal bump 155 is formed on the P-type semiconductor layer 140, and an N-type metal bump 150 is formed on the N-type semiconductor layer 120 for bumping. As the P-type and N-type metal bumps 155 and 150, at least one of Pb, Sn, Au, Ge, Cu, Bi, Cd, Zn, Ag, Ni and Ti can be used, and alloys thereof. Can also be used. For this purpose, after applying a photosensitive film on the entire structure, a photoetching step using a predetermined mask is performed to expose a part of the P-type semiconductor layer 140 and the N-type semiconductor layer 120. It forms a membrane pattern (not shown). After depositing a metal film on the entire structure, a metal film formed on the upper part of the P-type semiconductor layer 140 exposed by the photosensitive film pattern and a metal film formed on the upper part of the N-type semiconductor layer 120 are formed. The metal film and the photosensitive film pattern in the remaining region to be removed are removed. As a result, the P-type metal bump 155 is formed on the P-type semiconductor layer 140, and the N-type metal bump 150 is formed on the N-type semiconductor layer 120.

Next, referring to FIG. 9D, another submount substrate 200 is provided to form the P-type bonding pad 215 and the N-type bonding pad 210 connected to the P-type metal bump 155 and the N-type metal bump 150, respectively.

At this time, as the submount substrate 200, various substrates 200 having excellent thermal conductivity are used. That is, SiC, Si, Ge, SiGe, AlN, metal and the like are used. In this embodiment, AlN having excellent thermal conductivity and insulating property is used. Of course, the present invention is not limited to this, and a metallic substance having high thermal conductivity and excellent electrical conductivity can be used. In this case, an insulating film dielectric film is formed on the substrate 200 to provide sufficient insulation. As the dielectric film, SiO_２, MgO and SiN or insulating materials can be used. Further, the N-type bonding pad 210 and the P-type bonding pad 215 are formed by using a metal having excellent electrical conductivity. This is formed by a screen printing method or by a thin-film deposition step using a predetermined mask pattern.

After that, the submount substrate 200 and the base substrate 110 on which the light emitting layer is formed are flip-chip bonded.

Referring to FIG. 9E, in the light emitting element of the present invention, the N-type and P-type metal bumps 150 and 155 formed on the upper part of the light-emitting layer are connected to the N-type and P-type bonding pads 210 and 215 of the submount substrate 200. It is bonded as it is. At this time, bonding can be performed using either one of heat and ultrasonic waves, or both of them. The metal bumps 150, 155 and the lower bonding pads 210, 215 are connected by various bonding methods. In addition, the N-type and P-type metal bumps 150 and 155 are not necessarily formed on the upper part of the light emitting layer, and the respective metal bumps may be formed on the submount substrate 200.

As is clear from the drawings, a large number of light emitting elements may be manufactured on one substrate, and in this case, individual light emitting elements are cut out from the large number of light emitting elements for future use. At this time, the part A in FIG. 9E serves as a cutout part for cutting out individual light emitting elements from these a large number of light emitting elements.

The manufacturing process of the light emitting device of the present invention described above is merely an example, and the present invention is not limited thereto, and various steps and manufacturing methods can be modified or added according to the characteristics of the device and the convenience of the steps. Is. For example, in the same process as above, as shown in FIG. 9A, a base substrate in which an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially formed is formed, and first, the P is exposed so that the substrate is exposed. A large number of light emitting elements can be individually separated by removing a part of the type semiconductor layer, the active layer, and the N-type semiconductor layer. At this time, the side surfaces of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer etched by the above-mentioned steps may be formed so as to have a predetermined gradient rather than perpendicular to the horizontal plane.

This makes it possible to manufacture a light emitting device having a flip-chip structure in which a part of the side surface of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer has a predetermined gradient rather than perpendicular to the horizontal plane.

10A to 10E are cross-sectional views for explaining the manufacturing process of the sixth embodiment according to the present invention. The sixth embodiment according to the present invention is almost the same as the fifth embodiment. If there is a mere difference, in the sixth embodiment, a large number of light emitting cells are connected in various ways such as in series, parallel or series-parallel at the wafer level to reduce the size of the element and drive it to an appropriate voltage and current. It is to provide a light emitting element having a flip-chip structure that can be used as lighting and can be driven even with an AC power source. In the following, the description overlapping with the above-described embodiment will be omitted.

With reference to FIG. 10A, an N-type semiconductor layer is placed on the base substrate 110 by various vapor deposition methods such as an organic metal chemical vapor deposition method, a chemical vapor deposition method, a plasma chemical vapor deposition method, a molecular beam growth method, and a hydride vapor phase growth method. The 120, the active layer 130, and the P-type semiconductor layer 140 are sequentially formed. A buffer layer may be further formed on the base substrate 110 to reduce the lattice mismatch between the substrate 110 and the subsequent layer when the crystals are grown.

After that, a part of the N-type semiconductor layer 120, the active layer 130, and the P-type semiconductor layer 140 sequentially formed on the base substrate 110 is removed to form a large number of light emitting cells. For this purpose, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 140 shown in FIG. 10A for exposure, and then immediately developed without hard baking to obtain an etching mask pattern. Form. The P-type semiconductor layer 140, the active layer 130, and the predetermined N-type semiconductor layer 120 exposed by the etching mask pattern are removed by inductively coupled plasma or a dry etching step to separate the light emitting cells. Then, when the etching mask pattern is removed, as shown in FIG. 10B, all the side surfaces of the etched P-type semiconductor layer 140, active layer 130, and N-type semiconductor layer 120 are predetermined rather than perpendicular (90 °) from the horizontal plane. A slope having a slope of is obtained.

Further, a photosensitive film having a thickness of 3 to 50 μm is thickly applied onto the P-type semiconductor layer 140 shown in FIG. 10A for exposure, and then hard-baked at a temperature of 100 to 140 ° C. and then developed. The etching mask pattern may be formed. After etching the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 exposed by such an etching mask pattern, the etching mask pattern is removed to etch the P-type semiconductor layer 140 and the active layer 130. The sides can also have various gradients of 80-20 °.

Next, as shown in FIG. 10C, a part of the P-type semiconductor layer 140 and the active layer 130 is removed by a predetermined etching step to expose a part of the N-type semiconductor layer 120. The exposed N-type semiconductor layer 120 of one light emitting cell and the P-type semiconductor layer 140 of the other light emitting cell adjacent to each other are connected via a predetermined conductive wiring. At this time, the bridge wiring 160 is formed by using a conductive substance, but is formed by using a metal. Of course, a silicon compound doped with impurities can also be used. The bridge wiring 160 is formed by a bridge process.

Further, a large number of metal bumps are formed on the upper part of each light emitting cell for bumping, and above the P-type semiconductor layer 140 of the light emitting cell located on one peripheral edge and the N-type semiconductor layer 120 of the light emitting cell located on the other peripheral edge. Further, a P-type metal bump 155 and an N-type metal bump 150 are further formed in the above.

Next, as shown in FIG. 10D, another submount substrate 200 is provided, a large number of bonding layers 220 are provided on the upper part of the substrate 200, a P-type bonding pad 215 located on one peripheral edge of the submount substrate 200, and the other. The N-type bonding pad 210 located on the peripheral edge of the surface is formed.

After that, as shown in FIG. 10E, the base substrate 110 on which the above-mentioned large number of light emitting cells are formed and the submount substrate 200 are flip-chip bonded to manufacture a light emitting element. Bonding is performed via the metal bumps 150 and 155 formed on the upper part of the light emitting cell and the bonding layer 220 formed on the submount substrate 200. The P-type bonding pad 215 located on one peripheral edge of the submount substrate 200 is connected to the P-type metal bump 155 of the light emitting cell located on one peripheral edge, and the N-type bonding pad 210 located on the other peripheral edge is connected to the other peripheral edge. It is connected to the N-type semiconductor layer 150 of the light emitting cell located at.

The above-described method for manufacturing a light emitting device of the present invention is not limited to this, and various steps and manufacturing methods can be modified or added according to the characteristics of the device and the convenience of the steps. For example, in this embodiment, after forming a conductive wiring that electrically connects the N-type semiconductor layer and the P-type semiconductor layer of adjacent light emitting cells via a bridge step, flip-chip bonding is performed with the submount substrate. However, the present invention is not limited to this, and the conductivity for electrically connecting the N-type semiconductor layer and the P-type semiconductor layer of adjacent light emitting cells by the same step covering step as in the fourth embodiment. Wiring may be formed. Further, an electrode layer is formed on the submount substrate at the time of flip-chip bonding between a large number of light emitting cells and the submount substrate, and the N-type semiconductor layer and the P-type semiconductor layer of adjacent light emitting cells are electrically connected via metal bumps. You may.

This makes it possible to manufacture a light emitting element in which a large number of flip-chip-shaped light emitting cells are arranged on a submount substrate so that the side surface of the light emitting layer has a predetermined gradient rather than perpendicular to the horizontal plane. The light emitting cells can be connected in various ways such as series, parallel or series-parallel depending on the purpose.

FIG. 11 is a cross-sectional view showing a seventh embodiment according to the present invention. The seventh embodiment according to the present invention is almost the same as the sixth embodiment. If there is a mere difference, in the seventh embodiment, as shown in FIG. 10B, after etching so that the side surfaces have various gradients to separate a large number of light emitting cells, the N-type semiconductor layer is exposed. Therefore, even in the case of etching, the light emitting element can be manufactured by using the same etching process. That is, as shown in FIG. 11, the side surfaces of the P-type semiconductor layer 140 and the active layer 130 that are etched so that the N-type semiconductor layer 120 is exposed can have various gradients.

This makes it possible to manufacture a light emitting element in which a large number of flip-chip-shaped light emitting cells are arranged on a submount substrate so that all the side surfaces of the light emitting layer have a predetermined gradient rather than perpendicular to the horizontal plane. The light emitting cells can be connected in various ways such as series, parallel or series-parallel depending on the purpose.

As described above, in the light-emitting element having a flip-chip structure, the luminous efficiency is improved as compared with the conventional light-emitting element by allowing a part of the side surface of the light-emitting layer to have a predetermined gradient rather than perpendicular to the horizontal plane. Can be enhanced. This is because photons that were reflected on a conventional flat surface escape to the outside without being reflected by the surfaces at various angles.

12A and 12B are conceptual cross-sectional views for explaining the effects of the conventional technique and the light emitting device according to the present invention, respectively.

The optical efficiency of a light emitting element can be roughly divided into an internal quantum efficiency and an external quantum efficiency, and the internal quantum efficiency is determined by the design and quality of the active layer. In the case of external quantum efficiency, it is determined by the amount of photons generated in the active layer emitted to the outside of the light emitting device. FIG. 12A shows a light emitting device according to a conventional technique. With reference to the figure, when the side surface of the semiconductor layer is formed vertically from the horizontal plane, some photons cannot pass through the side surface of the semiconductor layer and are reflected from there, and the totally reflected light is transmitted to the outside. It cannot be done and disappears inside the light emitting element. On the other hand, referring to FIG. 12B showing the light emitting device according to the present invention, when the side surface of the semiconductor layer has a predetermined gradient rather than perpendicular to the horizontal plane, the side surface having the predetermined gradient determines the critical angle of light. It promotes that light can be taken out more easily by changing it. Therefore, there is a high probability that the light emitted from the active layer is emitted to the outside of the light emitting element without being totally reflected, resulting in a remarkable increase in external quantum efficiency.

The light emitting device and the method for manufacturing the light emitting device according to the present invention have been described above, but this is merely an example, and the present invention is not limited thereto. It should be noted that, as claimed in the claims, the technique of the present invention is made to the extent that any person having ordinary knowledge in this technical field can carry out various changes without deviating from the gist of the present invention. It can be said that there is a spirit of the world.

As described above, according to the light emitting device and the manufacturing method thereof according to the present invention, the light emitted from the side surface of the semiconductor layer having a predetermined gradient rather than vertical from the horizontal plane is emitted to the outside of the light emitting device without being totally reflected. Therefore, characteristics such as higher light extraction efficiency, external quantum efficiency, and luminous efficiency can be obtained. Further, the light emitting device of the present invention emits light having high luminous intensity and high brightness, and has an advantage that it can be applied to various product fields in which excellent light characteristics are required.

10, 110: Substrate, 20, 120: N-type semiconductor layer, 30, 130: active layer, 40, 140: P-type semiconductor layer, 50, 55: Bonding pad, 60, 160: Wiring, 200: Submount board, 210, 215: Metal bumps, 220: Bonding layer