Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device including a LOCOS offset field effect transistor having a high withstand voltage and a method for manufacturing the same.

Currently, the market demands for ICs called voltage regulators and switching regulators that control the power supply voltage and output a constant voltage are diversifying, and for example, ICs that can guarantee even in the voltage band of 50V or higher are required. It's coming. Examples of the field effect transistor (hereinafter referred to as MOS transistor) used in an IC having a high withstand voltage include a MOS transistor having a LOCOS offset drain structure as a conventional planar type MOS transistor having a high withstand voltage.

Figure 3 shows the manufacturing method of the LOCOS offset type MOS transistor. As shown in FIG. 3A, the sacrificial oxide film 22 and the nitride film 21 are deposited on the P-type silicon substrate, and the nitride film 21 is selectively removed using a photoresist patterned so as to open a desired region as a mask. , An N-type offset diffusion layer 31 is formed using an ion implantation method. Next, as shown in FIG. 3 (b), the nitride film 21 is used as a pattern, and the LOCOS oxide film 23 is selectively formed by, for example, Wet oxidation. Next, the nitride film 21 and the sacrificial oxide film 22 are removed to form a gate oxide film 24, for example, a polycrystalline silicon film is deposited on the gate oxide film 24. Then, the gate electrode 25 is formed by removing the polycrystalline silicon film using a photoresist patterned so as to open a desired region as a mask, and ions are used as a mask using a photoresist patterned so as to open a desired region. An N-type drain diffusion layer 34 and a source diffusion layer 35 are formed by the implantation method, and FIG. 3 (c) is obtained.

In the conventional structure shown in FIG. 3 (c), the electric field relaxation between the gate electrode and the drain electrode can be increased by appropriately selecting the thickness of the LOCOS oxide film 23 and the concentration of the offset diffusion layer 31. Is. However, regarding the joint portion between the offset diffusion layer 31 and the drain diffusion layer 34, the offset diffusion layer 31 covers the lower edge 34a of the drain diffusion layer due to variations in the thickness of the LOCOS oxide film 23 and the thickness of the nitride film 21 in the manufacturing process. The structure is insufficient to alleviate the electric field concentration on the lower edge 34a of the drain diffusion layer. For example, when the concentration of the offset diffusion layer 31 is sufficiently high and the offset diffusion layer 31 is diffused to the lower edge 34a of the drain diffusion layer, the depletion layer of the offset diffusion layer 31 does not extend, so that the electric field between the gate electrode and the drain electrode Becomes stronger and causes avalanche breakdown at relatively low voltage. It is difficult to apply the above structure in the device design of high withstand voltage elements such as 50V.

As the above countermeasure, as shown in Patent Document 1, a trench is formed in the offset portion of the LOCOS offset type MOS transistor, an offset diffusion layer is formed, and a LOCOS oxide film is embedded therein to generate an electric field of a high concentration drain layer. There is a method of covering the concentrated area with offset diffusion.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 6-29313</text></patcit>

<p> In the structure of the MOS transistor shown in Patent Document 1, since the effective offset diffusion layer width becomes large, the resistance component becomes large and the driving ability as a MOS transistor is lowered. Further, by expanding the shape of the concave portion in which the LOCOS oxide film is embedded, the offset diffusion layer also has a downward expansion structure, and the diffusion layer extends in the channel direction of the MOS transistor. This prevents the leak current from flowing due to the punch-through phenomenon by joining the drain offset diffusion layer and the depletion layer generated on the substrate to the depletion layer on the source diffusion layer side when a high voltage is applied to the drain electrode. Therefore, it is necessary to take a large gate length of the MOS transistor. Especially in the case of a structure in which high withstand voltage is required for both the drain electrode and the source electrode, the increase in size has a great influence on the manufacturing cost.</p><p> Above all, the structure is such that the withstand voltage between the gate electrode and the drain electrode fluctuates due to manufacturing variations in the formation of the recess in the offset region and the formation of the LOCOS oxide film embedded in the recess. For example, if the recesses become deeper due to manufacturing variations and the LOCOS oxide film grows thin, the channel end of the offset diffusion layer will have an angular shape, and the withstand voltage will drop extremely due to the occurrence of electric field concentration. .. Therefore, it can be said that it is very difficult to guarantee a high withstand voltage in the above structure in consideration of manufacturing variations and the like.</p>

<p> In order to solve the above problems, the present invention uses the following means. (1) In the manufacture of semiconductor devices including LOCOS offset field effect transistors The process of forming a sacrificial oxide film on the first conductive type semiconductor substrate, A step of forming a nitride film on the sacrificial oxide film and a step of etching the nitride film only in a desired region using a pattern using a photoresist. A step of forming a second conductive type offset diffusion layer by using an ion implantation method only in a region to be a first offset diffusion layer, and A step of forming a LOCOS oxide film in the region where the nitride film is etched, and The step of removing the nitride film and the sacrificial oxide film, and A step of forming a gate oxide film on the surface of the semiconductor substrate, forming a polycrystalline silicon film, and etching the polycrystalline silicon film only in a desired region by a pattern using a photoresist. The thickness of the oxide film in the region of the LOCOS oxide film forming portion where the high-concentration diffusion layer to be the drain diffusion layer is formed becomes thinner as it approaches the drain diffusion layer by the pattern using the photoresist. And the process of etching The process of forming a second conductive type high-concentration diffusion layer using the ion implantation method, A method for manufacturing a semiconductor device, which is characterized by having the above. (2) A method for manufacturing a semiconductor device, which comprises performing isotropic etching in the step of etching the LOCOS oxide film. (3) The first conductive type semiconductor substrate and A gate oxide film having both ends provided on the surface of the semiconductor substrate and A second conductive type source diffusion layer provided near the first surface of the semiconductor substrate at one end of the gate oxide film, and A LOCOS oxide film having both ends, one end of which is in contact with the gate oxide film at the other end of the gate oxide film, A gate electrode arranged on the gate oxide film so as to straddle the end of the source diffusion layer to the LOCOS oxide film. A second conductive type offset diffusion layer provided near the second surface of the semiconductor substrate below the LOCOS oxide film, and A semiconductor device composed of a second conductive type drain diffusion layer provided near the third surface of the semiconductor substrate adjacent to the other end of the LOCOS oxide film on the opposite side of the gate oxide film. And The thickness of the LOCOS oxide film is continuously thinner than the initial thickness from a position separated from the gate electrode to the other end of the LOCOS oxide film, and the LOCOS oxide film is oxidized at the other end of the LOCOS oxide film. The surface of the film is located below the surface of the semiconductor substrate, which is the surface of the drain diffusion layer, and the end portion of the drain diffusion layer extends to the vicinity of the fourth surface of the semiconductor substrate below the thinned region. , A semiconductor device that overlaps the offset diffusion layer.</p>

<p> In a LOCOS offset MOS transistor, the LOCOS oxide film around the drain diffusion layer or source diffusion layer, which requires high withstand voltage, is etched to form a drain diffusion layer or source diffusion layer so as to cover the region from which the LOCOS oxide film has been removed. By doing so, since the lower part of the drain diffusion layer or the source electrode is covered by the offset diffusion layer, the electric field concentration generated in the region under the drain diffusion layer can be alleviated and can be guaranteed even under a voltage of 50 V or more. It becomes possible to provide a semiconductor device including a MOS transistor.</p>

Hereinafter, the best mode according to the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1D show a semiconductor device according to an embodiment of the present invention and a manufacturing method thereof. In the following description, an N-channel MOS transistor will be described as an example.

A sacrificial oxide film 22 is formed on the P-type semiconductor substrate 11, a nitride film 21 is formed on the sacrificial oxide film 22, the nitride film 21 is patterned so that a desired region is opened, and then the P-type in the opened region is formed. FIG. 1A shows a state in which the offset diffusion layer 31 is formed on the surface region of the semiconductor substrate 11 by the ion implantation method. In the patterning of the nitride film 21, the photoresist is uniformly applied on the nitride film 21, the photoresist is opened so as to open a desired region by using a photolithography method, and the patterned photoresist is used as a mask. For example, dry etching is performed using a fluorine-based gas. When the offset diffusion layer 31 was formed by the ion implantation method, the mask used for etching the nitride film 21 was used, and the final impurity concentration of the offset diffusion layer 31 was 1 × 10.¹⁶atom / cm³~1×10¹⁸atom / cm³Make sure that the impurity concentration is about the same. Phosphorus is used as the impurity to be introduced. The injection energy is set so that the diffusion distance of the final offset diffusion layer 31 in the depth direction from the surface of the semiconductor substrate is 0.3 mm or more, although it depends on the amount of impurities to be introduced.

Next, using the nitride film 21 as a mask, thermal oxidation treatment is performed to form the LOCOS oxide film 23 having a size of about 600 nm to 800 nm as shown in FIG. 1 (b). Then, the nitride film 21 and the sacrificial oxide film 22 are removed, and the gate oxide film 24 is formed by thermal oxidation. Then, a polycrystalline silicon film having a film thickness of 200 nm to 400 nm is formed on the entire surface of the gate oxide film 24 by, for example, a chemical vapor deposition method, and phosphorus is, for example, 1 × 10 by a solid layer diffusion method.²⁰atom / cm³It is diffused in polycrystalline silicon so that the concentration of impurities is about the same, and it is made conductive. At this time, there is also a method of injecting impurities into polycrystalline silicon by ion implantation instead of the solid layer diffusion method. After that, a conductive polycrystalline silicon film was patterned and extended from a part of the LOCOS oxide film 23 onto the gate oxide film 24 on the source region side to form the gate electrode 25, as shown in FIG. 1 (c). Obtain the structure shown.

Next, a photoresist is formed so that the periphery of the region that will later become the drain diffusion layer opens, and a part of the LOCOS oxide film 23 located on both sides thereof and the gate oxide film 24 sandwiched therein are isotropically etched by wet etching. To do. At this time, the gate oxide film 24 on the region that will later become the source diffusion layer may also be etched at the same time.

After that, impurities are opened by using an ion implantation method using a photoresist patterned so as to open a desired region such as a region to be a drain diffusion layer and a region to be a source diffusion layer from which the LOCOS oxide film 23 has been removed as a mask. Inject into. The drain diffusion layer 34 and the source diffusion layer 35 are formed through heat treatment to obtain the structure shown in FIG. 1 (d). At this time, in the ion implantation method for forming the drain diffusion layer 34 and the source diffusion layer 35, phosphorus or arsenic is used as the impurities to be introduced, and the final surface impurity concentration of the drain diffusion layer 34 and the source diffusion layer 35 is increased. 1x10¹⁹atom / cm³Make it above. The ion implantation energy is set so that the diffusion distance of the drain diffusion layer 34 and the source diffusion layer 35 in the depth direction from the surface of the semiconductor substrate is about 0.2 um. In the above, in the etching of the LOCOS oxide film 23, the end of the drain diffusion layer 34 of the LOCOS oxide film 23 is formed in a round shape as shown in FIG. 1 (d) by performing isotropic etching. The thickness of the LOCOS oxide film 23 on the offset diffusion layer 31 becomes thinner as it approaches the end of the drain diffusion layer 34. Thereby, by forming the drain diffusion layer 34 so as to cover the region where the LOCOS oxide film 23 is etched by using the ion implantation method, the end of the drain diffusion layer 34 is formed extending into the offset diffusion layer 31. Further, it has a concentration distribution according to the thickness of the LOCOS oxide film 23 after etching. That is, the impurity concentration at the end of the drain diffusion layer 34 is lower than the impurity concentration at the center of the drain diffusion layer 34. That is, a diffusion layer region for relaxing the electric field is formed at the drain end. Further, since the depth of the drain diffusion layer 34 also changes according to the impurity concentration distribution of the drain diffusion layer 34, the lower edge 34b of the drain diffusion layer has a smooth shape, and electric field concentration is less likely to occur. As a result, high withstand voltage can be guaranteed.

FIG. 2 is a schematic cross-sectional view showing the semiconductor device of the present invention manufactured by the above-mentioned manufacturing method. A semiconductor device including an offset drain type MOS transistor formed on a P-type semiconductor substrate 11, in which a LOCOS oxide film 23 is provided on the surface of the substrate, and a gate oxide film 24 on an active region between the LOCOS oxide films is formed. Has been done. There is a source diffusion layer 35 made of high-concentration N-type impurities at a position separated from the LOCOS oxide film 23, and a gate electrode 25 is formed on the gate oxide film 24. The gate electrode 25 is the source diffusion layer 35. It is formed so as to extend from the end to a part of the LOCOS oxide film 23. An N-type offset diffusion layer 31 is formed under the LOCOS oxide film 23. The impurity concentration of the offset diffusion layer 31 is lower than the impurity concentration of the source diffusion layer 35 and the drain diffusion layer 34. A drain diffusion layer 34 is provided between the offset diffusion layers 31, and the LOCOS oxide film 23 adjacent to the offset diffusion layer 34 is partially hollowed out in a round shape having a shape peculiar to wet etching, and the LOCOS oxide film 23 is formed. The upper part of the drain diffusion layer 34, which is composed of a high concentration of N-type impurities, is higher than the end of the drain diffusion layer 34. The end 34 of the drain diffusion layer 34 is in contact with the 23 end of the LOCOS oxide film and the 31 end of the offset diffusion layer, but the impurity concentration at the end of the drain diffusion layer 34 is the impurity concentration in the center of the drain diffusion layer 34. The concentration is lower than the concentration. With the above structure, it is possible to alleviate the electric field concentration generated in the region below the drain diffusion layer, and it is possible to provide a semiconductor device including a MOS transistor that can be guaranteed even under a voltage of 50 V or more. It becomes.

In the above, the detailed description is given using the N-channel type MOS transistor, but it goes without saying that it can be applied to the P-channel type MOS transistor. As a method of operating a MOS transistor, when it is used in a situation where the source electrode and the drain electrode are interchanged, high withstand voltage must be guaranteed for both the source electrode and the drain electrode, but even in such a case, the source diffusion layer And by using the structure of the present invention for the drain diffusion layer, the withstand voltage can be guaranteed. Further, in this description, an example in which a MOS transistor is formed on a semiconductor substrate is given, but it can also be applied to a MOS transistor formed on a deep P-type diffusion layer, a so-called well diffusion layer. Furthermore, since the drain structure at the channel end is the same as that of the conventional LOCOS offset MOS transistor, the MOS transistor characteristics are not deteriorated as compared with the conventional structure.

<figref num="1">Schematic cross-sectional flow showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.</figref><figref num="2">Schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention.</figref><figref num="3">Schematic cross-sectional flow showing a method of manufacturing a semiconductor device according to a conventional embodiment.</figref>

Code description

11 P-type semiconductor substrate 21 Nitride film 22 Sacrificial oxide film 23 LOCOS oxide film 24 Gate oxide film 25 Gate electrode 31 Offset diffusion layer 34 Drain diffusion layer 35 Source diffusion layer