Semiconductor apparatus and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a high withstand voltage MOS transistor and a method for manufacturing the same.

High withstand voltage MOS transistors have high source / drain withstand voltage (BVDS) or high gate withstand voltage, and are widely used in various drivers such as LCD drivers and EL drivers, power supply circuits, and the like.

FIG. 6 is a cross-sectional view showing the structure of an N-channel type high withstand voltage MOS transistor according to a conventional example. A gate insulating film 101 and a thick field insulating film 102 are formed on the surface of the P-type semiconductor substrate 100. A gate electrode 103 is formed on a part of the adjacent field insulating film 102 from above the gate insulating film 101. In the surface region of the semiconductor substrate 100, a high-concentration (N ++ type) source layer 104 and a low-concentration source layer 105 are formed adjacent to one end of the gate electrode 103.

Further, a high-concentration (N ++ type) drain layer 106 is formed on the surface of the semiconductor substrate 100 separated from the other end of the gate electrode 103. Further, in the region extending from below the gate electrode 103 to below the field insulating film 102 and the high-concentration drain layer 106, the concentration is lower than that of the high-concentration drain layer 106, and the concentration is low (N-type) diffused deeply. Drain layer 107 is formed. The high-concentration drain layer 106 is formed in the low-concentration drain layer 107. As described above, the source region and the drain region have a so-called LDD (Lightly Doped Drain) structure composed of a high-concentration portion and a low-concentration portion. Further, a sidewall spacer film 108 such as a silicon nitride film is formed on the side wall of the gate electrode 103.

In the conventional high-voltage MOS transistor described above, when a high voltage is applied to the high-concentration drain layer 106, the depletion layer spreads in the low-concentration drain layer 107 to relax the drain electric field, resulting in a high source. Drain withstand voltage can be obtained. Further, since the gate electrode 103 extends from the gate insulating film 101 onto a part of the adjacent field insulating film 102, it has a structure resistant to the destruction of the gate insulating film 101.

The technology related to the present invention is described in the following patent documents.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2002-134738</text></patcit>

<p> However, the above-mentioned conventional transistor structure has a problem that the electrostatic discharge withstand capacity (hereinafter referred to as ESD withstand capacity) is not sufficient. For example, according to the general electrostatic discharge test based on the human body model (HBM) conducted by the present inventor, the ESD withstand capacity is less than 200 volts (V), and in the electrostatic discharge test based on the machine model (MM). The ESD withstand capacity was less than 50 volts (V), which was insufficient. Therefore, an object of the present invention is to provide a transistor structure having an improved ESD withstand capability.</p>

<p> The main features of the present invention are as follows. That is, in the semiconductor device of the present invention, the gate insulating film formed on the surface of the first conductive type semiconductor layer, the gate electrode formed on the gate insulating film, and the first formed on the surface of the semiconductor layer. The two conductive type source layer, the second conductive type high concentration drain layer formed on the surface of the semiconductor layer separated from the drain side end of the gate electrode, and the gate electrode and the high concentration The surface of the semiconductor layer between the semiconductor layer and the drain layer is provided with a first conductive type impurity layer adjacent to the high-concentration drain layer.</p><p> Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming a gate insulating film on the surface of the first conductive type semiconductor layer, a step of forming a gate electrode on the gate insulating film, and a step of forming the gate electrode from the gate electrode. A step of forming a second conductive type high-concentration drain layer on the separated surface of the semiconductor layer and a first conductive type impurity layer adjacent to the high-concentration drain layer on the surface of the semiconductor layer. It is characterized by having a step of forming.</p>

<p> In the present invention, on the surface of the semiconductor layer between the gate electrode and the high-concentration drain layer, a reverse conductive impurity layer is formed with the drain layer adjacent to the high-concentration drain layer. With this configuration, the electrons when an abnormal surge occurs move so as to avoid the vicinity where the impurity layer is formed, and wrap around to the drain electrode from a deeper position. That is, the movement of electrons near the surface of the semiconductor layer is suppressed. Therefore, the ESD withstand capacity can be improved.</p>

Next, the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. 1 to 4 are cross-sectional views showing the semiconductor devices according to the embodiment of the present invention in the order of manufacturing processes.

First, as shown in FIG. 1, an N-type impurity is injected into the surface of a P-type semiconductor substrate 1 and thermally diffused to form an N-type well layer 2 (NW). The ion implantation is, for example, phosphorus ion (³¹P⁺) Acceleration voltage 80KeV, injection amount 1.0 × 10¹³/cm²Perform under the conditions of. In the present invention, the formation of the N-type well layer 2 (NW) may be omitted.

Next, a P-type impurity is injected into the surface of the well layer 2 and thermally diffused to form a P-type well layer 3 (PW). The ion implantation is, for example, boron ion (¹¹B⁺) Acceleration voltage 80KeV, injection amount 2.3 × 10¹³/cm²Perform under the conditions of.

Next, by selectively injecting N-type impurities into the surface of the well layer 3, low-concentration (N-type) drain layers 4a and 4b are formed. The low-concentration drain layers 4a and 4b are separated from each other. That is, the ion implantation is performed using a predetermined mask so that the ion implantation is not performed between the drain layers 4a and 4b. This ion implantation is, for example, phosphorus ion (³¹P⁺) Acceleration voltage 100KeV, injection amount 1.5 × 10¹³/cm²Perform under the conditions of.

Next, as shown in FIG. 2, a thick field insulating film 5a, 5b, 5c is formed on a predetermined region of the well layer 3 by using the LOCOS (Local Oxidation Of Silicon) method. Of these, the field insulating films 5a and 5b are formed in regions that overlap with the low-concentration drain layers 4a and 4b, respectively. The field insulating film is generally formed for element separation, and the field insulating films 5a and 5b in this semiconductor device are used to improve the withstand voltage of the transistor. The film thickness of the field insulating films 5a, 5b, and 5c varies depending on the target withstand voltage, but is, for example, about 300 nm to 600 nm. The formation of the field insulating film is not limited to the LOCOS method, and other element separation methods including, for example, the STI (Shallow Trench Isolation) method may be used.

Next, for example, the gate insulating film 6 is formed by a thermal oxidation method. The film thickness of the gate insulating film 6 varies depending on the target withstand voltage, but is, for example, about 15 to 200 nm. The field insulating films 5a, 5b, and 5c are thicker than the gate insulating film 6.

Next, a polysilicon layer is formed as a conductive material on the entire surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method. Then, the polysilicon layer and the gate insulating film 6 are selectively removed to form the gate electrode 7. The gate electrode 7 is patterned so as to extend from the gate insulating film 6 onto a part of the adjacent field insulating film 5a. This improves the pressure resistance. Its film thickness is, for example, 300 nm. If necessary, impurities such as phosphorus ions are injected and diffused to reduce the resistance of the gate electrode 7.

Next, using the gate electrode 7 as a part of the mask, N-type impurities are injected into the surface region of the well layer 3 on the left side of the gate electrode 7 to form a low-concentration source layer 8 (LN). This ion implantation is, for example, phosphorus ion (³¹P⁺) Acceleration voltage 20KeV, injection volume 4.2 × 10¹³/cm²Perform under the conditions of. The low-concentration source layer 8 may be formed after the sidewall spacer films 9a and 9b, which will be described later, are formed.

Next, as shown in FIG. 3A, for example, a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by the CVD method, and then the silicon nitride film is etched back to surround the gate electrode 7. The surrounding sidewall spacer films 9a and 9b are formed. Instead of the silicon nitride film, a silicon oxide film made of, for example, a TEOS film or the like may be formed by a CVD method. When the sidewall spacer films 9a and 9b are made of a conductive material such as polysilicon, the entire gate electrode 7 and the sidewall spacer films 9a and 9b serve as gate electrodes.

Next, using the photoresist layer and field insulating films 5a and 5b (not shown) as masks, N-type impurities are injected into the surface region of the well layer 3 surrounded by the field insulating films 5a and 5b to inject N-type impurities into the low-concentration drain layer 4a, It forms a medium-concentration drain layer 10 (N) with an impurity concentration higher than 4b and with impurities injected deeply. The medium-concentration drain layer 10 is adjacent to the low-concentration drain layers 4a and 4b. This ion implantation is, for example, phosphorus ion (³¹P⁺) Acceleration voltage 1000KeV, injection amount 8.0 × 10¹³/cm²Perform under the conditions of. The medium-concentration drain layer 10 and the low-concentration drain layers 4a and 4b may be separated from each other or may be partially overlapped with each other.

Next, N-type impurities are injected using the photoresist layer and sidewall spacer film 9a (not shown) as masks to form a high-concentration source layer 11 (N +) in the region overlapping the low-concentration source layer 8. A high-concentration drain layer 12 (N +) is formed in a region that overlaps with the high-concentration drain layer 10. This ion implantation is, for example, arsenic ion (⁷⁵As⁺) Acceleration voltage 100KeV, injection amount 5.0 × 10¹³/cm²Perform under the conditions of. The high-concentration drain layer 12 is not formed on the entire surface of the medium-concentration drain layer 10, but is separated from the field insulating films 5a and 5b as shown in FIGS. It is formed in the vicinity of the region where the drain electrode 16 is formed. Note that FIG. 3B is a partial plan view showing the formation regions of the field insulating films 5a and 5b and the high-concentration drain layer 12 of FIG. 3A.

Next, a P-type impurity is injected into the medium-concentration drain layer 10 using a photoresist layer (not shown) as a mask to form a high-concentration P-type impurity layer 13. The P-type impurity layer 13 is a layer that contributes to improving the ESD resistance. This point will be described later. This ion implantation is, for example, boron difluoride (⁴⁹BF₂⁺) Ion acceleration voltage 40KeV, injection amount 2.0 × 10¹⁵/cm²Perform under the conditions of. As shown in FIG. 3B, the P-type impurity layer 13 of the present embodiment surrounds the high-concentration drain layer 12 in a ring shape and is adjacent to the high-concentration drain layer 12. From the viewpoint of improving the ESD resistance, it is considered preferable that the P-type impurity layer 13 is formed at least deeper than the high-concentration drain layer 12. From the viewpoint of improving the ESD resistance, as shown in FIGS. 3 (a) and 3 (b), it is preferable that the P-type impurity layer 13 is in contact with the high-concentration drain layer 12, but they should be separated from each other. You can also. Further, in the present embodiment, the P-type impurity layer 13 is adjacent to the field insulating films 5a and 5b. Next, annealing treatment is performed.

In addition, ion implantation for forming the high-concentration drain layer 12 is injected over the entire surface region of the medium-concentration drain layer 10, and then ion implantation for forming the P-type impurity layer 13 is partially performed in the region. By superimposing them, a high-concentration drain layer 12 and a P-type impurity layer 13 may be formed.

Next, as shown in FIG. 4, an interlayer insulating film 14 (for example, a BPSG film or a silicon nitride film by the CVD method) is formed on the entire surface of the semiconductor substrate 1. Next, contact holes leading to the high-concentration source layer 11 and the high-concentration drain layer 12 are formed, and the source electrode 15 and the drain electrode 16 are formed in each contact hole, respectively.

From the above manufacturing process, the semiconductor device 20 according to the present embodiment can be obtained. When an excessive positive surge voltage is generated in the drain electrode 16 of the semiconductor device 20 completed in this way, the parasitic NPN bipolar transistor 30 is turned on as shown in FIG. Current flows. In this parasitic bipolar operation, when the junction between the drain layer 4a and the well 3 breaks down and a current flows through the well layer 3, the voltage of the well layer 3 rises, and the well layer 3 to the source layer (8, 11). This is a phenomenon in which a base current flows to the side, which turns on the parasitic bipolar transistor 30.

During the parasitic bipolar operation, electrons move from the source electrode 15 side to the drain electrode 16 side. Here, in the conventional structure in which the P-type impurity layer 13 is not formed (see FIG. 6), it is considered that electrons flow intensively near the surface of the substrate and generate heat, which leads to destruction. On the other hand, in the configuration of this embodiment, the P-type impurity layer 13 is formed. Therefore, the electrons avoid X near the surface of the substrate on which the P-type impurity layer 13 is formed, and as shown by the arrow 25 in FIG. 4, the electrons flow in a dispersed manner and move from a deeper position to the drain electrode 16 side. It is thought that. In other words, it is considered that due to the action of the P-type impurity layer 13, electrons (= current) are dispersed and flow at a position deeper than the substrate surface, heat is not concentrated, and as a result, electrostatic breakdown is less likely to occur. Be done.

According to the electrostatic discharge test conducted by the present inventor, it was confirmed that the ESD withstand capacity was improved. Specifically, the ESD capacity of the human body model, which was less than 200 volts in the conventional structure (see Fig. 6), has been improved to about 3000 to 3500 volts, and the ESD capacity of the machine model, which was less than 50 volts in the conventional structure, is about 400. Improved to bolts. Further, when an electrostatic breakdown test was conducted on a semiconductor device having the same configuration as this embodiment except that the P-type impurity layer 13 was not formed, the ESD withstand capacity of the human body model was 2000 to 2250 volts, and the machine. The ESD capacity of the model was 200 to 220 volts. From these experiments, it is found that the structure of the present embodiment is a structure in which the ESD tolerance is dramatically improved as compared with the conventional structure, and that the P-type impurity layer 13 greatly contributes to the improvement of the ESD tolerance. understood.

Needless to say, the present invention is not limited to the above embodiment, and the design can be changed without departing from the gist thereof. For example, in the above configuration, the low-concentration drain layers 4a and 4b shown in the cross-sectional view have separated portions, but the low-concentration drain region may be seamlessly formed without separating them. It is also conceivable to further improve the ESD resistance by arranging another P-type impurity layer under the field insulating film 5a. Further, in the present embodiment, the field insulating film 5a is formed under a part of the gate electrode 7, but as shown in FIG. 5A, the design can be changed to a structure in which the field insulating film 5a is not formed. ..

Further, as shown in FIG. 5 (b), the source-side end of the medium-concentration drain layer 10 is configured to be located below the gate electrode 7 or the sidewall spacer membrane 9b, and the low-concentration drain layer 4a It is also possible to change the design to a structure that does not form.

Of course, it is also possible to change the order and conditions of the manufacturing process. For example, in the above, the drain layer 10 having a medium concentration is formed after the formation of the sidewall spacer films 9a and 9b, but it can be formed before this. Specifically, after the field insulating films 5a to 5c are formed, ions are implanted to form the medium-concentration drain layer 10 using a predetermined mask, and then the injected ions are thermally diffused to obtain a medium-concentration. The drain layer 10 may be formed. Then, the gate insulating film 6 and the gate electrode 7 can be formed thereafter. From the viewpoint of deeply forming the medium-concentration drain layer 10 by heat diffusion, the ion implantation related to the formation of the medium-concentration drain layer 10 in this case is a condition that is not highly accelerated by increasing the injection amount. Can be done with. The injection conditions at this time are, for example, arsenic ions (⁷⁵As⁺), Acceleration voltage 90 ~ 150KeV, injection amount 1.0 × 10¹⁵~6.0×10¹⁵/cm²And also Phosphorus (³¹P⁺), Acceleration voltage 40 ~ 80KeV, injection amount 1.0 × 10¹⁵~6.0×10¹⁵/cm²It is a condition of.

Further, although the description of the P-channel type MOS transistor is omitted, it is well known that the structure is the same except for the conductive type.

<figref num="1">It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and the manufacturing method thereof.</figref><figref num="2">It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and the manufacturing method thereof.</figref><figref num="3">It is sectional drawing and plan view explaining the semiconductor device which concerns on embodiment of this invention, and the manufacturing method thereof.</figref><figref num="4">It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and the manufacturing method thereof.</figref><figref num="5">It is sectional drawing explaining the modification example of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="6">It is sectional drawing explaining the conventional semiconductor device.</figref>

Code description

1 Semiconductor substrate 2 Well layer 3 Well layer 4a, 4b Low concentration drain layer 5a, 5b, 5c Field insulating film 6 Gate insulating film 7 Gate electrode 8 Low concentration source layer 9a, 9b sidewall spacer film 10 Medium concentration drain Layer 11 High-concentration source layer 12 High-concentration drain layer 13 P-type impurity layer 14 Interlayer insulating film 15 Source electrode 16 Drain electrode 20 Semiconductor device 25 Electron flow 30 Parasitic bipolar transistor 100 Semiconductor substrate 101 Gate insulating film 102 Field insulating film 103 Gate electrode 104 Source layer 105 Low-concentration source layer 106 High-concentration drain layer 107 Low-concentration drain layer 108 sidewall spacer film