Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

In recent years, attempts have been made to apply high withstand voltage MOS transistors to in-vehicle applications. In such applications, in order to realize low power consumption, not only low on-resistance while maintaining high off-voltage withstand voltage of 100V class is required, but also high resistance to ESD surge is required at the same time.

FIG. 8 shows the structure of a conventional VDMOS (Vertical Double-diffused MOS), which is a high withstand voltage MOS transistor. The semiconductor device 200 (VDMOS) is a p-type semiconductor substrate 204, n.⁺Impurity embedded layer 206, n⁺Sinker 208, n^-N formed in the drift region 210, the element separation insulating film 212, the p body region 214 and the p well region 218 formed in the drift region 210, and the p body region 214.⁺N formed in source region 216, sinker 208⁺It includes a drain lead region 220, a gate insulating film 224, and a gate electrode 222.

The drift region 210 is configured to have a low impurity concentration in order to secure a high withstand voltage of the semiconductor device 200. On the other hand, the impurity embedding layer 206, the sinker 208, and the drain extraction region 220 are configured to have a higher impurity concentration than the drift region 210 in order to reduce the on-resistance. The sinker 208 and the drain drawer area 220 function as a drain area. In such a configuration, as indicated by the arrows in the figure, the current between the source region 216 and the drain extraction region 220 flows through the impurity embedding layer 206 and the sinker 208.

The characteristics of a transistor having such a configuration are generally represented by withstand voltage and on-resistance. It is said that the higher the withstand voltage and the lower the on-resistance, the better the characteristics. However, there is a trade-off relationship between the two, and there is usually a problem that if one characteristic is increased, the other characteristic is deteriorated.

Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-303964) describes a technique for reducing the on-resistance and maintaining the withstand voltage. As shown in FIG. 9, in Patent Document 1, first and second epitaxial layers (23 and 24) are formed on the surface of the substrate 22, and the concentration between the substrate 22 and the first epitaxial layer 23 is increased. A configuration is described in which a second embedded layer 33 having a density lower than that of the first embedded layer 31 is formed between the dense first embedded layer 31, the first epitaxial layer 23, and the second epitaxial layer 24, respectively. ing.

In Patent Document 2 (Japanese Unexamined Patent Publication No. 2003-347546), as shown in FIG. 10, the main body region 126 (corresponding to the body region 214 in FIG. 8) is surrounded, and the bending of the main body region at the outermost angle where the electric field is concentrated. The configuration in which the well 110 formed so as not to include the portion 160 is described. As a result, we are trying to reduce the on-resistance while maintaining the withstand voltage.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-303964</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2003-347546</text></patcit>

<p> By the way, as shown in FIG. 8, local concentration of the electric field is likely to occur at the inner end of the element separation insulating film 212 (gate side bird's beak portion: A surrounded by a broken line in the figure) which is a gate-drain separation oxide film. Therefore, breakdown is likely to occur at this point. When breakdown occurs on the substrate surface in this way, there are problems that ESD resistance is lowered and hot carrier characteristics are lowered.</p><p> In the configuration described in Patent Document 1, as shown in FIG. 9, since the second embedded layer 33 extends to just below the LOCOS edge portion, the electric field is still likely to concentrate in this portion, and the substrate The problem of prone surface breakdown has not been resolved. As a result, there is a problem that resistance to ESD surge cannot be ensured. Further, as shown in FIG. 9, the second embedded layer 33 having a higher impurity concentration than the second epitaxial layer 24 is in contact with the diffusion regions 36, 37, and 38 (corresponding to the body region 214 in FIG. 8). Therefore, if the impurity concentration of the second embedded layer 33 is increased in order to reduce the on-resistance, the withstand voltage is also lowered, and the on-resistance cannot be significantly reduced.</p><p> Even in the configuration described in Patent Document 2, as shown in FIG. 10, the well 110 having a higher impurity concentration than the drift region 106 is in contact with the main body region (corresponding to the body region 214 in FIG. 8). Therefore, if the impurity concentration of the well 110 is increased in order to reduce the on-resistance, the withstand voltage is also lowered, and the on-resistance cannot be significantly reduced. Further, as shown in FIG. 10, the well 110 and the buried layer 104 are not connected and formed, and the drift region 106 is interposed between them. Therefore, there is also a problem that the effect of reducing the on-resistance is low. With such a configuration, it is difficult to secure the withstand voltage of 100V class required for in-vehicle use, for example.</p>

<p> According to the present invention A second conductive type drift region, a plurality of first conductive type body regions formed in the drift region, each including a second conductive type source region, and an outer periphery of the drift region are surrounded by the drift region. A second conductive type drain drawing region having a high impurity concentration is provided so as to surround the semiconductor layer formed on the surface and the outer periphery of the drift region on the semiconductor layer, and the drift region and the drain drawing region are provided. It is a method of manufacturing a semiconductor device including a VDMOS transistor composed of a separation insulating film that separates the two. A first impurity injection step of preparing a semiconductor substrate and injecting a first impurity of a second conductive type into a first region which is the entire region where the drift region and the drain extraction region of the semiconductor substrate are formed. , A second conductive type impurity is formed in a second region narrower than the first region, which is an internal region separated by a predetermined width in the inner direction from the inner end of the separation insulating film of the semiconductor substrate. A second impurity injection step of injecting a second impurity having a faster diffusion rate than the first impurity, An epitaxial layer is formed on the semiconductor substrate to form the semiconductor substrate and the semiconductor layer composed of the epitaxial layer, and at the same time, injection is performed in the first impurity injection step and the second impurity injection step. A second conductive type embedded layer having a higher impurity concentration than the drift region in the semiconductor layer by diffusing the first and second impurities is provided between the embedded layer and the body region. The step of forming the drift region so as to intervene in the Provided is a method for manufacturing a semiconductor device in which the second conductive type embedded layer forms a drain region.</p><p> According to the present invention With the semiconductor layer The second conductive type drift region formed on the surface of the semiconductor layer and A plurality of first conductive body regions formed in the drift region, each including a second conductive source region, On the surface of the semiconductor layer, a second conductive type drain extraction region that surrounds the outer periphery of the drift region and has a higher impurity concentration than the drift region, A separating insulating film provided on the semiconductor layer so as to surround the outer periphery of the drift region and separating the drift region and the drain extraction region. On the semiconductor layer, a gate electrode formed on the body region and opened on the source region, and In the semiconductor layer, a second conductive type embedded layer having a higher impurity concentration than the drift region, which is formed on the entire surface below the drift region and the drain extraction region and constitutes the drain region, Includes a VDMOS transistor composed of The embedded layer is selectively arranged in a first embedded region formed on the entire lower surface of the drift region and the drain extraction region, and a region further inwardly separated from the inner end of the separation insulating film by a predetermined width. A second embedded region formed continuously with the first embedded region is included on the first embedded region, and the drift region is interposed between the first embedded region and the body region over the entire surface. The semiconductor device formed in the above is provided.</p><p> According to the method for manufacturing a semiconductor device, a semiconductor device including an embedded layer including a first embedded region and a second embedded region can be obtained as described above. According to the semiconductor device of the present invention, the second embedded region is not provided directly under the element separation insulating film which is the gate-drain extraction separating oxide film in which the electric field is easily concentrated, and the embedded layer is provided in this region. Is provided only at a position deep from the surface of the semiconductor layer. By providing an embedded region having a higher impurity concentration than the drift region, the withstand voltage is lowered at that location. By selectively providing an embedded layer in the inner region from a position shallow from the surface of the semiconductor layer as in the configuration of the present invention, the withstand voltage of this portion is made lower than the withstand voltage of the region directly below the element separation insulating film. Can be done. This makes it possible to prevent the concentration of the electric field directly under the element separation insulating film. Therefore, it is possible to prevent breakdown from occurring on the surface of the semiconductor layer, and as will be described later, it is possible to cause breakdown in a wide range at a position considerably deep from the surface of the semiconductor layer, so that ESD resistance and hot carriers can be prevented. The characteristics can be improved.</p><p> Further, since the embedded layer in the inner region, which is the main current path, is formed from a shallow position, the on-resistance can be effectively reduced. Further, since a drift region having a low impurity concentration is interposed between the body region and the embedded region, high off resistance can be maintained. As a result, while maintaining a high withstand voltage of 100V class, the on-resistance can be lowered and at the same time, high resistance to ESD surge can be ensured.</p><p> It should be noted that the technique described in Cited Document 1 has a problem that the manufacturing cost is high because the epitaxial growth is performed a plurality of times in order to form the second embedded layer 33. However, according to the method for manufacturing a semiconductor device of the present invention, since the embedded layer is formed by using impurities having different diffusion rates, it is not necessary to perform epitaxial growth a plurality of times, the manufacturing procedure can be simplified, and the cost can be suppressed. Can be done. The order of the first impurity injection step and the second impurity injection step is not particularly limited, and any of them may be performed first.</p><p> According to the present invention, there is an embedded layer composed of two embedded regions formed by impurities of the same type having different diffusion rates, and the embedded region formed by impurities having a slow diffusion rate is a transistor forming region. A semiconductor device is provided in which the embedded region formed by impurities having a high diffusion rate is provided inside the gate-drain extraction separation oxide film region, which is a region where the electric field is locally concentrated. In this way, by using impurities with a high diffusion rate to form an embedded region only inside at a shallow position from the surface of the semiconductor layer, avoiding the peripheral part where local concentration of the electric field occurs, the oxide film separated between the gate and drain drawers is formed. It is possible to suppress the local concentration of the electric field in the region and cause breakdown in the embedded region inside, and it is possible to form a MOS transistor with low on-resistance and resistance to ESD surge while maintaining high withstand voltage. ..</p>

<p> According to the present invention, the on-resistance can be lowered while maintaining a high off-voltage withstand voltage, and at the same time, the resistance to ESD surge can be increased.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all drawings, similar components are designated by the same reference numerals, and description thereof will be omitted as appropriate.

In the present embodiment, the semiconductor device is a VDMOS (Vertical Double-diffused MOS) which is a high withstand voltage MOS transistor. In the following embodiment, a case where the first conductive type is the P type and the second conductive type is the N type will be described as an example.

1 and 2 are diagrams showing a configuration of a semiconductor device according to the present embodiment. FIG. 2 is a top view of the semiconductor device 300 (VDMOS transistor), and FIG. 1 is a cross-sectional view taken along the line A-A'of FIG.

The semiconductor device 300 includes a semiconductor layer 307 composed of a first conductive type (p) semiconductor substrate 304 and a second conductive type (n-) epitaxial layer 305 formed on the semiconductor substrate 304. The semiconductor device 300 is further formed on the surface of the semiconductor layer 307, and has a plurality of first conductive type (p) body regions 314 (body regions) including a second conductive type (n +) source region 316 and a semiconductor layer. On the surface of the semiconductor layer 307, the second conductive type (n-) drift region 310 (drift region) formed around the plurality of body regions 314 and the outer periphery of the drift region 310 on the surface of the semiconductor layer 307 are surrounded by the drift region 310. The second conductive type (n +) sinker (second conductive type drain extraction region) 308 and drain extraction region 320 (second conductive type drain extraction region) with high impurity concentration, and the drift region 310 on the semiconductor layer 307. The element separation insulating film 312 (separation insulating film), which is provided so as to surround the outer periphery of the surface and separates the drift region 310 and the drain extraction region 320, is included.

The semiconductor device 300 is further provided in the well region 318 of the second conductive type (p) provided below the inner end of the element separation insulating film 312 on the surface of the semiconductor layer 307 and in the body region 314 to provide the source region 316. First conductive type to separate (p⁺), And a gate electrode 322 formed on the element separation insulating film 312 and partially formed on the body region 314 via the gate insulating film 324 and opened on the source region 316. Including. In the present embodiment, the source area 316 and the body area 314 are connected and provided. By short-circuiting the source region 316 and the body region 314 in this way, the operation of the parasitic bipolar can be prevented.

The semiconductor device 300 further includes a second conductive type (n +) impurity-embedded layer 306 formed between the semiconductor substrate 304 and the epitaxial layer 305 and having a higher impurity concentration than the drift region 310. The impurity embedding layer 306 includes a first impurity embedding region 330 and a second impurity embedding region 332. The impurity-embedded layer 306 constitutes a drain region. The first impurity embedding region 330 is formed on the entire lower surface of the drift region 310 and the sinker 308, and is provided in connection with the sinker 308. The second impurity embedding region 332 is formed by embedding the first impurity above and below the first impurity embedding region 330 in an internal region separated by a predetermined width D1 in the inner direction from the inner end of the element separation insulating film 312. It is formed continuously with the region 330. Here, the impurity-embedded layer 306 is formed so that the drift region 310 is interposed between the impurity-embedded layer 306 and the body region 314 without being in contact with the body region 314 over the entire surface.

In the present embodiment, the second impurity-embedded region 332 is configured to have a higher impurity concentration than the drift region 310 and a lower impurity concentration than the first impurity-embedded region 330. By lowering the impurity concentration of the second impurity-embedded region 332 near the P-type body region 314 to that of the first impurity-embedded region 330, it is possible to suppress a decrease in withstand voltage. In the present embodiment, by lowering the withstand voltage of the region where the second impurity-embedded region 332 is formed from the region below the inner end of the device-separating insulating film 312, breakdown occurs in the vicinity of the device-separating insulating film 312. I try to suppress. It is preferable that the impurity concentration of the second impurity embedding region 332 is appropriately set so as to achieve such an object and to maintain the withstand voltage of the semiconductor device 300 at a desired value.

The first impurity embedding region 330 and the second impurity embedding region 332 each contain a first impurity and a second impurity different from the first impurity as the main components of the second conductive type impurity. Can be done. The second impurity can be made to have a higher diffusion rate than the first impurity. The diffusion rate of N-type impurities Sb (antimony), As (arsenic), and P (phosphorus) is P&gt; As&gt; Sb. The combination of the first impurity and the second impurity can be either As and P, Sb and P, or Sb and As in this order.

The drift region 310 is configured to have a low impurity concentration in order to secure a high withstand voltage of the semiconductor device 300. On the other hand, the impurity embedding layer 306, the sinker 308, and the drain extraction region 320 are configured to have a higher impurity concentration than the drift region 310 in order to reduce the on-resistance. In the figure, as indicated by the arrows, the current between the source region 316 and the drain extraction region 320 flows through the impurity embedding layer 306 and the sinker 308. In the present embodiment, since the impurity-embedded layer 306 includes the second impurity-embedded region 332, the on-resistance can be further reduced. In FIG. 1, four gate electrodes 322, three sources 316, and two drain extraction regions 320 are drawn. The above four gate electrodes 322 and the above three sources 316 are shown. , The above two drain extraction areas 320 are connected in common, and the whole functions as one transistor.

Next, the manufacturing procedure of the semiconductor device 300 according to the present embodiment will be described. 3 to 5 are process cross-sectional views showing a manufacturing procedure of the semiconductor device 300 according to the present embodiment. In the following, the case where the first impurity is As and the second impurity is P will be described as an example.

First, a first protective film 340 having a first region opened is formed on a P-type semiconductor substrate 304, and As is injected into the semiconductor substrate 304 using the first protective film 340 as a mask to form a first protective film 340. An impurity injection region 330a is formed (Fig. 3 (a)). The first region can be the entire region where the drift region 310 and the sinker 308 are formed. Here, the injection conditions for As are, for example, 50 to 100 keV, 5 × 10.^-13~5×10^-15(5e13 ~ 5e15) cm^-2Can be. The first protective film 340 can be, for example, a silicon oxide film.

Subsequently, a second protective film 342 having an opening of a second region narrower than the first region is formed on the semiconductor substrate 304, and the second protective film 342 is used as a mask to form As on the semiconductor substrate 304. A second impurity injection region 332a is formed by injecting P, which has a faster diffusion rate (Fig. 3 (b)). The second region has a predetermined width D in the direction further inward from the inner end of the element separation insulating film 312 formed later.₂(D₂&gt; D₁) Can be separated internal areas. Predetermined width D₂Is the predetermined width D shown in FIG. 1 when impurities are later diffused in the lateral direction.₁Can be determined to be about several μm. Here, the injection conditions for P are, for example, 50 to 100 keV, 5 × 10.¹³~5×10¹⁵(5e13 ~ 5e15) cm^-2Can be. After this, the second protective film 342 is removed.

The second protective film 342 can be, for example, a silicon oxide film. In this case, after injecting As in the step shown in FIG. 3A, the first protective film 340 is removed, a silicon oxide film is formed again on the semiconductor substrate 304, and the second protective film is patterned. Protective film 342 can be formed. Further, after injecting As, a resist film may be formed on the first protective film 340, and the second protective film 342 may be formed by patterning the resist film. Further, in the above, the process of injecting P is performed after the step of injecting As, but this step may be reversed. That is, after forming a second protective film 342 composed of, for example, a silicon oxide film on the semiconductor substrate 304 and injecting P, a resist film having a predetermined pattern is formed on the second protective film 342, and the resist film is formed. The first protective film 340 may be formed by selectively removing the second protective film 342 using the resist film as a mask.

Subsequently, heat of about 1100 ° C. is applied to form an N-type epitaxial layer 305 (for example, a film thickness of 5 to 10 μm) on the semiconductor substrate 304. Here, the concentration of N-type impurity ions in the epitaxial layer 305 is, for example, 1 × 10.¹⁵~1×10¹⁶(1e15 ~ 1e16) cm^-2Can be. As a result, the semiconductor layer 307 is formed (Fig. 4 (a)).

Due to the heat applied at this time, As in the first impurity injection region 330a and P in the second impurity injection region 332a are diffused at the same time as the growth of the epitaxial layer 305. Here, since P has a faster diffusion rate than As, the second impurity embedding region 332 in which P is the main component of the impurity is the first impurity in which As is the main component of the impurity. The width is formed wider in the stacking direction than the embedding region 330. That is, the second impurity embedding region 332 is formed above and below the first impurity embedding region 330.

Next, the device separation insulating film 312 (LOCOS) is selectively formed on the surface of the semiconductor layer 307. Then, using a mask with a predetermined pattern, N-type impurities are injected to form sinker 308 (Fig. 4 (b)). The sinker 308 can be formed by injecting P, and the injection conditions of P can be the same as those at the time of forming the second impurity injection region 332a described above. After that, a heat treatment exceeding 1000 ° C. is performed for about 1 to 3 hours to diffuse impurities and connect the sinker 308 and the first impurity embedding region 330. By the above treatment, the shape of the impurity embedded layer 306 is almost determined.

Subsequently, a P-type impurity is injected into the surface of the semiconductor layer 307 using a mask having a predetermined pattern to form a body region 314 and a well region 318 (FIG. 5 (a)). As described above, the local concentration of the electric field tends to occur in the vicinity of the bird's beak on the inner end side of the element separation insulating film 312. By forming the well region 318 at the inner end of the element separation insulating film 312, the electric field can be relaxed in this portion.

Then, using a mask of a predetermined pattern, a source region 316 and a separation region 317 are formed in the body region 314, respectively. Then, after forming the gate insulating film 324 on the semiconductor layer 307, a conductive film to be a gate electrode is formed and patterned into a predetermined shape to form the gate electrode 322 (FIG. 5 (b)). As a result, the semiconductor device 300 having the same configuration as that shown in FIG. 1 can be obtained.

In the present embodiment, as shown in FIG. 1, a first deep position is located directly below the inner end (gate-side bird's beak portion) of the element separation insulating film 312, which is a gate-drain separation oxide film in which local concentration of electric fields occurs. Only the impurity embedding region 330 is present. On the other hand, in the inner region, in addition to the first impurity embedding region 330, a second impurity embedding region 332 is formed at a shallow position on the first impurity embedding region 330. Therefore, the withstand voltage of the inner region can be relatively lowered as compared with the portion directly below the inner end of the element separation insulating film 312, and the local concentration of the electric field directly below the inner end of the element separation insulating film 312 can be suppressed. Therefore, the breakdown can be caused between the body region 314 and the second impurity embedding region 332, that is, considerably deep from the surface of the semiconductor layer 307, and high resistance to ESD surge can be ensured.

Further, since the drift region 310 having a low impurity concentration of the second conductive type is interposed between the second impurity embedding region 332 and the body region 314, high off resistance can be maintained. Further, in the inner region serving as the main current path, in addition to the first impurity embedding region 330, a second impurity embedding region 332 is formed at a shallow position on the first impurity embedding region 330. Therefore, the effect of reducing the on-resistance can be enhanced. Therefore, the on-resistance can be lowered while maintaining a high off-voltage withstand voltage, and at the same time, the resistance to ESD surge can be improved.

According to the manufacturing procedure of the semiconductor device 300 in the present embodiment, the first impurity embedding region 330 and the second impurity embedding region 332 are formed by utilizing the difference in the diffusion velocities of impurities having different diffusion velocities. Therefore, the impurity-embedded layer 306 can be formed by one epitaxial growth, the manufacturing procedure can be simplified, and the cost can be suppressed.

FIG. 6 is a diagram showing a potential distribution state in the semiconductor device 300 according to the present embodiment shown in FIG. 1 and the conventional VDMOS transistor 200 shown in FIG. Here, the distribution of impurity ions, the impact ionization generation rate distribution at the time of breakdown, and the potential distribution are shown. FIG. 7 is a diagram showing in detail the impact ionization generation rate distribution shown in FIG. FIG. 7 (a) shows the configuration of the semiconductor device 300, and FIG. 7 (b) shows the configuration of the VDMOS transistor 200.

As can be seen from the distribution diagram of impurity ions, in the semiconductor device 300, the depth of the drift region 310 is formed deeper than the central portion in the region directly below the element separation insulating film 312. Further, from the impact ionization generation rate distribution diagram, in the VDMOS transistor 200 shown on the right side, impact ionization occurs at the inner end portion of the element separation insulating film 212 on the gate side, and breakdown occurs at that portion. I understand. On the other hand, in the semiconductor device 300 shown on the left side, impact ionization occurs in the second impurity-embedded region 332 of the impurity-embedded layer 306, and breakdown occurs at that portion. Further, from the potential distribution, it can be seen that in the semiconductor device 300 shown on the left side, the potential is dense in the inner region and the electric field concentration portion is moved to the inner portion. Here, it is assumed that the concentrations of the drift region 310 of the semiconductor device 300 and the drift region 210 of the VDMOS transistor 200 are equal. Therefore, it was shown that the semiconductor device 300 in which the second impurity embedding region 332 is formed has a slightly lower withstand voltage than the VDMOS transistor 200, but the semiconductor device 300 can also maintain the resistance of the 100V class.

The present invention has been described above based on the embodiments. Embodiments are examples, and it will be understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. ..

In the above example, an example of forming an N-type epitaxial layer 305 on the semiconductor substrate 304 has been shown. However, as another example, the drift region 310 can be formed by forming a P-type epitaxial layer on the semiconductor substrate 304 and then ion-implanting N-type impurity ions.<u style="single"> Hereinafter, an example of the reference form will be added.</u><u style="single">1. A second conductive type drift region, a plurality of first conductive type body regions formed in the drift region, each including a second conductive type source region, and the outer periphery of the drift region are surrounded by the drift. A second conductive type drain extraction region having a higher impurity concentration than the region is provided so as to surround the semiconductor layer formed on the surface and the outer periphery of the drift region on the semiconductor layer, and the drift region and the drain are provided. A method for manufacturing a semiconductor device including a VDMOS transistor composed of a separation insulating film that separates the extraction region.</u><u style="single"> A first impurity injection step of preparing a semiconductor substrate and injecting a first impurity of a second conductive type into a first region which is the entire region where the drift region and the drain extraction region of the semiconductor substrate are formed. ,</u><u style="single"> A second conductive type impurity is formed in a second region narrower than the first region, which is an internal region separated by a predetermined width in the inner direction from the inner end of the separation insulating film of the semiconductor substrate. A second impurity injection step of injecting a second impurity having a faster diffusion rate than the first impurity,</u><u style="single"> An epitaxial layer is formed on the semiconductor substrate to form the semiconductor substrate and the semiconductor layer composed of the epitaxial layer, and at the same time, injection is performed in the first impurity injection step and the second impurity injection step. A second conductive type embedded layer having a higher impurity concentration than the drift region in the semiconductor layer by diffusing the first and second impurities is provided between the embedded layer and the body region. The step of forming the drift region so as to intervene in the</u><u style="single">A method for manufacturing a semiconductor device including the above, wherein the second conductive type embedded layer forms a drain region.</u><u style="single">In the method for manufacturing a semiconductor device described in 2.1.</u><u style="single"> The combination of the first impurity and the second impurity is, in this order, a method for manufacturing a semiconductor device, which is either As and P, Sb and P, or Sb and As.</u><u style="single">3. Semiconductor layer and</u><u style="single"> The second conductive type drift region formed on the surface of the semiconductor layer and</u><u style="single"> A plurality of first conductive body regions formed in the drift region, each including a second conductive source region,</u><u style="single"> On the surface of the semiconductor layer, a second conductive type drain extraction region that surrounds the outer periphery of the drift region and has a higher impurity concentration than the drift region,</u><u style="single"> A separating insulating film provided on the semiconductor layer so as to surround the outer periphery of the drift region and separating the drift region and the drain extraction region.</u><u style="single"> On the semiconductor layer, a gate electrode formed on the body region and opened on the source region, and</u><u style="single"> In the semiconductor layer, a second conductive type embedded layer having a higher impurity concentration than the drift region, which is formed on the entire surface below the drift region and the drain extraction region and constitutes the drain region,</u><u style="single">Includes a VDMOS transistor composed of</u><u style="single"> The embedded layer is selectively arranged in a first embedded region formed on the entire lower surface of the drift region and the drain extraction region, and a region further inwardly separated from the inner end of the separation insulating film by a predetermined width. A second embedded region formed continuously with the first embedded region is included on the first embedded region, and the drift region is interposed between the first embedded region and the body region over the entire surface. A semiconductor device formed in.</u><u style="single">In the semiconductor device described in 4.3.</u><u style="single"> The first embedding region and the second embedding region contain a first impurity and a second impurity different from the first impurity as main components of the second conductive type impurity, respectively, and the second one. Impurities are semiconductor devices with a faster diffusion rate than the first impurities.</u><u style="single">In the semiconductor device described in 5.3.</u><u style="single"> The first embedded region and the second embedded region each contain a first impurity and a second impurity different from the first impurity as the main components of the second conductive type impurity, and the first The combination of the impurities of the above and the second impurity is a semiconductor device which is either As and P, Sb and P, or Sb and As in this order.</u>

<figref num="1">It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention.</figref><figref num="2">It is a top view which shows the structure of the semiconductor device in embodiment of this invention.</figref><figref num="3">It is a process sectional view which shows the manufacturing procedure of the semiconductor device in embodiment of this invention.</figref><figref num="4">It is a process sectional view which shows the manufacturing procedure of the semiconductor device in embodiment of this invention.</figref><figref num="5">It is a process sectional view which shows the manufacturing procedure of the semiconductor device in embodiment of this invention.</figref><figref num="6">It is a figure which shows the potential distribution state in the semiconductor device in this embodiment shown in FIG. 1 and the conventional semiconductor device shown in FIG.</figref><figref num="7">It is a figure which shows the impact ionization occurrence rate distribution shown in FIG. 6 in detail.</figref><figref num="8">It is sectional drawing which shows the structure of the conventional semiconductor device.</figref><figref num="9">It is sectional drawing which shows the structure of the conventional semiconductor device.</figref><figref num="10">It is sectional drawing which shows the structure of the conventional semiconductor device.</figref>

Code description

102 board 104 buried layer 106 drift area 108 sink layer 110 We Le 116 Field oxide film 118 Gate insulating film 120 gate electrode 122 opening 126 Body area 126a outer body area 126b Internal body area 130 Source area 132 Drain area 136 Bulk area 145 channel area 147 Excess area 160 Bent part 200 semiconductor device 204 Semiconductor substrate 206 Impurity embedded layer 208 sinker 210 drift area 212 element separation insulating film 214 body area 216 Source area 218 well area 220 Drain drawer area 222 Gate electrode 224 Gate insulating film 300 semiconductor device 304 Semiconductor substrate 305 epitaxial layer 306 Impurity embedded layer 307 Semiconductor layer 308 sinker 310 drift area 312 Element separation insulating film 314 body area 316 Source area 317 Separation area 318 well area 320 drain drawer area 322 Gate electrode 324 Gate insulating film 330a First impurity injection area 330 First impurity embedding area 332a Second impurity injection area 332 Second impurity embedding area 340 First protective film 342 Second protective film