Photoelectric conversion device manufacturing method, semiconductor device manufacturing method, photoelectric conversion device, and image sensing system

0001The present invention relates to a method for manufacturing a photoelectric conversion device, a method for manufacturing a semiconductor device, a photoelectric conversion device, and an imaging system.

0002In recent years, photoelectric conversion devices have been used in two-dimensional image input devices centered on digital still cameras and video camcorders, or in one-dimensional image readers centered on facsimiles and scanners, and their demand is rapidly increasing. ..

0003As the photoelectric conversion device, for example, a CCD (Charge Coupled Device) or a MOS type sensor is used. As a representative of MOS type sensors, CMOS sensors have been put into practical use.

0004The CMOS sensor includes a pixel array and a control unit.

0005In the pixel arrangement, a plurality of pixels are arranged in the row direction and the column direction. Each pixel has the circuit configuration shown in FIG. FIG. 11 is a circuit configuration diagram of pixels in a conventional CMOS sensor.

0006In FIG. 11, 1001 is a photodiode (hereinafter referred to as PD) that converts light into a signal (charge) and stores it. The 1002 is a transfer MOS transistor that transfers the signal (charge) stored in the PD1001. 1003 is a floating diffusion (hereinafter referred to as "FD"). Reference numeral 1004 is a reset MOS transistor in which a reset signal for resetting the FD1003 and PD1001 is supplied to the gate. Reference numeral 1005 is a selection MOS transistor in which a selection signal for selecting an arbitrary line of the pixel array is supplied to the gate by the control unit. The 1006 is an amplified MOS transistor that amplifies the signal input from the FD1003 and outputs it to the column signal line 1007 by performing a source follower operation together with the low current source 1008.

0007The control unit controls each of the plurality of pixels in the pixel array. Although not shown, the control unit includes at least one of a circuit for processing a signal from a pixel and a drive circuit (shift register) for driving a transistor in the pixel. The control unit is formed as a peripheral circuit on the same substrate as the pixel array.

0008In order to realize the circuit configuration shown in FIG. 11, in the technique disclosed in Patent Document 1, each pixel is formed so as to have the cross-sectional structure shown in FIG. FIG. 12 is a cross-sectional configuration diagram of pixels in a conventional CMOS sensor.

0009As shown in FIG. 12, PD1001 includes a charge storage layer 1001a and a protective layer 1001b. The charge storage layer 1001a is an N-type semiconductor region for storing signals (charges, electrons) generated in response to light 1109 incident on PD1001. The protective layer 1001b is a P + type semiconductor region for protecting the charge storage layer 1001a. Here, "P + type" indicates that the concentration of P-type impurities is higher than that in the "P-type" region.

0010The element separation unit 1102 is formed of an insulating film and electrically separates the charge storage layers 1001a of the plurality of PD1001s. A channel stop region 1106, which is a P + type semiconductor region, is formed under the element separation unit 1102. Further, a well region 1107, which is a P-type semiconductor region, is formed around the channel stop region 1106 and the charge storage layer 1001a. Here, "P-type" indicates that the concentration of P-type impurities is lower than that in the "P-type" region.

0011According to Patent Document 1, such a structure can prevent electric charge from leaking to adjacent pixels at a high level.

0012In FIG. 12, the gates 1002a and FD1003 of the transfer MOS transistor 1002 are also shown.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2006-310650</text></patcit>

<p num="0013"> In recent years, in a photoelectric conversion device, it is required to increase the number of pixels in a predetermined chip area, so that the area occupied by a unit pixel is required to be reduced.</p><p num="0014"> When the pixel having the cross-sectional structure shown in FIG. 12 is miniaturized, the distance between adjacent PDs (photoelectric conversion units) 1001 may also be reduced.</p><p num="0015"> In this case, the signal accumulated by the charge storage layer 1001a of PD1001 may leak to the charge storage layer 1001a of the adjacent PD1001 via the well region 1107. Since the well region 1107 is a P-type semiconductor region, a sufficient potential barrier cannot be formed for the adjacent charge storage layer 1001a. This can reduce the sensitivity of the PD1001.</p><p num="0016"> Further, the charge storage layer 1001a of the PD 1001 is capacitively coupled to the charge storage layer 1001a of the adjacent pixel via the well region 1107, so that crosstalk may be received from the charge storage layer 1001a of the adjacent pixel.</p><p num="0017"> On the other hand, in a general method for manufacturing a semiconductor device, which is not limited to the photoelectric conversion device, it is difficult to accurately form semiconductor regions having different thicknesses in a predetermined region in the semiconductor substrate.</p><p num="0018"> Specifically, in an ion implantation device for forming a semiconductor region in a predetermined region in a semiconductor substrate, the acceleration energy of impurity ions may be structurally restricted by the ion accelerator. In the ion accelerator of the ion implanter, ionized impurities are usually accelerated by using a plurality of magnetic field accelerators. The energy that can be accelerated by such an ion implanter at a distance of several meters is limited to about 1 to 2 MeV in consideration of the floor area of a realistic device. Since the ionization efficiency of polyvalent ions decreases exponentially with respect to the distance in the traveling direction, the number of ions finally reaching the vicinity of the wafer, that is, the dose amount, is further reduced. This makes it difficult to inject impurity ions into the semiconductor substrate to a depth greater than or equal to a predetermined value.</p><p num="0019"> In addition, if the acceleration energy is increased in the ion implantation device, there is a possibility that the variation in the impurity concentration in the direction perpendicular to the implantation direction, the so-called lateral standard deviation, will increase in the semiconductor substrate into which the impurity ions have been implanted. is there. This may reduce the accuracy in the lateral direction when forming impurities having different concentrations in the semiconductor substrate.</p><p num="0020"> Further, since ion implantation into a silicon substrate destroys the silicon single crystal structure, post-implantation heat treatment for rearrangement of impurities between lattices and recovery of crystal defects is indispensable. In particular, the latter crystal defect has a particularly large effect on the photoelectric conversion device. There is a high possibility of forming defects that serve as a base point for heavy metals and the like that tend to form deep levels, which may cause fatal white scratches in the image obtained by the photoelectric conversion device. That is, the larger the implantation energy, the larger the ion implantation amount, and the larger the number of implantations, the higher and longer the heat treatment temperature and treatment time for defect recovery must be set, and the desired profile design can be obtained. Difficult and can leave defects.</p><p num="0021"> A first object of the present invention is to improve the sensitivity of the photoelectric conversion unit even when the distance between the photoelectric conversion units is reduced, and to suppress crosstalk between adjacent photoelectric conversion units.</p><p num="0022"> A second object of the present invention is to improve the accuracy when forming semiconductor regions having different thicknesses at positions having a depth of a predetermined value or more in a semiconductor substrate.</p>

<p num="0023"> The method for manufacturing a photoelectric conversion device according to the first aspect of the present invention is a method for manufacturing a photoelectric conversion device, which includes an oxide film forming step of forming an oxide film on the surface of a base substrate including an element region and an element separation region. The first conductive type impurity ion is injected into the base substrate through the mask forming step of forming a mask having an opening in the element region on the oxide film and the region exposed by the opening in the oxide film. Thereby, the first injection step of forming the first semiconductor region with the first thickness below the oxide film of the element region in the base substrate and the region exposed by the opening in the oxide film are oxidized. An oxidation step that increases the thickness of the exposed region, an exposure step that exposes a region that is not exposed by the opening in the oxide film, and a thickness in the oxidation step after the exposure step. By injecting the first conductive type impurity ion into the base substrate through the portion that did not increase, the first thickness is thicker than the first thickness below the oxide film in the element separation region in the base substrate. After the second injection step of forming the second semiconductor region with a thickness of 2 and the second injection step, the above-mentioned for accumulating the photoelectrically converted signal above the first semiconductor region. It is characterized by including an element forming step of forming a photoelectric conversion part including a third semiconductor region of the second conductive type opposite to the first conductive type.</p><p num="0024"> The method for manufacturing a semiconductor device according to the second aspect of the present invention is a method for manufacturing a semiconductor device, which includes an oxide film forming step of forming an oxide film on the surface of a base substrate including the first region and the second region, and the above-mentioned. The base substrate is formed by injecting impurity ions into the base substrate through a mask forming step of forming a mask having an opening in the first region on the oxide film and a region exposed by the opening in the oxide film. By forming a first semiconductor region with a first thickness below the oxide film of the first region in the above, and by oxidizing the region exposed by the opening in the oxide film. An oxidation step of increasing the thickness of the exposed region, an exposure step of exposing an unexposed region by the opening in the oxide film, and a portion where the thickness did not increase in the oxidation step after the exposure step. By injecting impurity ions into the base substrate, a second semiconductor region having a second thickness thicker than the first thickness is formed below the oxide film in the second region of the base substrate. After the second injection step of forming, the removal step of removing the oxide film including the portion whose thickness has been increased in the oxidation step, and the removal step of the base substrate, the base substrate is formed. It is characterized by including a growth step of forming the base substrate and the semiconductor substrate including the semiconductor layer by growing the semiconductor layer on the top.</p><p num="0025">The photoelectric conversion device according to the third aspect according to the present invention is a photoelectric conversion device having a semiconductor substrate including an element region and an element separation region, and the semiconductor substrate is arranged in the element region and photoelectrically converted. Opposite to the first conductive type arranged with a first thickness below the photoelectric conversion part in the element region and a plurality of photoelectric conversion units each including a first conductive type semiconductor region for accumulating signals. The first semiconductor region of the second conductive type, the element separation portion arranged in the element separation region for electrically separating the plurality of photoelectric conversion portions, and the element separation portion in the element separation region. It is provided below the second semiconductor region of the second conductive type, which is arranged with a second thickness thicker than the first thickness, and above the first semiconductor region and the second semiconductor region. A first conductive type first semiconductor layer, and a first conductive type second semiconductor layer arranged on the first semiconductor region and the second semiconductor region and on the first semiconductor layer. And, the plurality of photoelectric conversion units are formed on the second semiconductor layer.<u style="single">The photoelectric conversion device has an effective pixel region and an optical black region, and the plurality of photoelectric conversion units and the element separation unit are arranged in the effective pixel region and the optical black region, and the first semiconductor region is provided. And the second semiconductor region is arranged in the effective pixel region and not in the optical black region, and the photoelectric conversion device is below the plurality of photoelectric conversion units arranged in the optical black region. Further includes a second conductive semiconductor region arranged over the optical black region.</u>It is characterized by that.</p><p num="0026"> The imaging system according to the fourth aspect of the present invention processes image data by processing the above-mentioned photoelectric conversion device, an optical system that forms an image on the imaging surface of the photoelectric conversion device, and a signal output from the photoelectric conversion device. It is characterized by having a signal processing unit for generating the above.</p>

<p num="0027"> According to the present invention, the sensitivity of the photoelectric conversion unit can be improved even when the distance between the photoelectric conversion units is reduced, and crosstalk between adjacent photoelectric conversion units can be suppressed.</p><p num="0028"> Further, according to the present invention, it is possible to improve the accuracy when forming semiconductor regions having different thicknesses at positions having a depth of a predetermined value or more in the semiconductor substrate.</p>

0029Next, each embodiment of the present invention will be described with reference to the drawings. Although each embodiment of the present invention will be described with respect to the photoelectric conversion device, it can also be applied to other semiconductor devices. Other semiconductor devices include memory devices such as DRAM and logic devices such as microcomputers.

0030The photoelectric conversion device 200 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of a photoelectric conversion device 200 according to the first embodiment of the present invention.

0031The photoelectric conversion device 200 includes a pixel array PA and a control unit 10.

0032In the pixel array PA, a plurality of pixels 101 are arranged in the row direction and the column direction. In FIG. 1, a case where a plurality of pixels 101 are pixels of 4 rows and 4 columns is exemplified. Each pixel 101 includes a photoelectric conversion unit 102, a transfer MOS transistor 103, an amplification MOS transistor 104, an FD (floating diffusion) 119, a reset MOS transistor 105, and a selective MOS transistor 106. The photoelectric conversion unit 102 is, for example, a photodiode.

0033The control unit 10 includes a vertical scanning circuit 110, MOS transistors 113 and 114, a holding unit 118, and a horizontal scanning circuit 117.

0034The selection MOS transistor 106 in the same row is turned on when an active signal is supplied from the vertical scanning circuit 110 to the gate via the selection line 107. The pixel on which the selected MOS transistor 106 is turned on is in the state of being selected by the vertical scanning circuit 110.

0035The reset MOS transistor 105 in the same row is turned on when an active signal is supplied from the vertical scanning circuit 110 to the gate via the reset line 108. Reset The MOS transistor 105 resets the FD119 when it is turned on.

0036The transfer MOS transistor 103 in the same row is turned on when an active signal is supplied from the vertical scanning circuit 110 to the gate via the transfer line 109. When the transfer MOS transistor 103 is turned on, the transfer MOS transistor 103 transfers the signal accumulated by the photoelectric conversion unit 102 to the FD119. The FD119 inputs the transferred signal to the gate of the amplification MOS transistor 104. The amplification MOS transistor 104 performs a source follower operation together with the current source 112, amplifies the input signal (noise signal or optical signal), and outputs the input signal (noise signal or optical signal) to the column signal line 111.

0037The MOS transistors 113 and 114 transfer the optical signal and the noise signal output to the column signal line 111 to the holding unit 118, respectively. The holding unit 118 holds the optical signal and the noise signal for a predetermined period of time. The horizontal scanning circuit 117 sequentially selects the holding unit 118 for each row, and transfers the optical signal and the noise signal of each row to the optical signal output line 115 and the noise signal output line 116, respectively. A differential amplifier circuit (not shown) calculates and outputs the difference between the optical signal and the noise signal transferred to the optical signal output line 115 and the noise signal output line 116.

0038Next, the layout configuration of the photoelectric conversion device 200 will be described. FIG. 2 is an example of a plan view showing the layout configuration of the photoelectric conversion device 200.

0039In the region of the broken line surrounding the photoelectric conversion unit 102, a second semiconductor region 211, which will be described later, is arranged at a position deeper in the semiconductor substrate SB than the photoelectric conversion unit 102. The second semiconductor region 211 is a P + type semiconductor region. Here, "P + type" indicates that the concentration of P-type impurities is higher than that in the "P-type" region. As a result, the potential barrier between the adjacent photoelectric conversion units 102 can be increased. The second semiconductor region 211 is formed in a region corresponding to the element separation unit 202 surrounding the photoelectric conversion unit 102. However, it does not have to correspond completely, and it may be arranged in the region of the broken line so that the potential barrier between the adjacent photoelectric conversion units 102 can be raised. Further, in the region where the photoelectric conversion unit 102 is arranged (the region surrounded by the broken line inside), the first semiconductor region 210, which will be described later, is arranged at a position deeper in the semiconductor substrate SB than the photoelectric conversion unit 102. ing. The first semiconductor region 210 is a P-type semiconductor region. The thickness of the first semiconductor region 210 (first thickness) is thinner than the thickness of the second semiconductor region 211 (second thickness) so that the saturated charge of the photoelectric conversion unit 102 can be secured. ing.

0040The gate 103a of the transfer transistor 103 is arranged between the photoelectric conversion unit 102 and the FD119. The FD119 temporarily holds the signal (charge) transferred from the photoelectric conversion unit 102 via the transfer transistor 103. In FIG. 2, the amplification MOS transistor 104, the reset MOS transistor 105, and the selection MOS transistor 106 are not shown.

0041Next, the cross-sectional configuration of the photoelectric conversion device 200 will be described. FIG. 3 is a sectional view taken along line AA of FIG. In FIG. 3, the structure of the upper layer after the contact plug is not shown.

0042As shown in FIG. 3, the photoelectric conversion device 200 has a semiconductor substrate SB including an element region (first region) AR and an element separation region (second region) PR. The semiconductor substrate SB includes a plurality of photoelectric conversion units 102, a first semiconductor region 210, an element separation unit 202, a channel stop region 206, a second semiconductor region 211, a base region 212, and a semiconductor region 208.

0043Each photoelectric conversion unit 102 is arranged in the element region AR. The photoelectric conversion unit 102 includes a charge storage layer (third semiconductor region) 102a, a semiconductor region 205, and a protective layer 102b. The charge storage layer 102a is formed by, for example, epitaxial growth. The charge storage layer 102a is a region for accumulating photoelectrically converted signals, and is an N-type (first conductive type) semiconductor region. The semiconductor region 205 is an N-type semiconductor region. N-type indicates that the concentration of N-type impurities is lower than that in the N-type region. The charge storage layer 102a and the semiconductor region 205 function as a cathode of the photoelectric conversion unit 102. The protective layer 102b is a region that protects the charge storage layer 102a, and is a P + type semiconductor region. The first semiconductor region 210, the second semiconductor region 211, and the semiconductor region 208 function as the anode region of the photoelectric conversion unit 102.

0044The charge storage layer 102a has a lower potential for signals (charges, electrons) than the semiconductor region 205. The photoelectric conversion unit 102 accumulates signals (charges, electrons) in the charge storage layer 102a during the storage period. The charge storage layer 102a has a structure that partially enters under the gate 103a of the transfer MOS transistor 103. With this structure (structure suitable for complete charge transfer), when the transfer MOS transistor 103 is turned on, the signal (charge) is completely transferred from the charge storage layer 102a of the photoelectric conversion unit 102 to the FD119. By completely transferring the signal (charge), the fluctuation of the signal amount (number of electrons) remaining in the charge storage layer 102a of the photoelectric conversion unit 102 is reduced, so that a photoelectric conversion device having a small random noise can be realized. By forming the charge storage layer 102a by patterning and ion implantation before forming the gate 103a of the transfer MOS transistor 103, it is possible to form a charge storage layer 102a that partially enters under the gate 103a of the transfer MOS transistor 103. .. Alternatively, by forming the gate 103a of the transfer MOS transistor 103 and then implanting ions diagonally, a charge storage layer 102a that partially enters under the gate 103a of the transfer MOS transistor 103 can be formed.

0045The first semiconductor region 210 is arranged below the photoelectric conversion unit 102 in the element region AR with a first thickness d1. The first semiconductor region 210 is a P-type (second conductive type) semiconductor region opposite to the conductive type (N-type) of the charge storage layer 102a.

0046The element separation unit 202 is arranged in the element separation region PR. The element separation unit 202 electrically separates a plurality of photoelectric conversion units 102.

0047The channel stop region 206 is arranged below the element separation unit 202. The channel stop region 206 is a P + type semiconductor region 206.

0048The second semiconductor region 211 is arranged below the device separation portion 202 in the device separation region PR with a second thickness d2 thicker than the first thickness d1. The second semiconductor region 211 is a P + type (second conductive type) semiconductor region opposite to the conductive type (N type) of the charge storage layer 102a. In order to obtain a lateral potential barrier, the impurity concentration of the second semiconductor region 211 is made higher than the impurity concentration of the first semiconductor region 210.

0049Here, the lateral position of the boundary between the first semiconductor region 210 and the second semiconductor region 211 may be determined in consideration of the opening area of the photoelectric conversion unit 102 and the position where the incident light reaches. ..

0050The base region 212 is arranged below the first semiconductor region 210 and the second semiconductor region 211. The base region 212 is a region containing N-type impurities.

0051The semiconductor region 208 is arranged between the channel stop region 206 and the second semiconductor region 211.

0052As shown in FIG. 3, even if the semiconductor region 208 and the second semiconductor region 211 are not completely in contact with each other, these P-type semiconductor regions are formed in the charge storage layer 102a of the photoelectric conversion unit 102. On the other hand, it is good if a sufficient potential barrier is formed. Further, the semiconductor region 208 may have a plurality of profiles, the semiconductor region 207 may also serve as a potential barrier, and even if the semiconductor region 208 has a continuous profile with an impurity concentration, there is of course a problem. It is possible to obtain the desired characteristics without any problem.

0053In this way, the P-shaped semiconductor region surrounds the semiconductor region 205 and the charge storage layer 102a, so that the potential barrier between the adjacent photoelectric conversion units 102 can be increased. As a result, it is possible to prevent the signal (charge) generated by the photoelectric conversion unit 102 from leaking to the adjacent photoelectric conversion unit 102. That is, the photoelectric conversion unit 102 can reliably store the generated signal (charge). Further, since the semiconductor region 207 is formed so as to cover the FD119, it is possible to prevent the signal (charge) generated by the incident light from being absorbed by the FD119. Further, the characteristics of the transfer MOS transistor 103 can be determined so as to secure the withstand voltage between the FD119 and the charge storage layer 102a. Further, although not shown, the semiconductor region 207 is also arranged below other transistors in the pixel and can also act as wells for these MOS transistors.

0054Next, a method of manufacturing the photoelectric conversion device 200 for realizing the cross-sectional configuration shown in FIG. 3 will be described with reference to FIGS. 4 and 5. 4 and 5 are process cross-sectional views showing a manufacturing method of the photoelectric conversion device 200.

0055As shown in a of FIG. 4, first, the base substrate 312 is prepared. The base substrate 312 includes an element region AR and an element separation region PR. The base substrate 312 contains N-type impurities.

0056Next, the silicon oxide film 301 is formed on the surface of the base substrate 312 by thermally oxidizing the base substrate 312 (oxide film forming step).

0057Then, a silicon nitride film is formed on the silicon oxide film 301 by the thermal CVD growth method (nitriding film forming step of the mask forming step).

0058Next, a resist is applied on the silicon nitride film. The resist in the device region AR is selectively removed by photolithography. As a result, a resist mask 303 having a first opening 303a in the element region AR is formed on the silicon nitride film (resist mask forming step in the mask forming step).

0059Then, the region exposed by the first opening 303a in the silicon nitride film is etched by a dry etching method to form a nitride film mask 302 having a second opening 302a in the element region AR (etching step of the mask forming step). At that time, since the dry etching conditions are set so as to have a high selectivity with respect to the silicon oxide film, the silicon oxide film 301 is hardly etched.

0060The silicon oxide film 301 after etching can prevent channeling in the subsequent ion implantation step, and may have a film thickness that has a sufficient margin for the implantation energy. Therefore, about 5 to 100 nm is appropriate. is there.

0061Next, P-type impurity ions are injected into the substrate 312 through the regions exposed by the first opening 303a and the second opening 302a of the silicon oxide film 301. The P-type impurity ion is, for example, a boron ion. As a result, impurity ions 304 are injected below the silicon oxide film 301 in the element region AR of the base substrate 312 (first injection step). By heating to stabilize the impurity ions 304, as shown in b of FIG. 4, the first semiconductor region 210 has a first thickness below the silicon oxide film 301 of the element region AR in the base substrate 312. Formed at d1 (first injection step).

0062Next, the resist mask 303 is removed and cleaning is performed. The thickness of the exposed region is increased by oxidizing the region exposed by the second opening 302a in the silicon oxide film 301 (oxidation step). The portion 301a whose thickness has been increased in the oxidation step has a thickness of, for example, about 100 to 300 nm. Since the region where the nitride film mask 302 remains is not oxidized, the surface of the silicon oxide film 301 including the portion 301a whose thickness has increased in the oxidation step has the element region AR convex with respect to the element separation region PR. It has a step 301b.

0063For example, the thickness of the portion 301a whose thickness has increased in the oxidation step has a difference of 100 nm or more from the thickness of the portion 301c whose thickness has not increased in the oxidation step. In this case, the height H1 of the step 301b is 50 nm or more.

0064Then, by removing the nitride film mask 302, the region not exposed by the second opening 302a in the silicon oxide film 301 (the portion 301c whose thickness did not increase in the oxidation step) is exposed (exposure step).

0065After the exposure step, P-type impurity ions are injected into the substrate 312 through the portion 301c whose thickness did not increase in the oxidation step. As a result, impurity ions 306 are injected below the silicon oxide film 301 in the element separation region PR of the base substrate 312 (second injection step).

0066By heating to stabilize the impurity ions 306, as shown in FIG. 5a, a second semiconductor having a second thickness d2 is below the silicon oxide film 301 of the element separation region PR in the base substrate 312. Form region 211 (second injection step). The second thickness d2 is thicker than the first thickness d1.

0067Next, after the second injection step, the silicon oxide film 301 containing the portion 301a whose thickness has increased in the oxidation step is removed (removal step). Since the thickness of the portion 301a whose thickness increased in the oxidation step and the thickness of the portion 301c whose thickness did not increase in the oxidation step are different, as shown in FIG. 5a, the surface of the base substrate 312 is an element. The element region AR has a step 312b as a recess with respect to the separation region PR.

0068For example, in the removed silicon oxide film 301, the thickness of the portion 301a whose thickness increased in the oxidation step has a difference of 100 nm or more from the thickness of the portion 301c whose thickness did not increase in the oxidation step. Suppose you were doing it. In this case, the height H2 of the step 312b is 50 nm or more.

0069After the removal step, the semiconductor layer 405 is epitaxially grown on the substrate 312 as shown in FIG. 5b. As a result, the semiconductor substrate SB including the base substrate 312 and the semiconductor layer 405 is formed (growth step). Here, since the surface of the base substrate 312 has a step 312b in which the element region AR is recessed with respect to the element separation region PR, the surface of the semiconductor layer 405 also has the element region AR recessed with respect to the element separation region PR. It has a step 405b. This step 405b can be used for exposure alignment after epitaxial growth.

0070For example, the height H2 of the step 312b is assumed to be 50 nm or more. In this case, the height H3 of the step 405b is also 50 nm or more.

0071Next, the charge storage layer 102a is formed above the first semiconductor region 210. That is, a charge storage layer 102a is formed between the first semiconductor region 210 in the semiconductor substrate SB and the surface 405a of the semiconductor layer 405 (element forming step).

0072The process of forming the semiconductor region 208, the semiconductor region 207, the protective layer 102b, the channel stop region 206, the element separation unit 202, the gate 103a of the transfer MOS transistor 103, and the steps after the contact plug is created will be omitted.

0073Further, in the present embodiment, the conductive type of the epitaxially grown semiconductor layer is an N-type, but when this is a P-type and all other conductive types are inverted to form a hole storage type pixel. Needless to say, the present invention can be applied to the above.

0074As described above, according to the present embodiment, in principle, the first semiconductor region 210, which has the greatest effect on pixel sensitivity, and the second semiconductor region 211 adjacent thereto are self-aligned to the same depth. Can be formed. In addition, since the semiconductor region can be formed at a position deeper than the limit energy of the conventional high-energy injection device, the sensitivity of the photoelectric conversion device can be significantly improved, and leakage to adjacent pixels can be reduced to reduce color mixing. Can be done. Further, since the position of the semiconductor region for suppressing the leakage of electric charges to the substrate can be formed deeper, the photoelectric conversion unit 102 has a larger volume of the semiconductor region for accumulating electrons per unit area as compared with the conventional example. Can be configured. That is, the saturated charge of the photoelectric conversion element can also be increased.

0075As described above, even when the distance between the photoelectric conversion units is reduced, a sufficient potential barrier can be formed between the charge storage layers of the adjacent photoelectric conversion units, so that the sensitivity of the photoelectric conversion units can be improved. Further, since it is possible to prevent the charge storage layers of the adjacent photoelectric conversion units from being capacitively coupled, it is possible to suppress crosstalk between the adjacent photoelectric conversion units. That is, even when the distance between the photoelectric conversion units is reduced, the sensitivity of the photoelectric conversion units can be improved, and crosstalk between adjacent photoelectric conversion units can be suppressed.

0076In addition, ion implantation can be controlled to an arbitrary amount of ion implantation using a medium-current or large-current implantation device without using a high-energy implanter, and the resist patterning of each diffusion layer also has a low ion implantation energy value. Can be processed. Therefore, the low-damage semiconductor region can be easily and finely patterned and formed. That is, it is possible to improve the accuracy when forming semiconductor regions having different thicknesses in the semiconductor substrate.

0077Furthermore, the present embodiment may achieve at least one of the following effects.

0078The semiconductor region formed at a position deep from the light receiving surface on which the photoelectric conversion unit receives light is easily and accurately created, and the silicon step created when the semiconductor region is formed is easily formed on the silicon surface after epitaxial growth in the subsequent steps. Can provide the alignment steps required for.

0079On the other hand, since there is little leakage to the adjacent pixel at the deepest position, even if the photoelectric conversion unit 102 is saturated, the saturated charge is discharged to the N substrate through the P-type semiconductor region arranged at the deep position. Therefore, the smear characteristics are further improved.

0080Further, by arranging the P-type semiconductor regions in a grid pattern, the total resistance value of the charge storage layer 102a is lowered and the GND potential is stabilized, so that an image with less shading can be obtained even if a high-speed readout operation is performed. it can.

0081Next, FIG. 6 shows an example of an imaging system to which the photoelectric conversion device of the present invention is applied.

0082As shown in FIG. 6, the image pickup system 90 mainly includes an optical system, an image pickup device 86, and a signal processing unit. The optical system mainly includes a shutter 91, a photographing lens 92, and an aperture 93. The imaging device 86 includes a photoelectric conversion device 200. The signal processing unit is mainly an image pickup signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording unit. The medium 88 and the recording medium control I / F unit 94 are provided. The signal processing unit does not have to include the recording medium 88.

0083The shutter 91 is provided in front of the photographing lens 92 on the optical path to control the exposure.

0084The photographing lens 92 refracts the incident light to form an image of the subject on the imaging surface of the photoelectric conversion device 200 of the imaging device 86.

0085The diaphragm 93 is provided between the photographing lens 92 and the photoelectric conversion device 200 on the optical path, and adjusts the amount of light guided to the photoelectric conversion device 200 after passing through the photographing lens 92.

0086The photoelectric conversion device 200 of the imaging device 86 converts an image of a subject formed on the imaging surface of the photoelectric conversion device 200 into an image signal. The image pickup apparatus 86 reads the image signal from the photoelectric conversion apparatus 200 and outputs the image signal.

0087The image pickup signal processing circuit 95 is connected to the image pickup device 86 and processes the image signal output from the image pickup device 86.

0088The A / D converter 96 is connected to the image pickup signal processing circuit 95, and converts the processed image signal (analog signal) output from the image pickup signal processing circuit 95 into a digital signal.

0089The image signal processing unit 97 is connected to the A / D converter 96, and performs arithmetic processing such as various corrections on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. This image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

0090The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

0091The external I / F unit 89 is connected to the image signal processing unit 97. As a result, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

0092The timing generator 98 is connected to the image pickup device 86, the image pickup signal processing circuit 95, the A / D converter 96, and the image signal processing section 97. As a result, the timing signal is supplied to the image pickup device 86, the image pickup signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Then, the image pickup device 86, the image pickup signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

0093The overall control / calculation unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit. The unit 94 is controlled as a whole.

0094The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

0095With the above configuration, if a good image signal can be obtained in the photoelectric conversion device 200, a good image (image data) can be obtained.

0096Next, the photoelectric conversion device 500 according to the second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing a cross-sectional configuration of the photoelectric conversion device 500 according to the second embodiment of the present invention.

0097The photoelectric conversion device 500 includes a semiconductor layer 507. The semiconductor layer 507 contains P-type impurities. As a result, when forming the P-type semiconductor region, ion implantation may be performed over the entire pixel surface, so that the required processing accuracy can be reduced. Further, by adjusting the impurity profile of the P-type semiconductor region, the depletion voltage of the charge storage layer 102a can be adjusted, and at the same time, the variation in transfer characteristics can be reduced. Therefore, this embodiment is more effective with a photoelectric conversion device having a large number of pixels and a large chip area.

0098Next, the photoelectric conversion device 600 according to the third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a cross-sectional configuration of the photoelectric conversion device 600 according to the third embodiment of the present invention.

0099The pixel array PA of the photoelectric conversion device 600 has an effective pixel region and an optical black region. The configuration of the pixels included in the optical black region is different from that of the first embodiment.

0100As shown in FIG. 8, the first semiconductor region 210 and the second semiconductor region 211 (see FIG. 3) are not arranged in the pixels included in the optical black region (hereinafter referred to as OB pixels). That is, the manufacturing method of the photoelectric conversion device 600 is different from that of the first embodiment in the following points.

0101In the steps shown in FIGS. 4A and 4B, only the OB pixel is prevented from injecting the P-type impurity ion 304 without forming an opening in the resist and the silicon nitride film. Alternatively, resist patterning and ion implantation are performed using one mask laid out so as to hide the OB pixel portion. As a result, it is possible to obtain a structure in which only the OB pixel does not have the first semiconductor region 210 and the second semiconductor region 211.

0102However, if the first semiconductor region 210 is not formed, there is a concern that noise components from the substrate, mainly holes, may be mixed into the charge storage layer. Therefore, in the step shown in FIG. 5b, after the semiconductor layer 605 is epitaxially grown, the semiconductor region 608 is formed in the semiconductor layer 605 by injecting P-type impurity ions into the entire surface of the optical black region.

0103According to this embodiment, while maintaining high sensitivity of pixels other than OB pixels, it is possible to reduce mixing of optical carriers generated by long wavelengths, especially far-infrared wavelengths, into OB pixels, and the black level of OB pixels rises. It can be avoided. That is, the characteristics of the OB pixel can be improved.

0104The configuration of the pixels included in the effective pixel area is the same as that of the first embodiment.

0105Next, the photoelectric conversion device 700 according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a diagram showing a cross-sectional configuration of the photoelectric conversion device 700 according to the fourth embodiment of the present invention.

0106In the step shown in FIG. 5b, the semiconductor layer 405 is epitaxially grown at 1000 degrees or higher. Therefore, in the process of growing the semiconductor layer 405, N-type impurities may diffuse from the semiconductor layer 405 to the first semiconductor region 210.

0107On the other hand, in the present embodiment, the photoelectric conversion device 500 includes semiconductor layers 705a and 705b and a semiconductor region 711. The semiconductor layer 705a is arranged between the first semiconductor region 210 and the semiconductor layer 705b. The semiconductor region 711 is arranged between the semiconductor region 208 and the second semiconductor region 211. The semiconductor layer 705a is an N-- type semiconductor region, and the semiconductor layer 705b is an N-type semiconductor region. That is, since the N-type impurity concentration of the semiconductor layer 705a is lower than the N-type impurity concentration of the semiconductor layer 205 (see FIG. 3), the N-type impurities are from the semiconductor layer 705a to the first semiconductor region 210. It is difficult to spread to. By appropriately controlling the thicknesses of the semiconductor layers 705a and 705b in this way, it is possible to reduce the diffusion of impurities into the first semiconductor region 210 in the semiconductor layer 705a while ensuring the saturated charge amount in the 705b. , It is possible to realize high sensitivity of pixels.

0108Next, the photoelectric conversion device 900 according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a diagram showing a cross-sectional configuration of the photoelectric conversion device 900 according to the fifth embodiment of the present invention. The pixel array PA of the photoelectric conversion device 900 differs from the first embodiment in the configuration of the control unit 910.

0109As shown in FIG. 10, the control unit 910 is not provided with the first semiconductor region 210 and the second semiconductor region 211 (see FIG. 3). In the control unit 910, a P-type embedded diffusion layer 908 and a P-type embedded separation layer 911 are arranged under the P-type well 907 in which the NMOS transistor including the gate 901 and the source (or drain) 913 is formed. ing. As a result, the base resistance of the parasitic bipolar structure formed by the source (or drain) 913 of the NMOS transistor (901,913), the N-type base substrate 912, and the P-type well 907 can be lowered, and the latch-up resistance can be reduced. Can be improved.

0110Further, a P-type embedded separation layer 911 is arranged under an N-type well 903 in which a MOSFET including a gate 902 and a source (or drain) 904 is formed. Next to the N-type well 903, a P-type well 907 and a P-type diffusion separation layer 908 are arranged. As a result, the potential of the N-type well 903 can be floated, and the noise 915 generated from other circuits and mixed through the substrate can be shielded.

0111According to this embodiment, it is possible to improve the latch-up resistance of the control unit while improving the sensitivity of the photoelectric conversion unit, and reduce the noise component caused by the substrate current.

0112Needless to say, the third to fifth embodiments described above can be implemented in combination with the first and second embodiments, respectively, and effects can be obtained.

0113<figref num="1">The block diagram of the photoelectric conversion apparatus 200 which concerns on 1st Embodiment of this invention.</figref><figref num="2">An example of a plan view showing the layout configuration of the photoelectric conversion device 200.</figref><figref num="3">AA sectional view of FIG.</figref><figref num="4">The process sectional view which shows the manufacturing method of the photoelectric conversion apparatus 200.</figref><figref num="5">The process sectional view which shows the manufacturing method of the photoelectric conversion apparatus 200.</figref><figref num="6">The block diagram of the image pickup system which applied the photoelectric conversion apparatus which concerns on 1st Embodiment.</figref><figref num="7">The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 500 which concerns on 2nd Embodiment of this invention.</figref><figref num="8">The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 600 which concerns on 3rd Embodiment of this invention.</figref><figref num="9">The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 700 which concerns on 4th Embodiment of this invention.</figref><figref num="10">The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 900 which concerns on 5th Embodiment of this invention.</figref><figref num="11">Circuit block diagram of pixels in a conventional CMOS sensor.</figref><figref num="12">Cross-sectional configuration diagram of pixels in a conventional CMOS sensor.</figref>

Code description

011490 Imaging system 200,500,600,700,900 Photoelectric converter