Semiconductor memory device

The embodiment relates to a semiconductor storage device.

Conventionally, as an electrically rewritable non-volatile memory, a flash memory in which a memory cell having a floating gate structure is NAND-connected or NOR-connected to form a memory cell array is well known. Ferroelectric memory is also known as a non-volatile memory capable of high-speed random access.

On the other hand, as a technique for further miniaturization of a memory cell, a resistance change type memory using a variable resistance element for the memory cell has been proposed. Variable resistance elements include a phase change memory element that changes the resistance value by changing the crystal / amorphization state of the chalcogenide compound, an MRAM element that uses the resistance change due to the tunnel magnetoresistive effect, and a polymer in which the resistance element is formed of a conductive polymer. A memory element of strong dielectric RAM (PFRAM), a ReRAM element that causes a resistance change by supplying a voltage pulse, and the like are known.

However, for example, in the case of a memory cell using a ReRAM element, due to the instability of the memory cell, not only does the resistance change not occur simply by supplying a voltage pulse, but also the resistance changes in the direction opposite to the intention. May cause. If such a resistance change in the reverse direction is left unattended, there is a concern that the life of the memory cell may be shortened or the like may be adversely affected.

<p num="0005"><patcit num="1"><text>Japanese Patent Application Laid-Open No. 2006-344349</text></patcit></p>

<p num="0006"> The embodiment provides a semiconductor storage device having improved reliability during a memory cell set operation / reset operation.</p>

<p num="0007"> The semiconductor storage device according to the embodiment is a memory including a first wiring, a second wiring intersecting the first wiring, and a variable resistance element provided at the intersection of the first and second wirings. A memory cell array having cells, a data writing unit that applies a voltage pulse necessary for setting and / or resetting data to the memory cells via the first and second wirings, and a data set and / or A detection unit that compares the cell current flowing through the memory cell by applying the voltage pulse at the time of reset with the reference current generated from the initial value of the cell current, and controls the data writing unit according to the comparison result. It is characterized by that.</p>

<figref num="1">It is a figure which shows the memory cell array of the semiconductor storage device which concerns on embodiment.</figref><figref num="2">It is a perspective view which shows the structural example of the memory cell array of the semiconductor storage device which concerns on this embodiment.</figref><figref num="3">It is a table which shows the voltage and current applied to the memory cell of the semiconductor storage device which concerns on this embodiment.</figref><figref num="4A">It is a figure which shows the voltage applied to the memory cell array of the semiconductor storage device which concerns on this embodiment.</figref><figref num="4B">It is a figure explaining the bias state of the memory cell in FIG. 4A.</figref><figref num="5">It is a block diagram of the semiconductor storage device which concerns on this embodiment.</figref><figref num="6">It is a circuit diagram of the row circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="7">It is a circuit diagram of the row circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="8">It is a circuit diagram of the row circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="9">It is a circuit diagram of the row circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="10">It is a circuit diagram of the row circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="11">It is a circuit diagram of the column system circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="12">It is a circuit diagram of the column system circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="13">It is a circuit diagram of the column system circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="14">It is a circuit diagram of the column system circuit of the semiconductor storage device which concerns on this embodiment.</figref><figref num="15">It is a conceptual diagram of the reverse direction operation detection at the time of the reset operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="16">It is a conceptual diagram of the reverse direction operation detection at the time of the set operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="17">It is a circuit diagram of the write buffer for reset operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="18">It is a flowchart of the reset operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="19">It is an operation waveform figure at the time of the reset operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="20">It is a circuit diagram of the write buffer for set operation of the semiconductor storage device which concerns on this embodiment.</figref><figref num="21">It is a conceptual diagram of the reverse direction operation detection at the time of the reset operation of the semiconductor storage device which concerns on a comparative example.</figref><figref num="22">It is a conceptual diagram of the reverse direction operation detection at the time of a set operation of the semiconductor storage device which concerns on a comparative example.</figref><figref num="23">It is a circuit diagram of the write buffer for reset operation of the semiconductor storage device which concerns on a comparative example.</figref><figref num="24">It is an operation waveform figure at the time of the reset operation of the semiconductor storage device which concerns on a comparative example.</figref>

Hereinafter, the semiconductor storage device according to the embodiment will be described with reference to the drawings.

[Embodiment] &lt;Overview of memory cells&gt; First, an outline of a memory cell used in the semiconductor storage device according to the embodiment will be described.

FIG. 1 is a diagram showing a part of the memory cell array MA. As shown in FIG. 1, the memory cell array MA includes a word line WL (WL0, WL1 in the case of FIG. 1) which is a plurality of first wires intersecting each other and a bit line BL (a figure) which is a plurality of second wires. In the case of 1, BL0, BL1) and a memory cell MC having a variable resistance element VR connected to each intersection of the word line WL and the bit line BL are provided.

As the variable resistance element VR, for example, ReRAM composed of a metal oxide / electrode such as an electrode / binary system or a ternary system can be used. Memory cells using this variable resistance element VR can be roughly classified into two types according to the difference in operation.

The first is a bipolar memory cell MC. This is to change the polarity of the voltage applied to the memory cell MC to change the variable resistance element VR between the high resistance state and the low resistance state, and is composed of the variable resistance element VR and the transistor.

The second is a unipolar memory cell MC. This transitions between a high resistance state and a low resistance state by controlling the magnitude and application time of the voltage applied to the memory cell MC. As shown in FIG. 1, the variable resistance element VR and the diode Di It is composed of rectifying elements such as.

As described above, of the two types of memory cell MCs, the unipolar type memory cell MC is preferable to the bipolar type memory cell MC in terms of the degree of integration of the semiconductor storage device. In the case of the unipolar type, a memory cell MC can be formed by stacking a variable resistance element VR and a rectifying element such as a diode Di at the intersection of the word line WL and the bit line BL, and 4F per cell.²This is because the memory cell array MA can be realized with the minimum dimensions of.

Further, as shown in FIG. 2, by stacking a plurality of memory cell array MAs to form a three-dimensional structure, further high integration can be achieved without increasing the area of the memory cell array portion.

Next, a data writing operation to the unipolar type memory cell MC and a data reading operation from the memory cell MC will be described.

The data writing operation includes a set operation of transitioning the variable resistance element VR from a high resistance state to a low resistance state and a reset operation of transitioning the variable resistance element VR from a low resistance state to a high resistance state.

First, in the set operation, as shown in the upper part of Fig. 3, the voltage pulse of the variable resistance element VR is about 4V and the current is about several hundred nA to several tens of nA (for example, less than 0.3 μA) (hereinafter, less than 0.3 μA). (Sometimes called "set pulse") is applied for a period of several tens of ns to 1 μs. As a result, the variable resistance element VR transitions from the high resistance state to the low resistance state. This factor varies depending on the substance of the variable resistance element VR. For example, when a high voltage is applied, the positively charged ions move inside the variable resistance element VR, and the substance in the insulated state has an electrochemical potential. This is thought to be due to the phase change to a (quasi) stable series-bonded state of the conductor material.

Subsequently, in the reset operation, as shown in the middle part of FIG. 3, a voltage pulse (hereinafter, "reset pulse") of about 3 V in voltage and about 1 μA to 10 μA (for example, less than 3 μA) in current is applied to the variable resistance element VR. ) Is applied for a period of about several μs. As a result, the variable resistance element VR transitions from the low resistance state to the high resistance state. It is considered that this factor is because, for example, the Joule heat generated inside the variable resistance element VR due to the application of the voltage pulse causes the atoms to thermally diffuse and change to the original thermal equilibrium state.

On the other hand, in the read operation, as shown in the lower part of FIG. 3, a voltage pulse of about 2 V is applied to the variable resistance element VR as a voltage, and the current flowing through the resistance element is monitored to monitor the variable resistance element VR. Determines whether is in a low resistance state or a high resistance state.

Hereinafter, the state of the memory cell MC in which the variable resistance element VR is in a low resistance state may be referred to as a set state, and the state of the memory cell MC in which the variable resistance element VR is in a high resistance state may be referred to as a reset state. Further, the direction in which the variable resistance element VR transitions from the high resistance state to the low resistance state is called the "set direction", and conversely, the direction in which the variable resistance element VR transitions from the low resistance state to the high resistance state is called the "reset direction". There is also. Therefore, during the set operation, the set direction is the "forward direction" and the reset direction is the "reverse direction", and during the reset operation, the reset direction is the "forward direction" and the set direction is the "reverse direction".

Next, the bias state of the memory cell MC during the write operation will be described.

FIG. 4A shows an example of the voltage applied to the word line WL and the bit line BL during the writing operation, and FIG. 4B shows the bias state of each memory cell MC shown in FIG. 4A.

Here, a case where the write operation is executed to the selected memory cell MC with the word line WL1 as the selected word line, the bit line BL2 as the selected bit line, and the memory cell MC shown by the dotted line circle in FIG. 4A as the selected memory cell will be described. ..

In the examples of FIGS. 4A and 4B, during the writing operation, the selected word line WL1 has the selected word line voltage VSS (for example, 0V), the non-selected word line WL has the non-selected word line voltage VUX (for example, 3.2V), and the selection bit. The write voltage VWR (for example, 4V in the case of set operation) required for the write operation is applied to the line BL2, and the non-selection bit line voltage VUB (for example, 0.8V) is applied to the non-selection bit line BL.

That is, as shown on the left in FIG. 4B, the selected memory cell MC is subjected to the forward bias VWR-VSS of the diode Di. This bias functions as a voltage pulse, and the state of the selected memory cell MC changes.

On the other hand, the non-selected memory cell MC connected to the non-selected word line WL and the non-selected bit line BL is subjected to the reverse bias VUX-VUB of the diode Di as shown in the middle of FIG. 4B. .. Therefore, no voltage pulse is applied to the variable resistance element VR, and the state of the memory cell MC does not transition.

Further, as shown in the upper right of FIG. 4B, the non-selected memory cell MC (hereinafter referred to as semi-selected memory cell) connected to the selected bit line BL2 and the non-selected word line WL is in the order of the diode Di. Directional bias "VWR-VUX" is applied. However, this bias is insufficient for the write operation, and the state of the semi-selective memory cell MC does not change.

Similarly, the semi-selective memory cell MC connected to the non-selected bit line BL and the selected word line WL1 is also subjected to the forward bias "VUB-VSS" of the diode Di as shown in the lower right in FIG. 4B. However, the bias is insufficient for the write operation, and the state of the semi-selective memory cell MC does not transition.

It is considered that the write operation can be executed by creating such a bias state of the memory cell MC. However, in reality, the state of the memory cell MC may not transition well.

That is, when a cell current higher than the threshold level for determining whether or not the memory cell MC is in the set state flows, the memory cell MC is in the set state and the cell current is lower than the threshold level for determining whether or not the memory cell MC is in the reset state. If is flowing, the memory cell MC is in the reset state.

However, even if a reset pulse is applied to the memory cell MC in the set state and an attempt is made to perform the reset operation, the state of the memory cell MC does not easily transition to the reset state, and may also transition in the set direction ( In the following, the transition of the state of the memory cell MC in the set direction during the reset operation may be referred to as overset operation).

Further, even if a set pulse is applied to the memory cell MC in the reset state and the set operation is attempted, not only the set state does not easily transition but also the reset direction may be transferred (in the following, the memory during the set operation). The transition of the cell MC state in the reset direction is sometimes called "over-reset operation").

In particular, if the overset operation or overreset operation progresses too much and the state of the memory cell MC enters the dangerous area, further set operation / reset operation becomes difficult and the memory cell MC may be damaged. is there.

Therefore, in the semiconductor storage device according to the embodiment, the state of the memory cell MC is prevented from entering the dangerous area by detecting the overset operation and the overreset operation.

&lt;Semiconductor storage device configuration&gt; FIG. 5 is a block diagram of the semiconductor storage device according to the present embodiment.

This semiconductor storage device includes a memory cell array core unit 100 surrounded by a dotted line in FIG. 5, and a voltage generation circuit 200 that generates and supplies a voltage used for the memory cell array core unit 100.

The memory cell array core unit 100 selects a predetermined memory cell MC based on the memory cell array 110 and an address signal (Address) and a control signal (Control) supplied from the outside, and executes a write operation and a read operation. It has a control circuit 100R and a column system control circuit 100C. The voltage generation circuit 200 includes a row system voltage generation circuit that generates a voltage used for the row system control circuit 100R and a column system voltage generation circuit that generates a voltage used for the column system control circuit 100C. The row control circuit 100R and the column control circuit 100C function as a data writing unit during the writing operation.

First, a row circuit including a row control circuit 100R and a row voltage generation circuit will be described. Here, the example described is a hierarchical word line type circuit that selects the memory cell MC in the low direction by the main word line MWL and the word line WL.

The row control circuit 100R is defined by a main row decoder 120 that selects the main word line MWL based on the row address, and a plurality of word line WLs selected by the main word line MWL selected by the main row decoder 120. Supply selected word line voltage VSS or non-selected word line voltage VUX to the word line WL based on the selection of the write drive line (WDRV) driver 140, main row decoder 120 and write drive line driver 140 to select the word line WL. The row driver 130 and a row peripheral circuit 150 including other circuits necessary for controlling the row system are included. Each of these configurations will be described below.

First, the main row decoder 120 will be described.

FIG. 6 is a circuit diagram of the main row decoder 120. The main row decoder 120 is a pre-decoder and selects one of 256 pairs of main word lines MWLx and MWLbx (x = &lt;255: 0&gt;) based on the input row address. The main row decoder 120 includes the circuits shown in FIG. 6 for each of 256 pairs of main word lines MWLx and MWLbx. As shown in FIG. 6, one main row decoder 120 is supplied with a NAND gate G121 that inputs an address signal (Address), a level shifter L / S that level-shifts the output of this NAND gate G121, and a write voltage VWR. Input the output of the inverter IV121 that inputs the output of the level shifter L / S provided between the VWR terminal and the VSS terminal to which the selected word line voltage VSS is supplied, and the inverter IV121 provided between the VWR terminal and the VSS terminal. It is composed of the inverter IV122. Here, the outputs of the inverters IV121 and IV122 are connected to the main word lines MWLx and MWLbx, respectively.

The main row decoder 120 selects a predetermined x based on the address signal (Address), supplies voltages VSS and VWR to the selected main word lines MWLx and MWLbx, respectively, and supplies voltages to the non-selected main word lines MWLx and MWLbx, respectively. Supply VWR and VSS.

Next, the low driver 130 will be described.

FIG. 7 is a circuit diagram of the low driver 130. Input one of 256 pairs of main word lines MWLx and MWLbx (x = &lt;255: 0&gt;) to the low driver 130. Eight row drivers 130 are provided for one main row decoder 120. As shown in FIG. 7, the low driver 130 is provided between the write drive line WDRV &lt;7: 0&gt; and the word line WLx &lt;7: 0&gt;, and is controlled by the main word lines MWLbx and MWLx, respectively. , QN131 and a transistor QP132 controlled by a main word line MWLx provided between a VUX line to which a non-selected word line voltage VUX is supplied and a word line WLx &lt;7: 0&gt;.

This low driver 130 connects either one of the write drive line WDRV &lt;7: 0&gt; or the VUX line to the word line WLx &lt;7: 0&gt; depending on the selection / non-selection state of the main word line MWLx. .. As a result, either the voltage VSS or VUX is supplied to the word line WLx &lt;7: 0&gt;.

Subsequently, the write drive line driver 140 will be described.

FIG. 8 is a circuit diagram of the write drive line driver 140. The write drive line driver 140 is a pre-decoder. The write drive line circuit 140 includes an AND gate G141 that inputs an address signal (Address), a level shifter L / S that shifts the output of the AND gate G141, a VUX terminal to which a non-selected word line voltage VUX is supplied, and VSS. It is composed of an inverter IV141 that inputs the output of the level shifter L / S provided between the terminals. The output of this inverter IV141 is connected to the write drive line WDRV.

This write drive line circuit 140 supplies the select word line voltage VSS to the write drive line WDRV &lt;127: 0&gt; corresponding to the input address signal, and the non-select word to the other write drive lines WDRV &lt;127: 0&gt;. Supply line voltage VUX. The voltage of this write drive line WDRV is supplied to the word line WLx via the low driver 130.

Subsequently, the write voltage generation circuit 210 that generates the write voltage VWR supplied to the main row decoder 120 will be described. The write voltage generation circuit 210 is included in the voltage generation circuit 200.

FIG. 9 is a circuit diagram of the write voltage generation circuit 210. The write voltage generation circuit 210 has three transistors QN211 to QN213 connected in series between the VCC terminal to which the external power supply voltage VCC is input and the VWR terminal to which the write voltage VWR generated by the write voltage generation circuit 210 is output. Have. These three transistors QN211 to QN213 are diode-connected with the VCC terminal side as the anode and the VWR terminal side as the cathode, respectively. Further, the write voltage generation circuit 210 has capacitors C211 and C212, one end of which is connected to the drain side of the transistors QN211 and QN212, and QN213, and the other end of which is commonly connected, and a limiter circuit (Limiter).

The write voltage generation circuit 210 stores the electric charge supplied from the external power supply voltage VCC in the capacitor C211, and further accumulates this electric charge and the electric charge supplied from the external power supply voltage VCC in the capacitor C212 in a superimposed manner. By discharging the electric charge accumulated in the capacitor C212, a write voltage VWR higher than the external power supply voltage VCC can be obtained. The output of the write voltage generation circuit 210 is limited by the limiter circuit so that the write voltage does not exceed VWR.

Subsequently, the non-selection word line voltage generation circuit 220 that generates the non-selection word line voltage VUX supplied to the write drive line driver 140 will be described.

FIG. 10 is a circuit diagram of the non-selected word line voltage generation circuit 220. The non-selection word line voltage generation circuit 220 includes a MOSFET transistor QP221, a variable resistor R221, and a fixed resistor R222 connected in series between the VCC terminal and the VSS terminal. Further, the operational amplifier OP221 is provided in which the voltage at the connection point of the resistors R221 and R222 is input to the non-inverting input terminal, and a predetermined reference voltage VREF for generating the non-selected word line voltage VUX is input to the inverting input terminal. The output of this operational amplifier OP221 is input to the gate of the transistor QP221. A constant voltage circuit is configured in the non-selection word line voltage generation circuit 220 as described above, and a non-selection word line voltage VUX is generated at the connection node of the transistor QP221 and the variable resistor R221 of this circuit.

With the row circuit having the above configuration, the selected word line voltage VSS is supplied only to the word line WLx selected by the address signal, and the non-selected word line voltage VUX is supplied to the other word line WLs.

Next, a column system circuit including a column system control circuit 100C and a column system voltage generation circuit will be described.

The column system control circuit 100C includes a column decoder 160 that selects the column selection line CSL based on the address signal, and a column selection line CSL selected by the column decoder 160 that writes to the bit line BL with a voltage VWR or a non-selection bit line voltage VUB. The column driver 170 that supplies the data, the sense amplifier / write buffer 180 that applies the voltage pulse required for write operation to this column driver 170, and detects the data read from the memory cell MC, and other column systems. A column system peripheral circuit 190 including circuits necessary for control is included. Each of these configurations will be described below.

First, the column decoder 160 will be described.

FIG. 11 is a circuit diagram of the column decoder 160. The column decoder 160 inputs the column address and selects one of 128 pairs of column selection lines CSLy and CSLby (y = &lt;127: 0&gt;). The column decoder 160 has a circuit as shown in FIG. 11 for each of 128 pairs of column selection lines CSLy and CSLby. As shown in FIG. 11, one column decoder 160 is provided between the NAND gate G161 that inputs an address signal (Address), the level shifter L / S that shifts the output of the NAND gate G161, the VWR terminal, and the VSS terminal. It is composed of an inverter IV161 that receives the output of the level shifter L / S as an input, and an inverter IV162 that receives the output of the inverter IV161 provided between the VWR terminal and the VSS terminal. Here, the outputs of the inverters IV161 and IV162 are column selection lines CSLy and CSLby, respectively.

This column decoder 160 selects a predetermined y based on the address signal, supplies the selected column selection lines CSLy and CSLby with voltages VWR and VSS, respectively, and supplies the non-selected column selection lines CSLy and CSLby with voltage VSS and, respectively. Supply VWR.

Subsequently, the column driver 170 will be described.

FIG. 12 is a circuit diagram of the column driver 170. One pair of 128 pairs of column selection lines CSLy and CSLby (y = &lt;127: 0&gt;) is input to the column driver 170. Eight column drivers 170 are provided for one column decoder 160. As shown in FIG. 12, the column driver 170 is provided between the local data line LDQ &lt;7: 0&gt; and the bit line BLy &lt;7: 0&gt;, and is controlled by the column selection lines CSLy and CSLby, respectively. , QN171 and a transistor QN172 provided between the VUB terminal to which the non-selection bit line voltage VUB is supplied and the bit line BLy &lt;7: 0&gt; and controlled by the column selection line CSLby.

This column driver 170 connects the power line of the local data line LDQ &lt;7: 0&gt; / non-selected bit line voltage VUB and the bit line BLy according to the selected / unselected state of the column selection line CSCy. Here, the voltage of the local data line LDQ &lt;7: 0&gt; is either the write voltage VWR supplied from the sense amplifier / write buffer 180 or the non-selection bit line voltage VUB. As a result, either the write voltage VWR or the non-selection bit line voltage VUB is supplied to the bit line BLy &lt;7: 0&gt;.

By the above column decoder 160 and column driver 170, the write voltage VWR is supplied only to the bit line BLy selected by the address signal, and the non-selection bit line voltage VUB is supplied to the other bit line BLy.

Next, the sense amplifier / write buffer 180 will be described.

FIG. 13 is a circuit diagram of the sense amplifier / write buffer 180. The sense amplifier / write buffer 180 is roughly divided into a sense amplifier 181 and a write buffer 182.

The sense amplifier 181 is a circuit that transmits the data of the memory cell MC appearing on the local data line LDQ &lt;7: 0&gt; to the latch circuit LAT and the data input / output line I / O &lt;7: 0&gt;.

The sense amplifier 181 of FIG. 13 is controlled by the NMOS transistor QN181 controlled by the control signal BLDIS provided between the local data line LDQ and the VSS terminal, and the control signal BLCLAMP provided between the local data line LDQ and the sense node NSEN. Driven by an operational amplifier QN182 (clamp transistor), a NMOS transistor QP181 controlled by a control signal BLPREb provided between the VWR terminal and the sense node NSEN, a capacitor C181 provided between the sense node NSEN and the VSS terminal, and a write voltage VWR. It consists of an operational amplifier OP181 that compares the voltage of the sense node NSEN and the reference voltage VREFSA, and an operational amplifier IV181 in which the output terminals of the operational amplifier OP181 are connected to the input terminals and the latch circuit LAT is connected to the output terminals.

The transistor QN181 turns on when the control signal BLDIS is H and discharges the voltage of the local data line LDQ. Further, the transistor QN182 connects the sense node NSEN and the local data line LDQ, and limits the voltage of the local data line LDQ by the control signal BLCLAMP.

The transistor QP181 has the role of turning on when the control signal BLPREb is activated (L) and precharging the sense node NSEN. The charge charged in the sense node NSEN is discharged to the bit line BL via the local data line LDQ when the transistor QN182 is turned on, and at that time, the discharge rate is determined by the resistance value of the memory cell MC. Therefore, the operational amplifier OP181 compares the potential of the sense node NSEN with the reference voltage VREFSA to determine the data of the selected memory cell MC.

The inverter IV181 includes a MOSFET transistor QP183 and an NMOS transistor QN183 connected in series between the power supply V0 terminal and the ground terminal VSS. This inverter IV181 is activated when the control signal RE = H (REb = L), and transmits the output of the operational amplifier OP181 to the data latch LAT.

The write buffer 182 supplies a reset pulse to the memory cell MC, supplies a write buffer 183 for reset operation to detect the state of the memory cell MC during the reset operation, and supplies a set pulse to the memory cell MC, and also during the set operation. It has a write buffer circuit 184 for set operation that detects the state of the memory cell MC. The write buffer 183 for reset operation and the write buffer 184 for set operation will be described in detail later.

Subsequently, the non-selective bit line voltage generation circuit 230 that generates the non-selective bit line voltage VUB supplied to the column driver 170 will be described.

FIG. 14 is a circuit diagram of the non-selective bit line voltage generation circuit 230. The non-selective bit line voltage generation circuit 230 includes a MOSFET transistor QP231, a variable resistor R231, and a fixed resistor R232 connected in series between the VCC terminal and the VSS terminal. Further, the operational amplifier OP231 is provided in which the voltage of the connection node of the resistors R231 and R232 is input to the non-inverting input terminal and a predetermined reference voltage VREF for generating the non-selected word line voltage VUX is input to the inverting input terminal. The output of this operational amplifier OP231 is input to the gate of the transistor QP231. The non-selective bit line voltage generation circuit 230 is configured with a constant voltage circuit as described above, and a non-selective word line voltage VUB is generated at the connection node of the transistor QP231 and the variable resistor R231 of this circuit.

&lt;Write buffer&gt; Next, the write buffer 182 will be described, but before that, the write buffer 382 as a comparative example will be described.

The write buffer 382 according to the comparative example has a function of detecting a state transition of the memory cell MC in the reverse direction during a set operation / reset operation.

FIG. 21 is a conceptual diagram of a reverse motion detection function at the time of reset operation of the write buffer 382 according to the comparative example.

In the case of the comparative example, the reverse direction detection level common to all memory cell MCs is set in front of the dangerous area above the set level. Therefore, a reset pulse is applied to the memory cell MC in the set state, and even if the state of the memory cell MC changes in the set direction, the memory cell MC is overset before entering the dangerous area. Can be detected, and processing such as stopping the application of the reset pulse can be performed.

FIG. 22 is a conceptual diagram of reverse motion detection during set operation of the write buffer 382 according to the comparative example.

Similarly, in this case as well, the reverse direction detection level common to all memory cell MCs is set in front of the danger area below the reset level. Therefore, even if the memory cell MC is over-reset by applying the set pulse, it can be detected before entering the dangerous area, and processing such as stopping the application of the set pulse can be performed.

FIG. 23 is a circuit diagram of a reset operation write buffer 383 according to a comparative example that realizes the reverse operation detection function shown in FIG. 21. Although only the reset operation write buffer 383 will be described here, the set operation write buffer can also be realized by the same configuration as the reset operation write buffer 383.

The write buffer 383 for reset operation is a reset voltage supply circuit 383a that supplies the reset voltage required for reset operation to the bit line BL, and forward operation detection that detects that the memory cell MC in the set state has transitioned to the reset state. It consists of a circuit 383b and a reverse motion detection circuit 383c that detects that the memory cell MC in the set state has transitioned in the set direction.

The reset voltage supply circuit 383a includes transistors QP184 and QP185 connected in series between the VSEL terminal and node N181 to which a predetermined voltage VSEL is supplied, and transistors QP186, QP187 and QN185 connected in series between the VSEL terminal and the ground wire. Has.

The output terminal of the operational amplifier OP182 is connected to the gate of the transistors QP184 and QP186. The operational amplifier OP182 controls the transistors QP184 and QP186 according to the difference between the voltage VRESET, which is the reference of the reset voltage, and the voltage of the node N181. As a result, the reset voltage supply circuit 383a can stably supply the reset voltage to the bit line BL via the column decoder 160.

The transistors QP185 and QP187 constitute a current mirror circuit CM181 having the transistor QP185 side as an input and the transistor QP187 side as an output. The input of the current mirror circuit CM181 is the cell current Icell flowing through the memory cell MC.

The forward motion detection circuit 383b has transistors QP188 and QN186 connected in series between a V1 terminal and a ground line to which a predetermined voltage V1 is supplied, and transistors QP189 and QN187 also connected in series. Further, the node N182 between the transistors QP188 and QN186 is connected to the non-inverting input terminal, and the node N183 between the transistors QP189 and QN187 has an operational amplifier OP183 connected to the inverting input terminal. The output of the operational amplifier OP183 becomes the flag FLG_RST indicating that the memory cell MC has normally transitioned to the set state.

The transistor QN186, together with the transistor QN185 of the reset voltage supply circuit 383a, constitutes a current mirror circuit CM182 having the transistor QN185 side as an input and the transistor QN186 side as an output. As a result, the cell current Icell flows through the forward motion detection circuit 383b via the current mirror circuit CM181.

The transistor QN187 acts as a current source of the reference current I_rstwd by supplying the reference voltage IREF_RST to the gate. This reference current I_rstwd is a current larger than the cell current Icell flowing through the memory cell MC in the reset state, and is a reference current for the memory cell MC in the set state to normally transition to the reset state.

The transistors QP188 and QP189 constitute a current mirror circuit CM183 having the transistor QP189 side as an input and the transistor QP188 side as an output. As a result, the node N182 has a voltage value determined by the magnitude relationship between the reference current I_rstwd and the cell current Icell. As a result, the flag FLG_RST, which is the output of the operational amplifier OP183, becomes H on condition that I_rstwd&gt; Icell.

The reverse motion detection circuit 383c has transistors QP18A and QN188 connected in series between the V1 terminal and the ground wire, and transistors QP18B and QN189 also connected in series. Further, the node N184 between the transistors QP18A and QN188 is connected to the non-inverting input terminal, and the node N185 between the transistors QP18B and QN189 has an operational amplifier OP384 connected to the inverting input terminal. The output of the operational amplifier OP384 becomes the flag FLG_OVERSET indicating that the state of the memory cell MC has changed in the set direction.

The transistor QN188, together with the transistor QN185 of the reset voltage supply circuit 383a, constitutes a current mirror circuit CM184 having the transistor QN185 side as an input and the transistor QN188 side as an output. As a result, the cell current Icell flows through the reverse motion detection circuit 383c via the current mirror circuit CM181.

The transistor QN189 acts as a current source of the reference current I_setwd by supplying the reference voltage IREF_LIMIT to the gate. This reference current I_setwd is the cell current Icell when the state of the memory cell MC transitions to the reverse detection level, and is the current that serves as a reference for the memory cell MC in the set state being overset.

The transistors QP18A and QP18B constitute a current mirror circuit CM185 having the transistor QP18B side as an input and the transistor QP18A side as an output. As a result, the node N184 becomes a voltage value determined by the magnitude relationship between the reference current I_setwd and the cell current Icell. As a result, the flag FLG_OVERSET, which is the output of the operational amplifier OP183, becomes H on condition that I_setwd &lt;Icell.

FIG. 24 is an operation waveform at the time of the reset operation of the semiconductor storage device according to the comparative example including the write buffer 383 for the reset operation.

Before the reset operation, the non-selected word line voltage VUX is applied to the selected word line WL in advance.

First, at the timing t301, a write voltage VWR is applied to the selected bit line BL.

Subsequently, at the timing t302, the voltage of the selected word line WL is stepped down from the non-selected word line voltage VUX to the selected word line voltage VSS. This causes a VWR-VSS forward bias in the selected memory cell MC. The reset voltage supply circuit 383a takes in the cell current Icell flowing through the selection bit line BL while controlling the node N181 to a constant voltage.

Subsequently, at the timing t303, the state of the selected memory cell MC in the set state begins to transition.

For example, when the state of the selected memory cell MC normally transitions to the reset direction, the cell current Icell eventually becomes lower than the reference current I_rstwd, and the flag FLG_RST of the forward motion detection circuit 383b becomes H. This means that the selected memory cell MC has transitioned to the reset state.

On the other hand, when the state of the selected memory cell MC transitions to the reset direction, the cell current Icell eventually becomes higher than the reference current I_setwd, and the flag FLG_OVERSET of the reverse motion detection circuit 383c becomes H (timing t304). This means that the selected memory cell MC has overset. In this case, the selected bit line BL is discharged by the sense amplifier QN181, and the application of the reset pulse is interrupted.

As described above, by using the reset operation write buffer 383 according to the comparative example, it is possible to prevent the memory cell MC in the set state from entering the dangerous area due to the overset operation.

However, even in the memory cell MC in the same set state, the resistance value of the variable resistance element varies. Therefore, if a common reverse direction detection level is used for all memory cell MCs as in the comparative example, even if the state transitions in the same reverse direction, detection may or may not be possible for each memory cell MC. Cases occur.

Therefore, in the present embodiment, the reverse direction operation is detected by using an appropriate reverse direction detection level for each memory cell MC.

Specifically, the cell current Icell before the application of the voltage pulse is stored in advance as the initial cell current Icell0 (hereinafter referred to as "store operation"), and is M times the initial cell current Icell0 (M is a positive real number). The current is used as the reference currents I_setwd and I_rstwd. In this case, there are the following advantages as compared with the comparative example.

For example, as shown in FIG. 15, consider the case where the memory cells MC1 and MC2, which have variations in the initial cell current Icell0, are overset.

In the case of the comparative example, the reverse detection level common to the memory cells MC1 and MC2 is used. Therefore, it is possible to detect the reverse operation of the memory cell MC2 whose state has reached the reverse detection level due to the overset operation, but as shown by the dotted circle in FIG. 15, the memory cell MC1 has the overset operation. Despite this, the overset operation cannot be detected because the state has not reached the reverse detection level.

On the other hand, in the case of this embodiment, the initial cell currents of the memory cells MC1 and MC2 are Icell0 (1) and Icell0 (2) M times (for example, 1.1 times) the reference currents I_setwd (1) and I_setwd (2). Since it is used as (reverse direction detection level), oversetting operation can be detected regardless of the variation of memory cells MC1 and MC2.

Further, as shown in FIG. 16, consider the case where the memory cells MC1 and MC2, which have variations in the initial cell current Icell0, perform an over-reset operation.

In this case as well, as in the case shown in FIG. 16, as shown by the dotted line circle in the figure, the over-reset operation of the memory cell MC1 which could not be detected in the comparative example is also the initial cell current Icell0 according to the present embodiment. It can be detected by setting the current of M times (for example, 0.9 times) of (1) as the reference current I_rstwd (1) (reverse direction detection level).

As described above, by setting the reverse direction detection level based on the initial cell current of each memory cell MC as in the present embodiment, it is possible to detect the reverse direction operation regardless of the variation in the initial state of the memory cell MC. become. Further, by bringing the above constant M close to 1, it is possible to quickly detect the reverse operation and immediately stop the supply of the voltage pulse.

Next, the write buffer 182 according to the present embodiment that realizes such reverse motion detection will be described.

FIG. 17 is a circuit diagram of a write buffer 183 for reset operation according to the present embodiment. Note that the same components as those of the reset operation write buffer 383 according to the comparative example of FIG. 23 are designated by the same reference numerals.

The write buffer 183 for reset operation includes a reset voltage supply circuit 183a that supplies the reset voltage required for reset operation, a forward operation detection circuit 183b that detects that the memory cell MC in the set state has transitioned to the reset state, and a set state. The memory cell MC consists of a reverse motion detection circuit 183c that detects that the memory cell MC has been overset. The forward motion detection circuit 183b and the reverse motion detection circuit 183c constitute a detection unit.

Of these, the reset voltage supply circuit 183a and the forward motion detection circuit 183b have the same configurations as the reset voltage supply circuit 383a and the forward motion detection circuit 383b of the reset operation write buffer 383 according to the comparative example, respectively.

The reverse motion detection circuit 183c further includes an initial cell current storage circuit 183d with respect to the configuration of the reverse motion detection circuit 383 according to the comparative example.

The initial cell current storage circuit 183d has transistors QP18C and QN18A connected in series between the V1 terminal and the ground line, and transistors QP18D and QN18B similarly connected in series. The transistor QN18A, together with the transistor QN189, constitutes a current mirror circuit CM186 having the transistor QN189 side as an input and the transistor QN18A side as an output. The transistors QP18C and QP18D constitute a current mirror circuit CM187 having the transistor QP18D side as an input and the transistor QP18C side as an output. The transistor QN18B connects the transistor QN18A and the gate in common via the switch SW181, and forms a current mirror circuit together with the transistor QN189. However, the mirror ratio of the transistor QN189 and the transistor QN18B is 1: M (M is 1.1, for example), and M × Icell flows through the transistor QN18B.

Further, the initial cell current storage circuit 183d has a capacitor C182 provided between the gate of the transistor QN18B and the connection point of the switch SW181 and the ground wire to store the initial cell current.

In the reverse motion detection circuit 183c, the node N184 is connected to the non-inverting input terminal instead of the operational amplifier OP384 of the reverse motion detection circuit 383c according to the comparative example, and the node N186 is located between the transistor QP18C and the transistor QN18A. It has an operational amplifier OP184 to which an inverting input terminal is connected. The output of this operational amplifier OP184 is a flag FLG_OVERSET indicating that the memory cell MC has been overset.

Next, the reset operation of the semiconductor storage device using the write buffer 183 for the reset operation will be described.

FIG. 18 is a flowchart of the reset operation of the semiconductor storage device according to the present embodiment, and FIG. 19 is an operation waveform diagram at the time of the reset operation.

First, in step s101, a store operation is performed. This store operation is performed in (I) the reset pulse application cycle immediately before (II) sampling the voltage of the node N185 when the initial cell current Icell0 immediately after the reset pulse is applied to the capacitor C182 via the switch SW181. Two possible operations are to sample the voltage of node N185 when the final cell current Icell is flowing to the capacitor C182 via the switch SW181 as the initial cell current Icell0 in the next reset pulse application cycle. When sampling is complete, switch SW181 off. As a result, the current indicated by M × Icell0 flows through the transistors QP18D and QN18B.

Subsequently, in step s102, a reset pulse is applied to the memory cell MC, and the state detection of the memory cell MC is executed by the forward motion detection circuit 183c and the reverse motion detection circuit 183d. For the reset pulse, all word line WLs are boosted to the non-selected word line voltage VUX in advance (timing t101 in FIG. 19), and then the selected bit line BL is boosted to the write voltage VWR, and only the selected word line WL is used. Is applied by stepping down the selected word line voltage VSS (timing t102 in FIG. 19).

Also, when detecting reverse motion, switch SW181 is turned off. In this case, the charge stored in the capacitor C182, that is, the voltage corresponding to the initial cell current Icell0 is applied to the gate of the transistor QN18B. As a result, the reference current I_setwd corresponding to the initial cell current Icell0 flows through the transistor QN18B. Here, the reference current is I_setwd = M × Icell0. The constant M can be set by the gate width and gate length of the transistors QN189 and QN18B. This reference current I_setwd flows through the transistor QP18C via the current mirror CM187. Further, a cell current Icell flows through the transistor QN18A via the current mirror circuits CM181 and CM184 to CM186.

Subsequently, in step s103 (timing t103 in FIG. 19), when the memory cell MC transitions in the set direction and exceeds the reference current I_setwd (= M × Icell0) (timing t104 in FIG. 19), the flag FLG_OVERSET is set. Become "H". This means that the memory cell MC is overset. Therefore, the application of the reset pulse is immediately stopped (step s106).

However, in the case of (II) above, prior to stopping the application of the reset pulse (step s106), the store operation is executed in step s104, and the initial cell current Icell0 is updated to the current cell current Icell. As a result, when the next reset pulse is applied, the oversetting operation can be detected using the optimum reverse direction detection level.

If the cell current Icell is already in the danger zone at this point, or if it is close to it, the reset operation may be stopped without applying the next reset pulse.

Further, when the state of the memory cell MC gradually shifts to the reset direction and the cell current Icell becomes lower than the reference current I_rstwd, the flag FLG_RST becomes H. This means that the memory cell MC has normally transitioned to the reset state, so the application of the reset pulse is stopped (step s106).

If neither the flags FLG_RST and FLG_OVERSET are set to H, it is determined whether the application time of the predetermined reset pulse has elapsed (step s105), and if not, the processes of steps s102 and s103 are performed. repeat. On the other hand, when the application time of the predetermined reset pulse has elapsed, the application of the reset pulse is temporarily stopped (step s106).

Subsequently, in step s107, a verify operation is executed for the memory cell MC.

Finally, in step s108, the verification result in step s107 is referred to, and if data is normally written to the memory cell MC, the reset operation is terminated. On the other hand, if no data has been written to the memory cell MC, the process returns to step s102 and the above processing is repeatedly executed.

Next, the write buffer 184 for set operation will be described.

FIG. 20 is a circuit diagram of a write buffer 184 for set operation. The same reference numerals are given to the same configurations as those of the reset operation write buffer 183 shown in FIG.

The write buffer 184 for set operation includes a set voltage supply circuit 184a that supplies the set voltage required for set operation, a forward operation detection circuit 184b that detects that the memory cell MC in the reset state has transitioned to the set state, and a reset state. It consists of a reverse motion detection circuit 184c that detects that the memory cell MC of the memory cell MC has been over-reset.

The set voltage supply circuit 184a is a reset voltage except that the reference voltage VSET, which is the reference voltage of the set voltage, is input to the inverting input terminal of the operational amplifier OP182 ́ (corresponding to the operational amplifier OP182 of the write buffer 183 for reset operation). It is the same as the supply circuit 183a.

In the forward motion detection circuit 184b, the node N183 is connected to the non-inverting input terminal of the operational amplifier OP183 ́ (corresponding to the operational amplifier OP183 of the write buffer 183 for reset operation), and the node N182 is connected to the inverting input terminal. It is the same as the forward motion detection circuit 183b except that a predetermined reference voltage IREF_SET is applied to the gate of the transistor QN187 so that the set-level reference current I_setwd flows through the transistor QN187. With this circuit configuration, the output of the operational amplifier OP183 ́ becomes the flag FLG_SET indicating that the memory cell MC in the reset state has transitioned to the set state.

In the reverse motion detection circuit 184c, the node N186 is connected to the non-inverting input terminal of the operational amplifier OP184 ́ (corresponding to the operational amplifier OP184 of the write buffer 183 for reset operation), and the node N184 is connected to the inverting input terminal. And, it is the same as the reverse operation detection circuit 183c except that the constant M is set so that the reference current I_rstwd of the reverse detection level flows through the transistor QN18B ́ (corresponding to the transistor QN18B of the write buffer 183 for set operation). .. With this circuit configuration, the output of the operational amplifier OP184 ́ becomes the flag FLG_OVERRST indicating that the memory cell MC in the reset state has undergone an over-reset operation.

With the write buffer 184 for set operation as described above, the over-reset operation of the memory cell MC can be detected when the cell current Icell becomes lower than M × Icell0.

As described above, according to the present embodiment, since the reverse direction inspection level is set based on the initial cell current of the memory cell MC, the control of the memory cell MC during the overset operation and the overreset operation is optimal for each memory cell MC. It is possible to do it. As a result, the reliability of the memory cell MC can be improved because the reverse operation can be detected immediately regardless of the variation in the state of the memory cell MC. Further, since it is possible to suppress the prolongation of the reverse operation of the memory cell MC, it is possible to shorten the processing time associated with the write operation.

[Other] Although the embodiments of the invention have been described above, the present invention is not limited to these, and various modifications, additions, and the like can be made without departing from the spirit of the invention.

100: Memory cell array core, 110: Memory cell array, 120: Main row decoder, 130: Row driver, 140: Write drive line driver, 150: Row peripheral circuit, 160 Column decoder, 170 Column driver, 180 Sense amplifier / write buffer, 181 Sense amplifier, 182 Write buffer, 183 Write buffer for reset operation, 184 Write buffer for set operation, 190 Column system peripheral circuit, 200 Voltage generation circuit, 210 Write voltage generation circuit, 220 Non-selected word line voltage generation circuit, 230 Non Selected bit line voltage generation circuit.