Display device, method for manufacturing display device, and SOI substrate

0001The present invention relates to an SOI (Silicon on Insulator) substrate and a display device manufactured by the substrate. In particular, it relates to a bonded SOI technique, and relates to an SOI substrate in which a single crystal or polycrystalline semiconductor layer is bonded to a substrate having an insulating surface such as glass, and a display device manufactured by using the SOI substrate.

0002In recent years, with the dramatic progress of VLSI technology, attention has been paid to the SOI structure that can realize high speed and low power consumption. This technique is a technique for forming an active region (channel forming region) of a field effect transistor (FET), which has been conventionally formed of bulk single crystal silicon, into a single crystal silicon thin film. It is known that when a MOS field effect transistor is manufactured using an SOI structure, the parasitic capacitance can be reduced as compared with the case where a conventional bulk single crystal silicon substrate is used, which is advantageous for speeding up.

0003As a method for manufacturing a conventional SOI substrate, a hydrogen ion implantation peeling method is known (see, for example, Patent Document 1). In the hydrogen ion implantation peeling method, a microbubble layer is formed at a predetermined depth from the surface by implanting hydrogen ions into a silicon wafer, and the microbubble layer is used as a cleavage plane to form a thin single crystal on another silicon wafer. The crystalline silicon layer (SOI layer) is bonded. Furthermore, in addition to heat treatment for peeling off the SOI layer, the oxide film is removed after forming an oxide film on the SOI layer by heat treatment in an oxidizing atmosphere, and then reduction at 1000 ° C to 1300 ° C. It is said that it is necessary to increase the bonding strength by performing heat treatment in a sexual atmosphere.

0004An example of a semiconductor device using an SOI substrate is known by the applicant (see Patent Document 2). In this case as well, it is disclosed that a heat treatment of 1050 ° C to 1150 ° C is required to remove levels and defects caused by stress in the SOI layer.<patcit num="1"><text>International Publication No. 00/24059 Pamphlet</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2000-12864</text></patcit>

<p num="0005"> In the conventional method for manufacturing an SOI substrate, it is necessary to heat-treat at a high temperature of 1000 ° C. or higher in order to strengthen the bonding strength of the SOI layer. Therefore, it has been difficult to form an SOI layer on a substrate having a heat resistant temperature of about 600 ° C., such as a glass substrate used for manufacturing a display device such as a liquid crystal panel. Even if the SOI layer is provided on the glass substrate by the hydrogen ion implantation peeling method, there is a problem that the bonding strength of the SOI layer is weak because the high temperature heat treatment cannot be applied. Furthermore, in the SOI substrate using the conventional hydrogen ion implantation peeling method, one silicon wafer is bonded to one silicon wafer and one of the silicon wafers is thinned to obtain an SOI structure. Was there. Therefore, it depends on the size of the silicon wafer, and it is difficult to increase the area.</p><p num="0006"> In view of the above problems, one object of the present invention is to increase the area of the SOI substrate and improve the productivity of manufacturing a display device using the SOI substrate. Another purpose is to improve the performance of the display device.</p>

<p num="0007"> The gist is to manufacture a display device by joining a plurality of single crystal semiconductor layers on a substrate having an insulating surface and forming a circuit including a transistor from the single crystal semiconductor layers.</p><p num="0008"> As the single crystal semiconductor layer, one peeled from the single crystal semiconductor substrate is applied. A polycrystalline semiconductor substrate may be applied instead of the single crystal semiconductor substrate. The single crystal semiconductor layer is divided into a size corresponding to one display panel (panel size), specifically, an area including one panel, and is bonded onto a substrate having an insulating surface.</p><p num="0009"> When transposing a plurality of single crystal semiconductor layers from a single crystal semiconductor substrate, a plurality of single crystal semiconductor layers may belong to one alignment marker.</p><p num="0010"> One of the present invention is selected from a plurality of single crystal semiconductor layers by joining a plurality of single crystal semiconductor layers divided into an area including one panel via an insulating layer on a substrate having an insulating surface. This is a method for manufacturing a display device that forms a circuit including a transistor by using individual single crystal semiconductor layers by simultaneously exposing a group of semiconductors to transfer and form a circuit pattern.</p><p num="0011"> One of the present invention is a silicon oxide layer in which a plurality of single crystal semiconductor layers divided into an area including one panel are formed on a substrate having an insulating surface by a chemical vapor deposition method using organic silane as a raw material gas. A circuit including a transistor is formed by using each single crystal semiconductor layer by simultaneously exposing a group selected from a plurality of single crystal semiconductor layers to transfer and form a circuit pattern. This is a method for manufacturing a display device.</p><p num="0012"> Further, in one of the present inventions, a group selected from a plurality of single crystal semiconductor layers may be a group that can be exposed at one time by an exposure device, that is, a range that the exposure device exposes at one time. Further, a plurality of the single crystal semiconductor layers may belong to one alignment marker in one group.</p><p num="0013"> Further, one of the present inventions has a circuit including a transistor on a substrate having an insulating surface, the transistor has a channel forming region including a single crystal semiconductor, and the substrate has a channel forming region of the transistor and the insulating surface. The display device is provided with a silicon oxide layer formed by a chemical vapor deposition method using an organic silane as a raw material gas.</p><p num="0014"> Further, one of the present inventions includes tetraethoxysilane, trimethylsilane, tetramethylsilane, tetramethylcyclotetrasiloxane, octamethylcyclotetrasiloxane, hexamethyldisilazane, triethoxysilane, and trisdimethylaminosilane as organic silanes. Can be used.</p><p num="0015"> Further, in one of the present inventions, as a substrate having an insulating surface, aluminosilicate glass, aluminosilicate glass, or barium borosilicate glass, quartz substrate, sapphire substrate, or ceramic substrate can be used.</p><p num="0016"> In the present specification, the display device refers to a device using a display element such as a liquid crystal element, a light emitting element, or an electrophoresis element, that is, an image display device. In addition, a module or TAB tape to which an external input terminal (FPC: Flexible Printed Circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to the display panel (liquid crystal panel, light emitting panel). All modules with a printed wiring board at the end of TCP or TCP, or modules with ICs (integrated circuits) and CPUs (central processing units) directly mounted on the display panel by the COG (Chip On Glass) method are also display devices. It shall include.</p>

<p num="0017"> By applying the present invention, it is possible to increase the area of the SOI substrate, and it is possible to improve the productivity in manufacturing a display device using the SOI substrate. In addition, the performance of the display device using the SOI substrate can be improved.</p>

0018Embodiments of the present invention will be described below with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention is not limited to the following description, and its form and details can be variously changed without departing from the gist and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, reference numerals indicating the same thing may be commonly used between different drawings.

0019(Embodiment 1) The SOI substrate according to the present embodiment is formed by transposing a single crystal semiconductor substrate to a dissimilar substrate (hereinafter, also referred to as base substrate). Hereinafter, one embodiment of the SOI substrate and the manufacturing method thereof according to the present embodiment will be described.

00201 (A) and 1 (B) show an example of a perspective view showing the configuration of the SOI substrate according to the present invention. Further, FIGS. 2 (A) and 2 (B) and FIGS. 3 (A) and 3 (B) show examples of cross-sectional views of the SOI substrate according to the present invention.

0021In FIGS. 1 (A), 2 (A), and (B), in the SOI substrate 100, an insulating layer 120 and a single crystal semiconductor layer 130 (hereinafter, also referred to as an SOI layer) are sequentially arranged on one surface of the base substrate 110. It has a structure in which a plurality of laminated bodies are provided. The SOI layer 130 is provided on the base substrate 110 via the insulating layer 120, and forms a so-called SOI structure. That is, a plurality of SOI layers 130 are provided on one base substrate 110 to form one SOI substrate 100. Note that FIG. 2 shows an example in which two SOI layers 130 are provided on one base substrate 110 for convenience.

0022The SOI layer 130 is a single crystal semiconductor, and single crystal silicon is typically applied. In addition, a crystalline semiconductor layer which is a compound semiconductor such as silicon, germanium, gallium arsenide, or indium phosphide, which can be peeled from a single crystal semiconductor substrate or a polycrystalline semiconductor substrate by using a hydrogen ion injection peeling method, can also be applied. it can.

0023One of the features of the SOI substrate according to the present invention is that the size of the SOI layer 130 constituting the SOI substrate is set to a desired panel size. The SOI layer 130 is divided into an area including one panel having a desired panel size. The term "panel size" as used herein refers to the combined size of the display portion of the display panel and the frame portion (non-display portion) around the display unit. In addition, "size" shall indicate the area. In the SOI substrate according to the present invention, a plurality of SOI layers 130 divided into an area including one panel having a desired panel size are bonded to the base substrate 110 via an insulating layer 120.

0024The panel size may be appropriately selected depending on the intended use, and for example, a small and medium-sized panel size of less than 10 inches diagonally can be used. When a mobile phone is assumed as a small and medium-sized panel, for example, the size of the display unit (screen size) is known to be 2.2 inches (56 mm) diagonally, 2.4 inches (61 mm) diagonally, 2.6 inches (66 mm) diagonally, and the like. ing. When these panel sizes are used, the screen size may be set in consideration of the size of the frame portion around the display unit (screen frame size).

0025The shape of the SOI layer 130 is not particularly limited, but a rectangular shape (including a square) facilitates processing and is preferable because it can be bonded to the base substrate 110 with a good degree of integration. Further, in the case of a panel of a display device such as a display, it is preferable that the aspect ratio of the SOI layer 130 is 4: 3. By setting the SOI layer 130 to the area including one desired panel, that is, about the desired panel size, when various display devices are manufactured by incorporating the display panel manufactured using the completed SOI substrate, each panel is used. It becomes possible to manage the yield. Further, when the individual panels are divided, it is possible to prevent the element from being damaged. Therefore, the yield can be improved. Further, by dividing the SOI layer 130 into an area including one desired panel, that is, by setting the SOI layer 130 to a desired panel size, the elements of each panel can be formed by one SOI layer, which is a characteristic. It becomes possible to suppress the variation of.

0026As the base substrate 110, a substrate having an insulating surface or an insulating substrate is used. Specific examples thereof include various glass substrates used for the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, quartz substrates, ceramic substrates, and sapphire substrates. It is preferable to use a glass substrate as the base substrate 110. For example, a large-area mother glass substrate called the 6th generation (1500 mm × 1850 mm), the 7th generation (1870 mm × 2200 mm), and the 8th generation (2200 mm × 2400 mm) can be used. Use. By using a large-area mother glass substrate as the base substrate 110 and manufacturing the SOI substrate by applying the present invention, it is possible to realize a large area of the SOI substrate. Further, on a base substrate which is a substrate having an insulating surface, a plurality of SOI layers divided into an area including one panel, specifically, a plurality of SOI layers divided into a desired panel size are formed via an insulating layer. Since each SOI layer of the bonded SOI substrate has a desired panel size, the number of display panels (chamfered number) that can be manufactured with one base substrate can be increased. Therefore, it is possible to improve the productivity of the final product (display device) manufactured by incorporating the display panel.

0027An insulating layer 120 is provided between the base substrate 110 and the SOI layer 130. The insulating layer 120 may have a single-layer structure or a laminated structure, but the surface to be bonded to the base substrate 110 (hereinafter, also referred to as bonding surface) has a smooth surface and is made to be a hydrophilic surface. Hereinafter, in the present specification, the layer formed on the bonding surface is also referred to as a bonding layer. FIG. 2A shows an example in which the bonding layer 122 is formed as the insulating layer 120. A silicon oxide layer is suitable as the bonding layer 122 having a smooth surface and capable of forming a hydrophilic surface. In particular, a silicon oxide layer produced by a chemical vapor deposition method using organic silane as a raw material gas is preferable. As an organic silane, tetraethoxysilane (abbreviation; TEOS: chemical formula Si (OC)₂H₅)₄), Tetramethylsilane (TMS: Chemical formula Si (CH)₃)₄), Trimethylsilane ((CH)₃)₃SIH), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), Triethoxysilane (SiH (OC))₂H₅)₃), Trisdimethylaminosilane (SiH (N (CH))₃)₂)₃) And other silicon-containing compounds can be used.

0028The bonding layer 122 having a smooth surface and forming a hydrophilic surface is preferably provided in a film thickness range of 5 nm to 500 nm. By setting the film thickness of the bonding layer 122 within the above range, it is possible to smooth the surface roughness of the surface to be filmed and to secure the smoothness of the growth surface of the film. In addition, distortion with the substrate to be joined (base substrate 110 in FIG. 2A) can be alleviated. The base substrate 110 may also be provided with the same silicon oxide layer as the bonding layer 122. The SOI substrate according to the present invention is formed by using organic silane as a raw material gas on one or both of the surfaces forming the bond when the SOI layer 130 is bonded to the substrate having an insulating surface or the base substrate 110 which is an insulating substrate. A strong bond can be formed by providing a bonding layer made of a filmed silicon oxide layer.

0029FIG. 2B shows an example in which the insulating layer 120 has a laminated structure. Specifically, an example of forming a laminated structure of the bonding layer 122 and the nitrogen-containing insulating layer 124 as the insulating layer 120 is shown. In order to form a bonding layer 122 on the bonding surface with the base substrate 110, a nitrogen-containing insulating layer 124 is provided between the SOI layer 130 and the bonding layer 122. The nitrogen-containing insulating layer 124 is formed in a single-layer structure or a laminated structure by using a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide nitride layer. For example, a silicon oxynitride layer and a silicon nitride layer can be laminated from the SOI layer 130 side to form a nitrogen-containing insulating layer 124. The bonding layer 122 is provided to form a bond with the base substrate 110, whereas the nitrogen-containing insulating layer 124 is provided to prevent impurities such as movable ions and moisture from diffusing and contaminating the SOI layer 130. Is preferable.

0030The silicon oxide layer has a higher oxygen content than nitrogen as its composition, and the Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering (HFS) methods are used. When measured using, the concentration range is 50 atomic% to 70 atomic% for oxygen, 0.5 atomic% to 15 atomic% for nitrogen, 25 atomic% to 35 atomic% for Si, and 0.1 atomic% to 10 atomic% for hydrogen. It means what is included in the range. Further, the silicon nitride layer indicates a layer having a higher nitrogen content than oxygen as its composition, and when measured using RBS and HFS, the concentration range is 5 atomic% to 30 atomic% of oxygen. Nitrogen is contained in the range of 20 atomic% to 55 atomic%, Si is contained in the range of 25 atomic% to 35 atomic%, and hydrogen is contained in the range of 10 atomic% to 30 atomic%. However, assuming that the total number of atoms constituting silicon oxide or silicon nitride oxide is 100 atomic%, the content ratios of nitrogen, oxygen, Si and hydrogen shall be included in the above range.

00311 (B) and 3 (A) and 3 (B) show an example of forming an insulating layer 150 including a bonding layer on the base substrate 110. The insulating layer 150 may have a single-layer structure or a laminated structure, but the joint surface with the SOI layer 130 has a smooth surface and forms a hydrophilic surface. A barrier layer is preferably provided between the base substrate 110 and the bonding layer in order to prevent the diffusion of movable ions such as alkali metal or alkaline earth metal from the glass substrate used as the base substrate 110. ..

0032FIG. 3A shows an example in which a laminated structure of a barrier layer 152 and a bonding layer 154 is formed as the insulating layer 150. As the bonding layer 154, a silicon oxide layer similar to that of the bonding layer 122 may be provided. Further, the SOI layer 130 may be appropriately provided with a bonding layer. FIG. 3A shows an example in which the bonding layer 122 is also provided on the SOI layer 130. With such a configuration, when the base substrate 110 and the SOI layer 130 are joined, the joining layers form a joining, so that a stronger joining can be formed. The barrier layer 152 is formed in a single-layer structure or a laminated structure by using a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, or a silicon nitride layer. Preferably, it is formed by using an insulating layer containing nitrogen.

0033FIG. 3B shows an example in which a bonding layer is provided on the base substrate 110. Specifically, the base substrate 110 is provided with a laminated structure of a barrier layer 152 and a bonding layer 154 as an insulating layer 150. Further, the SOI layer 130 is provided with a silicon oxide layer 126. When the SOI layer 130 is bonded to the base substrate 110, the silicon oxide layer 126 forms a bond with the bonding layer 154. The silicon oxide layer 126 is preferably formed by a thermal oxidation method. Further, a chemical oxide can be applied as the silicon oxide layer 126. The chemical oxide can be formed, for example, by treating the surface of the semiconductor substrate with ozone-containing water. Chemical oxides are preferable because they are formed reflecting the flatness of the surface of the semiconductor substrate.

0034Next, a method for manufacturing the SOI substrate according to the present invention will be described. Here, an example of the method for manufacturing the SOI substrate shown in FIG. 2 (A) will be described with reference to FIGS. 4 to 6.

0035First, the semiconductor substrate 101 is prepared (see FIGS. 4 (A) and 6 (A)). As the semiconductor substrate 101, a commercially available semiconductor substrate, for example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate may be used. Specific examples thereof include semiconductor substrates such as silicon substrates and germanium substrates, and compound semiconductor substrates such as gallium arsenide and indium phosphide. Typical commercially available silicon substrates are 5 inches (125 mm) in diameter, 6 inches (150 mm) in diameter, 8 inches (200 mm) in diameter, and 12 inches (300 mm) in diameter, and the shape is circular. Most. The film thickness can be appropriately selected up to about 1.5 mm.

0036Next, an electric field-accelerated ion 104 is injected from the surface of the semiconductor substrate 101 to form an ion doping layer 103 in a region having a predetermined depth (see FIGS. 4 (A) and 6 (A)). In addition, the injection of ions in the present specification refers to irradiating accelerated ions to include the elements constituting the irradiated ions in the semiconductor substrate. The ion-doping layer is a region in which a semiconductor substrate is irradiated with ions and weakened so as to have minute cavities by the irradiation of ions. Hereinafter, the "ion-doping layer" is referred to as a "separation layer". The SOI layer can be formed on the base substrate by dividing the separation layer by a subsequent heat treatment. The irradiation of ions 104 is performed in consideration of the film thickness of the SOI layer that is later transposed to the base substrate. Preferably, the thickness of the SOI layer is 5 nm to 500 nm, more preferably 10 nm to 200 nm. The acceleration voltage and the amount of ion dose when irradiating the ions are appropriately selected in consideration of the film thickness of the SOI layer to be transposed. As the ion 104, halogen ions such as hydrogen, helium, and fluorine can be used. As the ion 104, it is preferable to irradiate an ion species composed of one atom or a plurality of the same atoms generated by plasma-exciting a source gas selected from hydrogen, helium, or a halogen element. When injecting hydrogen, H⁺, H₂⁺, H₃⁺In addition to containing ions, H₃⁺It is preferable to increase the ratio of ions because the irradiation efficiency of ions can be increased and the irradiation time can be shortened. Further, with such a configuration, peeling can be easily performed.

0037In addition, in order to form the separation layer 103 at a predetermined depth, it may be necessary to irradiate the ion 104 under high dose conditions. At this time, the surface of the semiconductor substrate 101 becomes rough depending on the conditions. Therefore, a silicon nitride layer, a silicon oxide layer, or the like may be provided as a protective layer on the surface of the semiconductor substrate to be irradiated with ions in a film thickness range of 50 nm to 200 nm.

0038Next, the bonding layer 122 is formed on the semiconductor substrate 101 (see FIGS. 4 (B) and 6 (B)). The bonding layer 122 is formed on a surface on which the semiconductor substrate 101 forms a bond with the base substrate. As the bonding layer 122 formed here, a silicon oxide layer formed by a chemical vapor deposition method using organic silane as a raw material gas as described above is preferable. In addition, a silicon oxide layer formed by a chemical vapor deposition method using silane as a raw material gas can also be applied. In the film formation by the chemical vapor deposition method, a temperature at which degassing does not occur from the separation layer 103 formed on the semiconductor substrate 101 is applied. For example, a film formation temperature of 350 ° C. or lower is applied. For the heat treatment for peeling the SOI layer from a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate, a heat treatment temperature higher than the film formation temperature by the chemical vapor deposition method is applied.

0039Next, the semiconductor substrate 101 is processed into a desired size and shape (see FIGS. 4 (C) and 6 (C)). Specifically, it is processed so as to have a desired panel size. FIG. 6C shows an example in which the circular semiconductor substrate 101 is divided to form the rectangular semiconductor substrate 102. At this time, the bonding layer 122 and the separating layer 103 are also separated. That is, a semiconductor substrate 102 having a desired panel size, the separation layer 103 formed at a predetermined depth, and the bonding layer 122 formed on the surface (bonding surface with the base substrate) can be obtained.

0040The semiconductor substrate 102 is preferably set to the panel size of various display devices. The panel size may be appropriately selected depending on the final product to be incorporated, and may be, for example, a panel size of a small or medium-sized panel having a diagonal of less than 10 inches. For example, when applied to a mobile phone with a screen size diagonal of 2.4 inches, the panel size is set to 2.4 inches diagonally with the screen size in consideration of the screen frame size. Further, the shape of the semiconductor substrate 102 may be appropriately selected depending on the application such as the final product, but when applied to a display device such as a display, it is preferably a rectangle having an aspect ratio of about 3: 4. Further, it is preferable that the semiconductor substrate 102 has a rectangular shape because it can be easily processed in a later manufacturing process and can be efficiently cut out from the semiconductor substrate 101. For the division of the semiconductor substrate 101, a cutting device such as a dicer or a wire saw, laser cutting, plasma cutting, electron beam cutting, or any other cutting means can be used.

0041The process order until the bonding layer is formed on the surface of the semiconductor substrate can be changed as appropriate. FIGS. 4 and 6 show an example in which a separation layer is formed on a semiconductor substrate, a bonding layer is formed on the surface of the semiconductor substrate, and then the semiconductor substrate is processed into a desired panel size. On the other hand, for example, after processing a semiconductor substrate to a desired panel size, a separation layer is formed on the semiconductor substrate of the desired panel size, and a bonding layer is formed on the surface of the semiconductor substrate of the desired panel size. You can also.

0042Next, the base substrate 110 and the semiconductor substrate 102 are bonded together. In FIG. 5A, the surface of the base substrate 110 and the semiconductor substrate 102 on which the bonding layer 122 is formed is brought into close contact with each other, the base substrate 110 and the bonding layer 122 are bonded, and the base substrate 110 and the semiconductor substrate 102 are attached. An example of matching is shown. It is preferable that the surface (joint surface) on which the joint is formed is sufficiently cleaned. A bond is formed by bringing the base substrate 110 and the bond layer 122 into close contact with each other. Van der Waals force acts on this bond, and by pressing the base substrate 110 and the semiconductor substrate 102 together, it is possible to form a strong bond by hydrogen bonding.

0043In addition, the joint surface may be activated in order to form a good bond between the base substrate 110 and the joint layer 122. For example, one or both of the surfaces forming the junction are irradiated with an atomic beam or an ion beam. When an atomic beam or an ion beam is used, an inert gas neutral atom beam such as argon or an inert gas ion beam can be used. In addition, the joint surface can be activated by plasma irradiation or radical treatment. Such a surface treatment makes it easy to form a bond between dissimilar materials even at a temperature of 400 ° C. or lower.

0044Further, after the base substrate 110 and the semiconductor substrate 102 are bonded to each other via the bonding layer 122, it is preferable to perform a heat treatment or a pressure treatment. It is possible to improve the joint strength by performing heat treatment or pressure treatment. The temperature of the heat treatment is preferably equal to or lower than the heat resistant temperature of the base substrate 110. The pressurization process is performed so that the pressure is applied in the direction perpendicular to the joint surface, and the pressure resistance of the base substrate 110 and the semiconductor substrate 102 is taken into consideration.

0045Next, heat treatment is performed to peel off a part of the semiconductor substrate 102 from the base substrate 110 with the separation layer 103 as a cleavage plane (see FIG. 5 (B)). The temperature of the heat treatment is preferably equal to or higher than the film formation temperature of the bonding layer 122 and lower than the heat resistant temperature of the base substrate 110. For example, by performing the heat treatment at 400 ° C to 600 ° C, the volume of the minute cavities formed in the separation layer 103 changes, and it becomes possible to cleave along the separation layer 103. Since the bonding layer 122 is bonded to the base substrate 110, the SOI layer 130 having the same crystallinity as the semiconductor substrate 102 remains on the base substrate 110. Cleavage in the present specification is a separation layer weakened to have minute cavities by irradiating with halogen ions such as hydrogen, helium, or fluorine, and a part of the semiconductor substrate is peeled off. Refers to forming an SOI layer on a base substrate. The cleavage surface refers to a separation surface (a surface opposite to the base substrate) of the SOI layer provided on the base substrate by peeling.

0046As described above, the SOI structure in which the SOI layer 130 is provided on the base substrate 110 via the bonding layer 122 is formed. One of the features of the SOI substrate according to the present invention is that a plurality of SOI layers are provided on one base substrate via a bonding layer. For example, a desired number of semiconductor substrates 102 having a separation layer formed and a bonding layer formed on the surface and processed to a desired panel size are prepared. Then, as shown in FIG. 8 (A), a desired number of semiconductor substrates 102 are attached to the base substrate 110, and then the SOI substrates are collectively peeled off by heat treatment as shown in FIG. 8 (B) to form the SOI substrate. Can be manufactured. It is also possible to manufacture an SOI substrate by repeating the steps of laminating one or a certain number of semiconductor substrates 102 and peeling them without performing the peeling by heat treatment all at once.

0047Further, it is preferable that the semiconductor substrate 102 is regularly arranged on the base substrate 110 because the subsequent steps are facilitated. For example, by using a control device such as a CCD camera or a computer, it becomes possible to regularly arrange and bond the semiconductor substrates 102. Further, a marker or the like may be formed on the base substrate 110 or the semiconductor substrate 102 to perform alignment. In FIG. 8, the adjacent SOI layers are configured to have a certain gap, but they may be laid out so as not to leave a gap as much as possible.

0048The SOI layer obtained by peeling is preferably subjected to chemical mechanical polishing (CMP) in order to flatten the surface thereof. Further, the surface of the SOI layer may be flattened by irradiating the surface of the SOI layer with a laser beam without using a physical polishing means such as CMP. When irradiating the laser beam, it is preferable to perform it in a nitrogen atmosphere having an oxygen concentration of 10 ppm or less. This is because the surface of the SOI layer may be roughened when the laser beam is irradiated in an oxygen atmosphere. Further, CMP or the like may be performed for the purpose of thinning the obtained SOI layer.

0049Further, FIG. 7 shows a process of forming a SOI layer by providing a bonding layer on the base substrate side. Here, an example of the method for manufacturing the SOI substrate shown in FIG. 3 (B) will be described.

0050FIG. 7A shows a process of irradiating the semiconductor substrate 101 on which the silicon oxide layer 126 is formed with the ions 104 accelerated by an electric field to form the separation layer 103 at a predetermined depth. The silicon oxide layer 126 can be formed by a CVD method or a sputtering method, but is preferably formed by a thermal oxidation method. Further, as the silicon oxide layer 126, a chemical oxide formed by treating the surface of the semiconductor substrate with ozone-containing water or the like may be applied. As the semiconductor substrate 101, the same semiconductor substrate 101 as in the case of FIG. 4A described above can be applied. Further, the irradiation of halogen ions such as hydrogen, helium or fluorine is the same as in the case of FIG. 4 (A) described above. By forming the silicon oxide layer 126 on the surface of the semiconductor substrate 101, it is possible to prevent the surface of the semiconductor substrate from being damaged during irradiation with ions and the flatness from being impaired.

0051FIG. 7B shows a step of forming a bond by bringing the base substrate 110 on which the barrier layer 152 and the bonding layer 154 are formed and the surface of the semiconductor substrate 102 on which the silicon oxide layer 126 is formed into close contact with each other. A bond is formed by bringing the bond layer 154 on the base substrate 110 and the silicon oxide layer 126 of the semiconductor substrate 102 into close contact with each other. The semiconductor substrate 102 is a semiconductor substrate 101 in which the separation layer 103 is formed and the silicon oxide layer 126 is formed on the surface thereof, and the semiconductor substrate 101 is processed into a desired panel size. The barrier layer 152 may be formed in a single layer structure or a laminated structure by using a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer or a silicon nitride layer by a CVD method or a sputtering method. The bonding layer 154 may form a silicon oxide layer similar to the bonding layer 122 described above.

0052Then, as shown in FIG. 7C, a part of the semiconductor substrate 102 is peeled off. The heat treatment for peeling is performed in the same manner as in the case of FIG. 5 (B), and the separation layer 103 is peeled from the base substrate 110 with the separation layer 103 as a cleavage plane. After the peeling treatment, the SOI layer 130 having the same crystallinity as the semiconductor substrate 102 remains on the base substrate 110, and the SOI substrate as shown in FIG. 1 (B) can be obtained. The SOI substrate shown in FIG. 7 has a structure in which the SOI layer 130 is provided on the base substrate 110 via the barrier layer 152, the bonding layer 154, and the silicon oxide layer 126. After the peeling treatment, in order to flatten or thin the obtained SOI layer, CMP or laser beam irradiation may be performed.

0053According to the method for manufacturing an SOI substrate according to the present invention, it is possible to obtain an SOI layer 130 having a strong adhesive force at a joint even if the base substrate 110 has a heat resistant temperature of 600 ° C. or less, such as a glass substrate. In addition, since a temperature process of 600 ° C or less may be applied, various glass substrates used for the electronic industry called non-alkali glass such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used as the base substrate 110. Can be applied. Of course, it is also possible to apply a ceramic substrate, a sapphire substrate, a quartz substrate, or the like. That is, the single crystal semiconductor layer can be formed on a substrate having a side of more than 1 meter. A display device such as a liquid crystal display or a semiconductor integrated circuit can be manufactured by using such a large area substrate.

0054Further, the SOI substrate according to the present invention has a configuration in which a panel-sized SOI layer is provided on the base substrate. By doing so, a desired display panel can be formed with one SOI layer, and the yield can be improved. Further, since a desired display panel can be formed by one SOI layer, it is possible to suppress variations in the elements forming the display panel.

0055Further, even if a defect occurs in the crystal of the SOI layer when the SOI layer is transposed and formed on the base substrate, the yield can be controlled for each panel. Further, since the SOI layer is transposed to the base substrate in a panel size, stress such as stress can be alleviated even when dissimilar materials are bonded together, and the yield can be improved.

0056Further, the SOI substrate according to the present invention can realize a large area by providing a plurality of SOI layers on the base substrate. Therefore, it is possible to manufacture a large number of display panels in one manufacturing process, and it is possible to improve the productivity of the final product manufactured by incorporating the display panels.

0057A display device can be manufactured using the SOI substrate manufactured as described above. For example, FIG. 9 shows a schematic diagram of an example of the display device according to the present invention. Here, an example of forming a liquid crystal display device is shown. FIG. 9 (A) shows an example of a schematic view of the upper surface, FIG. 9 (B) shows an example of a cross-sectional view in the line segment OP of FIG. 9 (A), and FIG. 9 (C) is a perspective view of the display device. An example is shown.

0058The liquid crystal display device according to the present embodiment includes a display unit 620 provided on the first substrate 600, a first drive circuit unit 630, and a second drive circuit unit 650. The display unit 620, the first drive circuit unit 630, and the second drive circuit unit 650 are sealed between the first substrate 600 and the second substrate 690 by the sealing material 680. Further, on the first substrate 600, a terminal area 670 is provided in which an external input terminal for transmitting an external signal or potential is connected to the first drive circuit unit 630 and the second drive circuit unit 650.

0059As shown in FIG. 9B, the display unit 620 is provided with a pixel circuit unit 628 having a transistor. Further, the first drive circuit unit 630 is provided with a peripheral circuit unit 638 having a transistor. An insulating layer 602, an insulating layer 604, and a bonding layer 606 that function as an underlying insulating layer are sequentially laminated between the first substrate 600 and the pixel circuit unit 628 and the peripheral circuit unit 638. An insulating layer 608 and an insulating layer 609 functioning as an interlayer insulating layer are provided on the pixel circuit unit 628 and the peripheral circuit unit 638, or an upper layer thereof. The source electrode or drain electrode of the transistor formed in the pixel circuit unit 628 is electrically connected to the pixel electrode 660 via an opening formed in the insulating layer 609. A circuit using a transistor is integrated in the pixel circuit unit 628, but here, for convenience, a cross-sectional view of one transistor is shown. Similarly, a circuit using transistors is also integrated in the peripheral circuit section 638, but a cross-sectional view of the two transistors is shown for convenience.

0060On the pixel circuit unit 628 and the peripheral circuit unit 638, an alignment film 682 formed so as to cover the pixel electrode 660 and a liquid crystal layer 684 sandwiched between the alignment film 687 are provided. The distance (cell gap) of the liquid crystal layer 684 is controlled by the spacer 686. A second substrate 690 is provided on the alignment film 687 via a counter electrode 688 and a color filter 689. The first substrate 600 and the second substrate 690 are fixed by the sealing material 680.

0061Further, a polarizing plate 692 is arranged on the outside of the second substrate 690. In this embodiment, in order to show a reflective liquid crystal display device, an example in which a polarizing plate is provided on the second substrate 690 is shown. For example, in the case of a transmissive liquid crystal display device, polarizing plates may be provided on both the first substrate 600 and the second substrate 690.

0062Further, a terminal electrode 674 is provided in the terminal region 670. The terminal electrode 674 is electrically connected to the external input terminal 678 by an anisotropic conductive layer 676.

0063Next, an example of the manufacturing method of the liquid crystal display device shown in FIG. 9 will be described.

0064First, the SOI substrate according to the present invention is prepared (see FIG. 11 (A)). Here, an example of applying an SOI substrate similar to that shown in FIG. 2 (A) is shown.

0065A plurality of SOI layers 610 are provided on the substrate 600, which is a base substrate, via an insulating layer 602, an insulating layer 604, and a bonding layer 606. The SOI layer 610 is processed to the desired panel size. Here, for convenience, an example in which a display device is manufactured using the panel forming region 610b including one SOI layer will be described, but it is possible to manufacture the display device in the adjacent panel forming region 610a at the same time.

0066As the substrate 600, a substrate having an insulating surface or an insulating substrate is used. For example, various glass substrates used for the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, quartz substrates, ceramic substrates, sapphire substrates, and the like are used. Here, it is assumed that a glass substrate is used.

0067The insulating layer 602 and the insulating layer 604 are provided to prevent the diffusion of movable ions such as alkali metal or alkaline earth metal from the glass substrate. Specifically, an insulating layer similar to the above-mentioned barrier layer may be provided. It is preferable that at least one layer of the insulating layer 602 and the insulating layer 604 is provided with an insulating layer containing nitrogen such as a silicon nitride layer or a silicon nitride layer. Further, the bonding layer 606 may be provided with a silicon oxide layer similar to the bonding layer 122 described above.

0068In the present embodiment, the insulating layer 602 and the insulating layer 604 are formed on the substrate 600, the bonding layer 606 is formed on the semiconductor substrate side from which the SOI layer is peeled off, the substrate 600 and the semiconductor substrate are bonded together, and then the above-mentioned An example is shown in which a part of the semiconductor substrate is peeled off to form the SOI layer 610. Specifically, the insulating layer 604 formed on the substrate 600 and the bonding layer 606 formed on the semiconductor substrate are brought into close contact with each other, the insulating layer 604 and the bonding layer 606 are bonded to each other, and the substrate 600 and the semiconductor substrate are attached. match. The semiconductor substrate is irradiated with hydrogen, helium or halogen ions to a predetermined depth to form a separation layer. Then, heat treatment is performed, and a part of the semiconductor substrate is peeled off using the separation layer formed on the semiconductor substrate as a cleavage plane to obtain the SOI layer 610. Here, since the bonding layer 606 is formed on the semiconductor substrate side, the bonding layer 606 has the same size as the SOI layer 610. That is, the bonding layer 606 is separated from the adjacent panel forming region 610a and the panel forming region 610b in the same manner as the SOI layer 610. Further, since the insulating layer 602 and the insulating layer 604 are formed on the substrate 600 which is the base substrate, they are continuous layers in the adjacent panel forming region 610a and the panel forming region 610b. The SOI substrate to be applied may have any structure according to the present invention, and any of the above-mentioned structures shown in FIGS. 2 (A) to 3 (B) may be applied. For example, a bonding layer may be provided on the base substrate side, or an insulating layer such as a thermal oxide film may be provided between the semiconductor substrate and the bonding layer.

0069The SOI layer 610 is selectively etched to form a first SOI layer 621 on the display unit 620, a second SOI layer 631 on the first drive circuit unit 630, and a third SOI layer 641. .. Then, a gate electrode 614 is formed on the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 via the gate insulating layer 612 (see FIG. 11 (B)).

0070The first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 selectively etch the SOI layer 610 to process it into a desired shape. Here, the SOI layer 610 is processed into a plurality of islands and separated. If it is desired to make the film thickness of the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 thinner than the SOI layer of the prepared SOI substrate, the SOI layer is etched to make it thinner. It is also good. Further, a part of the SOI layer may be altered, and the altered portion may be selectively etched to form a thin film. Here, the alteration of the SOI layer means, for example, an oxidation treatment, a nitriding treatment, or the like. Further, the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 may be formed so that the ends thereof have a tapered shape close to vertical by appropriately controlling the etching conditions and the like. However, it may be formed so as to have a gently tapered shape. For example, the shape may have a taper angle of 45 ° or more and less than 95 °, preferably 60 ° or more and less than 95 °, or a gentle shape with a taper angle of less than 45 °.

0071In order to control the threshold voltage of the completed transistor, even if an impurity element that imparts a low-concentration monoconductive type is added to the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641. Good. In this case, an impurity element is also added to the channel forming region of the transistor. The impurity element added here is added at a concentration lower than that of the high-concentration impurity region that functions as the source region or the drain region and the low-concentration impurity region that functions as the LDD region.

0072The gate electrode 614 forms a conductive layer on the entire surface of the substrate, and then selectively etches the conductive layer to process it into a desired shape. Here, after forming a laminated structure of conductive layers as the gate electrode 614, the conductive layers are selectively etched to separate the conductive layers into the first SOI layer 621, the second SOI layer 631, and the third SOI layer 641. Each is processed to cross.

0073The conductive layer forming the gate electrode 614 is made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), and copper (Cu) by the CVD method or sputtering method. ), Or a metal element such as niobium (Nb), or an alloy material or compound material containing the metal element to form a conductive layer on the entire surface of the substrate, and then selectively etching the conductive layer to form the conductive layer. it can. It can also be formed by using a semiconductor material typified by polycrystalline silicon to which an impurity element that imparts a single conductive type such as phosphorus is added.

0074Although an example in which the gate electrode 614 is formed by a laminated structure of two conductive layers is shown here, the gate electrode may have a single layer structure or a laminated structure of three or more layers. Further, the side surface of the conductive layer may have a tapered shape. When the gate electrode has a laminated structure of conductive layers, the width of the lower conductive layer may be increased, or the side surfaces of the respective layers may be tapered at different angles.

0075A gate insulating layer 612 is formed between the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641, and the gate electrode 614. The gate insulating layer 612 can be formed by using a material such as silicon oxide, silicon oxide nitride, hafnium oxide, aluminum oxide, and tantalum oxide by using a CVD method, a sputtering method, an ALD method, or the like. Further, the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 can be formed by solid phase oxidation or solid phase nitriding by plasma treatment. In addition, after forming an insulating layer by a CVD method or the like, the insulating layer may be formed by solid-phase oxidation or solid-phase nitriding by plasma treatment.

0076The solid phase oxidation treatment or solid phase nitriding treatment is preferably performed using plasma excited by a high frequency such as microwave (typically 2.45 GHz). Specifically, the electron density excited by using high frequency is 1 × 10.¹¹cm^-3Above 1 × 10¹³cm^-3It is preferable to perform plasma treatment using plasma having an electron temperature of 0.5 eV or more and 1.5 eV or less. This is to form a dense insulating layer and obtain a practical reaction rate at a temperature of 500 ° C. or lower in the solid phase oxidation treatment or the solid phase nitriding treatment.

0077When the surfaces of the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 are oxidized by plasma treatment, the surface contains an oxygen-containing atmosphere (for example, oxygen, ozone, nitrogen dioxide, nitric oxide, nitric oxide). In an atmosphere containing nitrogen or nitric oxide, and a rare gas (including at least one of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenone (Xe)), or oxygen, ozone, Perform in an atmosphere containing nitrogen peroxide, nitric oxide or nitrogen dioxide, hydrogen, and a rare gas). Further, when the surfaces of the insulating layers formed on the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 by plasma treatment are nitrided, the atmosphere containing nitrogen (for example, nitrogen) is used. And in an atmosphere containing rare gas (including at least one of He, Ne, Ar, Kr, Xe), in an atmosphere containing nitrogen, hydrogen and rare gas, or NH₃Plasma treatment is performed in an atmosphere containing rare gas. As the rare gas, for example, Ar is preferably used. Moreover, you may use the gas which mixed Ar and Kr.

0078Here, FIG. 16 shows a configuration example of the plasma processing apparatus 1080 for performing plasma processing. The plasma processing device 1080 includes a support base 1088, a gas supply unit 1084 for supplying gas, an exhaust port 1086 connected to a vacuum pump for exhausting gas, an antenna 1098, a dielectric plate 1082, and for plasma generation. It has a high frequency supply unit 1092 that inputs high frequencies. The object to be processed 1010 is held by a support base 1088. Further, it is also possible to control the temperature of the object to be processed 1010 by providing the temperature control unit 1090 on the support base 1088. The object to be treated 1010 is a substrate to be subjected to plasma treatment, and in the present embodiment, the insulating layer 602, the insulating layer 604, the bonding layer 606, the first SOI layer 621, the second SOI layer 631 and the second SOI layer 631 are placed on the substrate 600. Corresponds to the one in which the SOI layer 641 of 3 is laminated. Alternatively, it corresponds to an insulating layer formed on the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641.

0079Hereinafter, a specific example of forming an insulating layer on the surface of the SOI layer using the plasma processing apparatus 1080 shown in FIG. 16 will be described. The plasma treatment includes surface modification treatments such as oxidation treatments, nitriding treatments, nitriding treatments, and hydrogenation treatments for substrates, semiconductor layers (SOI layers), insulating layers, and conductive layers. In these treatments, the gas supplied from the gas supply unit 1084 may be selected according to the purpose.

0080First, the processing chamber of the plasma processing apparatus 1080 shown in FIG. 16 is evacuated. Then, a gas containing rare gas, oxygen or nitrogen is supplied from the gas supply unit 1084. The object to be treated 1010 is heated at room temperature or in the range of 100 ° C or more and 550 ° C or less by the temperature control unit 1090. The distance between the object to be processed 1010 and the dielectric plate 1082 (hereinafter, also referred to as electrode distance) is about 20 mm or more and 200 mm or less (preferably 20 mm or more and 60 mm or less).

0081Next, a high frequency is input from the high frequency supply unit 1092 to the antenna 1098. Here, microwaves (frequency 2.45 GHz) are input as high frequencies. Then, by inputting microwaves from the antenna 1098 through the dielectric plate 1082 into the processing chamber, plasma 1094 is generated, and the plasma 1094 may contain oxygen radicals (which may contain OH radicals) or nitrogen radicals (which may contain NH radicals). There is also). At this time, the plasma 1094 is generated by the supplied gas.

0082When plasma 1094 is generated by high-frequency input such as microwaves, it has a high electron density (1 × 10) at a low electron temperature (3 eV or less, preferably 1.5 eV or less).¹¹cm^-3The above) plasma can be generated. Specifically, the electron temperature is 0.5 eV or more and 1.5 eV or less, and the electron density is 1 × 10.¹¹cm^-3Above 1 × 10¹³It is preferable to generate plasma of cm or less. In the present specification, a plasma having a low electron temperature and a high electron density generated by microwave input is also referred to as a high electron density plasma. Further, performing plasma processing using high-density plasma is also referred to as high-density plasma processing.

0083Oxygen radicals (which may contain OH radicals) or nitrogen radicals (which may contain NH radicals) generated by plasma 1094 oxidize the surface of the SOI layer formed on the object to be treated 1010 to form an insulating layer. It is formed. Alternatively, the surface or vicinity of the insulating layer formed on the SOI layer is oxidized or nitrided. At this time, if a rare gas such as argon is mixed with the supplied gas, oxygen radicals and nitrogen radicals can be efficiently generated by the excited species of the rare gas. When a rare gas is used as the supply gas, the formed insulating layer may contain the rare gas. In this method, by effectively using active radicals excited by plasma, oxidation and nitriding by solid phase reaction can be performed at a low temperature of 500 ° C. or lower.

0084In the present embodiment, an example of a suitable production method for forming the gate insulating layer 612 by plasma treatment is an example of a first SOI layer 621, a second SOI layer 631 and a third SOI layer 641 in an atmosphere containing oxygen. Is plasma-treated to form a silicon oxide layer, and then the surface of the silicon oxide layer is treated with nitriding plasma in an atmosphere containing nitrogen to form a nitrogen plasma-treated layer. Specifically, plasma treatment is first performed in an atmosphere containing oxygen, and a silicon oxide layer having a thickness of 3 nm to 6 nm is formed on the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641. Form. Subsequently, plasma treatment is performed in an atmosphere containing nitrogen to form a nitrogen plasma-treated layer having a high nitrogen concentration on or near the surface of the silicon oxide layer. The vicinity of the surface means a depth of approximately 0.25 nm to 1.5 nm from the surface of the silicon oxide layer. For example, by forming a silicon oxide layer and then performing plasma treatment in an atmosphere containing nitrogen, nitrogen containing nitrogen at a ratio of 20 atomic% to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer. A plasma-treated layer can be formed. The nitrogen plasma-treated layer is formed of silicon nitride or silicon nitride depending on the plasma treatment conditions.

0085In any case, by using the solid phase oxidation treatment or the solid phase nitriding treatment by the plasma treatment as described above, even if a glass substrate having a heat resistant temperature of 600 ° C or less is used as the substrate 600, the temperature is 950 ° C to 1050 °. An insulating layer equivalent to the thermal oxide film formed in the range of C can be obtained. That is, it is possible to form a highly reliable insulating layer as an insulating layer that functions as a gate insulating layer of a semiconductor element, particularly a transistor or a non-volatile memory element.

0086Note that FIG. 11B shows an example in which the gate insulating layer 612 and the side ends of the gate electrode 614 are aligned, but the present invention is not particularly limited, and the gate insulating layer 612 is left in the etching of the gate electrode 614. It may be processed as follows.

0087When a high dielectric constant material (called a high-k material) is used for the gate insulating layer 612, the gate electrode 614 is formed of polycrystalline silicon, silicide, metal, or metal nitride. It is preferably formed of metal or metal nitride. For example, of the gate electrode 614, the conductive layer in contact with the gate insulating layer 612 is formed of a metal nitride material, and the conductive layer on the conductive layer is formed of a metal material. By using this combination, it is possible to prevent the depletion layer from spreading to the gate electrode even when the gate insulating layer is thinned, and it is possible to prevent the transistor driving ability from being impaired even when the gate insulating layer is miniaturized.

0088Next, the insulating layer 616 is formed on the gate electrode 614. Then, using the gate electrode 614 as a mask, an impurity element that imparts a monoconductive type is added (see FIG. 11 (C)). Here, an example of adding an impurity element that imparts a different conductive type to the second SOI layer 631 and the third SOI layer 641 formed in the first drive circuit unit 630 will be shown. Further, an example is shown in which an impurity element that imparts the same conductive type as that of the second SOI layer 631 is added to the first SOI layer 621 formed on the display unit 620.

0089In the first SOI layer 621 formed on the display unit 620, a pair of impurity regions 623 and a channel forming region 622 located between the pair of impurity regions 623 are formed in a self-aligned manner using the gate electrode 614 as a mask. Will be done.

0090In the second SOI layer 631 formed in the first drive circuit unit 630, a channel is formed between the pair of impurity regions 633 and the pair of impurity regions 633 in a self-aligned manner using the gate electrode 614 as a mask. Region 632 is formed. In the third SOI layer 641, a pair of impurity regions 643 and a channel forming region 642 located between the pair of impurity regions 643 are formed in a self-aligned manner using the gate electrode 614 as a mask. Different conductive type impurity elements are added to the impurity region 633 and the impurity region 643.

0091(1) Impurity elements that impart a conductive type include elements that impart a p-type such as boron (B), aluminum (Al), and gallium (Ga), and n-type elements such as phosphorus (P) and arsenic (As). Elements can be used. In the present embodiment, an element that imparts n-type, such as phosphorus, is added to the first SOI layer 621 formed on the display unit 620 and the second SOI layer 631 formed on the first drive circuit unit 630. .. In addition, an element that imparts p-type to the third SOI layer 641 such as boron is added. When adding an impurity element to the first SOI layer 621 and the second SOI layer 631, the third SOI layer 641 may be selectively covered with a resist mask or the like. Similarly, when adding an impurity element to the third SOI layer 641, the first SOI layer 621 and the second SOI layer 631 may be selectively covered with a resist mask or the like.

0092The insulating layer 616 can be formed by using a material such as silicon oxide or silicon oxide, silicon nitride or silicon nitride by using a CVD method, a sputtering method, an ALD method or the like. (1) When the impurity element that imparts the conductive type is added, the damage given to the SOI layer can be reduced by making the configuration so that the impurity element is added by passing through the insulating layer 616.

0093Next, a sidewall insulating layer 618 is formed on the side surface of the gate electrode 614. Then, using the gate electrode 614 and the sidewall insulating layer 618 as masks, an impurity element that imparts a single conductive type is added (see FIG. 11 (D)). The impurities added to the first SOI layer 621, the second SOI layer 631 and the third SOI layer 641 in the previous steps (the step of forming the impurity region 623, the impurity region 633 and the impurity region 643), respectively. Add the same conductive impurity element as the element. In addition, it is added at a higher concentration than the impurity element added in the previous step.

0094In the first SOI layer 621, a pair of high-concentration impurity regions 626 and a pair of low-concentration impurity regions 624 are self-aligned with the gate electrode 614 and the sidewall insulating layer 618 as masks. The high-concentration impurity region 626 formed here functions as a source region or a drain region, and the low-concentration impurity region 624 functions as an LDD (Lightly Doped Drain) region.

0095In the second SOI layer 631, a pair of high-concentration impurity regions 636 and a pair of low-concentration impurity regions 634 are self-aligned with the gate electrode 614 and the sidewall insulating layer 618 as masks. The high-concentration impurity region 636 formed here functions as a source region or a drain region, and the low-concentration impurity region 634 functions as an LDD region. In the third SOI layer 641, a pair of high-concentration impurity regions 646 and a pair of low-concentration impurity regions 644 are self-aligned with the gate electrode 614 and the sidewall insulating layer 618 as masks. When adding an impurity element to the first SOI layer 621 and the second SOI layer 631, the third SOI layer 641 may be selectively covered with a resist mask or the like. Similarly, when adding an impurity element to the third SOI layer 641, the first SOI layer 621 and the second SOI layer 631 may be selectively covered with a resist mask or the like.

0096The sidewall insulating layer 618 is provided on the side surface of the gate electrode 614 via the insulating layer 616. For example, the insulating layer formed so as to embed the gate electrode 614 can be self-aligned on the side surface of the gate electrode 614 by performing anisotropic etching mainly in the vertical direction. The sidewall insulating layer 618 can be formed by using a material such as silicon nitride or silicon nitride, silicon oxide or silicon oxide. When the insulating layer 616 is formed of silicon oxide or silicon oxide, the sidewall insulating layer 618 can be formed of silicon nitride or silicon nitride so that the insulating layer 616 can function as an etching stopper. it can. When the insulating layer 616 is formed of silicon nitride or silicon nitride, the sidewall insulating layer 618 may be formed of silicon oxide or silicon oxide. By providing the insulating layer that can function as an etching stopper in this way, it is possible to prevent the SOI layer from being etched due to overetching when forming the sidewall insulating layer.

0097Next, the exposed portion of the insulating layer 616 is etched (see FIG. 12 (A)). The insulating layer 616 is provided between the sidewall insulating layer 618 and the gate electrode 614, between the sidewall insulating layer 618 and the first SOI layer 621, between the sidewall insulating layer 618 and the second SOI layer 631, and the sidewall. It remains between the insulating layer 618 and the third SOI layer 641.

0098A silicide layer may be formed in order to reduce the resistance of the high-concentration impurity region that functions as the source region or the drain region. As the silicide layer, cobalt silicide or nickel silicide may be applied. When the film thickness of the SOI layer is thin, the VDD reaction may proceed to the bottom of the SOI layer on which the high-concentration impurity region is formed to make it fully silicid.

0099Next, after forming the insulating layer 608 on the entire surface of the substrate 600, the insulating layer 608 is selectively etched to open an opening reaching the high-concentration impurity region 626 formed in the first SOI layer 621 of the display unit 620. Form. Further, openings are formed to reach the high-concentration impurity region 636 and the high-concentration impurity region 646 formed in the second SOI layer 631 and the third SOI layer 641 of the first drive circuit unit 630, respectively. Then, the conductive layer 619 is formed so as to embed the opening. Further, the terminal electrode 674 is formed in the terminal region 670 (see FIG. 12 (B)).

0100The insulating layer 608 is formed in a single layer structure or a laminated structure by a CVD method, a sputtering method, an ALD method, a coating method, or the like. For example, the insulating layer 608 may be an inorganic insulating material containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxide, silicon nitride, etc., DLC (diamond-like carbon), etc. by the CVD method, sputtering method, or ALD method. It can also be formed using an insulating material containing carbon, or it can be formed using an organic insulating material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane material such as siloxane resin, depending on the coating method. You can also do it. Further, it is also possible to form a laminated structure of a layer formed by using an inorganic insulating material or an insulating material containing carbon and a layer formed by using an organic insulating material or a siloxane material. The siloxane material corresponds to a material containing a Si-O-Si bond. The skeleton structure of siloxane is composed of the bonds of silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. Further, the insulating layer 608 may be subjected to plasma treatment in an oxygen atmosphere or a nitrogen atmosphere in the insulating layer after forming the insulating layer by using a CVD method, a sputtering method or an ALD method. Although the insulating layer 608 shows an example of a single layer structure here, it may be a laminated structure of two or more layers. Further, it may be formed by combining an inorganic insulating layer and an organic insulating layer. For example, a silicon nitride film or silicon oxide film that can function as a passivation layer is formed on the entire surface of the substrate 600, and a phospholytic glass (PSG) or a boron silicate glass (BPSG) that can function as a flattening layer is used as a material. The existing insulating layer can be formed.

0101The conductive layer 619 functions as an electrode that functions as a source electrode or a drain electrode. The conductive layer 619, which functions as a source electrode or a drain electrode, is electrically connected to the first SOI layer 621, the second SOI layer 631 or the third SOI layer 641 through an opening formed in the insulating layer 608. Will be done.

0102The conductive layer 619 is made of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), and copper by using a CVD method or a sputtering method. Metal elements such as (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or alloy materials or compound materials containing the metal elements. After forming a conductive layer on the entire surface of the substrate in a single-layer structure or a laminated structure, the conductive layer can be selectively etched to form the conductive layer. Examples of the alloy material containing aluminum include a material containing aluminum as a main component and containing nickel, and an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. Moreover, as a compound material containing tungsten, for example, tungsten silicide can be mentioned. For the conductive layer 619, for example, a laminated structure of a barrier layer, an aluminum silicon layer, and a barrier layer, or a laminated structure of a barrier layer, an aluminum silicon layer, a titanium nitride layer, and a barrier layer can be adopted. The barrier layer corresponds to a thin film made of titanium, titanium nitride, molybdenum, or molybdenum nitride. Since aluminum and aluminum silicon have low resistance values and are inexpensive, they are most suitable as materials for forming a conductive layer that functions as a source electrode or a drain electrode. Further, it is preferable that the conductive layer that functions as the source electrode or the drain electrode has a laminated structure in which barrier layers are provided on the upper layer and the lower layer because it is possible to prevent the generation of hillocks of aluminum and aluminum silicon.

0103The terminal electrode 674 formed in the terminal region 670 functions as an electrode for electrically connecting an external input terminal such as an FPC formed later and the first drive circuit unit 630 and the second drive circuit unit 650. To do. Here, an example in which the terminal electrode 674 is formed in the same layer using the same material as the conductive layer 619 is shown.

0104As described above, the pixel circuit unit 628 in which the transistor having the first SOI layer 621 is formed on the display unit 620 is formed. Further, a peripheral circuit unit 638 is formed in which a transistor having a second SOI layer 631 and a transistor having a third SOI layer 641 are formed in the first drive circuit unit 630.

0105Next, the insulating layer 609 is formed on the display unit 620 and the first drive circuit unit 630. Next, the insulating layer 609 formed on the display unit 620 is selectively etched to form an opening reaching the conductive layer 619 of the transistor formed in the pixel circuit unit 628. Then, the pixel electrode 660 is formed so as to embed the opening (see FIG. 12 (C)).

0106The insulating layer 609 preferably smoothes the irregularities of the display unit 620 and the first drive circuit unit 630 to form a flattening layer capable of forming a flat surface. For example, it can be formed by using an organic insulating material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene or acrylic, or a siloxane material such as siloxane resin. Although the insulating layer 609 shows an example of a single layer structure here, it may be a laminated structure of two or more layers. In the case of a laminated structure, for example, a laminated structure in which an organic resin or the like is used as an upper layer and an inorganic insulating layer such as silicon oxide, silicon nitride or silicon oxide is used as a lower layer, or a structure in which the organic insulating layer is sandwiched between the inorganic insulating layers. be able to. The insulating layer 609 can be formed by selectively etching other than a desired region (here, the display unit 620 and the first drive circuit unit 630) after being formed on the entire surface of the substrate. Further, the insulating layer 609 can be selectively formed by using various printing methods (screen printing, lithographic printing, letterpress printing, gravure printing, etc.), a droplet ejection method, a dispenser method, and the like.

0107The pixel electrode 660 functions as a reflective electrode in this embodiment. Therefore, it is formed by using a conductive material having a reflective property. Examples of such a material include metal elements such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), and silver (Ag), or the metal elements. An alloy material or a compound material containing the above can be used. In addition, when forming a reflective layer or using a transmissive liquid crystal display device, the pixel electrode 660 may be formed by using a conductive material having translucency. Translucent conductive materials include indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), zinc oxide (IZO), or oxidation with gallium added. Zinc (GZO) or the like can be used.

0108Next, after forming the spacer 686, the alignment film 682 is formed so as to cover the pixel electrode 660 and the spacer 686. Next, the sealing material 680 is formed so as to surround the display unit 620, the first drive circuit unit 630, and the second drive circuit unit 650 (see FIG. 13 (A)).

0109The spacer 686 has a single-layer structure or a laminated structure using an organic insulating material such as epoxy, polyimide, polyamide, polyimide amide, or acrylic, or an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxide, or silicon nitride. Can be formed. In the present embodiment, since the columnar spacer is formed as the spacer 686, an insulating layer is formed on the entire surface of the substrate and then etched to obtain a spacer having a desired shape. The shape of the spacer 686 is not particularly limited, and a spherical spacer may be sprayed. The spacer 686 can hold the cell gap.

0110For the alignment film 682, the material may be selected according to the operation mode of the liquid crystal to be used, and a layer capable of arranging the liquid crystals in a certain direction is formed. For example, it can be formed by using a material such as polyimide or polyamide and can function as an alignment film by undergoing an alignment treatment. As the orientation treatment, rubbing, irradiation with light such as ultraviolet rays, or the like may be performed. The method for forming the alignment film 682 is not particularly limited, but it can be selectively formed on the insulating layer 609 by using various printing methods and droplet ejection methods.

0111After the display device is completed, the sealing material 680 is formed so as to surround at least the display area. In the present embodiment, a frame-shaped seal pattern is formed so as to surround the display unit 620, the first drive circuit unit 630, and the second drive circuit unit 650. As the sealing material 680, a thermosetting resin or a photocurable resin can be used. The cell gap can also be maintained by including a filler in the sealing material. When the sealing material 680 is later sealed with a substrate provided with a counter electrode, a color filter, or the like, the sealing material 680 is cured by performing light irradiation, heat treatment, or the like.

0112The liquid crystal layer 684 is formed in the area surrounded by the sealing material 680. Further, the second substrate 690 and the first substrate 600 on which the color filter 689, the counter electrode 688, and the alignment film 687 are sequentially laminated are bonded together (see FIG. 13 (B)).

0113The liquid crystal layer 684 is formed by using a desired liquid crystal material. For example, the liquid crystal layer 684 can be formed by dropping the liquid crystal material into the frame-shaped seal pattern formed of the seal material 680. The liquid crystal material may be dropped by using a dispenser method or a droplet ejection method. It is preferable that the liquid crystal material is degassed in advance under reduced pressure, or degassed under reduced pressure after dropping. In addition, it is preferable to carry out the liquid crystal material in an inert atmosphere so that impurities and the like are not mixed when the liquid crystal material is dropped. Further, after the liquid crystal material is dropped to form the liquid crystal layer 684, it is preferable to carry out the process under reduced pressure so that air bubbles or the like do not enter the liquid crystal layer 684 until the first substrate 600 and the second substrate 690 are bonded together. ..

0114Further, the liquid crystal layer 684 may be formed by injecting a liquid crystal material into the frame-shaped pattern of the sealing material 680 by using the capillary phenomenon after laminating the first substrate 600 and the second substrate 690. it can. In this case, a portion to be an injection port of the liquid crystal is formed in advance on the sealing material or the like. The liquid crystal material is preferably injected under reduced pressure.

0115The first substrate 600 and the second substrate 690 can be brought into close contact with each other, and then the sealing material 680 can be cured and bonded. At this time, the alignment film 687 provided on the second substrate 690 and the alignment film 682 provided on the first substrate 600 are bonded so as to have a structure in which the liquid crystal layer 684 is sandwiched. It is also possible to correct the orientation disorder of the liquid crystal layer 684 by performing heat treatment after bonding the first substrate 600 and the second substrate 690 and forming the liquid crystal layer 684.

0116As the second substrate 690, a translucent substrate is used. For example, various glass substrates such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, quartz substrates, ceramic substrates, and sapphire substrates can be used.

0117A color filter 689, a counter electrode 688, and an alignment film 687 are formed on the second substrate 690 in this order before bonding. The second substrate 690 may be provided with a black matrix in addition to the color filter 689. Further, the color filter 689 may be provided on the outside of the second substrate 690. Further, in the case of monochromatic display, it is not necessary to provide the color filter 689. Further, the sealing material may be provided on the second substrate 690 side. When the sealing material is provided on the second substrate 690 side, the liquid crystal material is dropped into the frame-shaped pattern of the sealing material provided on the second substrate 690.

0118The counter electrode 688 is made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide containing gallium (GZO), or the like. It can be formed by using a conductive material having translucency. The alignment film 687 can be formed in the same manner as the alignment film 682.

0119As described above, the structure in which the display unit 620 including the liquid crystal layer 684, the first drive circuit unit 630, and the second drive circuit unit 650 are sealed between the first substrate 600 and the second substrate 690 is formed. can get. In addition to the transistor, a resistor, a capacitor, or the like may be simultaneously manufactured in the circuit unit formed in the display unit 620, the first drive circuit unit 630, and the second drive circuit unit 650. Further, the structure of the transistor is not particularly limited. For example, a multi-gate structure in which a plurality of gates are provided for one SOI layer can be used.

0120Next, the bonded first substrate 600 and the second substrate 690 are separated and processed into a desired panel size (see FIG. 14 (A)). Here, the panel forming region 610a and the panel forming region 610b are separated so as to be separated. In the sectional section, the terminal electrode 674 is exposed. The display unit 620 including the liquid crystal layer 684 and the first drive circuit unit 630 are sealed by the sealing material 680. The first substrate 600 and the second substrate 690 can be divided by using a cutting device such as a scriber device, a breaker device, and a roll cutter.

0121Next, the second substrate 690 on the terminal area 670 is divided (see FIG. 14 (B)). Here, the second substrate 690 on the terminal electrode 674, the color filter 689, the counter electrode 688, and the alignment film 687 are separated so as to be removed. With the above, a display panel having a desired panel size can be obtained.

0122Here, the division of the bonded substrates will be described in detail with reference to the schematic view of the upper surface shown in FIG.

0123FIG. 10 (A) shows a schematic view of the upper surface corresponding to the SOI substrate shown in FIG. 11 (A). Here, an example is shown in which a panel forming region 610a, a panel forming region 610b, a panel forming region 610c, and a panel forming region 610d having separated SOI layers 610 are provided on one substrate 600. The SOI layer 610 provided in each of the panel forming regions 610a, 610b, 610c, and 610d has a desired panel size.

012410 (B) shows the steps shown in FIGS. 11 (B) to 13 (A) to the step of bonding the first substrate 600 and the second substrate 690 as shown in FIG. 13 (B). A schematic view of the finished upper surface is shown. A display unit 620, a first drive circuit unit 630, and a second drive circuit unit 650 are provided for each of the panel forming regions 610a, 610b, 610c, and 610d, and are sealed by a sealing material 680. Note that FIG. 13 (B) corresponds to a cross-sectional view of the line segment QR of FIG. 10 (B).

0125Next, the bonded first substrate 600 and the second substrate 690 are divided along the arrows 6002 and 6004 in FIG. 10 (B), and separated into panel formation regions as shown in FIG. 10 (C). To do. Note that FIG. 14 (A) corresponds to a cross-sectional view of the line segment Q'R'of FIG. 10 (C).

0126Next, the second substrate 690 is divided along the arrows 6012 and 6014 in FIG. 10 (C) to expose the terminal region 670 as shown in FIG. 10 (D). A terminal electrode 674 is provided in the terminal region 670, and is connected to an external input terminal to be formed later by using an anisotropic conductive layer or the like. Note that FIG. 14 (B) corresponds to a cross-sectional view of the line segment Q R of FIG. 10 (D). With the above, the display panel 6100a, the display panel 6100b, the display panel 6100c, and the display panel 6100d can be obtained. The elements constituting the display panel 6100a are formed by one SOI layer provided in the panel forming region 610a. Similarly, the elements constituting the other display panels are also formed by one SOI layer provided in each panel forming region. Therefore, it is possible to suppress variations in characteristics.

0127Here, an example is shown in which the first substrate 600 and the second substrate 690 are separated and then the second substrate 690 is further divided, but the second substrate is processed to a desired size in advance. The substrate 690 may be bonded to each other.

0128Further, although an example in which four display panels are manufactured from one base substrate for convenience is shown here, the present invention is not particularly limited. As described above, the SOI substrate according to the present invention is provided with a plurality of SOI layers having a desired panel size, and it is possible to manufacture a plurality of display panels at the same time by using the individual SOI layers. Therefore, the number of chamfers increases in proportion to the number of SOI layers provided on the base substrate, and the productivity is dramatically improved.

0129Next, a polarizing plate 692 is provided on the second substrate 690. Further, the external input terminal 678 is connected to the terminal electrode 674 via the anisotropic conductive layer 676, and the display panel is electrically connected to the outside (see FIG. 15).

0130The polarizing plate 692 is provided on the outside of the second substrate 690 (the surface side where the liquid crystal layer 684 and the like are not sealed). In the case of a transmissive liquid crystal display device, a polarizing plate may be provided on the outside of the first substrate 600 (the surface side where the liquid crystal layer 684 or the like is not sealed). Further, in addition to the polarizing plate, an optical film such as a retardation plate and an antireflection film may be provided.

0131The external input terminal 678 plays a role of transmitting an external signal (for example, a video signal, a clock signal, a start signal, a reset signal, etc.) and an electric potential. Here, the FPC is connected as the external input terminal 678. It is assumed that the terminal electrode 674 is electrically connected to the first drive circuit unit 630 and the second drive circuit unit 650.

0132From the above, a display device can be obtained. In the case of a reflective liquid crystal display device, display can be performed using external light (sunlight or indoor light), but it is composed of a light source such as a cold cathode fluorescent lamp or an LED element, a light guide plate, or the like. A front light, a reflective sheet, or the like may be provided. The front light can be provided on the visual side of the display device. By providing a front light, a clear display can be performed even when sufficient outside light cannot be obtained.

0133Further, in the case of a transmissive liquid crystal display device or a semi-transmissive liquid crystal display device, a backlight composed of a light source such as a cold cathode tube or an LED element, a light guide plate, a reflective sheet, or the like is provided. The backlight is provided on the side opposite to the visible side (rear side) of the display device. In the case of a transmissive liquid crystal display device, light from a light source can be transmitted to the viewing side for display.

0134Here, an SOI substrate in which a plurality of SOI layers 610 having a desired panel size are provided on the substrate 600 is used. Then, the SOI layer forming the element is separated for each display panel constituting one display device. Therefore, it is possible to prevent damage to the SOI layer when dividing and dividing into individual display panels, and it is possible to improve the yield. Further, since the elements forming one display device are formed by using one SOI layer, the variation in characteristics can be suppressed.

0135Although FIGS. 9 to 15 show an example of manufacturing a display device using a liquid crystal element as a display element, the present invention is not particularly limited. For example, a light emitting element can be used, or an electrophoresis element can be used. FIG. 21 shows an example of a display device (also called a light emitting device or an EL display device) that uses a light emitting element. Further, FIG. 22 shows an example of a display device (also called an electronic paper or an electrophoresis display device) that uses an electrophoresis element. Since the configurations other than the display element are the same as those shown in FIGS. 9 to 15, the description thereof will be omitted.

0136FIG. 21 shows a display device in which the light emitting element 710 is used instead of the liquid crystal element. Here, an example is shown in which the organic compound layer 714 sandwiched between the pixel electrode (cathode) 712 and the counter electrode (anode) 716 is provided. The organic compound layer 714 includes at least a light emitting layer, and may also include an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, and the like. Further, the end portion of the pixel electrode 712 is covered with the partition wall layer 718. The partition wall layer 718 may be formed on the entire surface of the substrate using an insulating material and then processed so that a part of the pixel electrode 712 is exposed, or may be selectively formed by a droplet ejection method or the like. The organic compound layer 714 and the counter electrode 716 are laminated in this order on the pixel electrode 712 and the partition wall layer 718. The space 720 between the light emitting element 710 and the second substrate 690 may be filled with an inert gas or the like, or may be formed of a resin or the like.

0137FIG. 22 shows a display device in which an electrophoresis element is used instead of the liquid crystal element. Here, an example is shown in which the electrophoresis layer 820 sandwiched between the pixel electrode 812 and the counter electrode (common electrode) 814 is provided. The electrophoresis layer 820 contains a plurality of microcapsules 810 fixed by a binder 816. The microcapsule 810 has a diameter of about 10 μm to 200 μm, and has a structure in which a transparent liquid, positively charged white fine particles, and negatively charged black fine particles are enclosed. When an electric field is applied by the pixel electrode 812 and the counter electrode 814, the microcapsules 810 can display white or black by moving the white fine particles and the black fine particles in opposite directions. A display element to which this principle is applied is an electrophoresis element. Since the electrophoresis element has a higher reflectance than the liquid crystal element, it is possible to recognize the display unit in a dim place even without an auxiliary light (for example, a front light). Also, the power consumption is small. Further, even when power is not supplied to the display unit, it is possible to retain the image once displayed.

0138Next, an example of an electronic device to which the display device (display panel) according to the present invention is applied will be described. Specifically, an example of application to a mobile phone will be described with reference to FIG.

0139The mobile phone shown in FIG. 17 includes a main body (A) 1901 equipped with operation switches 1904, a microphone 1905, etc., a display panel (A) 1908, a backlight section 1911, a display panel (B) 1909, a speaker 1906, etc. The main body (B) 1902 provided is connected so that it can be opened and closed with a hinge 1910. The display panel (A) 1908 and the display panel (B) 1909 are housed in the housing 1903 of the main body (B) 1902 together with the circuit board 1907 and the backlight unit 1911. The display units of the display panel (A) 1908 and the display panel (B) 1909 are arranged so as to be visible from the opening window formed in the housing 1903. Here, the backlight unit 1911 and the display panel (A) 1908 are arranged so as to overlap each other to form a transmissive liquid crystal display device. As the backlight unit 1911, a cold cathode tube or an LED element may be used. Further, as the backlight unit, a combination of a light guide plate and an LED element may be used.

0140The display panel (A) 1908 and the display panel (B) 1909 are manufactured using the SOI substrate according to the present invention. Therefore, it can be manufactured with a good yield.

0141Further, in the display panel (A) 1908 and the display panel (B) 1909, specifications such as the number of pixels can be appropriately set according to the function of the mobile phone 1900. For example, the display panel (A) 1908 can be combined as the main screen, and the display panel (B) 1909 can be combined as the sub screen.

0142The mobile phone according to the present embodiment can be transformed into various modes depending on its function and application. For example, an image sensor may be incorporated in the hinge 1910 to form a mobile phone with a camera. Further, the operation switches 1904, the display panel (A) 1908, and the display panel (B) 1909 may be housed in one housing.

0143Further, FIG. 18A shows an example of the configuration of the display panel (A) 1908. In the display panel (A) 1908, a first substrate 1920 provided with pixel electrodes and a second substrate 1923 facing the first substrate are bonded together with a sealing material 1922. Further, the sealing material 1922 is formed so as to surround the display unit 1921, and a liquid crystal layer is provided in the region (inside the frame-shaped seal pattern) surrounded by the first substrate 1920, the second substrate 1923, and the sealing material 1922. Has been done.

0144Further, FIG. 18 (B) shows an example of a display panel configuration different from that of FIG. 18 (A). In FIG. 18 (B), the same reference numerals are used for the parts common to those in FIG. 18 (A). In the panel of FIG. 18B, a drive IC 1927 for driving the display unit is mounted on the first board 1920. The circuit is integrated by mounting the drive IC 1927 on the first board 1920.

0145Further, FIG. 18 (C) shows an example of a display panel configuration different from that of FIG. 18 (A). In FIG. 18 (C), the same reference numerals are used for the parts common to those in FIG. 18 (A). In the display panel of FIG. 18C, the drive circuit unit 1928 for driving the display unit 1929 is formed on the same substrate as the first substrate 1920. Further, not only the drive circuit but also other circuits (optical sensor circuit, CPU, etc.) may be formed on the same substrate.

0146A desired optical film, for example, a polarizing plate, an antireflection film, a color filter, or the like may be superposed on the display panel shown in FIGS. 18 (A), 18 (B), and 18 (C). The FPC 1924 shown in FIGS. 18 (A), 18 (B), and 18 (C) is connected to the first substrate 1920.

0147By manufacturing the display device (display panel) using the SOI substrate according to the present invention in this way, the manufacturing process can be carried out at once using the large-area substrate, and the productivity can be improved. .. Further, although the SOI substrate is manufactured from a plurality of SOI layers, the yield can be improved in the manufacture of a display device such as a display panel by setting the size of each SOI layer to a desired panel size. ..

0148(Embodiment 2) In this embodiment, an example of manufacturing an SOI substrate by a method different from that of the above embodiment is shown.

0149First, the semiconductor substrate 200 is prepared (see FIG. 23 (A)). As the semiconductor substrate 200, the same semiconductor substrate 101 as described above may be used, and a silicon substrate, a germanium substrate, a compound semiconductor substrate such as gallium arsenide or indium phosphide may be used.

0150It is preferable to provide the nitrogen-containing insulating layer 202 on one surface of the semiconductor substrate 200. The nitrogen-containing insulating layer 202 may be formed in a single-layer structure or a laminated structure by using a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide nitride layer. By providing the nitrogen-containing insulating layer 202, it is possible to prevent impurities such as movable ions and moisture from diffusing into the SOI layer and being contaminated. It can also function as a protective layer when irradiating ions to form a separation layer.

0151Next, the semiconductor substrate 200 is selectively etched (see FIG. 23 (B)). In the present embodiment, a groove (hereinafter, also referred to as a "concave portion") is formed on the semiconductor substrate by etching, and a portion remaining in a convex shape (hereinafter, also referred to as a "convex portion") is a desired panel size. The area should include the panel. In this specification, the process of selectively etching a semiconductor substrate to form a groove is also referred to as groove processing.

0152The convex portion formed by grooving is preferably formed so as to have an area including one panel having a desired panel size, for example, a panel size of small and medium-sized panels having a diagonal of less than 10 inches. When applied to a mobile phone, it is known that the screen size is about 2.4 inches diagonally to 3 inches diagonally, and the screen size may be set in consideration of the screen frame size. The convex portion remaining on the semiconductor substrate 200 forms an SOI layer that is later transposed to the base substrate. That is, by forming the convex portion so as to have an area including one panel by grooving, the SOI layer divided into the area including one panel can be transposed on the base substrate. Further, by forming a plurality of divided convex portions by grooving, a plurality of SOI layers can be transposed on the base substrate.

0153The semiconductor substrate 200 can obtain a convex portion having an area including one panel having a desired panel size by selectively covering a portion to be retained with a mask and etching. As the mask, a resist mask or a hard mask formed of an insulating layer may be applied. After etching, the mask that is no longer needed may be removed as appropriate. Further, in the present embodiment, since the nitrogen-containing insulating layer 202 is provided on the semiconductor substrate 200, it is assumed that the nitrogen-containing insulating layer 202 is also selectively etched. Therefore, after grooving, the nitrogen-containing insulating layer 202 remains in the convex portion.

0154Further, the etching depth (grooving depth) of the semiconductor substrate 200 is appropriately selected in consideration of the film thickness of the SOI layer to be transposed to the base substrate later. The film thickness of the SOI layer can be set by irradiating ions and adding elements constituting the irradiated ions. In the present embodiment, it is preferable that the groove processing depth (the depth of the groove to be formed) of the semiconductor substrate 200 is deeper than that of the separation layer. By making the groove depth deeper than the separation layer in the groove processing of the semiconductor substrate 200, when the SOI layer is later transposed to the base substrate, only the convex portion of the semiconductor substrate 200 can be easily transposed. Become.

0155Next, ions accelerated by an electric field are irradiated from the surface of the semiconductor substrate 200 to a predetermined depth to form the separation layer 204 (see FIG. 23 (C)). The separation layer 204 may be formed in the same manner as in the case of FIG. 4A described above, and can be formed by irradiating with halogen ions such as hydrogen, helium, and fluorine. The ion irradiation is performed from the surface side where the semiconductor substrate 200 is grooved (in the present embodiment, the surface side where the nitrogen-containing insulating layer 202 is provided).

0156Since the semiconductor substrate 200 is formed with a groove deeper than the separation layer 204 in advance, the separation layer 204 can be formed so that the desired SOI layer is transposed to the base substrate. Specifically, the separation layer 204 is formed so as to be staggered at the convex portion and the concave portion of the semiconductor substrate 200. The depth of the separation layer from the surface of the semiconductor substrate 200 is about the same in the concave and convex portions of the semiconductor substrate 200.

0157Next, the bonding layer 222 is formed on the semiconductor substrate 200 (see FIG. 23 (D)). The bonding layer 222 is formed on a surface on which the semiconductor substrate 200 forms a bonding with the base substrate. In the present embodiment, the bonding layer 222 is formed so as to cover the entire side of the semiconductor substrate 200 on which the nitrogen-containing insulating layer 202 is provided. The bonding layer 222 may be formed in the same manner as the bonding layer 122 described above, and preferably a silicon oxide layer is formed by a chemical vapor deposition method using organic silane as a raw material gas.

0158Next, the semiconductor substrate 200 is attached to the base substrate 224 (see FIG. 24 (A)). Here, an example is shown in which the base substrate 224 and the surface of the semiconductor substrate 200 provided with the bonding layer 222 are brought into close contact with each other, and the base substrate 224 and the semiconductor substrate 200 are bonded together. It is preferable that the surfaces forming the joints of both the base substrate 224 and the semiconductor substrate 200 are sufficiently cleaned. A bond is formed by bringing the base substrate 224 and the bond layer 222 into close contact with each other. Van der Waals force acts on this bond, and by pressure-welding the base substrate 224 and the semiconductor substrate 200, it is possible to form a strong bond by hydrogen bonding. In the present embodiment, since the semiconductor substrate 200 is grooved, the convex portion comes into contact with the base substrate 224.

0159As in the first embodiment, the bonding surface (the surface of the bonding layer 222 or the base substrate 224 in the present embodiment) is activated by irradiation with an atomic beam or an ion beam, or plasma or radical treatment. You can leave it to me. By activating the joint surface in advance, it is possible to facilitate the joint between different materials. Further, after the base substrate 224 and the semiconductor substrate 200 are bonded together with the bonding layer 222 in between, it is preferable to perform a heat treatment or a pressure treatment.

0160Next, heat treatment is performed, and a part of the semiconductor substrate 200 is peeled off from the base substrate 224 with the separation layer 204 as a cleavage plane. In the present embodiment, the semiconductor substrate 200 is grooved so that the groove depth is deeper than that of the separation layer 204, and the separation layer 204 is formed in a stepped manner. Further, the bonding layer 222 provided on the semiconductor substrate 200 is in contact with the base substrate 224 only in a convex portion. Therefore, only the convex portion of the semiconductor substrate 200 can be left as the SOI layer on the base substrate 224. Therefore, an SOI layer having a desired panel size and having the same crystallinity as the semiconductor substrate 200 remains on the base substrate 224. If a plurality of convex portions having a desired panel size are formed on the semiconductor substrate 200, a plurality of SOI layers can be formed on the base substrate. FIG. 24B shows an example in which four SOI layers 226, SOI layer 228, SOI layer 230, and SOI layer 232 remain on the base substrate 224 for convenience.

0161The heat treatment for peeling is preferably performed at a temperature equal to or higher than the film formation temperature of the bonding layer 222 and lower than the heat resistant temperature of the base substrate 224. For example, by performing the heat treatment at 400 ° C to 600 ° C, the volume of the minute cavities formed in the separation layer 204 changes, and it becomes possible to cleave along the separation layer 204.

0162Further, in order to flatten or thin the SOI layer obtained by peeling, CMP or laser beam irradiation may be performed.

0163With the above, it is possible to obtain an SOI substrate in which a plurality of SOI layers are provided on the base substrate 224 via the bonding layer 222. In FIG. 24B, for convenience, an SOI substrate in which the SOI layer 226, the SOI layer 228, the SOI layer 230, and the SOI layer 232 are provided on the base substrate 224 via the bonding layer 222 is shown.

0164It is preferable that the SOI layer is transposed to the base substrate with the exposure range of the exposure device as one unit. Specifically, when a plurality of SOI layers are transposed on the base substrate to form the SOI substrate, it is preferable to transpose the SOI layers with one exposure range of the exposure apparatus as one unit. That is, it is preferable that one unit of the transposed SOI layer has an area of about one exposure range. Hereinafter, in the present specification, one exposure range of the exposure apparatus is referred to as "one shot size". It is also preferable to transpose the alignment marker along with the SOI layer.

0165Here, a schematic view of the upper surface of the semiconductor substrate 200 after grooving is shown in FIG. 25 (A). It is assumed that the cross-sectional view of the line segment AA'in FIG. 25 (A) corresponds to FIG. 23 (B).

0166The semiconductor substrate 200 is selectively etched, and the nitrogen-containing insulating layer 202 remains in the portion corresponding to the convex portion in FIG. 23 (B). The convex portion formed on the semiconductor substrate 200 has an area including one panel whose surface is a desired panel size when viewed from the upper surface. Here, when viewed from the upper surface, the nitrogen-containing insulating layer 202 remains divided on the semiconductor substrate 200 into an area including one panel having a desired panel size. A convex portion formed on the semiconductor substrate 200 is located under the nitrogen-containing insulating layer 202.

0167In the manufacturing field of display devices, semiconductor devices, etc., photolithography is often applied when forming fine patterns and the like. In photolithography, an exposure device typified by a stepper is used to transfer a desired pattern shape to a resist layer coated on a substrate to form a desired pattern, and then the pattern shape is used to form a desired pattern on the substrate. To do. For example, a circuit pattern is formed on a resist layer coated on a substrate as a desired pattern shape, and a circuit including a transistor is formed on the substrate by using the circuit pattern. The 1-shot size of the exposure device depends on the device, but when using an existing stepper, the 1-shot size is about 25 mm square, 100 mm square, 113 mm square, 132 mm square, or 144 mm square, and one side exceeds 1 meter. It is difficult to expose such a large-area substrate at once. Therefore, a desired circuit pattern can be efficiently formed by transposing the 1-shot size SOI layer group of the exposure apparatus as one group in advance. This is because by transposing one shot-sized SOI layer group as one group, one group of the SOI layer groups can be simultaneously exposed to form a desired pattern, for example, a circuit pattern. The circuit pattern is formed in each SOI layer constituting the SOI layer group, and for example, a circuit pattern including a transistor can be formed in each SOI layer. The individual SOI layers of the SOI layer group forming one unit are divided into an area including one panel having a desired panel size.

0168In FIG. 25 (A), the one-shot size area 250 of the stepper is surrounded by a broken line. The semiconductor substrate 200 is selectively etched so that the region transposed as the SOI layer is efficiently arranged with the one-shot size region 250 of the stepper as one unit.

0169In addition, a portion 240 that serves as an alignment marker also remains in the region 250. The portion 240 serving as the alignment marker can be left by covering the portion to be the SOI layer with a mask when selectively covering the portion to be the SOI layer. In the semiconductor substrate 200 shown in FIG. 25 (A), the nitrogen-containing insulating layer 202 also remains in the portion 240 that serves as an alignment marker. The portion 240 serving as an alignment marker is omitted in the cross-sectional view.

0170FIG. 25B shows a schematic view of the upper surface of the base substrate 224 on which the SOI layer is transposed. It is assumed that the cross-sectional view of the line segment AA'in FIG. 25 (B) corresponds to FIG. 24 (B).

0171The base substrate 224, stearyl the region 250 of the one shot size wrapper as a unit, SOI layer group becomes person chunks and are arranged regularly. In addition, the same crystalline alignment marker 260 as the SOI layer is also formed.

0172In FIG. 25 (B), one alignment marker and a plurality of SOI layers are provided in a one-shot size region 250 of one stepper. That is, it is transposed to the base substrate so that a plurality of single crystal semiconductor layers belong to one alignment marker.

0173When the display device is manufactured in the same manner as in the first embodiment using the SOI substrate shown in FIG. 25 (B), the position is aligned with the alignment marker 260, and the SOI layer located in the region 250 of one shot size is formed. It can be exposed at the same time and photolithography can be performed. Further, since the SOI layers are arranged in consideration of the one-shot size of the stepper and the SOI layers have a desired panel size, a pattern can be efficiently formed.

0174For example, in FIGS. 26A and 26B, one of the one-shot size regions 250 of the stepper on the base substrate 224 will be used. In FIG. 26 (A), the SOI layer 226a, the SOI layer 226b, the SOI layer 228a, and the SOI layer 228b are arranged in the region 250a with respect to one alignment marker 260a. The SOI layer 226a, SOI layer 226b, SOI layer 228a, and SOI layer 228b are the desired panel size sizes. The SOI layer 226a, SOI layer 226b, SOI layer 228a, and SOI layer 228b are located in the region 250a and form a unit.

0175FIG. 26B shows an example in which alignment is performed using the alignment marker 260a and the SOI layer 226a, SOI layer 226b, SOI layer 228a, and SOI layer 228b are selectively etched to form a desired pattern. .. For example, a group consisting of the SOI layer 226a, the SOI layer 226b, the SOI layer 228a, and the SOI layer 228b is simultaneously exposed to transfer and form a circuit pattern. At this time, by forming the alignment marker 260a, alignment and the like can be easily performed during photolithography. The pattern of each SOI layer after etching can form, for example, a channel portion of a transistor formed in a circuit portion. Then, through other steps, individual SOI layers can be used to form a circuit containing transistors.

0176Further, when a desired SOI layer pattern for forming a channel portion of a transistor or the like is formed by selectively etching an SOI layer using a circuit pattern formed by simultaneous exposure and transfer, later pattern formation (gate electrode) is performed. Etc.), it is preferable to form an alignment marker. For example, FIG. 26B shows an example in which an alignment marker 271a, an alignment marker 271b, an alignment marker 272a, and an alignment marker 272b are formed for each panel forming region. Although it is possible to perform alignment at the time of later pattern formation with the alignment marker 260a formed earlier, it is preferable to form a new alignment marker in order to correspond to a finer pattern shape. By doing so, even when forming a fine pattern shape, alignment and the like can be easily performed.

0177Here, for the sake of convenience, an example is shown in which four SOI layers are regarded as one unit and one unit of one shot size of the stepper, but the present invention is not particularly limited. The number of SOI layers that make up a unit is arbitrary. That is, an arbitrary number of SOI layers can be selected from a plurality of transposed SOI layers to form a single unit.

0178The present embodiment can be freely combined with the above-described first embodiment.

0179(Embodiment 3) In the present embodiment, an example in which an element having a configuration different from that of the above-described embodiment is manufactured by using the SOI substrate according to the present invention is shown. Specifically, a configuration in which an insulating layer is embedded between SOI layers as an element separation structure will be described with reference to FIGS. 19 and 20.

0180In FIG. 19 (A), the SOI layer 302 is provided on the base substrate 300 via the bonding layer 304. The SOI layer 302 has a desired panel size size. A silicon nitride layer 305 and a silicon oxide layer 306 are formed on the SOI layer 302 according to the element formation region. The silicon oxide layer 306 is used as a hard mask when etching the SOI layer 302 for element separation. The silicon nitride layer 305 is an etching stopper.

0181The film thickness of the SOI layer 302 is preferably 5 nm to 500 nm, preferably 10 nm to 200 nm. The thickness of the SOI layer 302 can be appropriately set by controlling the depth of the separation layer described in the above embodiment. P-type impurities such as boron, aluminum, and gallium are added to the SOI layer 302 in order to control the threshold voltage. For example, 5 × 10 boron as a p-type impurity¹⁷cm^-3Above 1 × 10¹⁸cm^-3It may be added at the following concentrations.

0182FIG. 19B is a step of etching the SOI layer 302 and the bonding layer 304 using the silicon oxide layer 306 as a mask. The exposed end faces of the silicon oxide layer 306, the silicon nitride layer 305, the SOI layer 302, and the bonding layer 304 are nitrided by plasma treatment. By this nitriding treatment, the nitriding treatment layer 307 is formed at the peripheral ends of the silicon oxide layer 306, the silicon nitride layer 305, the SOI layer 302, and the bonding layer 304. Further, as the nitriding treatment layer 307, a silicon nitride layer is formed at least at the peripheral end of the SOI layer 302. The silicon nitride layer formed at the peripheral end of the SOI layer 302 is insulating and has an effect of preventing leakage current from flowing at the end face of the SOI layer 302. Further, since it has an oxidation resistance effect, it is possible to prevent an oxide film from growing from the end face and forming a bird's beak between the SOI layer 302 and the bonding layer 304.

0183FIG. 19C shows a step of depositing the element separation insulating layer 308. In the device separation insulating layer 308, TEOS is used as a raw material gas and a silicon oxide layer is deposited by a chemical vapor deposition method. The element separation insulating layer 308 is thickly deposited so that the SOI layer 302 is embedded.

0184FIG. 19D shows a process of removing the element separation insulating layer 308 until the silicon nitride layer 305 is exposed. This removing step may be performed by dry etching or by chemical mechanical polishing. The silicon nitride layer 305 serves as an etching stopper. The element separation insulating layer 308 remains so as to be embedded between the SOI layers 302. The silicon nitride layer 305 is then removed.

0185In FIG. 19E, after the SOI layer 302 is exposed, the gate insulating layer 309, the gate electrode 310, and the sidewall insulating layer 311 are formed, and the high-concentration impurity region 312 and the low-concentration impurity region 313 are formed. The insulating layer 314 is made of silicon nitride and is used as a hard mask when etching the gate electrode 310.

0186In FIG. 20 (A), the interlayer insulating layer 315 is formed. The interlayer insulating layer 315 forms a BPSG (Boron Phosphorus Silicon Glass) layer and is flattened by reflow. Further, TEOS may be used as a raw material gas to form a silicon oxide layer and flattened by a chemical mechanical polishing treatment. In the flattening process, the insulating layer 314 on the gate electrode 310 functions as an etching stopper. A contact hole 316 is formed in the interlayer insulating layer 315. The contact hole 316 has a self-aligned contact structure using the sidewall insulating layer 311.

0187Then, as shown in FIG. 20 (B), the contact plug 317 is formed by the CVD method using tungsten hexafluoride. Further, an insulating layer 318 is formed, an opening is formed in accordance with the contact plug 317, and the wiring 319 is provided. The wiring 319 is formed of aluminum or an aluminum alloy, and the upper and lower layers are formed of a metal film such as molybdenum, chromium, or titanium as a barrier metal.

0188In this way, the transistor can be manufactured by using the SOI layer 302 bonded to the base substrate 300. The transistor shown in the present embodiment can be applied to a pixel circuit unit, a peripheral circuit unit, or the like of the display device according to the present invention. According to the present embodiment, by using the SOI substrate manufactured in the first or second embodiment, it is possible to form an element constituting one display panel with one SOI layer, so that variation in characteristics is suppressed. be able to. Further, although the SOI substrate is manufactured from a plurality of SOI layers, the yield can be improved in the manufacture of the display device by setting the size of each SOI layer to a desired panel size.

0189The present embodiment can be freely combined with the above-described first embodiment or second embodiment.

0190<figref num="1">The perspective view which shows the example of the structure of the SOI substrate which concerns on this invention.</figref><figref num="2">The cross-sectional view which shows the example of the structure of the SOI substrate which concerns on this invention.</figref><figref num="3">The cross-sectional view which shows the example of the structure of the SOI substrate which concerns on this invention.</figref><figref num="4">The cross-sectional view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="5">The cross-sectional view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="6">Top view showing an example of a method for manufacturing an SOI substrate according to the present invention.</figref><figref num="7">The cross-sectional view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="8">The perspective view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="9">Top view, cross-sectional view and perspective view showing an example of the display device according to the present invention.</figref><figref num="10">The top view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="11">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="12">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="13">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="14">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="15">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="16">The figure which shows the example of the structure of the plasma processing apparatus.</figref><figref num="17">The exploded view which shows the example of the display device which concerns on this invention.</figref><figref num="18">The perspective view which shows the example of the display device which concerns on this invention.</figref><figref num="19">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="20">The cross-sectional view which shows the example of the manufacturing method of the display device which concerns on this invention.</figref><figref num="21">The cross-sectional view which shows the example of the display device which concerns on this invention.</figref><figref num="22">The cross-sectional view which shows the example of the display device which concerns on this invention.</figref><figref num="23">The cross-sectional view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="24">The cross-sectional view which shows the example of the manufacturing method of the SOI substrate which concerns on this invention.</figref><figref num="25">The top view which shows the example of the SOI substrate which concerns on this invention.</figref><figref num="26">The top view which shows the example of the SOI substrate which concerns on this invention.</figref>

Code description

0191100 SOI board 101 Semiconductor substrate 102 Semiconductor substrate 103 Separation layer 104 ions 110 base board 120 insulation layer 122 Bonding layer 124 Nitrogen-containing insulating layer 126 Silicon oxide layer 130 SOI layer 150 insulation layer 152 Barrier layer 154 Bonding layer