JP5315134B2

Semiconductor device

Abstract

An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device atlow cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.

JP5315134B2, drawing sheet 1 — Sheet 1 of 26

Term

Projected expiry 3 June 2029.

1 claim: 1 independent, 0 dependent

1
半導体集積回路と、前記半導体集積回路の上方に設けられ、前記半導体集積回路と電気的に接続されたアンテナと、前記半導体集積回路及び前記アンテナを挟持する、第1の絶縁体及び第2の絶縁体と、前記第1の絶縁体の表面に設けられた第1の導電性遮蔽体と、前記第2の絶縁体の表面に設けられた第2の導電性遮蔽体と、を有し、前記第1の絶縁体は、前記アンテナの上方に設けられ、前記第2の絶縁体は、前記半導体集積回路の下方に設けられ、前記第2の導電性遮蔽体は、前記第1の導電性遮蔽体の膜厚よりも膜厚が厚い領域を有することを特徴とする半導体装置。

304 paragraphs, as filed

0001The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

0002In semiconductor devices (also called non-contact signal processing devices, semiconductor integrated circuit chips, and IC chips) that transmit and receive data by wireless communication via an antenna, the problem of semiconductor device destruction (electrostatic destruction) due to external electrostatic discharge It is an important problem that causes a decrease in reliability and productivity from the manufacturing process of semiconductor devices to inspection and use as a product, and countermeasures have been reported (see, for example, Patent Document 1).

0003Patent Document 1 is an example of the above-mentioned semiconductor device in which a conductive polymer layer is used for a substrate and an adhesive to prevent electrostatic breakdown.

<patcit num="1"><text>Japanese Patent Application Laid-Open No. 2007-241999</text></patcit>

As the market for the semiconductor devices expands, there are various requirements for their shapes and required characteristics. Therefore, there is a demand for a semiconductor device that has high resistance to electrostatic breakdown and has the required characteristics.It is also important to increase the strength against external stress in the semiconductor device, which has been made smaller and thinner.Therefore, one of the purposes of the present invention is to provide a highly reliable semiconductor device that is resistant to external stress and electrostatic discharge while achieving thinness and miniaturization. Another object of the present invention is to prevent defects in shape and characteristics due to external stress or electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with a good yield. One of the purposes is to manufacture a semiconductor device at low cost and with high productivity.

One aspect of the semiconductor device of the present invention has an antenna and a pair of insulators sandwiching a semiconductor integrated circuit electrically connected to the antenna, and is located outside the insulator (on the side opposite to the semiconductor integrated circuit side). A conductive shield is provided by the plating method. In the present invention, the conductive shields are formed so as to be electrically connected to each other.The conductive shield may be formed by a plating method so as to cover the entire periphery (upper surface, lower surface, side surface) of the semiconductor device (so as to wrap the semiconductor device), or a pair of conductive shields provided on the outside of each insulator. Conductive regions may be formed that electrically connect the bodies. The conductive region may be a part of the side surface of the semiconductor device, or may be an electrode layer penetrating the inside of the semiconductor device. In the semiconductor device, the side surface is a cut surface (divided cross section) generated when a plurality of semiconductor integrated circuit chips provided in the same insulator are cut (divided) into individual chips. The cut surface may be completely covered with a conductive shield, or may be partially covered.One aspect of the semiconductor device of the present invention is a non-contact signal processing device having a function of transmitting and receiving signals to and from an external device by wireless communication. Therefore, the conductive shield transmits electromagnetic waves to be transmitted and received by the antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit inside the semiconductor device.The conductive shield diffuses and releases the static electricity applied by the electrostatic discharge, or prevents the local existence (localization) of the electric charge (to prevent the local potential difference from occurring), so that the semiconductor integrated circuit It is possible to prevent static electricity destruction. The conductive shield is formed so as to cover (overlap) both surfaces of the semiconductor integrated circuit with the insulator interposed therebetween.The conductive shield is not electrically connected to the antenna and the semiconductor integrated circuit.Such a conductive shield is formed of a film thickness and a material that transmit electromagnetic waves to be transmitted and received by the sandwiching antenna and the semiconductor integrated circuit and block static electricity. Therefore, it is possible to provide a highly reliable semiconductor device capable of transmitting and receiving data by wireless communication via an antenna, which is resistant to electrostatic breakdown.The pair of insulators sandwiching the semiconductor integrated circuit also function as an impact resistant layer against a force (also referred to as external stress) applied to the semiconductor device from the outside and a shock diffusing layer for diffusing the force. By providing the insulator, the force applied locally can be reduced, so that it is possible to prevent the semiconductor device from being damaged or having poor characteristics due to external stress.In a semiconductor device, a semiconductor integrated circuit is sandwiched by a pair of insulators. The semiconductor integrated circuit is manufactured on a substrate, adheres to an insulator, and is peeled off from the substrate. In the present specification, the surface generated in the semiconductor integrated circuit by peeling the semiconductor integrated circuit from the substrate is referred to as a peeled surface.As the conductive shield, it suffices to have conductivity, and a conductive layer formed by using a conductive material can be used. In the present invention, the conductive layer, which is a conductive shield, is formed of a film containing a metal by a plating method.As a method for forming the conductive shield, a wet plating method is used in which a film containing a metal is formed by reducing metal ions existing in an aqueous solution with electrons. Wet plating methods are classified by reduction method: electric reduction method (electrolytic (electroplating) plating method), reduction method with a reducing agent (electroless plating method), reduction method according to the difference in ionization tendency (replacement plating). Law) and so on. In the present invention, the above-mentioned wet plating method can be used, and the above-mentioned wet plating method may be used in combination.Since the wet plating method can form a film isotropically formed on the object, the area where the film can be formed is wide, and the periphery (upper surface, lower surface, side surface) of the semiconductor device is covered by one plating step. A conductive shield can be formed. The conductive shield formed in the plating step of the same step can be a continuous film.The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost. Therefore, when the plating method is used for forming the conductive shield, the semiconductor device of the present invention can be manufactured at low cost and with high productivity. The cost reduction of the process makes it possible to provide a semiconductor device at a lower price.As the conductive shield, a film such as a metal or a metal alloy, or a laminate thereof can be used. The film thickness of the conductive shield is larger than 0 nm and may be about 1 μm or less.Further, the protective layer on the conductive shield may be laminated. Even when the conductive shield is provided on the surface of the semiconductor device by the protective layer, the protective layer becomes the outermost surface, and deterioration of the conductive shield can be prevented.As the insulator, a structure in which the fiber body is impregnated with an organic resin can be used.Further, as the insulator, a material having a low elastic modulus and a high breaking strength may be used.The insulator is preferably made of a high-strength material. Typical examples of high-strength materials include polyvinyl alcohol-based resins, polyester-based resins, polyamide-based resins, polyethylene-based resins, aramid-based resins, polyparaphenylene benzobisoxazole resins, and glass resins. If an insulator made of an elastic high-strength material is provided, a load such as local pressing is diffused and absorbed throughout the layer, so that damage to the semiconductor device can be prevented.More specifically, as the insulator, an aramid resin, a polyethylene naphthalate (PEN) resin, a polyether sulfone (PES) resin, a polyphenylene sulfide (PPS) resin, a polyimide (PI) resin and the like can be used.In the present specification, transposition (also referred to as transposition) means that a semiconductor integrated circuit formed on a certain substrate is peeled off from the substrate and transferred to another substrate. In other words, it can be said that the place where the semiconductor integrated circuit is provided is moved to another substrate.One embodiment of the method for manufacturing a semiconductor device of the present invention is a first insulator in which an antenna electrically connected to the semiconductor integrated circuit and the semiconductor integrated circuit is formed, and the semiconductor integrated circuit and the antenna are provided so as to face each other. A conductive shield is formed by a plating method, which is sandwiched between the first insulator and the second insulator and electrically connected to the surface of the first insulator and the second insulator on the opposite side of the semiconductor integrated circuit.One embodiment of the method for manufacturing a semiconductor device of the present invention is a first insulator in which an antenna electrically connected to the semiconductor integrated circuit and the semiconductor integrated circuit is formed, and the semiconductor integrated circuit and the antenna are provided so as to face each other. The semiconductor integrated circuit, the antenna, the first insulator, and the second insulator are immersed in a plating solution containing a conductive material to cover the surface of the laminate. Form a sex shield.One embodiment of the method for manufacturing a semiconductor device of the present invention is a first insulator in which an antenna electrically connected to the semiconductor integrated circuit and the semiconductor integrated circuit is formed, and the semiconductor integrated circuit and the antenna are provided so as to face each other. The semiconductor integrated circuit, the antenna, the first insulator, and the laminate of the second insulator are immersed in a solution containing the catalyst substance, and the catalyst substance is placed on the surface of the laminate. The laminate to be adsorbed and the catalyst substance is adsorbed is immersed in a plating solution containing a conductive material to form a conductive shield covering the surface of the laminate to which the catalyst substance is adsorbed.The insulator may be adhered to the semiconductor integrated circuit by an adhesive layer, and in this case, the insulator has an adhesive layer between the semiconductor integrated circuit and the insulator. Further, the insulator and the semiconductor integrated circuit may be directly bonded by heating and pressurizing treatment.In the present invention, the semiconductor device refers to a device that can function by utilizing semiconductor characteristics. Using the present invention, it is possible to manufacture a device having a circuit including a semiconductor element (transistor, memory element, diode, etc.) or a semiconductor device such as a chip having a processor circuit.

The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

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0034Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

0035(Embodiment 1) In the present embodiment, a more reliable semiconductor device and a method for manufacturing a semiconductor device having a high yield will be described in detail with reference to FIGS. 1 to 3.

0036In the semiconductor device of the present embodiment, the semiconductor integrated circuit is peeled off from the substrate at the time of fabrication and sandwiched between flexible insulators. In this specification, the substrate on which the semiconductor integrated circuit is manufactured is also referred to as a fabrication substrate. Therefore, the semiconductor integrated circuit is formed on the fabrication substrate via the release layer.

0037Figures 3 (A), (B), and (C) show the semiconductor device of this embodiment. In FIG. 3A, the antenna 101 and the semiconductor integrated circuit 100 electrically connected to the antenna 101 are sandwiched between the first insulator 112 and the second insulator 102, and the first insulator 112. , And the conductive shield 140 is provided on the outside (opposite side of the semiconductor integrated circuit 100) and the side surface of the second insulator 102. Further, the antenna 101 may be provided below or outside the semiconductor integrated circuit 100 (so as not to overlap the semiconductor integrated circuit 100). The conductive shield 140 formed on the outside of the first insulator 112 and the second insulator 102 is a continuous film formed in the same step, or at least electrically connected.

0038In particular, by electrically connecting the conductive shield 140 formed on the outside of the first insulator 112 and the second insulator 102, the outside of the first insulator 112 and the second insulator 102 Compared with the case where the conductive shields formed in the above are not electrically connected to each other, or when the conductive shields are provided on one of the first insulator 112 and the second insulator 102, It is possible to effectively diffuse static electricity and effectively prevent the localization of electricity. As a result, it is possible to more effectively prevent the semiconductor integrated circuit 100 from being destroyed by static electricity.

0039The conductive shield 140 may be formed by a plating method so as to cover the entire periphery (upper surface, lower surface, side surface) of the semiconductor device (so as to wrap the semiconductor device), or the first insulator 112 and the second insulator, respectively. A conductive region may be formed to electrically connect the conductive shield 140 provided on the outside of the insulator 102. The conductive region may be a part of the side surface of the semiconductor device, or may be an electrode layer penetrating the inside of the semiconductor device. In the semiconductor device, the side surface is a cut surface (divided cross section) generated when a plurality of semiconductor integrated circuit chips provided in the same insulator are cut (divided) into individual chips. The cut surface may be completely covered by the conductive shield 140, or may be partially covered.

0040FIG. 3 (C) shows a plan view of the semiconductor device shown in FIGS. 3 (A) and 3 (B). In FIG. 3C, the laminate 143 of the first insulator 112, the antenna 101, the semiconductor integrated circuit 100, and the second insulator 102 is the conductive shield 140a (first insulator 112 side (surface side)). , 140b (second insulator 102 side (also called back surface side, bottom surface side)), 140c1, 140c2, 140c3, 140c4 (side surface side).

0041FIG. 22 (A) shows a structure in which the conductive shield 140 covers at least one side surface. Further, FIG. 22 (B) shows an example in which the conductive shields 140a and 140b formed on the surface are electrically connected by the electrode layers 141a and 141b penetrating the inside of the semiconductor device, and FIG. 22 (C) shows an example in which the electrode layers 141a and 141b are electrically connected. Is. The electrode layers 141a and 141b can be formed by forming through holes before forming the conductive shield by the plating method and filling them with a plating solution. In addition, in FIGS. 22 (B) and 22 (C), the individual antenna 101 and the semiconductor integrated circuit 100 are separated before the second insulator 102 is bonded, and the second insulator 102 is formed so as to fill the opening. This is an example of bonding. Therefore, in the cross-sectional view of FIGS. 22 (B) and 22 (C), the antenna 101 and the semiconductor integrated circuit 100 are separated by an insulator.

0042The conductive shield 140 is provided over the entire region overlapping the semiconductor integrated circuit 100 so as to cover the semiconductor integrated circuit 100, and sandwiches the semiconductor integrated circuit 100.

0043Further, the conductive shield 140, the semiconductor integrated circuit 100, and the antenna 101 are not electrically connected to each other.

0044The semiconductor device of the present embodiment is a non-contact signal processing device having a function of transmitting and receiving signals to and from an external device by wireless communication. Therefore, the conductive shield 140 transmits electromagnetic waves to be transmitted and received by the antenna 101 included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit 100 inside the semiconductor device. The conductive shield 140 is a semiconductor integrated circuit in order to diffuse and release the static electricity applied by the electrostatic discharge or to prevent the local existence (localization) of the electric charge (to prevent the occurrence of a local potential difference). It can prevent 100 electrostatic destruction.

0045Since the semiconductor integrated circuit 100 is provided with a conductive shield that is electrically connected to both the front surface and the back surface, it is protected over a wide area against static electricity from the outside, and has a higher antistatic effect. Can be obtained.

0046Since the surface of the antenna 101 on the opposite side of the semiconductor integrated circuit 100 is less resistant to electrostatic discharge (ESD), the thickness of the conductive shield 140 on the second insulator 102 side is set to the thickness of the first insulator 112 side. It may be thicker than the conductive shield 140 of.

0047Further, the semiconductor device shown in the present embodiment operates by generating an induced electromotive force by an electromagnetic wave from the outside (having a wireless function). Therefore, the conductive shield needs to be formed by using a conductive material that transmits electromagnetic waves while preventing the semiconductor integrated circuit from being destroyed by static electricity.

0048It is generally known that electromagnetic waves are attenuated in a substance, and this attenuation is particularly remarkable in a conductive material. Therefore, in the present embodiment, the film thickness is sufficiently thin so that electromagnetic waves can pass through the conductive shield.

0049The film thickness of the conductive shield may be determined based on the frequency of electromagnetic waves used for communication, the resistivity of the conductive material used as the conductive shield, and the magnetic permeability.

0050For example, the frequency of electromagnetic waves is 13.56 MHz, and the resistivity ρ: 5.5 × 10 as a conductive shield.-7When using a conductive material of (Ω m), the film thickness should be at least about 500 nm or less. As a result, it is possible to suppress the destruction of the semiconductor device due to electrostatic discharge and to perform good communication with the outside.

0051Further, when a conductive material having a higher resistivity is used, the film thickness may be formed to be about 700 nm or less.

0052Further, the lower limit of the film thickness of the conductive shield is preferably determined based on the resistivity. For example, when the resistivity of the conductive material used as the conductive shield is high, it is preferable to form the conductive shield thickly in order to effectively diffuse static electricity. If the conductive shield is made too thin using a conductive material with high resistivity, the sheet resistance will increase, and static electricity cannot be effectively diffused when electrostatic discharge occurs, and a large current will flow through the semiconductor integrated circuit. This is because there is a risk of being destroyed.

0053Therefore, in order to effectively prevent the destruction of the semiconductor device due to static electricity, the sheet resistance of the conductive shield is 1.0 × 10.7Ω / or less, preferably 1.0 × 104Ω / or less, more preferably 1.0 × 102It is preferable to set the film thickness so that it is Ω / or less.

0054If the sheet resistance of the conductive shield is within the above range, it is preferable to reduce the film thickness as much as possible from the viewpoint of transmitting electromagnetic waves.

0055When a material having a low resistivity is used as the conductive material, the sheet resistance can be sufficiently reduced and electromagnetic waves can be easily transmitted even when the film thickness is extremely thin. Considering the process and the like, the thickness may be about 1 nm or more (preferably 3 nm or more).

0056On the other hand, when a material having a relatively high resistivity is used, the thickness is preferably at least 5 nm or more.

0057By forming the conductive shield as described above, it is possible to obtain a semiconductor device capable of effectively suppressing destruction of the semiconductor device due to electrostatic discharge and satisfactorily communicating with the outside.

0058Next, the materials and the like applicable to the configuration shown in FIG. 1 will be described in detail.

0059As the conductive shield, it suffices to have conductivity, and a conductive layer formed by using a conductive material can be used. In the present invention, the conductive layer, which is a conductive shield, is formed of a film containing a metal by a plating method.

0060In the present invention, a wet plating method is used in which a film containing a metal is formed by reducing metal ions existing in an aqueous solution with electrons. Wet plating methods are classified by reduction method: electric reduction method (electrolytic (electroplating) plating method), reduction method with a reducing agent (electroless plating method), reduction method according to the difference in ionization tendency (replacement plating). Law) and so on. In the present invention, the above-mentioned wet plating method can be used, and the above-mentioned wet plating method may be used in combination.

0061Since the wet plating method can form a film isotropically formed on the object, the area where the film can be formed is wide, and the periphery (upper surface, lower surface, side surface) of the semiconductor device is covered by one plating step. A conductive shield can be formed. The conductive shield formed in the plating step of the same step can be a continuous film.

0062The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost. Therefore, when the plating method is used for forming the conductive shield, the semiconductor device of the present invention can be manufactured at low cost and with high productivity. The cost reduction of the process makes it possible to provide a semiconductor device at a lower price.

0063Such a conductive shield 140 is formed of a film thickness and a material that transmit electromagnetic waves to be transmitted and received by the sandwiching antenna and the semiconductor integrated circuit and block static electricity. Therefore, it is possible to provide a highly reliable semiconductor device capable of transmitting and receiving data by wireless communication via an antenna, which is resistant to electrostatic breakdown.

0064As the conductive shield 140, a single layer or a laminate of a film containing a metal that can be formed by a wet plating method can be used.

0065The conductive shield 140 is, for example, an element selected from nickel, copper, tin, silver, gold, platinum, palladium, zinc, cadmium, chromium, iron, cobalt, and tungsten, or an alloy material containing the element as a main component. It may be formed with.

0066Alloy materials include nickel alloys (nickel phosphorus (NiP) alloy, nickel boron (NiB) alloy, nickel cobalt (NiCo) alloy, nickel cobalt phosphorus (NiCoP) alloy, nickel iron phosphorus (NiFeP) alloy, nickel tungsten phosphorus (NiWP). ) Alloys, etc.), zinc alloys (zinc-iron alloys, zinc-nickel alloys, tin-zinc alloys), tin alloys (tin-silver alloys, tin-cobalt alloys), copper-zinc alloys (brass), etc.

0067By a film containing a metal formed by a plating method and other manufacturing methods (sputtering method, plasma CVD method, various dry methods such as vapor deposition method, coating method, printing method, droplet ejection method (inkprint method), etc.) A film of a formed metal, metal nitride, metal oxide or the like, and a laminate thereof may be used. Metal nitrides and metal oxides can also be formed by nitriding or oxidizing the surface of a metal film.

0068As the metal nitride, tantalum nitride, titanium nitride and the like can be used.

0069As the metal oxide, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide and the like can be used. In addition, indium zinc oxide containing zinc oxide (ZnO) (IZO (Indium Zinc Oxide)), zinc oxide (ZnO), zinc oxide containing gallium (Ga), tin oxide (SnO).2), Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and the like may also be used.

0070Depending on the wet plating method used and the conductive material, treatments such as formation of a conductive film (seed layer) in a region (object to be plated) on which a plating film is formed and adsorption of a catalytic substance are appropriately performed.

0071Further, the protective layer on the conductive shield 140 may be laminated. The protective layer can be formed by using a nitride material (for example, tantalum nitride, titanium nitride, etc.) or an oxide material (for example, titanium oxide, etc.). Even when the conductive shield 140 is provided on the surface of the semiconductor device by the protective layer, the protective layer becomes the outermost surface, and deterioration of the conductive shield 140 can be prevented. The protective layer may have a film thickness of 10 nm or more and 200 nm or less.

0072As the insulator, a structure in which the fiber body is impregnated with an organic resin can be used. FIGS. 2 (A) to 2 (C) show examples of using a structure in which the fiber body is impregnated with an organic resin in the first insulator 112 and the second insulator 102. FIGS. 2 (A) and 2 (B) correspond to FIGS. 3 (A) and 3 (B).

0073The first insulator 112 and the second insulator 102 use a structure in which the fiber body is impregnated with an organic resin, and the first insulator 112 is a structure in which the fiber body 160 is impregnated with an organic resin 161. The second insulator 102 is a structure in which the fiber body 150 is impregnated with the organic resin 151.

0074FIG. 2 (C) shows a plan view of a woven fabric in which the fiber body 160 is woven with a fiber yarn bundle as warp and weft.

0075As shown in FIG. 2C, the fiber body 160 is woven with warp yarns at regular intervals and weft yarns at regular intervals. The fiber body woven using such warp and weft has a region where the warp and weft do not exist. In such a fiber body 160, the proportion of the organic resin 161 impregnated increases, and the adhesion between the fiber body 160 and the semiconductor integrated circuit can be improved.

0076Further, the fiber body 160 may have a high density of warp and weft and a low proportion of regions where the warp and weft do not exist.

0077The structure in which the fiber body 160 is impregnated with the organic resin 161 is also called a prepreg. Specifically, the prepreg is obtained by impregnating a fiber body with a varnish obtained by diluting a matrix resin with an organic solvent, and then drying and volatilizing the organic solvent to semi-cure the matrix resin. The thickness of the structure is preferably 10 μm or more and 100 μm or less, and more preferably 10 μm or more and 30 μm. By using a structure having such a thickness, a thin and bendable semiconductor device can be manufactured. For example, as an insulator, a prepreg having an elastic modulus of 13 GPa or more and 15 GPa or less and a breaking coefficient of 140 MPa can be used.

0078The structure in which the fiber body is impregnated with the organic resin may have a plurality of layers laminated. In this case, a structure may be formed by laminating a plurality of structures impregnated with an organic resin on a single layer fiber body, or a structure impregnated with an organic resin on a plurality of laminated fibrous bodies. You may use it. Further, when a plurality of structures impregnated with an organic resin are laminated on a single layer fiber body, another layer may be sandwiched between the structures.

0079Further, as the organic resin 161, a thermosetting resin such as an epoxy resin, an unsaturated polyester resin, a polyimide resin, a bismaleimide triazine resin, or a cyanate resin can be used. Alternatively, as the organic resin 161, a thermoplastic resin such as a polyphenylene oxide resin, a polyetherimide resin, or a fluororesin can be used. Further, as the organic resin 161, a plurality of the above thermoplastic resin and the above thermosetting resin may be used. By using the above organic resin, the fibrous body can be fixed to the semiconductor integrated circuit by heat treatment. The higher the glass transition temperature of the organic resin 161 is, the more difficult it is to break due to local pressing, which is preferable.

0080The high thermal conductivity filler may be dispersed in the organic resin 161 or in the yarn bundle of the fiber. Examples of the high thermal conductive filler include aluminum nitride, boron nitride, silicon nitride, and alumina. Further, examples of the highly thermally conductive filler include metal particles such as silver and copper. Since the conductive filler is contained in the organic resin or the fiber yarn bundle, the heat generated in the semiconductor integrated circuit is easily released to the outside, so that it is possible to suppress the heat storage of the semiconductor device and reduce the destruction of the semiconductor device. can do.

0081The fiber body 160 is a woven fabric or a non-woven fabric using high-strength fibers of an organic compound or an inorganic compound, and is arranged so as to partially overlap. Specific examples of the high-strength fiber are fibers having a high tensile elastic modulus or Young's modulus. Typical examples of high-strength fibers include polyvinyl alcohol-based fibers, polyester-based fibers, polyamide-based fibers, polyethylene-based fibers, aramid-based fibers, polyparaphenylene benzobisoxazole fibers, glass fibers, and carbon fibers. Examples of the glass fiber include glass fibers using E glass, S glass, D glass, Q glass and the like. The fiber body 160 may be formed of one type of the above-mentioned high-strength fiber. Further, it may be formed of a plurality of the above-mentioned high-strength fibers.

0082Further, in the fiber body 160, a woven fabric woven using a bundle of fibers (single yarn) (hereinafter referred to as a yarn bundle) as a warp and a weft, or a yarn bundle of a plurality of types of fibers is randomly deposited or unidirectionally deposited. It may be a non-woven fabric. In the case of woven fabric, plain weave, twill weave, satin weave and the like can be appropriately used.

0083The cross section of the yarn bundle may be circular or elliptical. As the fiber yarn bundle, a fiber yarn bundle that has been opened by high-pressure water flow, high-frequency vibration using a liquid as a medium, vibration of continuous ultrasonic waves, pressing by a roll, or the like may be used. The fiber yarn bundle that has been subjected to the fiber opening process has a wider yarn bundle width, can reduce the number of single yarns in the thickness direction, and has an elliptical or flat cross section of the yarn bundle. Further, by using low-twisted yarn as the fiber yarn bundle, the yarn bundle is easily flattened, and the cross-sectional shape of the yarn bundle becomes an elliptical shape or a flat plate shape. As described above, the fiber body 160 can be thinned by using a thread bundle having an elliptical or flat cross section. Therefore, the structure can be made thin, and a thin semiconductor device can be manufactured.

0084In the drawings of the present embodiment, the fiber body 160 is shown as a plain weave with a yarn bundle having an elliptical cross section.

0085Further, in order to increase the penetration rate of the organic resin into the fiber yarn bundle, the fiber may be surface-treated. For example, there are corona discharge treatment, plasma discharge treatment, etc. for activating the fiber surface. In addition, there is a surface treatment using a silane coupling agent and a titanate coupling agent.

0086Further, as the first insulator 112 and the second insulator 102, materials having a low elastic modulus and high breaking strength may be used. For example, as the first insulator 112 and the second insulator 102, a film having rubber elasticity having an elastic modulus of 5 GPa or more and 12 GPa or less and a breaking coefficient of 300 MPa or more can be used.

0087The first insulator 112 and the second insulator 102 are preferably made of a high-strength material. Typical examples of high-strength materials include polyvinyl alcohol-based resins, polyester-based resins, polyamide-based resins, polyethylene-based resins, aramid-based resins, polyparaphenylene benzobisoxazole resins, and glass resins. When the first insulator 112 and the second insulator 102 formed of a high-strength material having elasticity are provided, a load such as local pressing is diffused and absorbed throughout the layer, thereby preventing damage to the semiconductor device. be able to.

0088More specifically, as the first insulator 112 and the second insulator 102, aramid resin, polyethylene naphthalate (PEN) resin, polyether sulfone (PES) resin, polyphenylene sulfide (PPS) resin, polyimide ( PI) Resin or the like can be used.

0089An adhesive layer may be used to bond the semiconductor integrated circuit 100 or the antenna 101 to the first insulator 112 and the second insulator 102. As the adhesive layer, it is sufficient that the insulator and the semiconductor integrated circuit can be fixed, and thermosetting resin, ultraviolet curable resin, acrylic resin type, urethane resin type, epoxy resin type, silicone resin type and the like can be used. The adhesive layer may have a film thickness of 3 μm or more and 15 μm or less. When the semiconductor integrated circuit 100, the first insulator 112, and the second insulator 102 are bonded by heat and pressure treatment, it is not necessary to use an adhesive layer.

0090Further, a protective layer may be formed on the semiconductor integrated circuit. FIG. 3 (B) and FIG. 2 (B) show an example in which an inorganic insulating layer 105 is formed as a protective layer on the semiconductor integrated circuit 100. Further, FIGS. 3B and 2B are examples in which the antenna 101 is formed on the semiconductor integrated circuit 100 and the inorganic insulating layer 105 is formed on the antenna 101. By covering the antenna 101 with the inorganic insulating layer 105, it is possible to prevent oxidation of the conductive layer that functions as an antenna.

0091The inorganic insulating layer 105 is formed by a single layer or a laminate using an inorganic compound by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. Typical examples of inorganic compounds include silicon oxides and silicon nitrides. Typical examples of silicon oxides and silicon nitrides include silicon oxide, silicon nitride nitride, silicon nitride, silicon nitride and the like. In the present specification, the silicon oxide film has a composition of oxygen content higher than that of nitrogen, and has a concentration range of 55 to 65 atomic% of oxygen and 1 to 20 atomic% of nitrogen. Si is contained in the range of 25 to 35 atomic% and hydrogen is contained in the range of 0.1 to 10 atomic%. The silicon nitride film has a higher nitrogen content than oxygen in its composition, and has a concentration range of 15 to 30 atomic% of oxygen, 20 to 35 atomic% of nitrogen, and 25 to Si. It refers to those containing 35 atomic% and hydrogen in the range of 15 to 25 atomic%.

0092Further, the inorganic insulating layer 105 may have a laminated structure. For example, it may be laminated using an inorganic compound, and typically, it may be formed by laminating silicon oxide, silicon nitride oxide, and silicon nitride nitride.

0093The method for manufacturing the semiconductor device of the present invention will be described with reference to FIGS. 1 (A) to 1 (E). The antenna 101 and the semiconductor integrated circuit 100 are formed on the substrate 110 having an insulating surface, which is a fabrication substrate, via the release layer 111 (see FIG. 1 (A)).

0094As the substrate 110 as the fabrication substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the process to be performed.

0095The release layer 111 may be formed of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), or the like by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. Elements selected from cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), Alternatively, an alloy material containing an element as a main component or a layer made of a compound material containing the element as a main component is formed as a single layer or laminated. The crystal structure of the layer containing silicon may be amorphous, microcrystal, or polycrystalline. Here, the coating method includes a spin coating method, a droplet ejection method, and a dispensing method.

0096When the release layer 111 has a single layer structure, it preferably forms a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum. Alternatively, a layer containing an oxide or nitride of tungsten, a layer containing an oxide or nitride of molybdenum, or a layer containing an oxide or nitride of a mixture of tungsten and molybdenum is formed. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

0097When the release layer 111 has a laminated structure, preferably, the first layer is a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum, and the second layer is tungsten, molybdenum, or a mixture of tungsten and molybdenum. Form oxides, nitrides, oxide nitrides or oxides.

0098When forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 111, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer. It may be utilized that a layer containing an oxide of tungsten is formed at the interface between the tungsten layer and the insulating layer. Further, the surface of the layer containing tungsten may be subjected to thermal oxidation treatment, oxygen plasma treatment, treatment with a solution having strong oxidizing power such as ozone water, or the like to form a layer containing an oxide of tungsten. Further, the plasma treatment and the heat treatment may be carried out in an atmosphere of oxygen, nitrogen, nitrous oxide, or a mixed gas atmosphere of the gas and another gas. This also applies to the case of forming a layer containing a tungsten nitride, an oxide nitride and a nitride oxide. After forming a layer containing tungsten, a silicon nitride layer, a silicon oxide layer and a silicon nitride oxide are formed on the layer. It is good to form a layer.

0099Further, according to the above step, the release layer 111 is formed so as to be in contact with the substrate 110, but the present invention is not limited to this step. An insulating layer as a base may be formed so as to be in contact with the substrate 110, and a release layer 111 may be provided so as to be in contact with the insulating layer.

0100The semiconductor integrated circuit 100 and the first insulator 112 are adhered to each other, and the semiconductor integrated circuit 100 is separated from the substrate 110 by using the release layer 111. Therefore, the semiconductor integrated circuit 100 is provided on the side of the first insulator 112 (see FIG. 1 (B)).

0101In the present embodiment, a structure in which the fiber body 160 is impregnated with the organic resin 161 is used as the first insulator 112. The structure is heated and crimped to plasticize or cure the organic resin of the structure. When the organic resin is a plastic organic resin, the plasticized organic resin is cured by cooling to room temperature. The organic resin is uniformly spread and cured so as to be in close contact with the semiconductor integrated circuit by heating and crimping. The step of crimping the structure is performed under atmospheric pressure or reduced pressure.

0102In the transfer step to another substrate, a release layer is formed between the substrate and the semiconductor integrated circuit, a metal oxide film is provided between the release layer and the semiconductor integrated circuit, and the metal oxide film is fragile due to crystallization. A method of peeling off the semiconductor integrated circuit, an amorphous silicon film containing hydrogen is provided between a substrate having high heat resistance and the semiconductor integrated circuit, and the amorphous silicon film is removed by irradiation or etching with laser light. By doing so, a method of peeling the semiconductor integrated circuit, a peeling layer is formed between the substrate and the semiconductor integrated circuit, a metal oxide film is provided between the peeling layer and the semiconductor integrated circuit, and the metal oxide film is crystallized. Weakened by, and part of the peeling layer is made into a solution or NF.3, BrF3, ClF3After removing by etching with a fluorinated halogen gas such as, a method of peeling off with a weakened metal oxide film, mechanically removing the substrate on which a semiconductor integrated circuit is formed, or using a solution or NF3, BrF3, ClF3A method of removing by etching with a fluorinated halogen gas or the like can be appropriately used. Further, a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, etc.) is used as the release layer, and the release layer is irradiated with laser light for release. A method of releasing nitrogen, oxygen or hydrogen contained in the layer as a gas to promote the separation between the semiconductor integrated circuit and the substrate may be used.

0103By combining the above peeling methods, the transposition step can be performed more easily. In other words, laser light irradiation, etching to the peeling layer with gas or solution, mechanical removal with a sharp knife or knife, etc. are performed to make the peeling layer and the semiconductor integrated circuit easy to peel off, and then physical. It can also be peeled off by force (by machine, etc.).

0104Further, the semiconductor integrated circuit may be peeled off from the manufactured substrate by infiltrating the liquid into the interface between the peeling layer and the semiconductor integrated circuit.

0105Similar to the first insulator 112, the second insulator 102 also uses a structure in which the fiber body 150 is impregnated with the organic resin 151.

0106The structure is heated and crimped to the exposed peeling surface of the semiconductor integrated circuit 100 to bond the second insulator 102, and the antenna 101 and the semiconductor integrated circuit 100 are attached to the first insulator 112 and the second insulator. It is sandwiched between 102 (see Fig. 1 (C)).

0107Although not shown, the first insulator 112 and the second insulator 102 sandwich a plurality of semiconductor integrated circuits, and are divided into individual semiconductor integrated circuits 100 to prepare a laminate 143 which is a semiconductor integrated circuit chip. To do. The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam.

0108By dividing, the antenna 101 and the semiconductor integrated circuit 100 are sealed by the first insulator 112 and the second insulator 102, and the chip has a divided cross section (side surface caused by the division).

0109The laminate 143 is immersed in a plating solution 145 containing a metal material for plating, and a film containing a metal is grown on the laminate 143 (see FIG. 1 (D)). The immersion time is controlled to reach the desired film thickness to form the conductive shield 140 (see FIG. 1 (E)).

0110Therefore, the antenna 101 and the semiconductor integrated circuit 100 are sealed by the first insulator 112 and the second insulator 102, and the first insulator 112 and the second insulator corresponding to the front surface and the back surface of the semiconductor device are provided. The structure is protected against electrostatic discharge by the conductive shield 140 provided on the outside and the side surface of the 102.

0111Since the plating solution 145 may be in contact with the area to be plated of the laminate 143, the dipping method is not limited. Therefore, the laminate 143 may be installed diagonally (or vertically), and the plating solution 145 may be applied so as to flow on the surface of the laminate 143. If plating is performed so that the laminate 143 is erected and the solution is applied, there is an advantage that the apparatus used in the process can be miniaturized even if the substrate has a large area.

0112The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0113(Embodiment 2) In the present embodiment, a semiconductor device for the purpose of imparting high reliability using the present invention, and another example of a method for manufacturing the semiconductor device will be described with reference to FIGS. 14 to 17. In the configuration of the present embodiment described below, the same reference numerals are commonly used between different drawings for the same parts as those of the first embodiment or the parts having the same functions, and the repeated description thereof will be omitted.

0114In this embodiment, an example in which the insulator has a laminated structure is shown. In FIG. 14A, the semiconductor integrated circuit 100 connected to the antenna 101 and the antenna 101 is sandwiched between the first insulator 112 and the second insulator 102, and the semiconductor integrated circuit 100 and the second insulator 102. A third insulator 103 is provided between the two, and a conductive shield 140 is provided on the outside (opposite side of the semiconductor integrated circuit 100) and the side surface of the first insulator 112 and the second insulator 102. The conductive shield 140 may be formed on all side surfaces and may be provided so as to surround (wrap) the periphery of the semiconductor device, or may be formed so as to cover a part of the side surfaces. In the present invention, the conductive shield formed on the outside of the first insulator 112 and the second insulator 102 is electrically connected. In the present embodiment, the conductive shield 140 is formed by the same plating step over the outside of the first insulator 112 and the second insulator 102, and is a continuous film.

0115FIG. 14B shows an example in which the semiconductor integrated circuit 100 and the third insulator 103 are fixed to each other by using the adhesive layer 104. In FIG. 14B, an acrylic resin is used as the adhesive layer 104.

0116The third insulator 103 provided between the semiconductor integrated circuit 100 and the second insulator 102 functions as a shock diffusion layer, and therefore has a lower elastic modulus than the first insulator 112 and the second insulator 102. And, it is preferable that the breaking strength is high.

0117The third insulator 103 has an effect of diffusing and reducing the force applied to the semiconductor integrated circuit from the outside by being provided in contact with the semiconductor integrated circuit.

0118As the first insulator 112 and the second insulator 102 in FIG. 14, a structure in which the fiber body is impregnated with an organic resin can be used. The first insulator 112 and the second insulator 102 in FIG. 14 preferably have an elastic modulus of 13 GPa or more and a breaking coefficient of less than 300 MPa.

0119As the third insulator 103, it is preferable to use a material having a low elastic modulus and a high breaking strength. For example, as the third insulator 103, a film having rubber elasticity having an elastic modulus of 5 GPa or more and 12 GPa or less and a breaking coefficient of 300 MPa or more can be used.

0120The third insulator 103 is preferably made of a high-strength material. Typical examples of high-strength materials include polyvinyl alcohol-based resins, polyester-based resins, polyamide-based resins, polyethylene-based resins, aramid-based resins, polyparaphenylene benzobisoxazole resins, and glass resins. When the third insulator 103 made of an elastic high-strength material is provided, a load such as local pressing is diffused and absorbed throughout the layer, so that damage to the semiconductor device can be prevented.

0121More specifically, as the third insulator 103, an aramid resin, a polyethylene naphthalate (PEN) resin, a polyether sulfone (PES) resin, a polyphenylene sulfide (PPS) resin, a polyimide (PI) resin, or the like is used. Can be done. In this embodiment, an aramid resin film (elastic modulus 10 GPa, breaking strength 480 MPa) is used as the third insulator 103.

0122Further, as shown in FIGS. 15A and 15B, a fourth insulator 113 similar to the third insulator 103 is provided on the outside of the first insulator 112 (opposite to the antenna 101). May be good.

0123FIG. 15A shows an example in which a fourth insulator 113 similar to the third insulator 103 is fixed to the outside of the first insulator 112 by using the adhesive layer 114. In this embodiment, an aramid film is used as the fourth insulator 113, and an acrylic resin is used as the adhesive layer 114. When the first insulator 112 and the fourth insulator 113 are bonded by heat and pressure treatment, the adhesive layer 114 may not be used. In this case, the antenna 101, the first insulator 112, and the fourth insulator 113 are directly bonded as shown in FIG. 15 (B). The bonding step between the antenna 101 and the first insulator 112 and the bonding step between the first insulator 112 and the fourth insulator 113 may be performed at the same time or may be performed in a separate process.

0124The method for manufacturing the semiconductor device of the present invention will be described with reference to FIGS. 16A to 16D. The antenna 101 and the semiconductor integrated circuit 100 are formed on the substrate 110 having an insulating surface, which is a fabrication substrate, via the release layer 111 (see FIG. 16 (A)).

0125The antenna 101, the semiconductor integrated circuit 100, and the first insulator 112 are adhered to each other, and the semiconductor integrated circuit 100 is separated from the substrate 110 by using the release layer 111. Therefore, the semiconductor integrated circuit 100 is provided on the side of the first insulator 112 (see FIG. 16 (B)).

0126Also in FIG. 16, a structure in which the fiber body 160 is impregnated with the organic resin 161 is used as the first insulator 112. The structure is heated and crimped to plasticize or cure the organic resin of the structure.

0127Similar to the first insulator 112, the second insulator 102 also uses a structure in which the fiber body 150 is impregnated with the organic resin 151. The structure is heated and crimped to bond the third insulator 103 and the second insulator 102. An adhesive layer 104 is provided on the opposite surface of the second insulator 102 of the third insulator 103.

0128The adhesive layer 104 is adhered to the exposed peeling surface of the semiconductor integrated circuit 100 (see FIG. 16 (C)).

0129Next, a conductive shield 140 is formed on the surface of the first insulator 112, the second insulator 102, and the side surface cut into chips by a wet plating method (see FIG. 16 (D)). In the present embodiment, a nickel phosphorus (NiP) alloy film is formed as the conductive shield 140 by an electroless plating method.

0130Further, as shown in FIG. 17 (D), the first insulator 112 and the second insulator 102 using the prepreg are bonded to the semiconductor integrated circuit 100 or the antenna 101, and the first insulator 112 and the second insulator 112 are attached. A fourth insulator 113 and a third insulator 103 are provided on the outside of the insulator 102 (semiconductor integrated circuit 100, opposite to the antenna 101), and the fourth insulator 113, the surface of the third insulator 103, and the surface of the third insulator 103 are provided. The side surface may be covered with a conductive shield 140.

0131In the manufacturing process of the structure of FIG. 17 (D), the antenna 101 and the semiconductor integrated circuit 100 are formed on the substrate 110 having an insulating surface, which is the manufacturing substrate, via the release layer 111 (see FIG. 17 (A)). ..

0132Next, the fourth insulator 113, the first insulator 112, the antenna 101, and the semiconductor integrated circuit 100 are heated and crimped, and the antenna 101 and the semiconductor integrated circuit 100 are peeled from the substrate 110 using the peeling layer 111. (See Figure 17 (B).).

0133The third insulator 103 and the second insulator 102 are heated and crimped to the semiconductor integrated circuit 100 to bond the third insulator 103 and the second insulator 102 to the semiconductor integrated circuit 100 (FIG. 17). See (C).).

0134A conductive shield that covers a laminate in which a fourth insulator 113, a first insulator 112, an antenna 101, a semiconductor integrated circuit 100, a second insulator 102, and a third insulator 103 are laminated. 140 is formed by a wet plating method (see Fig. 17 (D)).

0135The third insulator 103 and the fourth insulator 113 have the effect of increasing the strength of the semiconductor device against external stress, and in particular, like the third insulator 103, the semiconductor integrated circuit 100 and the second insulator 102. If it is provided between the above and the semiconductor integrated circuit 100, the semiconductor integrated circuit 100 will not be damaged or have poor characteristics because the third insulator 103 diffuses the force even if the pressure treatment is performed in the manufacturing process. Therefore, the semiconductor device can be manufactured with a good yield.

0136The conductive shield 140 transmits electromagnetic waves to be transmitted and received by the antenna 101 included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit 100 inside the semiconductor device. The conductive shield 140 is a semiconductor integrated circuit in order to diffuse and release the static electricity applied by the electrostatic discharge or to prevent the local existence (localization) of the electric charge (to prevent the occurrence of a local potential difference). It can prevent 100 electrostatic destruction.

0137Further, by providing the semiconductor device with a first insulator 112 and a second insulator 102 against a force applied from the outside, and a fourth insulator 113 and a third insulator 103 for diffusing the force, the semiconductor device is locally provided. Since the force applied to the target can be reduced, it is possible to prevent the semiconductor device from being damaged or having poor characteristics.

0138Further, in the structure of FIG. 15A of the present embodiment, the insulators are the first insulator 112 and the second insulator, which are structures in which a fiber body mainly functioning as an impact resistant layer is impregnated with an organic resin. It is composed of four layers of insulator 102, a third insulator 103 and a fourth insulator 113, which mainly function as a shock diffusion layer and have a low elastic modulus and high breaking strength, but at least an antenna 101 and a semiconductor. It suffices if there is a two-layer insulator that sandwiches the integrated circuit 100. Therefore, it may be configured to use 3 layers or 2 layers out of the above 4 layers. At least the semiconductor integrated circuit 100 and the antenna 101 may be covered with a conductive shield 140 that is electrically connected to each other via an insulator, and then the insulator may be further laminated on the conductive shield 140. If the surface of the conductive shield is not exposed, it has the effect of preventing deterioration of the conductive shield such as oxidation, wear, and cracks.

0139The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0140(Embodiment 3) In the present embodiment, a semiconductor device for the purpose of imparting high reliability using the present invention, and another example of a method for manufacturing the semiconductor device will be described with reference to FIGS. 22 to 24. In the configuration of the present embodiment described below, the same reference numerals are commonly used between different drawings for the same parts as those of the first and second embodiments or the parts having the same functions, and the description thereof is repeated. Is omitted.

0141In this embodiment, an example of a method for manufacturing a semiconductor device having an electrode layer penetrating the inside of the semiconductor device as shown in FIGS. 22 (B) and 22 (C) in the first embodiment is shown in FIGS. 23 (A1) and 23 (A2). (B1) (B2) and FIGS. 24 (A1) and (A2) are shown. In FIGS. 23 and 24, FIGS. 23 (A2) (B2), FIG. 24 (A2) are plan views, and FIGS. 23 (A1) (B1) and 24 (A1) correspond to the corresponding FIGS. 23 (A2) (B2). ) It is a cross-sectional view in line EF of FIG. 24 (A2).

0142FIG. 23 shows the semiconductor device of this embodiment during the manufacturing process. The first insulator 112 and the second insulator 102 have a plurality of semiconductor integrated circuits 100 and an antenna 101, and constitute a laminate 144. The laminate 144 includes a plurality of semiconductor integrated circuits before being divided into individual chips, and a through hole 189 is provided outside the semiconductor integrated circuits in the chip region (see FIGS. 23 (A1) and 23 (A2)). ). The shape and number of through holes are not limited and can be appropriately selected according to the size and shape of the chip. For example, a plurality of circular through holes (cylindrical as through holes) may be provided in the plan view.

0143The through hole 189 penetrates the laminate 144 and reaches from the first insulator 112 to the second insulator 102. The through hole 189 may be processed by a physical treatment such as a needle or a cone, or may be processed by a chemical treatment such as etching. In this embodiment, processing is performed using laser light.

0144Next, the laminated body 144 having the through hole 189 is plated. A laminate 144 having through holes 189 is immersed in a plating solution containing a metal material to form conductive shields 140a and 140b on the surface of the laminate 144 (see FIGS. 23 (B1) and (B2)). Since the liquid plating solution adheres to the exposed surface of the laminated body 144, it is formed on the surfaces of the first insulator 112 side and the second insulator 102 side in addition to the conductive shields 140a and 140b, as well as in the through holes 189. Electrode layers 141a and 141b that function as through electrodes are formed. The conductive shields 140a and 140b are electrically connected by the electrode layers 141a and 141b. The electrode layers 141a and 141b may be formed so as to fill the through hole 189, or may be formed so as to cover the side surface of the through hole 189.

0145In the present embodiment, since the conductive shields 140a and 140b and the electrode layers 141a and 141b are formed by the same plating step, the conductive shields 140a and 140b and the electrode layers 141a and 141b form a continuous film. The steps of manufacturing the conductive shields 140a and 140b and the electrode layers 141a and 141b may be performed in separate steps, or different materials may be used.

0146The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost.

0147The laminate 144 forming the conductive shields 140a and 140b and the electrode layers 141a and 141b is divided into individual semiconductor integrated circuit chips 145a, 145b, 145c, 145d, 145e and 145f (see FIGS. 24 (A1) and 145f). .). The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam. The semiconductor integrated circuit chips 145a, 145b, and 145c each have a laminate 143 in which the laminate 144 is divided. The semiconductor integrated circuit chip 145b corresponds to FIG. 22 (C). It should be noted that the structure may be such that the semiconductor integrated circuit chips 145a and 145c have electrode layers 141a and 141b that function as through electrodes, and the side surfaces other than the cut surface are covered with a conductive shield. In the above steps, it is possible to manufacture a semiconductor device having a conductive shield electrically connected so as to cover the periphery of the semiconductor integrated circuit.

0148The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0149(Embodiment 4) In this embodiment, an example of a plating method used for forming a conductive shield in the manufacturing process of the semiconductor device of the present invention is shown. In the configuration of the present embodiment described below, the same reference numerals are commonly used between different drawings for the same parts as those of the first embodiment or the parts having the same functions, and the repeated description thereof will be omitted.

0150In this embodiment, an example of forming the conductive shield by the electroless plating method will be described with reference to FIGS. 26 (A) to 26 (D).

0151Similar to the first embodiment, the first insulator 112 and the second insulator 102 form a laminate 143 in which the semiconductor integrated circuit 100 and the antenna 101 are sandwiched (see FIG. 26 (A)).

0152The electroless plating method is a wet plating method in which electrons are given to metal ions in an aqueous solution (sometimes an organic solvent) which is a plating solution to reduce the metal ions and precipitate them as a metal thin film. This is a method of precipitating a metal by the reducing action of.

0153Therefore, it is necessary that the object to be plated is catalyzed so that a precipitation reaction occurs. It is not always necessary when the object to be plated itself serves as a catalyst, but the catalyst substance is adsorbed on the surface of the object to be plated.

0154The catalytic substance 170 is adsorbed on the region of the laminated body 143 where the conductive shield 140 is formed by the plating method (see FIG. 26 (B)).

0155The catalyst substance is appropriately selected depending on the metal material to be plated. As the catalyst substance, palladium (Pd), rhodium (Rh), ruthenium (Ru), osmium (Os), iridium (Ir), gold (Au), platinum (Pt), silver (Ag) and the like may be used. The catalytic substance is dissolved in a solution and treated as a solution containing the catalytic substance. In this embodiment, palladium is used as the catalyst substance 170.

0156The laminate 143 on which the catalyst substance 170 is adsorbed is immersed in a plating solution 171 containing a metal material to be plated, and a film containing the metal is grown on the catalyst substance 170 (see FIG. 26 (C)). The immersion time, the temperature and concentration of the plating solution are controlled so as to reach the desired film thickness, and the conductive shield 140 is formed (see FIG. 26 (D)).

0157The plating solution contains a metal salt (a salt containing a metal material to be precipitated, typically a chloride or a sulfate) and a reducing agent (which gives electrons to precipitate metal ions as a metal) as main components. In addition, as auxiliary components, a pH adjuster, a buffer, a complexing agent, an accelerator, a stabilizer, an improving agent and the like may be added. Even with only the main component, metal ions are precipitated as metal as long as the conditions such as pH and bath temperature are adjusted. With respect to the main component, the function of the auxiliary component has the role of prolonging the life of the plating bath (plating solution) and improving the efficiency of the reducing agent, and depending on this selection method, it is highly economical. Electroplating can be performed. The pH regulator affects the plating rate, reduction efficiency and the condition of the plating film. In the electroless plating method, the buffer agent suppresses pH fluctuations caused by metal precipitation caused by the reduction of metal ions (various organic acids and inorganic weak acids). The complexing agent contributes to prevention of hydroxide precipitation in alkaline solution, adjustment of free metal ion concentration, adjustment of plating rate, prevention of decomposition of plating solution, etc. (typically, ammonia, ethylenediamine, pyrophosphate). Salts, citric acid, acetic acid, various organic acid salts, etc. are used.) The accelerator is added in a small amount to accelerate the plating rate and at the same time suppress the generation of hydrogen gas to improve the metal precipitation efficiency (sulfide and fluoride are typically used). The stabilizer has a role of suppressing the reduction reaction from occurring on the surface other than the surface of the object to be plated. It suppresses the natural decomposition of the plating bath and prevents the sediment generated by the aging of the plating bath from reacting with the reducing agent to generate hydrogen gas violently (typically, lead chloride and sulfurization). Things, sulphides, etc. are used.) The improver improves the condition of the plating film and improves the gloss (typically, a surfactant is used).

0158The material of the conductive shield 140 that can be formed by the electroless plating method is, for example, an element selected from nickel, copper, tin, silver, gold, platinum, palladium, iron, cobalt, and tungsten, or the element as a main component. It may be formed of an alloy material to be used.

0159Examples of alloy materials include nickel alloys (nickel phosphorus (NiP) alloys, nickel cobalt (NiCo) alloys, nickel cobalt phosphorus (NiCoP) alloys, nickel iron phosphorus (NiFeP) alloys, nickel tungsten phosphorus (NiWP) alloys, etc.). Be done.

0160In the present embodiment, a nickel-phosphorus alloy film is formed as the conductive shield 140 by an electroless plating method. Nickel is a magnetic substance, but if the phosphorus content is controlled to 11% or more as a nickel-phosphorus alloy film, its magnetism can be reduced (disappeared). Therefore, it can be applied as the conductive shield 140 without reducing the communication distance of the semiconductor device.

0161The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost.

0162The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0163It should be noted that this embodiment can be carried out in combination with the above-described first to fourth embodiments as appropriate.

0164(Embodiment 5) In this embodiment, an example of a plating method used for forming a conductive shield in the manufacturing process of the semiconductor device of the present invention is shown. In the configuration of the present embodiment described below, the same reference numerals are commonly used between different drawings for the same parts as those of the first embodiment or the parts having the same functions, and the repeated description thereof will be omitted.

0165In this embodiment, an example of forming the conductive shield by the electrolytic plating method will be described with reference to FIGS. 25 (A) to 25 (D).

0166Similar to the first embodiment, the first insulator 112 and the second insulator 102 form a laminate 143 in which the semiconductor integrated circuit 100 and the antenna 101 are sandwiched (see FIG. 25 (A)).

0167The electrolytic plating method is a wet plating method in which electrons are given to metal ions in an aqueous solution (sometimes an organic solvent) which is a plating solution to reduce the metal ions and precipitate them as a metal thin film. This is a method of reducing metal ions and precipitating metal.

0168When the electrolytic plating method is used, a conductive film (also called a seed layer) that allows electricity to flow through the region (object to be plated) where the plating film is formed is required. Therefore, in order to form a conductive shield on the insulator, A conductive film is formed on the insulator.

0169In the laminated body 143, the conductive film 180 is formed in the region where the conductive shield 140 is formed by the plating method (see FIG. 25 (B)).

0170The conductive film 180 is appropriately selected depending on the metal material to be plated. It is preferable that the conductive film 180 has conductivity and has high adhesion to the plating film to be plated.

0171As the conductive film 180, a film of silver, copper, nickel material, or an alloy material thereof can be used. In the present embodiment, a copper film (thickness 100 nm) is formed as the conductive film 180 by a sputtering method.

0172After performing pretreatment such as cleaning, the laminate 143 on which the conductive film 180 is formed is immersed in a plating solution 181 containing a metal material to be plated, an electric current is passed through the conductive film 180, and the metal is contained on the conductive film 180. Grow the membrane (see Figure 25 (C)). The immersion time is controlled to reach the desired film thickness to form the conductive shield 140 (see FIG. 25 (D)).

0173In the plating solution, a metal salt (salt containing a metal material to be precipitated, typically chloride or sulfate) and a reducing agent (metal ions are precipitated as a metal) as in the electroless plating method shown in the fourth embodiment. (Gives electrons) is included as the main component. In addition, as auxiliary components, a pH adjuster, a buffer, a complexing agent, an accelerator, a stabilizer, an improving agent and the like may be added. With respect to the main component, the function of the auxiliary component has the role of prolonging the life of the plating bath (plating solution) and improving the efficiency of the reducing agent, and depending on this selection method, it is highly economical. Electroplating can be performed.

0174The material of the conductive shield 140 that can be formed by the electrolytic plating method is, for example, an element selected from nickel, copper, tin, silver, gold, platinum, zinc, cadmium, chromium, iron, cobalt, tungsten, or the above-mentioned element. It may be formed of an alloy material as a main component.

0175Examples of the alloy material include zinc alloys (zinc-iron alloys, zinc-nickel alloys, tin-zinc alloys), tin alloys (tin-silver alloys, tin-cobalt alloys), and copper-zinc alloys (brass).

0176In the present embodiment, a copper thin film is formed as the conductive shield 140 by an electrolytic plating method. When a conductive shield is formed on the insulator by the electrolytic plating method, it has a laminated structure with the conductive film 180. When the conductive shield is formed by the electrolytic plating method, the conductive film which is the seed layer also functions as the conductive shield, so it can be said that the conductive shield is formed by laminating the conductive film 180 and the conductive shield 140. ..

0177The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost.

0178The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0179It should be noted that this embodiment can be carried out in combination with the above-described first to fourth embodiments as appropriate.

0180(Embodiment 6) In the present embodiment, a more reliable semiconductor device and a method for manufacturing a semiconductor device having a high yield will be described in detail with reference to FIGS. 4 and 5. In this embodiment, CMOS (Complementary Metal Oxide Semiconductor) will be described as an example of a semiconductor device.

0181Transistors 210, 211, an insulating film 212, an insulating film 213, and an insulating layer 214 are provided on a substrate 200 having an insulating surface, which is a fabrication substrate, via a release layer 201 and an insulating film 202 that functions as a base film, and semiconductor integration is performed. Circuit 250 is formed (see Figure 4 (A)).

0182The transistor 210 is a thin film transistor, and is an impurity region 223a, 223b, a channel forming region 226, a gate insulating layer 227, and a gate electrode layer, which are lower concentration impurity regions than the source region or drain region 224a, 224b, source region or drain region 224a, 224b. 228, including sidewall structure insulating layers 229a, 229b. The source region or drain region 224a, 224b is in contact with and electrically connected to the wiring layers 230a, 230b that function as the source electrode layer or drain electrode layer. In the present embodiment, the transistor 210 is a p-channel thin film transistor, and an impurity element that imparts p-type to the source region or drain regions 224a and 224b and the impurity regions 223a and 223b which are LDD (Lightly Doped Drain) regions (for example, boron (for example)). B), aluminum (Al), gallium (Ga), etc.) are included.

0183The transistor 211 is a thin film transistor, and is an impurity region 203a, 203b, a channel forming region 206, a gate insulating layer 207, and a gate electrode layer, which are lower concentration impurity regions than the source region or drain region 204a, 204b, source region or drain region 204a, 204b. 208, including sidewall structure insulating layers 209a, 209b. The source region or drain region 204a, 204b is in contact with and electrically connected to the wiring layers 210a, 210b that function as the source electrode layer or drain electrode layer. In the present embodiment, the transistor 211 is an n-channel thin film transistor, and is an impurity element (for example, phosphorus (P) or arsenic) that imparts n-type to the source region or drain regions 204a and 204b and the impurity regions 203a and 203b which are LDD regions. (As) etc.) are included.

0184Next, a conductive layer 263 that functions as an antenna is formed on the insulating layer 214, and an inorganic insulating layer 254 is formed as a protective layer on the conductive layer 263. In this embodiment, a silicon nitride film is formed as the inorganic insulating layer 254. The conductive layer 263 is electrically connected to the semiconductor integrated circuit 250.

0185As the first insulator 262, a structure in which the fiber body 280 is impregnated with the organic resin 281 is used. The inorganic insulating layer 254, the conductive layer 263, and the semiconductor integrated circuit 250 are bonded to the first insulator 262, and the inorganic insulating layer 254, the conductive layer 263, and the semiconductor integrated circuit 250 are peeled from the substrate 200 using the release layer 201. Therefore, the semiconductor integrated circuit 250 is provided on the side of the first insulator 262 (see FIGS. 4B and 4C).

0186Similar to the first insulator 262, the second insulator 252 also uses a structure in which the fiber body 270 is impregnated with the organic resin 271.

0187The structure is heated and crimped to the exposed peeled surface of the semiconductor integrated circuit 250 to bond the second insulator 252, and the inorganic insulating layer 254, the conductive layer 263 and the semiconductor integrated circuit 250 are attached to the first insulator 262. And sandwich it between the second insulator 252 (see Fig. 5 (A)).

0188Although not shown, the first insulator 262 and the second insulator 252 sandwich a plurality of semiconductor integrated circuits, and are divided into individual semiconductor integrated circuits 250 to manufacture a semiconductor integrated circuit chip. The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam.

0189By dividing, the conductive layer 263 and the semiconductor integrated circuit 250 are sealed by the first insulator 262 and the second insulator 252, and the chip has a divided cross section (side surface caused by the division).

0190The conductive shield 260 is formed by a wet plating method so as to cover the laminated body in which the first insulator 262, the conductive layer 263, the semiconductor integrated circuit 250, and the second insulator 252 are laminated (FIG. 5 (B). )reference.).

0191The conductive shield 260 may be formed on all side surfaces and may be provided so as to surround (wrap) the periphery of the semiconductor device, or may be formed so as to cover a part of the side surface (divisional cross section). In the present invention, the conductive shield 260 formed on the outside of the first insulator 262 and the second insulator 252 is electrically connected. In the present embodiment, the conductive shield 260 is formed by the same plating step over the outside of the first insulator 262 and the second insulator 252, and is a continuous film.

0192The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost. Therefore, when the plating method is used for forming the conductive shield, the semiconductor device of the present invention can be manufactured at low cost and with high productivity. The cost reduction of the process makes it possible to provide a semiconductor device at a lower price.

0193Therefore, the conductive layer 263 and the semiconductor integrated circuit 250 are sealed by the first insulator 262 and the second insulator 252, and the first insulator 262 and the second insulator corresponding to the front surface and the back surface of the semiconductor device are insulated. The structure is protected against electrostatic discharge by a conductive shield 260 provided on the outside of the body 252 and on the cut surface.

0194The conductive shield 260 transmits electromagnetic waves to be transmitted and received by the conductive layer 263, which is an antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit 250 inside the semiconductor device. The conductive shield 260 is a semiconductor integrated circuit in order to diffuse and release the static electricity applied by the electrostatic discharge, or to prevent the local existence (localization) of the electric charge (to prevent the occurrence of a local potential difference). It can prevent 250 electrostatic destruction.

0195Further, since the insulator and the conductive shield are provided by sandwiching the semiconductor integrated circuit, it is possible to prevent adverse effects such as damage to the semiconductor integrated circuit and poor characteristics due to external stress and electrostatic discharge even in the manufacturing process. Therefore, the semiconductor device can be manufactured with a good yield.

0196The semiconductor device produced in the present embodiment can be made into a flexible semiconductor device by using a flexible insulator.

0197The material forming the semiconductor layer of the transistors 210 and 211 is amorphous (amorphous, also referred to as "AS") produced by a vapor phase growth method or a sputtering method using a semiconductor material gas typified by silane or Germanan. A semiconductor, a polycrystalline semiconductor obtained by crystallizing the amorphous semiconductor using light energy or thermal energy, or a microcrystal (also referred to as semi-amorphous or microcrystal; hereinafter also referred to as SAS) semiconductor is used. be able to. The semiconductor layer can be formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like.

0198The microcrystalline semiconductor film belongs to a metastable state intermediate between amorphous and single crystal in consideration of Gibbs free energy. That is, it is a semiconductor having a third state that is stable in free energy, has short-range order, and has lattice distortion. Columnar or acicular crystals grow in the normal direction with respect to the substrate surface. Microcrystalline silicon, which is a typical example of microcrystalline semiconductor, has a Raman spectrum of 520 cm, which indicates single crystal silicon.-1It is shifting to the lower wavenumber side. That is, 520 cm showing single crystal silicon-1And 480 cm showing amorphous silicon-1There is a peak in the Raman spectrum of microcrystalline silicon between. It also contains at least 1 atomic% or more of hydrogen or halogen to terminate unbonded hands (dangling bonds). Further, by adding rare gas elements such as helium, argon, krypton, and neon to further promote the lattice strain, the stability is increased and a good polycrystalline semiconductor film can be obtained.

0199This microcrystalline semiconductor film can be formed by a high-frequency plasma CVD method having a frequency of several tens of MHz to several hundreds of MHz, or a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4It can be formed by diluting silicon hydride such as hydrogen with hydrogen. Further, in addition to silicon hydride and hydrogen, it can be diluted with one or more rare gas elements selected from helium, argon, krypton, and neon to form a microcrystalline semiconductor film. At these times, the flow rate ratio of hydrogen to silicon hydride is 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and more preferably 100 times.

0200Typical examples of amorphous semiconductors include hydrogenated amorphous silicon, and typical examples of crystalline semiconductors include polysilicon. Polysilicon (polycrystalline silicon) includes so-called high-temperature polysilicon that uses polysilicon formed at a process temperature of 800 ° C or higher as the main material, and polysilicon that is formed at a process temperature of 600 ° C or lower. It contains so-called low-temperature polysilicon used as a main material, and polysilicon obtained by crystallizing amorphous silicon using an element that promotes crystallization. Of course, as described above, a microcrystalline semiconductor or a semiconductor containing a crystal phase in a part of the semiconductor layer can also be used.

0201Further, as the material of the semiconductor, not only a simple substance such as silicon (Si) and germanium (Ge) but also a compound semiconductor such as GaAs, InP, SiC, ZnSe, GaN and SiGe can be used. In addition, zinc oxide (ZnO) and tin oxide (SnO), which are oxide semiconductors,2), Magnesium oxide zinc, gallium oxide, indium oxide, and oxide semiconductors composed of a plurality of the above oxide semiconductors can be used. For example, an oxide semiconductor composed of zinc oxide, indium oxide, and gallium oxide can also be used. When zinc oxide is used for the semiconductor layer, the gate insulating layer is Y.2O3, Al2O3, TiO2, These layers may be used, and ITO, Au, Ti, etc. may be used as the gate electrode layer, the source electrode layer, and the drain electrode layer. In addition, In, Ga, etc. can be added to ZnO.

0202When a crystalline semiconductor layer is used as the semiconductor layer, the method for producing the crystalline semiconductor layer is various methods (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. Crystallinity method, etc.) may be used. It is also possible to improve the crystallinity by irradiating a microcrystalline semiconductor which is SAS with a laser to crystallize it. When no element that promotes crystallization is introduced, the hydrogen content of the amorphous silicon film is reduced by 1 by heating at 500 ° C for 1 hour in a nitrogen atmosphere before irradiating the amorphous silicon film with laser light. × 1020atoms / cm3Release to the following. This is because the amorphous silicon film is destroyed when the laser beam is applied to the amorphous silicon film containing a large amount of hydrogen.

0203Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element (also referred to as a catalyst element or a metal element) that promotes crystallization is added to the amorphous semiconductor layer, and heat treatment (also referred to as a catalyst element or a metal element) is performed. Crystallization may be carried out at 550 ° C to 750 ° C for 3 minutes to 24 hours). Elements that promote (promote) crystallization include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), and iridium (Ir). ), Platinum (Pt), copper (Cu) and gold (Au).

0204The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, a sputtering method, a CVD method, or the like. Plasma treatment methods (including plasma CVD methods), adsorption methods, and methods of applying a metal salt solution can be used. Of these, the method using a solution is convenient in that the concentration of the metal element can be easily adjusted. Further, at this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and spread the aqueous solution over the entire surface of the amorphous semiconductor layer, UV light irradiation in an oxygen atmosphere, thermal oxidation method, and hydroxyl radical are applied. It is desirable to form an oxide film by treatment with ozone water containing ozone or hydrogen peroxide.

0205In order to remove or reduce the elements that promote crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer to function as a gettering sink. As the impurity element, an impurity element that imparts n-type, an impurity element that imparts p-type, a rare gas element, and the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), and antimony (Sb) can be used. ), Bismus (Bi), Boron (B), Helium (He), Neon (Ne), Argon (Ar), Kr (Krypton), Xe (Xenon). A semiconductor layer containing a rare gas element is formed on a crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (3 minutes to 24 hours at 550 ° C to 750 ° C) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing the rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. Then, the semiconductor layer containing the rare gas element that has become the gettering sink is removed.

0206The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or the heat treatment or laser light irradiation may be performed independently or a plurality of times.

0207Further, the crystalline semiconductor layer may be formed directly on the substrate by the plasma method. Further, the crystalline semiconductor layer may be selectively formed on the substrate by using the plasma method.

0208The gate insulating layers 207 and 227 may be formed of silicon oxide or a laminated structure of silicon oxide and silicon nitride. The gate insulating layers 207 and 227 may be formed by depositing an insulating film by a plasma CVD method or a reduced pressure CVD method, or may be formed by solid phase oxidation or solid phase nitriding by plasma treatment. This is because the gate insulating layer formed by oxidizing or nitriding a single crystal semiconductor layer by plasma treatment is dense, has a high dielectric strength, and is excellent in reliability. For example, nitrous oxide (N2O) is diluted 1 to 3 times (flow rate ratio) with Ar, and microwave (2.45 GHz) power of 3 to 5 kW is applied at a pressure of 10 to 30 Pa to oxidize or nitride the surface of the semiconductor layer. By this treatment, an insulating film of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. In addition, nitrous oxide (N)2O) and silane (SiH)4) Is introduced, and a microwave (2.45 GHz) power of 3 to 5 kW is applied at a pressure of 10 to 30 Pa to form a silicon oxide nitride film by a vapor phase growth method to form a gate insulating layer. By combining the solid-phase reaction and the reaction by the vapor phase growth method, a gate insulating layer having a low interface state density and an excellent dielectric strength can be formed.

0209Further, as the gate insulating layers 207 and 227, high dielectric constant materials such as zirconium dioxide, hafnium oxide, titanium dioxide and tantalum pentoxide may be used. By using a high dielectric constant material for the gate insulating layers 207 and 227, the gate leakage current can be reduced.

0210The gate electrode layers 208 and 228 can be formed by using a CVD method, a sputtering method, a droplet ejection method, or the like. The gate electrode layer is an element selected from Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba. Alternatively, it may be formed of an alloy material or a compound material containing the element as a main component. Further, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used. Further, it may have a single-layer structure or a multi-layer structure. For example, it may have a two-layer structure of a tungsten nitride film and a molybdenum film, a tungsten film having a thickness of 50 nm, and an aluminum-silicon alloy (Al-) having a film thickness of 500 nm. A three-layer structure in which a Si) film and a titanium nitride film having a thickness of 30 nm are sequentially laminated may be used. Further, in the case of a three-layer structure, titanium nitride may be used instead of the titanium of the first conductive film, or aluminum may be used instead of the aluminum-silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al-Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.

0211A translucent material having translucency with respect to visible light can also be used for the gate electrode layers 208 and 228. As the translucent conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide and the like can be used. In addition, indium zinc oxide containing zinc oxide (ZnO) (IZO (Indium Zinc Oxide)), zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO).2), Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and the like may also be used.

0212When processing is required by etching to form the gate electrode layers 208 and 228, a mask may be formed and processed by dry etching or dry etching. Using the ICP (Induatively Coupled Plasma) etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted. By adjusting, the electrode layer can be etched into a tapered shape. The etching gas is Cl.2, BCl3, SiCl4Or CCl4Chlorine-based gas represented by, CF4,SCIENCE FICTION6Or NF3Fluorine-based gas represented by2Can be used as appropriate.

0213The insulating layers 209a, 209b, 229a, and 229b form an insulating layer that covers the gate electrode layer and the semiconductor layer, and then process this by anisotropic etching by the RIE (Reactive ion Etching) method. Insulating layers 209a, 209b, 229a, and 229b having a sidewall structure may be formed consistently. Here, the insulating layer is not particularly limited, and it is a silicon oxide having good step covering property formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECR CVD, and sputtering.

0214In the present embodiment, the single gate structure has been described, but a multi-gate structure such as a double gate structure may be used. In this case, a structure in which gate electrode layers are provided above and below the semiconductor layer may be used, or a structure in which a plurality of gate electrode layers are provided only on one side (upper or lower) of the semiconductor layer may be used.

0215Further, the structure may be such that VDD is provided in the source region and the drain region of the transistor. Silicide forms a conductive film on the source region and drain region of the semiconductor layer, and reacts the silicon in the semiconductor layer in the exposed source region and drain region with the conductive film by heat treatment, GRTA method, LRTA method, etc. To form. Silicide may be formed by laser irradiation or light irradiation by a lamp. Materials for the conductive film that forms palladium include titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), and tantalum (Ta). , Vanadium (V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd) and the like can be used.

0216The wiring layers 210a, 210b, 230a, and 230b that function as the source electrode layer or the drain electrode layer can be formed by forming a conductive film by a PVD method, a CVD method, a vapor deposition method, or the like, and then etching into a desired shape. it can. Further, the wiring layer can be selectively formed at a predetermined place by a printing method, an electrolytic plating method, or the like. Further, the reflow method and the damascene method may be used. The materials of the wiring layers 210a, 210b, 230a, 230b are Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, etc. It may be formed by using a metal, a semiconductor such as Si or Ge, an alloy thereof, or a nitride thereof. A translucent material can also be used.

0217If it is a translucent conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), and indium zinc oxide containing zinc oxide (ZnO) (IZO (indium zinc oxide)) )), Zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO)2), Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and the like can be used.

0218For the insulating films 212 and 213 and the insulating layer 214, silicon oxide, silicon nitride, silicon nitride nitride, aluminum oxide, aluminum nitride, aluminum nitride and other inorganic insulating materials can be used.

0219The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield.

0220The semiconductor device of the present invention can be applied not only to a field effect transistor but also to a storage device using a semiconductor layer as a semiconductor element, and manufactures and provides a semiconductor device satisfying a function required for various purposes. be able to.

0221In addition, this embodiment can be carried out in combination with the above-described first to fifth embodiments as appropriate.

0222(Embodiment 7) In the present embodiment, an example of a semiconductor device for the purpose of imparting higher reliability and a semiconductor device having a memory in a method of manufacturing the semiconductor device will be described with reference to FIGS. 6 to 8.

0223The semiconductor device of this embodiment has a memory cell array and a drive circuit unit for driving the memory cell array in the memory.

0224The release layer 301 is formed on the substrate 300, which is a manufacturing substrate having an insulating surface, and the insulating film 302 that functions as a base film is formed on the release layer 301.

0225Next, a semiconductor film is formed on the insulating film 302. The semiconductor film may be formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by various means (sputtering method, LPCVD method, plasma CVD method, etc.).

0226In the present embodiment, an amorphous semiconductor film is formed on the insulating film 302, and the amorphous semiconductor film is laser-crystallized to form a semiconductor film which is a crystalline semiconductor film.

0227The semiconductor film thus obtained is selectively doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor. Doping of this impurity element may be performed on the amorphous semiconductor film before the crystallization step. When an impurity element is doped in the state of an amorphous semiconductor film, the impurity can also be activated by a subsequent heat treatment for crystallization. In addition, defects and the like generated during doping can be improved.

0228Next, the semiconductor film is processed into a desired shape using a mask. In the present embodiment, after removing the oxide film formed on the semiconductor film, a new oxide film is formed. Then, a photomask is produced, and semiconductor layers 303, 304, 305, and 306 are formed by processing using a photolithography method. An inclination angle (taper angle) may be provided at the end of the semiconductor layer.

0229Either plasma etching (dry etching) or wet etching may be adopted for the etching process, but plasma etching is suitable for processing a large-area substrate. As an etching gas, CF4, NF3, Cl2, BCl3, Fluorine-based or chlorine-based gas may be used, and an inert gas such as He or Ar may be added as appropriate. Further, if the etching process of atmospheric pressure discharge is applied, local electric discharge machining is also possible, and it is not necessary to form a mask on the entire surface of the substrate.

0230An insulating film 310 is formed on the semiconductor layer 305. The insulating film 310 may be formed of silicon oxide or a laminated structure of silicon oxide and silicon nitride. The insulating film 310 may be formed by depositing an insulating layer by a plasma CVD method or a reduced pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitriding by plasma treatment. This is because the insulating layer formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has a high dielectric strength, and is excellent in reliability. Since the insulating film 310 is used as a tunnel insulating layer for injecting charges into the charge storage layer 311, it is preferable that the insulating film 310 is durable in this way. The insulating film 310 is preferably formed to have a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm.

0231An example of a suitable insulating film 310 formed by plasma treatment is that a silicon oxide layer having a thickness of 3 nm to 6 nm is formed on a semiconductor layer by plasma treatment in an oxidizing atmosphere, and then the silicon oxide layer is formed in a nitrogen atmosphere. A nitrogen plasma-treated layer whose surface is treated with nitrided plasma is formed. Specifically, first, a silicon oxide layer having a thickness of 3 nm to 6 nm is formed on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, by continuously performing plasma treatment in a nitrogen atmosphere, a nitrogen plasma treatment layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer. The vicinity of the surface means a depth of approximately 0.5 nm to 1.5 nm from the surface of the silicon oxide layer. For example, by performing plasma treatment in a nitrogen atmosphere, a structure in which nitrogen is contained at a depth of approximately 1 nm from the surface of the silicon oxide layer at a ratio of 20 to 50 atomic% is obtained.

0232By oxidizing the surface of the silicon layer, which is a typical example of the semiconductor layer, by plasma treatment, it is possible to form a dense oxide layer without distortion at the interface. Further, by nitriding the oxide layer by plasma treatment, oxygen in the surface layer portion is replaced with nitrogen to form a nitrided layer, which enables further densification. As a result, an insulating layer having a high dielectric strength can be formed.

0233In any case, by using the solid phase oxidation treatment or solid phase nitriding treatment by plasma treatment as described above, even if a glass substrate having a heat resistant temperature of 700 ° C or less is used, it is formed at 950 ° C to 1050 ° C. An insulating layer equivalent to that of the thermal oxide film to be obtained can be obtained. That is, a highly reliable tunnel insulating layer can be formed as the tunnel insulating layer of the non-volatile memory element.

0234The charge storage layer 311 is formed on the insulating film 310. The charge storage layer 311 may be a single layer or may be provided by stacking a plurality of layers.

0235The charge storage layer 311 can be formed of a layer or particles of a semiconductor material or a conductive material to form a floating gate. Examples of semiconductor materials include silicon and silicon germanium. When silicon is used, amorphous silicon or polysilicon can be used. Furthermore, phosphorus-doped polysilicon can be used. As the conductive material, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, and an alloy film combining the elements (typical). It may be formed of a MoW alloy film, a MoTa alloy film), or a silicon film imparted with conductivity. Under the conductive layer made of such a material, a nitride such as tantalum nitride, tungsten nitride, titanium nitride and molybdenum nitride, and silicide such as tungsten silicide, titanium silicide and molybdenum silicide may be formed. Further, the semiconductor materials may be used, the conductive materials may be used, or the semiconductor material and the conductive material may be laminated. For example, it may be a laminated structure of a silicon layer and a germanium layer.

0236Further, the charge storage layer 311 can be formed of a layer having an insulating and charge-holding trap. Typical examples of such materials are silicon compounds and germanium compounds. Examples of the silicon compound include silicon nitride, silicon oxynitride, and silicon oxynitride to which hydrogen has been added. Germanium compounds include germanium nitride, germanium nitride added with oxygen, germanium oxide added with nitrogen, germanium nitride added with oxygen and hydrogen, germanium compounds such as germanium oxide added with nitrogen and hydrogen, and the like. ..

0237Next, a mask covering the semiconductor layers 303, 304, and 306 is formed. An impurity element that imparts n-type is added using a mask and charge storage layer 311 as a mask to form an n-type impurity region 362a and an n-type impurity region 362b. In this embodiment, phosphorus (P), which is an impurity element that imparts n-type as an impurity element, is used. Here, 1 × 10 impurity elements that impart n-type to the n-type impurity region 362a and n-type impurity region 362b.17~5×1018/cm3Add so that it is contained in a moderate concentration. Remove the mask covering the semiconductor layers 303, 304, 306.

0238The oxide film on the semiconductor layer 306 is removed to form a gate insulating layer 309 covering the semiconductor layer 305, the semiconductor layer 306, the insulating film 310, and the charge storage layer 311. When the thickness of the gate insulating layer 309 is thick in the memory cell array, the resistance to high voltage of the thin film transistor and the memory element can be increased, and the reliability can be improved.

0239The gate insulating layer 309 formed above the semiconductor layer 305 functions as a control insulating layer in the memory element to be completed later, but functions as a gate insulating layer in the thin film transistor formed on the semiconductor layer 306. In this specification, it is referred to as a gate insulating layer 309.

0240The oxide film on the semiconductor layers 303 and 304 is removed to form a gate insulating layer 308 covering the semiconductor layer 303 and the semiconductor layer 304 (see FIG. 6 (A)). The gate insulating layer 308 can be formed by using a plasma CVD method, a sputtering method, or the like. The film thickness of the gate insulating layer 308 of the thin film transistor provided in the drive circuit unit may be 1 nm or more and 10 nm or less, more preferably about 5 nm. Thinning the gate insulating layer 308 has the effect of operating the transistor at low voltage and high speed in the drive circuit section.

0241The gate insulating layer 308 may be formed of silicon oxide or a laminated structure of silicon oxide and silicon nitride. The gate insulating layer 308 may be formed by depositing an insulating film by a plasma CVD method or a reduced pressure CVD method, or may be formed by solid phase oxidation or solid phase nitriding by plasma treatment. This is because the gate insulating layer formed by oxidizing or nitriding the semiconductor layer by plasma treatment is dense, has a high dielectric strength, and is excellent in reliability.

0242Further, a high dielectric constant material may be used as the gate insulating layer 308. By using a high dielectric constant material for the gate insulating layer 308, the gate leakage current can be reduced. As the high dielectric constant material, zirconium dioxide, hafnium oxide, titanium dioxide, tantalum pentoxide and the like can be used. Further, a silicon oxide layer may be formed by solid phase oxidation by plasma treatment.

0243Further, as a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region using the GRTA method, the LRTA method, or the like to form a thermal oxide film. .. In order to form a dense insulating film with a small gate leak current at a low film formation temperature, it is preferable to include a rare gas element such as argon in the reaction gas and mix it in the formed insulating film.

0244Next, the first conductive film having a film thickness of 20 to 100 nm used as the gate electrode layer and the second conductive film having a film thickness of 100 to 400 nm are laminated and formed on the gate insulating layers 308 and 309. The first conductive film and the second conductive film can be formed by a method such as a sputtering method, a vapor deposition method, or a CVD method. The first conductive film and the second conductive film are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd). ), Or an alloy material or a compound material containing the element as a main component. Further, as the first conductive film and the second conductive film, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used. Further, the structure is not limited to the two-layer structure, and for example, a tungsten film having a film thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film having a film thickness of 500 nm is used as the second conductive film, and a third conductive film. As the conductive film, a three-layer structure in which titanium nitride films having a thickness of 30 nm are sequentially laminated may be used. Further, in the case of a three-layer structure, titanium nitride may be used instead of the titanium of the first conductive film, or aluminum may be used instead of the aluminum-silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al-Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Further, it may have a single-layer structure. In the present embodiment, tantalum nitride is formed with a film thickness of 30 nm as the first conductive film, and tungsten (W) is formed with a film thickness of 370 nm as the second conductive film.

0245The first conductive film and the second conductive film are etched to form the first gate electrode layer 312, 313, 314, the second gate electrode layer 316, 317, 318, the first control gate electrode layer 315, And a second control gate electrode layer 319 is formed (see FIG. 6 (B)).

0246In the present embodiment, an example in which the first gate electrode layer and the second gate electrode layer (first control gate electrode layer, second control gate electrode layer) are formed with vertical side surfaces is shown. The present invention is not limited thereto, and both the first gate electrode layer and the second gate electrode layer (first control gate electrode layer, second control gate electrode layer) may have a tapered shape. , Only one of the gate electrode layers (first control gate electrode layer, second control gate electrode layer) has a tapered shape, and the other has vertical sides due to anisotropic etching. May be good. The taper angle may be different or the same between the laminated gate electrode layers. By having the tapered shape, the coating property of the film laminated on the taper shape is improved, and defects are reduced, so that the reliability is improved.

0247The gate insulating layers 308 and 309 are slightly etched by the etching process when forming the gate electrode layer (and the control gate electrode layer), and the film thickness may be reduced (so-called film reduction).

0248Next, masks 321, 363 that cover the semiconductor layers 304, 305, and 306 are formed. Using the masks 321, 363, the first gate electrode layer 312, and the second gate electrode layer 316 as masks, an impurity element 320 that imparts p-type is added to form a p-type impurity region 322a and a p-type impurity region 322b. In this embodiment, boron (B) is used as an impurity element. Here, 1 × 10 impurity elements that impart p-type to the p-type impurity region 322a and p-type impurity region 322b.20~5×1021/cm3Add so that it is contained in a moderate concentration. In addition, a channel formation region 323 is formed in the semiconductor layer 303 (see FIG. 6 (C)).

0249The p-type impurity region 322a and the p-type impurity region 322b are high-concentration p-type impurity regions and function as source regions and drain regions.

0250Next, a mask 325 that covers the semiconductor layer 303 is formed. Mask 325, 1st gate electrode layer 313, 2nd gate electrode layer 317, 1st gate electrode layer 314, 2nd gate electrode layer 318, 1st control gate electrode layer 315, and 2nd control gate An impurity element 324 that imparts n-type is added using the electrode layer 319 as a mask to form n-type impurity regions 326a, 326b, 327a, 327b, 328a, and 328b. In this embodiment, phosphorus (P) is used as an impurity element. Here, 5 × 10 impurity elements that impart n-type to the n-type impurity regions 326a, 326b, 327a, 327b, 328a, and 328b.19~5×1020/cm3Add so that it is contained in a moderate concentration. Further, a channel forming region 329 and an n-type impurity region 364a and 364b are formed in the semiconductor layer 304, a channel forming region 330 is formed in the semiconductor layer 305, and a channel forming region 331 is formed in the semiconductor layer 306 (see FIG. 6 (D)). ).

0251The n-type impurity regions 326a, 326b, 327a, 327b, 328a, and 328b are high-concentration n-type impurity regions, which function as source regions and drain regions. On the other hand, the n-type impurity region 364a and the n-type impurity region 364b are low-concentration impurity regions and are LDD regions.

0252Mask 325 O2Remove with ashing or resist stripping solution, and also remove oxide film. After that, an insulating film, a so-called sidewall, may be formed so as to cover the side surface of the gate electrode layer. The sidewall can be formed by an insulating film having silicon by using a plasma CVD method or a reduced pressure CVD (LPCVD) method.

0253Heat treatment, irradiation with strong light, or irradiation with laser light may be performed to activate the impurity element. At the same time as activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

0254Next, an interlayer insulating layer covering the gate electrode layer and the gate insulating layer is formed. In the present embodiment, the insulating film 367 and the insulating film 368 are laminated. The insulating film 367 and the insulating film 368 may be a silicon nitride film, a silicon nitride film, a silicon nitride film, or a silicon oxide film using a sputtering method or plasma CVD, and an insulating film containing another silicon may be a single layer or 3 It may be used as a laminated structure of layers or more.

0255Further, a heat treatment is performed at 300 to 550 ° C for 1 to 12 hours in a nitrogen atmosphere to hydrogenate the semiconductor layer. Preferably, it is carried out at 400 to 500 ° C. This step is a step of terminating the dangling bond of the semiconductor layer with hydrogen contained in the insulating film 367 which is the interlayer insulating layer. In this embodiment, the heat treatment is performed at 410 degrees (° C) for 1 hour.

0256Other insulating films 367 and 368 include aluminum nitride (AlN), aluminum oxide (AlON), aluminum nitride (AlNO) or aluminum oxide, which has a higher nitrogen content than the oxygen content, and diamond dryk carbon (DLC). , Nitrogen-containing carbon film (CN) and other materials selected from materials including inorganic insulating materials. Moreover, you may use a siloxane resin. The siloxane resin corresponds to a resin containing a Si-O-Si bond.

0257Next, a contact hole (opening) reaching the semiconductor layer is formed in the insulating film 367, the insulating film 368, and the gate insulating layers 308 and 309 using a mask made of a resist. Etching may be performed once or multiple times depending on the selection ratio of the material to be used. By etching, the insulating film 368, the insulating film 367, and the gate insulating layers 308 and 309 are removed, and the p-type impurity regions 322a and 322b and the n-type impurity regions 326a, 326b, 327a, 327b and 328a, which are source or drain regions, Form an opening reaching 328b. The etching may be wet etching or dry etching, or both may be used. As the wet etching etchant, it is preferable to use a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride. As an etching gas, Cl2, BCl3, SiCl4Or CCl4Chlorine-based gas represented by, CF4,SCIENCE FICTION6Or NF3Fluorine-based gas represented by2Can be used as appropriate. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more kinds of elements selected from He, Ne, Ar, Kr and Xe can be used.

0258A wiring layer 369a and a wiring layer 369b, which are source electrode layers or drain electrode layers, are formed by forming a conductive film so as to cover the opening and then electrically connecting the conductive film to a part of each source region or drain region, respectively. , Wiring layer 370a, Wiring layer 370b, Wiring layer 371a, Wiring layer 371b, Wiring layer 372a, Wiring layer 372b are formed. The wiring layer can be formed by forming a conductive film by a PVD method, a CVD method, a vapor deposition method, or the like, and then etching it into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet ejection method, a printing method, an electrolytic plating method or the like. Further, the reflow method and the damascene method may be used. The material of the source electrode layer or drain electrode layer is a metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, etc. And Si, Ge, or an alloy thereof, or a nitride thereof. Further, these laminated structures may be used. In the present embodiment, titanium (Ti) is formed with a film thickness of 60 nm, a titanium nitride film is formed with a film thickness of 40 nm, aluminum is formed with a film thickness of 700 nm, and titanium (Ti) is formed with a film thickness of 200 nm to form a laminated structure. Process into the desired shape.

0259In the above steps, the drive circuit unit includes a thin film transistor 373 which is a p-channel type thin film transistor having a p-type impurity region, a thin film transistor 374 which is an n-channel type thin film transistor having an n-channel impurity region, and a memory having an n-type impurity region as a memory cell array. A semiconductor integrated circuit 350 having the element 375 and the thin film transistor 376, which is an n-channel thin film transistor having an n-type impurity region, can be manufactured (see FIG. 6 (E)).

0260In this embodiment, the insulating layer 390 is formed on the semiconductor integrated circuit 350 (see FIG. 7 (A)). Next, a conductive layer 380 that functions as an antenna is formed on the insulating layer 390, and an inorganic insulating layer 381 is formed on the conductive layer 380 as a protective layer (see FIG. 7 (B)).

0261As the first insulator 382, a structure in which the fiber body 386 is impregnated with the organic resin 387 is used. The structure is heated and crimped to bond the semiconductor integrated circuit 350, the first insulator 382, and the fourth insulator 391, and the semiconductor integrated circuit 350 is peeled from the substrate 300 by using the peeling layer 301. Therefore, the semiconductor integrated circuit 350 is provided on the side of the first insulator 382 (see FIG. 7 (C)).

0262Similar to the first insulator 382, the second insulator 385 also uses a structure in which the fiber body 386 is impregnated with the organic resin 387. The structure is heated and crimped to bond the third insulator 388 and the second insulator 385. An adhesive layer 389 is provided on the opposite surface of the second insulator 385 of the third insulator 388 that is bonded to the semiconductor integrated circuit 350.

0263An adhesive layer 389 is adhered to the exposed peeling surface of the semiconductor integrated circuit 350, and the semiconductor integrated circuit 350 is attached to the fourth insulator 391 and the first insulator 382, and the third insulator 388 and the second insulator. It is sandwiched between insulators 385 (see Fig. 8 (A)).

0264Although not shown, the first insulator 382 and the second insulator 385 sandwich a plurality of semiconductor integrated circuits, and divide each of the individual semiconductor integrated circuits 350 to manufacture a semiconductor integrated circuit chip. The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam. By dividing, the conductive layer 380 and the semiconductor integrated circuit 350 are sealed by the first insulator 382 and the second insulator 385, and the chip has a divided cross section (side surface caused by the division).

0265A conductive shield 395 is formed by a wet plating method so as to cover the laminated body in which the first insulator 382, the conductive layer 380, the semiconductor integrated circuit 350, and the second insulator 385 are laminated (FIG. 8 (B). )reference.).

0266The conductive shield 395 may be formed on all side surfaces and may be provided so as to surround (wrap) the periphery of the semiconductor device, or may be formed so as to cover a part of the side surface (divisional cross section). In the present invention, the conductive shield 395 formed on the outside of the first insulator 382 and the second insulator 385 is electrically connected. In the present embodiment, the conductive shield 395 is formed by the same plating step over the outside of the first insulator 382 and the second insulator 385, and is a continuous film.

0267The plating method has a wide area that can be processed at one time, improves productivity, reduces the cost required for the process, and can reduce the cost. Therefore, when the plating method is used for forming the conductive shield, the semiconductor device of the present invention can be manufactured at low cost and with high productivity. The cost reduction of the process makes it possible to provide a semiconductor device at a lower price.

0268Therefore, the conductive layer 380 and the semiconductor integrated circuit 350 are sealed by the first insulator 382 and the second insulator 385, and the first insulator 382 and the second insulator corresponding to the front surface and the back surface of the semiconductor device are insulated. The structure is protected against electrostatic discharge by the conductive shield 395 provided on the outside and the side surface of the body 385.

0269The semiconductor device produced in the present embodiment can be made into a flexible semiconductor device by using a flexible insulator.

0270The conductive shield 395 transmits electromagnetic waves to be transmitted and received by the conductive layer 380, which is an antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit 350 inside the semiconductor device. The conductive shield 395 is a semiconductor integrated circuit in order to diffuse and release the static electricity applied by the electrostatic discharge or to prevent the local existence (localization) of the electric charge (to prevent the local potential difference from occurring). It can prevent 350 electrostatic destruction.

0271Further, since the insulator and the conductive shield are provided by sandwiching the semiconductor integrated circuit, it is possible to prevent adverse effects such as damage to the semiconductor integrated circuit and poor characteristics due to external stress and electrostatic discharge even in the manufacturing process. Therefore, the semiconductor device can be manufactured with a good yield.

0272The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0273In addition, this embodiment can be carried out in combination with the above-described first to sixth embodiments as appropriate.

0274(Embodiment 8) In the present embodiment, an example of a semiconductor device for the purpose of imparting higher reliability will be described. More specifically, as an example of a semiconductor device, an example of a semiconductor device having a microprocessor and a computing function capable of transmitting and receiving data in a non-contact manner will be described.

0275FIG. 12 shows an example of the microprocessor 500 as an example of the semiconductor device. The microprocessor 500 is manufactured by the semiconductor device according to the above embodiment. This microprocessor 500 includes an arithmetic circuit 501 (Arithmetic logic unit, also called ALU), an arithmetic circuit control unit 502 (ALU Controller), an instruction analysis unit 503 (Instruction Decoder), an interrupt control unit 504 (Interrupt Controller), and timing control. It has a section 505 (Timing Controller), a register 506 (Register), a register control section 507 (Register Controller), a bus interface 508 (Bus I / F), a read-only memory 509, and a memory interface 510 (ROM I / F). ing.

0276Instructions input to the microprocessor 500 via the bus interface 508 are input to the instruction analysis unit 503, decoded, and then sent to the arithmetic circuit control unit 502, interrupt control unit 504, register control unit 507, and timing control unit 505. Entered. The arithmetic circuit control unit 502, interrupt control unit 504, register control unit 507, and timing control unit 505 perform various controls based on the decoded instructions. Specifically, the arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. Further, the interrupt control unit 504 processes an interrupt request from an external input / output device or a peripheral circuit based on its priority and mask state during program execution of the microprocessor 500. The register control unit 507 generates the address of the register 506, and reads or writes the register 506 according to the state of the microprocessor 500. The timing control unit 505 generates a signal for controlling the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above-mentioned various circuits. The microprocessor 500 shown in FIG. 12 is only an example in which the configuration is simplified, and in reality, a wide variety of configurations can be provided depending on the application.

0277Next, an example of a semiconductor device having an arithmetic function capable of transmitting and receiving data in a non-contact manner will be described with reference to FIG. FIG. 13 shows an example of a computer (hereinafter referred to as RFCPU) that operates by transmitting and receiving signals to and from an external device by wireless communication. The RFCPU511 has an analog circuit unit 512 and a digital circuit unit 513. The analog circuit unit 512 includes a resonance circuit 514 having a resonance capacitance, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, a modulation circuit 520, and a power supply management circuit 530. The digital circuit unit 513 has an RF interface 521, a control register 522, a clock controller 523, an interface 524, a central processing unit 525, a random access memory 526, and a read-only memory 527.

0278The operation of RFCPU511 with such a configuration is as follows. The signal received by the antenna 528 generates an induced electromotive force by the resonant circuit 514. The induced electromotive force is charged to the capacitance section 529 via the rectifier circuit 515. The capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitance portion 529 does not have to be integrally formed with the RF CPU 511, and may be attached to a substrate having an insulating surface constituting the RF CPU 511 as a separate component.

0279The reset circuit 517 generates a signal to reset and initialize the digital circuit unit 513. For example, a signal that rises after a delay in the rise in power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal according to the control signal generated by the constant voltage circuit 516. The demodulation circuit 519 formed by the low-pass filter binarizes the fluctuation of the amplitude of the received signal of the amplitude modulation (ASK) method, for example. The modulation circuit 520 transmits the transmission data by varying the amplitude of the amplitude-shifted (ASK) transmission signal. The modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514. The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal according to the power supply voltage or the current consumption in the central processing unit 525. The power supply voltage is monitored by the power management circuit 530.

0280The signal input from the antenna 528 to the RF CPU 511 is demodulated by the demodulation circuit 519 and then decomposed into control commands and data by the RF interface 521. The control command is stored in the control register 522. The control commands include reading data stored in the read-only memory 527, writing data to the random access memory 526, and arithmetic instructions to the central processing unit 525. The central processing unit 525 accesses the read-only memory 527, the random access memory 526, and the control register 522 via the interface 524. The interface 524 has a function of generating an access signal to any one of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

0281As the calculation method of the central processing unit 525, a method of storing the OS (operating system) in the read-only memory 527 and reading and executing the program at startup can be adopted. It is also possible to adopt a method in which an arithmetic circuit is configured with a dedicated circuit and arithmetic processing is processed in hardware. In the method of using both hardware and software, it is possible to apply a method in which some processing is performed by a dedicated arithmetic circuit and the remaining arithmetic is executed by the central processing unit 525 using a program.

0282Also in the microprocessor of the present embodiment, the conductive shield covering the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to the semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity.

0283(Embodiment 9) In this embodiment, an example of the usage mode of the semiconductor device shown in the above embodiment will be described. Specifically, an application example of a semiconductor device capable of inputting / outputting data in a non-contact manner will be described below with reference to the drawings. Semiconductor devices that can input and output data in a non-contact manner are also called RFID tags, ID tags, IC tags, RF tags, wireless tags, electronic tags, or wireless chips, depending on the mode of use.

0284An example of the upper surface structure of the semiconductor device shown in the present embodiment will be described with reference to FIG. 21 (A). The semiconductor device shown in FIG. 21 (A) includes a semiconductor integrated circuit chip 400 provided with an antenna (also referred to as an on-chip antenna) and a support substrate 406 provided with an antenna 405 (also referred to as a booster antenna). .. The semiconductor integrated circuit chip 400 is provided on the insulating layer 410 formed on the support substrate 406 and the antenna 405. The semiconductor integrated circuit chip 400 can be fixed on the support substrate 406 and the antenna 405 by the insulating layer 410. If the resistance of the conductive shield provided on the surface of the semiconductor integrated circuit chip 400 is high and the patterns of the antenna 405 are not made conductive, what is the conductive shield provided on the surface of the antenna 405 and the semiconductor integrated circuit chip 400? It may be provided in contact with each other.

0285The semiconductor integrated circuit provided in the semiconductor integrated circuit chip 400 is provided with elements such as a plurality of transistors constituting the memory unit and the logic unit. As the semiconductor device according to the present embodiment, not only a field effect transistor but also a storage element using a semiconductor layer can be applied as the semiconductor element, and a semiconductor device satisfying the functions required for various purposes is manufactured. Can be provided.

0286FIG. 20 (A) shows an enlarged view of the antenna and the semiconductor integrated circuit included in the semiconductor integrated circuit chip 400 shown in FIG. 21 (A). In FIG. 20A, the antenna 101 is a rectangular loop antenna having one turn, but the present invention is not limited to this configuration. The shape of the loop antenna is not limited to having a rectangular shape, and may have a curved shape, for example, a circular shape. The number of turns is not limited to one, and may be a plurality. However, when the number of turns of the antenna 101 is 1, the parasitic capacitance generated between the semiconductor integrated circuit 100 and the antenna 101 can be reduced.

0287Further, in FIGS. 21 (A) and 20 (A), the antenna 101 is arranged so as to surround the semiconductor integrated circuit 100, and the antenna 101 is provided except for the portion corresponding to the feeding point 408 shown by the broken line. It is arranged in a region different from that of the semiconductor integrated circuit 100. However, the present invention is not limited to this configuration, and as shown in FIG. 20 (B), the antenna 101 is arranged so as to overlap at least a part of the semiconductor integrated circuit 100 except for the portion corresponding to the feeding point 408 shown by the broken line. You may be. However, as shown in FIGS. 21 (A) and 20 (A), since the antenna 101 is arranged in a region different from that of the semiconductor integrated circuit 100, the parasitic capacitance generated between the semiconductor integrated circuit 100 and the antenna 101 Can be reduced.

0288In FIG. 21 (A), the antenna 405 can send and receive signals or supply electric power by electromagnetic induction with the antenna 101 mainly in a loop-shaped portion surrounded by a broken line 407. Further, the antenna 405 can mainly exchange signals with the interrogator or supply electric power by radio waves in a region other than the portion surrounded by the broken line 407. The frequency of the radio wave used as a carrier between the interrogator and the semiconductor device is preferably about 30 MHz or more and 5 GHz or less, and for example, a frequency band such as 950 MHz or 2.45 GHz may be used.

0289Further, the antenna 405 has a rectangular loop shape with one turn in the portion surrounded by the broken line 407, but the present invention is not limited to this configuration. The loop-shaped portion is not limited to having a rectangular shape, and may have a curved shape, for example, a circular shape. The number of turns is not limited to one, and may be a plurality.

0290The semiconductor device of the present invention can also be applied with an electromagnetic induction method, an electromagnetic coupling method, and a microwave method. In the case of the microwave method, the shapes of the antenna 101 and the antenna 405 may be appropriately determined depending on the wavelength of the electromagnetic wave used.

0291For example, when a microwave method (for example, UHF band (860 MHz band to 960 MHz band), 2.45 GHz band, etc.) is applied as a signal transmission method in a semiconductor device, the wavelength of the electromagnetic wave used for signal transmission is taken into consideration. The length and shape of the antenna may be set as appropriate. For example, the antenna can be formed into a linear shape (for example, a dipole antenna), a flat shape (for example, a patch antenna or a ribbon shape), or the like. Further, the shape of the antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of the electromagnetic wave.

0292FIG. 10 shows an example in which the antenna 101 and the antenna 405 are provided in a coil shape and the electromagnetic induction method or the electromagnetic coupling method is applied.

0293In FIG. 10, a semiconductor integrated circuit chip 400 provided with a coiled antenna 101 is provided on a support substrate 406 provided with a coiled antenna 405 as a booster antenna. The antenna 405, which is a booster antenna, has a capacitance formed by sandwiching the support substrate 406.

0294Next, the structure of the semiconductor integrated circuit chip 400 and the booster antenna and their arrangement will be described. FIG. 21B corresponds to a perspective view of a semiconductor device in which the semiconductor integrated circuit chip 400 and the antenna 405 formed on the support substrate 406 are laminated as shown in FIG. 21A. Then, FIG. 21 (C) corresponds to a cross-sectional view taken along the broken line XY of FIG. 21 (B).

0295As the semiconductor integrated circuit chip 400 shown in FIG. 21 (C), the semiconductor devices shown in the first to sixth embodiments can be used. Here, the semiconductor integrated circuit chips that are individually divided into chips are referred to as semiconductor integrated circuit chips. The semiconductor integrated circuit chip shown in FIG. 21C is an example in which the first embodiment is used, but the present embodiment can be applied to other embodiments and is not limited to this structure. ..

0296The semiconductor integrated circuit 100 shown in FIG. 21 (C) is sandwiched between the first insulator 112 and the second insulator 102, and its side surfaces are also sealed. In the present embodiment, after sandwiching a plurality of semiconductor integrated circuits and bonding the first insulator and the second insulator, the semiconductor integrated circuits are divided into laminates. A conductive shield is formed on the divided laminate by a plating method to produce a semiconductor integrated circuit chip 400. The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam.

0297The semiconductor device of the present invention has a conductive shield 140 on the outside (opposite side to the semiconductor integrated circuit side) and side surface of an antenna and a pair of insulators sandwiching a semiconductor integrated circuit electrically connected to the antenna. The conductive shield 140 transmits electromagnetic waves to be transmitted and received by the antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit inside the semiconductor device.

0298In FIG. 21C, the semiconductor integrated circuit 100 is arranged at a position closer to the antenna 405 than the antenna 101, but the present invention is not limited to this configuration. The antenna 101 may be arranged closer to the antenna 405 than the semiconductor integrated circuit 100. Further, the semiconductor integrated circuit 100 and the antenna 101 may be directly fixed to the first insulator 112 and the second insulator 102, or may be fixed by an adhesive layer that functions as an adhesive.

0299Next, the operation of the semiconductor device according to the present embodiment will be described. FIG. 19 is an example of a block diagram showing the configuration of the semiconductor device according to the present embodiment. The semiconductor device 420 shown in FIG. 19 has an antenna 422 as a booster antenna, a semiconductor integrated circuit 423, and an antenna 424 as an on-chip antenna. When an electromagnetic wave is transmitted from the interrogator 421, the antenna 422 receives the electromagnetic wave, so that an alternating current is generated in the antenna 422 and a magnetic field is generated around the antenna 422. Then, the loop-shaped portion of the antenna 422 and the antenna 424 having the loop-shaped shape are electromagnetically coupled to generate an induced electromotive force in the antenna 424. The semiconductor integrated circuit 423 receives a signal or power from the interrogator 421 by using the induced electromotive force. On the contrary, according to the signal generated in the semiconductor integrated circuit 423, a current is passed through the antenna 424 to generate an induced electromotive force in the antenna 422, so that the interrogator is placed on the reflected wave of the radio wave sent from the interrogator 421. A signal can be sent to the 421.

0300The antenna 422 is mainly divided into a loop-shaped portion that is electromagnetically coupled to the antenna 424 and a portion that mainly receives radio waves from the interrogator 421. The shape of the antenna 422 in the part that mainly receives the radio waves from the interrogator 421 may be any shape that can receive the radio waves. For example, shapes such as a dipole antenna, a folded dipole antenna, a slot antenna, a meander line antenna, and a microstrip antenna may be used.

0301Further, although FIG. 21 has described the configuration of a semiconductor integrated circuit having only one antenna, the present invention is not limited to this configuration. It may have two antennas, an antenna for receiving electric power and an antenna for receiving signals. If there are two antennas, the frequency of the radio wave that supplies power and the frequency of the radio wave that sends the signal can be used properly.

0302In the semiconductor device according to the present embodiment, an on-chip antenna is used, and signals or power can be exchanged between the booster antenna and the on-chip antenna in a non-contact manner. Therefore, the external antenna is a semiconductor. Unlike the case of connecting to an integrated circuit, the connection between the semiconductor integrated circuit and the antenna is not easily broken by an external force, and the occurrence of initial failure in the connection can be suppressed. Further, since the booster antenna is used in this embodiment, the size or shape of the on-chip antenna is not easily restricted by the area of the semiconductor integrated circuit, and the frequency band of the receivable radio wave is different from the case of only the on-chip antenna. The advantage of the external antenna is that the communication distance can be extended without limitation.

0303The semiconductor device to which the present invention is applied prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit by a conductive shield covering the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield. Further, since the plating method is used for forming the conductive shield, a semiconductor device can be manufactured at low cost and with high productivity. Therefore, it is effective when a small semiconductor device is capable of inputting / outputting data in a non-contact manner as shown in the present embodiment. Since the semiconductor device of the present embodiment has high reliability against an external force, it is possible to expand the conditions of the environment in which the semiconductor device can be used, and further expand the range of applications of the semiconductor device.

0304(Embodiment 10) In the present embodiment, an application example of the semiconductor device formed by using the present invention and capable of inputting / outputting data in a non-contact manner will be described below with reference to the drawings. Semiconductor devices that can input and output data in a non-contact manner are also called RFID tags, ID tags, IC tags, IC chips, RF tags, wireless tags, electronic tags, or wireless chips, depending on the form of use.

0305The semiconductor device 800 has a function of communicating data in a non-contact manner, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. It has a control circuit 870, a storage circuit 880, and an antenna 890 to perform (see FIG. 11 (A)). The high frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the received signal input from the antenna 890, and the data demodulation circuit 850 demolishes the received signal and controls the control circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. Further, as the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instructions sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with the code corresponding to the reference. It is a circuit that determines the content of an instruction, and the CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

0306Next, an example of the operation of the above-mentioned semiconductor device will be described. First, the radio signal is received by the antenna 890. The radio signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. Further, the signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter referred to as a demodulated signal). Further, the signal and the demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, according to the analyzed signal, the information of the semiconductor device stored in the storage circuit 880 is output. The output semiconductor device information is encoded through the output unit circuit 940. Further, the coded information of the semiconductor device 800 is transmitted on the radio signal by the antenna 890 through the data modulation circuit 860. In the plurality of circuits constituting the semiconductor device 800, the low power supply potential (hereinafter, VSS) is common, and VSS can be GND.

0307In this way, by sending a signal from the communication device to the semiconductor device 800 and receiving the signal sent from the semiconductor device 800 in the communication device, it is possible to read the data of the semiconductor device.

0308Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by electromagnetic waves without mounting a power supply (battery), or by mounting a power supply (battery) and using electromagnetic waves and power supply (battery) in each circuit. It may be a type that supplies a power supply voltage to the battery.

0309Next, an example of a usage pattern of a semiconductor device capable of inputting / outputting data in a non-contact manner will be described. A communication device 3200 is provided on the side surface of the mobile terminal including the display unit 3210, and a semiconductor device 3230 is provided on the side surface of the product 3220 (FIG. 11 (B)). When the communication device 3200 is held over the semiconductor device 3230 included in the product 3220, the information about the product such as the raw material and place of origin of the product, the inspection result for each production process, the history of the distribution process, and the description of the product are displayed on the display unit 3210. To. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected by using the communication device 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 11 (C)). In this way, by utilizing the semiconductor device in the system, it is possible to easily acquire information, and it is possible to realize high functionality and high added value.

0310As described above, the highly reliable semiconductor device of the present invention has an extremely wide range of applications and can be used in a wide range of electronic devices.

0311(Embodiment 11) According to the present invention, it is possible to form a chip having a processor circuit (hereinafter, also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) or a semiconductor device that functions as an RFID tag. The semiconductor device of the present invention has a wide range of applications, and can be applied to any product that is non-contact, clarifies information such as the history of an object, and is useful for production, control, and the like. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, foods, clothing, health supplies, daily necessities, chemicals and It can be installed in electronic devices and used. These examples will be described with reference to FIG.

0312Banknotes and coins are money that circulates in the market, and include things that can be used in the same way as money in a specific area (gold tickets), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, etc., and a chip 190 having a processor circuit can be provided (see FIG. 9 (A)). The certificate refers to a driver's license, resident's card, etc., and a chip 191 having a processor circuit can be provided (see FIG. 9 (B)). Personal belongings refer to bags, eyeglasses, etc., and can be provided with a chip 197 having a processor circuit (see FIG. 9 (C)). Bearer bonds refer to stamps, gift certificates, various gift certificates, etc. The packaging containers refer to wrapping paper such as lunch boxes, PET bottles, etc., and a chip 193 having a processor circuit can be provided (see FIG. 9 (D)). Books refer to books, books, etc., and a chip 194 having a processor circuit can be provided (see FIG. 9 (E)). The recording medium may be a DVD software, a video tape, or the like, and a chip 195 having a processor circuit may be provided (see FIG. 9 (F)). Vehicles refer to vehicles such as bicycles, ships, etc., and can be provided with a chip 196 having a processor circuit (see FIG. 9 (G)). Foods refer to foodstuffs, beverages, etc. Clothing refers to clothing, footwear, and the like. Health products refer to medical equipment, health equipment, etc. Living goods refer to furniture, lighting equipment, etc. Pharmaceuticals refer to pharmaceuticals, pesticides, etc. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (television receivers, flat-screen television receivers), mobile phones, and the like.

0313As a method of providing such a semiconductor device, it is attached to the surface of an article or embedded in an article. For example, in the case of a book, it may be embedded in paper, and in the case of a package made of organic resin, it may be embedded in organic resin.

0314In this way, by installing semiconductor devices in packaging containers, recording media, personal belongings, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. Further, by providing a semiconductor device on the vehicle, forgery and theft can be prevented. In addition, individual creatures can be easily identified by embedding them in creatures such as animals. For example, by embedding or attaching a semiconductor device equipped with a sensor to a living thing such as livestock, it becomes possible to easily manage a health condition such as body temperature as well as the year of birth, gender or type.

0315In addition, this embodiment can be carried out in combination with the above-described first to ninth embodiments as appropriate.

0316(Embodiment 12) In the present embodiment, an implementation example of the semiconductor device of the present invention will be described with reference to FIG.

0317As shown in the ninth embodiment, various semiconductor devices of the present invention can be mounted on articles. In this embodiment, an example of manufacturing a flexible semiconductor device by mounting it on a flexible substrate (also referred to as a flexible substrate) is shown.

0318FIGS. 18 (A) to 18 (C) are examples of mounting the semiconductor integrated circuit chip in a flexible substrate so as to be embedded in the flexible substrate. As the semiconductor integrated circuit chip, the semiconductor devices shown in the first to sixth embodiments can be used. Here, the semiconductor integrated circuit chip is individually divided into chips. FIG. 18 (D) shows the details of the semiconductor integrated circuit chip 600. The semiconductor integrated circuit chip of FIG. 18D is an example in which the first embodiment is used, but the present embodiment can be applied to other embodiments and is not limited to this structure.

0319In FIG. 18D, the antenna 101 and the semiconductor integrated circuit 100 are sandwiched between the first insulator 112 and the second insulator 102, and the side surfaces thereof are also sealed. In the present embodiment, the first insulator 112 and the second insulator 102 sandwich a plurality of semiconductor integrated circuits, and are divided into individual antennas 101 and semiconductor integrated circuits 100 to form a semiconductor integrated circuit chip. To make. The dividing means is not particularly limited as long as it can be physically divided, but in the present embodiment, it is divided by irradiating a laser beam.

0320By splitting, the antenna 101 and the semiconductor integrated circuit 100 are sealed by the first insulator 112 and the second insulator 102, and a cross section is formed as the side surface of the chip. In the divided semiconductor integrated circuit chip, the conductive shield 140 is formed by a plating method so as to surround the periphery thereof.

0321Therefore, the antenna 101 and the semiconductor integrated circuit 100 are sealed by the first insulator 112 and the second insulator 102, and the first insulator 112 and the second insulator corresponding to the front surface and the back surface of the semiconductor device are provided. The structure is protected against electrostatic discharge by the conductive shield 140 provided on the outside and the side surface of the 102.

0322The conductive shield that covers the semiconductor integrated circuit prevents static electricity destruction (circuit malfunction and damage to semiconductor elements) due to electrostatic discharge of the semiconductor integrated circuit. Further, by using a pair of insulators sandwiching a semiconductor integrated circuit, it is possible to provide a highly reliable semiconductor device having resistance while achieving thinness and miniaturization. Further, also in the manufacturing process, it is possible to prevent defects in shape and characteristics due to external stress or electrostatic discharge, and to manufacture a semiconductor device with a good yield.

0323FIG. 18A shows a flexible substrate 601 and a semiconductor integrated circuit chip 600 sandwiched between the flexible substrate 602, and the semiconductor integrated circuit chip 600 is arranged in a recess provided in the flexible substrate 601. There is.

0324The recess in which the semiconductor integrated circuit chip 600 is arranged may be provided on one of the flexible substrates, or may be provided on both. FIG. 18B is an example in which the semiconductor integrated circuit chip 600 is arranged in the recesses provided in both the flexible substrate 601 and the flexible substrate 602.

0325Further, the flexible substrate may have a three-layer structure, and the flexible substrate in the center may be provided with an opening for arranging the semiconductor integrated circuit chip 600. In FIG. 18C, an opening is provided in the flexible substrate 603, a semiconductor integrated circuit chip 600 is arranged in the opening, and the flexible substrate 601 and the flexible substrate 602 are referred to as a flexible substrate 603 and a semiconductor. This is an example of sandwiching the integrated circuit chip 600 so as to sandwich it.

0326In FIGS. 18A to 18C, the flexible substrate may be further laminated on the outer side of the flexible substrate 601 and the flexible substrate 602.

0327As the flexible substrates 601, 602, and 603, a woven fabric woven using a bundle of fibers (single yarn) (hereinafter referred to as a yarn bundle) as a warp and a weft, or a yarn bundle of a plurality of types of fibers is randomly selected or used. Nonwoven fabric, paper, etc. deposited in one direction can be used. Specifically, from PET (polyester terephthalate), PEN (polyester naphthalate), PES (polyether sulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyftalamide, etc. A substrate made of polypropylene, polyester, vinyl, polyvinyl chloride, vinyl chloride, polyester, polyamide or the like, a film, paper made of a fibrous material, or the like can be used. A laminated film with an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.) can be used. When the substrate or film adheres to the object to be treated, an adhesive layer may be used. Conditions can be selected according to the type of substrate or film, and bonding can be performed by heat treatment or pressurization. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin-based adhesive, or a resin additive.

0328If a recess or an opening is provided in the flexible substrate to be mounted so as to embed the semiconductor integrated circuit chip 600 as in the present embodiment, the convex portion due to the semiconductor integrated circuit chip 600 is not formed. , The surface of the flexible substrate is flat, and the film thickness can be made uniform. Therefore, when mounting a semiconductor integrated circuit chip on a flexible substrate, even if pressure processing is performed by a roller or the like for bonding, pressure is locally applied to the semiconductor integrated circuit chip (pressure is concentrated). Can be prevented. Therefore, damage to the semiconductor integrated circuit chip can be reduced in the mounting process, and the yield of the semiconductor device is improved. Further, even after mounting, the semiconductor device can be highly reliable and resistant to external stress.

0329Further, since the surface can be flat and smooth, it is excellent in storage and stackability on a machine and transportability. Further, since the semiconductor integrated circuit chip is not visible from the outside (because there is no convex portion on the surface reflecting the shape of the semiconductor integrated circuit chip), the semiconductor device can be made into a highly secure semiconductor device.

Every citation, both ways

Citations
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JP09118086A	Cites	Japan
JP62008283A	Cites	Japan
JP2003160876A	Cites	Japan
JP2006086544A	Cites	Japan
WO2006038438A1	Cites	World Intellectual Property Organization (WIPO)
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Document	Office	Kind	Date
2008149603	Japan	–	2008-06-06
2008149603	Japan	A	2008-06-06

Members8

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Document	Office	Kind
US2009305467A1	United States of America	A1	2009-12-10
JP2010016362A	Japan	A	2010-01-21
US8053253B2	United States of America	B2	2011-11-08
US2012108014A1	United States of America	A1	2012-05-03
US8420409B2	United States of America	B2	2013-04-16
JP5315134B2This record	Japan	B2	2013-10-16
JP2013251555A	Japan	A	2013-12-12
JP5581426B2	Japan	B2	2014-08-27

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