Memory device having multi-channel and memory access method in the same device

An embodiment of the present invention relates to a memory device having a multi-channel and a memory access method in the device.

Conventionally, a memory device having a memory typified by a NAND flash memory and having a multi-channel for executing a plurality of access commands in parallel has been known. On the other hand, it is known that the data retention of a flash memory such as a NAND flash memory is relatively weak. Therefore, the quality of the data stored in the flash memory may deteriorate with the passage of time, for example.

Therefore, in a conventional memory device provided with a flash memory, a patrol process for appropriately inspecting data garbled due to the data stored in the flash memory being left for a long time is executed. This patrol process involves read access and is performed by the memory controller, for example, in block units. When garbled data (degradation of quality) is detected, the data in the corresponding block is rewritten to another block in the flash memory. As a result, the data of the block in which the deterioration of quality is detected is refreshed.

In the patrol process, a plurality of access commands (read commands) are speculatively issued in order to efficiently read and access the entire area of the block to be inspected (patrol). That is, the subsequent access command group is issued without waiting for the execution completion of the preceding access command group. Therefore, the memory controller is configured to record all issued access commands in order to deal with an error in read access according to the access command group. This is not limited to patrol processing. For example, the same applies to the self-diagnosis process in which the memory device itself diagnoses the data (user data) stored in the flash memory in response to a request from the host. The same applies to the refresh process for refreshing the peripheral page by detecting the garbled data of the peripheral page due to the repeated read.

By the way, while rewriting the data of the block in the flash memory, the power supply of the memory device provided with the flash memory may be cut off. In this case, the data rewriting may not be completed normally. Therefore, there is also known a memory device configured to record information (data rewriting progress information) indicating the progress state of the data rewriting when the data rewriting of the block in the flash memory occurs. When the power is turned on again, this memory device recovers the data of the block in which the data rewriting has not been normally completed, based on the information indicating the data rewriting progress state when the power is cut off.

<p num="0006"><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2005-56144</text></patcit></p>

<p num="0007"> As described above, a conventional memory device equipped with flash memory records all speculatively issued access commands in read / write processing (that is, memory access processing) covering the entire area of a block. It is configured in. Therefore, the conventional memory device requires a memory area (that is, a management area) for recording all access commands. This is the same even for a memory device having a memory other than the flash memory, as long as it is a memory device that executes a plurality of speculatively issued access commands in parallel.</p><p num="0008"> An object of the present invention is to provide a memory device having a multi-channel and a memory access method in the device, which can execute memory access processing in block units at high speed by management using a small capacity memory area.</p>

<p num="0009"> According to the embodiment, the memory device includes a memory, a memory interface, a command generation means, a purge means, and a command progress management means. The memory is accessed via a plurality of channels. The memory interface accesses the memory in parallel via the plurality of channels according to a plurality of access commands. The command generation means sequentially speculatively inputs a group of channel-specific access commands to the memory interface in a predetermined access process for accessing the memory in block units. When an error occurs in any of the memory access via the plurality of channels by the memory interface, the purge means returns a series of unexecuted access commands that have already been input by a purge response. The command progress management means is a command progress management means for managing the command progress of an access command in the predetermined process for each channel based on the command progress information, and the command progress in each channel is the returned unexecuted access command. The command progress information is updated so that the command progress information is returned to the position specified by the oldest unexecuted access command in the series. Based on the updated command progress information, the command generation means inputs a group of channel-specific access commands including the oldest returned unexecuted access command to the memory interface.</p>

<figref num="1">The block diagram which shows the typical structure of the memory apparatus which has the multi-channel which concerns on one Embodiment.</figref><figref num="2">The figure which shows the example of the access command of 4,096 generated when the self-diagnosis process is executed for one logical block in the same embodiment in association with a page, a channel, a plane and a cluster.</figref><figref num="3">The figure which shows a part of the flowchart for demonstrating the procedure of the self-diagnosis process applied in the same embodiment.</figref><figref num="4">The figure which shows the rest of the flowchart for explaining the procedure of the self-diagnosis process applied in the same embodiment.</figref><figref num="5">An example of the format of the logical address and the physical address applied in the same embodiment is shown.</figref><figref num="6">The figure which shows an example of the time series of the read command group which is sequentially input by a command generation part in the same embodiment.</figref>

Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a block diagram showing a typical configuration of a memory device having a multi-channel according to one embodiment. In this embodiment, the memory device 10 shown in FIG. 1 is connected to, for example, a host (not shown). The host uses the memory device 10 as its own storage device.

The memory device 10 includes a NAND flash memory 11 and a NAND controller 12. The NAND flash memory 11 is a storage medium for storing user data. The NAND flash memory 11 includes a plurality of NAND flash memory chips, and is configured to be accessible in parallel by the NAND controller 12 in response to a plurality of access commands. Note that a memory other than the NAND flash memory may be used instead of the NAND flash memory 11 as long as it can be accessed in parallel in response to a plurality of access commands.

The NAND controller 12 accesses the NAND flash memory 11 in response to a request from the host. The NAND controller 12 also accesses the NAND flash memory 11 for block-by-block memory access processing, such as self-diagnosis processing, patrol processing, or refresh processing. Here, it is assumed that the self-diagnosis process is performed.

The NAND controller 12 includes the NAND interface 1201, the control unit 1202, the progress management unit 1203, the command progress management unit 1204, the command progress judgment unit 1205, the command generation unit 1206, the table management unit 1207, and the response accumulation. It includes a unit 1208, a response analysis unit 1209, a compaction unit 1210, and an interchannel error correction status management unit (hereinafter referred to as an ICPCS management unit) 1211. Control unit 1202, progress control management unit 1203, command progress management unit 1204, command progress judgment unit 1205, command generation unit 1206, table management unit 1207, response storage unit 1208, response analysis unit 1209, compaction unit 1210, and ICPCS management unit. Each part (module) of 1211 is interconnected by the internal bus 1212.

The NAND interface 1201 exchanges information between the NAND flash memory 11 and the command generation unit 1206 and the response storage unit 1208. The NAND interface 1201 includes a purge mechanism 1201a and an interchannel error correction mechanism (hereinafter referred to as an ICP correction mechanism) 1201b.

When an error occurs in the execution of the input access command, the purge mechanism 1201a returns all the unexecuted access commands to the response storage unit 1208 by a special command response (hereinafter referred to as a purge response). When an error that cannot be corrected by the error correction code (ECC) occurs, the ICP correction mechanism 1201b corrects the error location based on the data between the channels. This correction is called interchannel error correction (ICP correction).

The control unit 1202 controls the operation of each of the above modules connected via the internal bus 1211. The progress control management unit 1203 manages the command progress of the processing unit (self-diagnosis processing unit). The progress control management unit 1203 comprehensively manages the command progress status for each channel managed by the command progress management unit 1204, and determines the division of processing units (for example, completion of one logical block).

The command progress management unit 1204 is speculative for each channel in the NAND interface 1201 in order to process one logical block in the access processing (here, the access processing for self-diagnosis processing) executed in units of logical blocks and for each channel. Manages the progress of access commands issued to (that is, the progress of inputting access commands). The command progress management unit 1204 holds command progress information for managing the progress of inputting access commands for each channel (hereinafter referred to as command progress). Command progress information for each channel is stored in a memory area such as DRAM.

Command progress information for each channel consists of (page number, plane number, cluster number). More specifically, the command progress information for each channel consists of (page number, plane-cluster number). The command progress information for each channel is the relative position (page, plane, cluster) within the physical block specified by the next (or most recently submitted) access command to the corresponding channel, that is, the command progress. Indicates the position. The command progress information for each channel also indicates a relative position (hereinafter, simply referred to as a position) for each channel in the logical block to which the specified physical block is assigned. Page numbers, plane numbers, cluster numbers and plane-cluster numbers and pages, planes and clusters will be described later.

In this embodiment, the NAND interface 1201 has 16 channels 0,1, ..., 14,15 as described in detail later. Therefore, the command progress management unit 1204 is a channel-specific command progress management unit (hereinafter referred to as CH progress management unit) corresponding to 16 channels 0,1, ..., 14,15, 1204-0,1204-1, It consists of ..., 1204-14, 1204-15. CH progress management unit 1204-i (i = 0,1, ..., 14,15) manages the progress of access commands issued to channel i, and command progress information (page number) corresponding to the channel i. , Plain-cluster number).

The command progress determination unit 1205 identifies the oldest position (page, plane, and cluster) for each channel based on the command response described later, and determines whether the command progress needs to be updated based on the specified position. The oldest position refers to the position specified by the oldest access command in the series of unexecuted access commands submitted to the corresponding channel.

The command generation unit 1206 speculatively issues a plurality of access commands for accessing the NAND flash memory 11 to the NAND interface 1201 for each channel. The command generation unit 1206 executes the issue of the access command for each channel based on the command progress information for each channel managed by the command progress management unit 1204.

The table management unit 1207 includes a logical-physical address conversion table (hereinafter referred to as a theory conversion table) 1207a for converting a logical address into a physical address. In this embodiment, the theory conversion table 1207a is constructed in a memory area such as DRAM. For example, when performing self-diagnosis processing, the table management unit 1207 converts the address (logical address) of the logical block to be processed into the address (physical address) of the corresponding physical block based on the theory conversion table 1207a. .. The logical address of the logical block to be processed can be specified from the logical block ID for identifying the logical block and the command progress information (page number, plane-cluster number). The table management unit 1207 also holds information (hereinafter, referred to as logical block information) indicating the state of the corresponding logical block for each logical block (logical block ID). The logical block information includes information indicating whether the corresponding logical block is the logical block used (that is, the active logical block).

The response storage unit 1208 stores the response (hereinafter referred to as a command response) from the NAND interface 1201 to the access command input to the NAND interface 1201 by the command generation unit 1206. Of the command responses, the command response that notifies an error is sometimes called an error response. The response storage unit 1208 also stores the above-mentioned purge response as a command response.

The response storage unit 1208 has a FIFO structure configured by using, for example, a first-in first-out buffer. The response storage unit 1208 is managed by the write pointer and the read pointer. The write pointer indicates the position in the response storage unit 1208 where the command response returned from the NAND interface 1201 should be stored next. The read pointer indicates the position in the response storage unit 1208 in which the command response to be analyzed next by the response analysis unit 1209 is stored.

The response analysis unit 1209 analyzes the command response pointed to by the read pointer among the command responses returned by the NAND interface 1201 and stored in the response storage unit 1208. When the response analysis unit 1209 finishes analyzing the command response pointed to by the read pointer, the response analysis unit 1209 advances the read pointer so as to point to the next position in the response storage unit 1208.

The compaction unit 1210 executes the compaction process when it is determined in the self-diagnosis process that it is necessary to move the data of the logical block to another block. That is, the compaction unit 1210 executes the compaction process when the logical block ID of the logical block to be the target of the compaction process is registered. By this compaction processing, the data of the first physical block group in the NAND flash memory 11 currently assigned to the logical block indicated by the logical block ID is transferred to another second physical block group in the NAND flash memory 11. Can be rewritten. After rewriting this data, the physical block group assigned to the logical block indicated by the logical block ID is changed from the first physical block group to the second physical block group.

The ICPCS management unit 1211 manages the logical page (here, one of logical pages 0 to 63) in which the ICP correction is executed in the logical block indicated by the logical block ID. In the present embodiment, the ICPCS management unit 1211 manages whether or not the ICP correction of the logical pages 0 to 63 is completed by using a 64-bit length bitmap (hereinafter, referred to as an ICP completion page bitmap). The ICP completion page bitmap is stored in an area of memory such as DRAM.

Next, the operation of the memory device 10 in the present embodiment will be described by taking a self-diagnosis process as an example. First, in the present embodiment, it is assumed that the memory device 10 is operating under the following preconditions (1) to (6). (1) The command generator 1206 can input a plurality of access commands to the NAND interface 1201 at the same time. The maximum number of access commands that can be simultaneously input from the command generator 1206 to the NAND interface 1201 is set when the memory device 10 is started. In this embodiment, the NAND interface 1201 has 16 channels 0,1, ..., 15, and the command generator 1206 can simultaneously issue access commands for up to 16 channels. The channel numbers of channels 0,1, ..., 15 are 0,1, ..., 15 (decimal notation), respectively.

(2) One logical block consists of 64 pages (logical pages) 0,1, ..., 63, and access (here, read access) is performed in cluster units that are half of one page. In other words, access shall be divided into clusters 0 and 1. The page numbers of pages 0,1, ..., 63 are 0,1, ..., 63 (decimal representation), respectively. The cluster numbers of clusters 0 and 1 are 0 and 1 (decimal notation), respectively.

(3) Each of channels 0,1, ..., 15 is connected to two planes 0,1. Access processing (here, read processing) via each channel is executed in four steps of 2 (plain) x 2 (cluster) per page.

(4) For access commands (here, read commands), execution orders are guaranteed in the order in which they are entered for each channel. (5) If an error occurs on a certain channel i, all unexecuted commands are purged. (6) Errors that cannot be corrected by ECC are corrected using the ICP correction mechanism 1201b.

Figure 2 shows the 4,096 (64 × 16 × 4) access commands C0000, C0001, C0002, C0003, C1000 generated when the self-diagnosis process is executed for one logical block under the above prerequisites. , C1001, C1002, C1003, ..., CF3F0, CF3F1, CF3F2, CF3F3, page 0,1, ..., 63, channel 0,1, ..., 15, plane 0,1 and cluster 0, Shown in association with 1. In the example shown in Figure 2, 32 physical blocks are assigned to one logical block. The 32 physical blocks correspond to planes 0,1 on 16 channels 0,1, ..., 15, respectively.

Of the access commands Cpqrs, C indicates the access command, and p (0,1, ..., F) is a one-digit hexadecimal number indicating the channel number of the channel to which the access command Cpqrs is input. The qr (00,01, ..., 3F) in the access command Cpqrs is a 2-digit hexadecimal number indicating the page number of the page to be accessed.

The s (0,1,2,3) in the access command Cpqrs is a one-digit hexadecimal number indicating the plane-cluster number for identifying the combination of planes and clusters in the channel to which the access command Cpqrs is issued. Is. s = 0 indicates the combination of plane 0 and cluster 0, and s = 1 indicates the combination of plane 0 and cluster 1. s = 2 indicates the combination of plane 1 and cluster 0, and s = 3 indicates the combination of plane 1 and cluster 1. Therefore, s (0,1,2,3), or plane-cluster number, is equivalent to indicating the plane number of the plane (0,1) and the cluster number of the cluster (0,1).

In the present embodiment, the pages in the logical block are accessed in the order of pages 0, 1, ..., 63 for each channel. However, the progress of the accessed page differs for each channel. In addition, the four access commands Cpqr0, Cpqr1, Cpqr2, and Cpqr3 that instruct to access the page qr (qr is a two-digit hexadecimal representation) via the channel p (p is a hexadecimal representation) of NAND flash memory 11 , Is executed in this order.

Specifically, four access commands C0000, C0001, C0002, C0003 that instruct to access page 0 (0 is decimal representation) via, for example, channel 0 (0 is decimal representation) of NAND flash memory 11. Is executed in this order. In addition, the four access commands CF000, CF001, CF002, and CF003 that instruct to access page 0 via, for example, channel 15 (F in hexadecimal notation) of the NAND flash memory 11 are executed in this order. Similarly, the four access commands C03F0, C03F1, C03F2, C03F3 that direct access to page 63 (3F in hexadecimal notation) via, for example, channel 0 of the NAND flash memory 11 are executed in this order. .. Similarly, the four access commands CF3F0, CF3F1, CF3F2, CF3F3 that direct access to page 63 (3F in hexadecimal notation) via, for example, channel 15 (F in hexadecimal notation) of NAND flash memory 11 It is executed in this order.

Hereinafter, the outline of the procedure of the self-diagnosis process applied in the present embodiment will be described by taking the self-diagnosis process for one logical block as an example. The logical block that is the target of self-diagnosis processing is the target of read access. Therefore, in the following description, the logical block that is the target of the self-diagnosis process may be referred to as the read target logical block.

1) The NAND controller 12 reads all the clusters in the read target logical block for each channel, and determines whether the data of the corresponding clusters is normal. 2) When the NAND controller 12 detects an effective cluster whose error cannot be corrected, it determines whether or not ICP correction is possible. If the correction is not possible, the NAND controller 12 ends the self-diagnosis process of the read target logical block and notifies the error cluster to the requester of the self-diagnosis process.

3) If the ICP can be corrected in 2) above, the NAND controller 12 returns to 1) above and reads the subsequent cluster. 4) If one or more error-uncorrectable clusters are detected when the processing of the read target logical block is completed, the NAND controller 12 uses the read target logical block as the target logical block for compaction processing. Register as.

Next, the details of the procedure of the self-diagnosis process described above will be described with reference to the flowcharts of FIGS. 3 and 4. Now, it is assumed that the host requests the NAND controller 12 of the memory device 10 in FIG. 1 to perform self-diagnosis processing. In the present embodiment, the self-diagnosis process is performed as a background process for the access process requested by the host. That is, the self-diagnosis process is performed by utilizing the free time of the access process requested by the host. The self-diagnosis process shown in the flowcharts of FIGS. 3 and 4 targets one logical block. Therefore, when self-diagnosing a plurality of logical blocks, the self-diagnosis process shown in the flowcharts of FIGS. 3 and 4 is repeated for the number of logical blocks to be diagnosed.

The control unit 1202 of the NAND controller 12 specifies the logical block (that is, the read target block) to be the target of the self-diagnosis process to the command progress management unit 1204. For this specification, for example, the logical block ID of the read target logical block is used. Although omitted in the flowcharts of FIGS. 3 and 4, the command progress information of channels 0, 1, ..., 14, 15 held in the command progress management unit 1204 at the start of the self-diagnosis process is Each is initialized to "000" to indicate the initial position (page 0, plane 0, cluster 0).

When the read target logical block is specified by the control unit 1202, the command progress management unit 1204 acquires the logical block information of the specified read target logical block from the table management unit 1207 (step 301). If the acquired logical block information indicates that the read target logical block is not an active logical block, reading (more specifically, self-diagnosis processing) of the read target logical block is unnecessary. In this case, although omitted in the flowcharts of FIGS. 3 and 4, the control unit 1202 ends the self-diagnosis process for the current read target logic block.

On the other hand, when the acquired logical block information indicates that the read target logical block is an active logical block, the command progress management unit 1204 discusses based on the logical block ID of the read target logical block. Refer to the object conversion table 1207a. As a result, the command progress management unit 1204 acquires the information (referred to as physical block information) of the read target physical block group assigned to the read target logical block (step 302). The physical block information includes each ID (physical block ID) of the corresponding physical block group (read target physical block group).

Next, the command progress management unit 1204 is based on the physical block ID in the physical block information acquired in step 302 and the command progress information (page number, plane-cluster number) for each current channel that it holds. Obtain the physical address indicating the physical location to be accessed for each channel in the NAND flash memory 11 (step 303). If the physical block information acquired in step 302 indicates that the corresponding physical block is a NULL block, the command progress management unit 1204 sets the current command progress information of the corresponding channel to the next position. Update as shown. That is, the command progress management unit 1204 advances the command progress (page, plane, cluster) of the corresponding channel to the next. Then, the command progress management unit 1204 acquires the physical address in the physical block (read target physical block) to be accessed via the corresponding channel in the same procedure as described above.

FIG. 5 shows an example of the logical address and physical address formats applied in the present embodiment. The logical address is composed of the logical block ID, page number, plane number, channel number, and cluster number of the corresponding logical block. The logical address is also referred to as a logical NAND cluster address in the present embodiment in which the NAND flash memory 11 is used in the memory device 10. The physical address is composed of a physical block ID for identifying the corresponding physical block, a plane number, a page number, a cluster number, and a sector number. This physical address is also known as the physical NAND cluster address.

On the other hand, in step 303, the progress control management unit 1203 is the final cluster in the read target logical block based on the command progress status for each channel managed by the command progress management unit 1204 (more specifically, the final page). Judge by channel whether it has reached the final cluster). The progress control management unit 1203 holds the determination results for each of the above channels. In step 303, the command generation unit 1206 provides read access to the corresponding physical location (page, plane, cluster) for each channel based on the physical address (that is, the physical NAND cluster address) acquired by the command progress management unit 1204. Generates the specified access command (hereinafter referred to as read command). The generated read command contains a NAND cluster address in the format shown in Figure 5.

The command generation unit 1206 further sets specific specified information in the read commands generated for each channel that satisfy the predetermined conditions. The read command that satisfies the predetermined conditions refers to the read command (that is, the final read command) corresponding to the physical NAND cluster address determined by the progress control management unit 1203 to be in the final cluster processing. The specific specified information specifies that a command response (success response) should be returned when the corresponding final read command is successfully executed. That is, a read command in which specific specified information is set specifies that a command response should be returned when the execution of the read command is successful. On the other hand, a read command for which specific specified information is not set (that is, a non-final read command) implicitly specifies that a command response is not returned when the execution of the read command is successful. In addition, the read command implicitly specifies that if the execution of the read command fails, a command response (error response) is returned regardless of whether specific specified information is set. Note that the read command (non-final read command) that does not satisfy the predetermined conditions may be set with the specified information that explicitly specifies that the command response is not returned when the command execution is successful.

In step 303, the command generation unit 1206 simultaneously issues a maximum of 16 generated read command groups to the NAND interface 1201. As in this example, in the first step 303 following the flowcharts of FIGS. 3 and 4, 16 read commands C0000, C1000, ..., corresponding to 16 channels 0,1, ..., 14,15, respectively. CE000 and CF000 are issued at the same time. Figure 6 shows an example of the time series of read commands that are sequentially input by the command generator 1206. In the example of FIG. 6, it is shown that 16 read commands C0000, C1000, ..., CE000, CF000 were issued at time t1.

The read commands C0000, C1000, ..., CE000, CF000 simultaneously input to the NAND interface 1201 by the command generator 1206 are stored in the command queue (not shown) in the NAND interface 1201.

If the command queue is not full, the command generator 1206 can speculatively submit subsequent physical read commands to the NAND interface 1201. In the present embodiment, as shown in FIG. 6, 16 read commands C0001, C1001, ..., CE001, CF001 are input at time t2 after time t1, and 16 read commands are input at time t3 thereafter. It is assumed that C0002, C1002, ..., CE002, CF002 have been input. In this way, the command generation unit 1206 can speculatively input subsequent read command groups until the command queue is full.

At the start of the self-diagnosis process, the NAND interface 1201 retrieves the 16 read commands C0000, C1000, ..., CE000, CF000 that were initially stored in the command queue. The NAND interface 1201 is then based on the fetched read command C0000, C1000, ..., CE000, CF000 via plane 0 connected to the corresponding channels 0,1, ..., 14,15, respectively. Access the NAND flash memory 11 in parallel.

Here, it is assumed that an error has occurred in any of the read access based on the speculatively input read command group. In this embodiment, this error is called an ECC error because it is detected based on the ECC attached to the read data.

When an ECC error occurs, the NAND interface 1201 returns an error response to the response storage unit 1208 as a command response to the read command that specifies the read access in which the ECC error occurred. The error response (command response) returned to the response storage unit 1208 is stored in the response storage unit 1208.

If an ECC error occurs, the purge mechanism 1201a of NAND interface 1201 has not been submitted to all commands stored in the command queue corresponding to the channel in which the ECC error occurred (that is, the channel in which the ECC error occurred). All read commands for execution) are returned to the response storage unit 1208 by the purge response. The purge response (command response) returned to the response storage unit 1208 is stored in the response storage unit 1208.

As mentioned above, the self-diagnosis process is performed in the background of the system. Therefore, depending on the channel, the access command for access requested by the host may be executed in preference to the execution of the read command for self-diagnosis. In the present embodiment, the purge mechanism 1201a of the NAND interface 1201 returns all unexecuted commands to the response storage unit 1208 by a purge response even if an ECC error occurs in the access requested by the host.

Now, it is assumed that the command response is returned by the NAND interface 1201 and the returned command response is stored in the response storage unit 1208. The response analysis unit 1209 analyzes all the command responses accumulated in the area starting from the position in the response storage unit 1208 pointed by the read pointer (step 304).

Based on the analysis result of the command response, the response analysis unit 1209 determines whether the analysis result includes one or more error responses (ECC error responses) for notifying the ECC error (step 305). If one or more error responses are included, that is, if the number of ECC errors N1 exceeds zero (N1&gt; 0) (Yes in step 305), the response analysis unit 1209 turns the refresh flag ON. Set (step 306). The refresh flag is used to indicate that the logical block should be registered as a target for compaction processing at the end of the self-diagnosis processing for the logical block.

Next, the response analysis unit 1209 inquires the table management unit 1207 whether or not the cluster for which the ECC error is determined in step 305 is a valid cluster. A valid cluster is a cluster that contains valid data. If the data stored in the valid cluster is moved to another cluster, the valid cluster becomes an invalid cluster. The enable / disable of the cluster is managed by the table management unit 1207.

Based on the result of inquiring to the table management unit 1207, the response analysis unit 1209 determines whether the number of valid clusters for which ECC errors have been determined (that is, the number of ECC errors of valid clusters) N2 exceeds zero (step 307). ). If the number of ECC errors N2 in the valid cluster exceeds zero (N2&gt; 0) (Yes in step 307), the self-diagnosis process proceeds to step 308. In step 308, the control unit 1202 causes the ICP correction mechanism 1201b to perform ICP correction on the page (logical page) including the valid cluster in which the ECC error is determined (that is, the valid cluster in which ECC cannot be corrected).

In this embodiment, one of 16 channels is assigned to store error correction data for ICP correction in order to enable ICP correction of the corresponding page for each logical page in the logical block. .. The channel assigned to store the error correction data is changed for each logical page, but it may be a specific channel. The error correction data for ICP correction is, for example, parity data (interchannel parity data) generated based on the data of the corresponding logical page stored in the other 15 channels. The ICP correction mechanism 1201b uses this parity data to perform ICP correction for repairing the error part of the logical page j (j = qr) including the valid clusters that cannot be corrected by ECC. In other words, the ICP correction mechanism 1201b is on the logical page j corresponding to the parity data and the channel group (second channel group) excluding the channel (first channel) having the effective cluster that cannot be ECC corrected among the other 15 channels. Make ICP corrections based on the data.

The control unit 1202 determines whether the ICP correction on the logical page j was successful based on the result of the ICP correction by the ICP correction mechanism 1201b (step 309). If the ICP correction of the logical page j fails, that is, if the ICP correction is not possible (No in step 309), the control unit 1202 sets the logical block ID of the read target logical block as the target of compaction processing. It is registered in the compaction unit 1210 as a logical block (step 310). In step 310, the control unit 1202 switches the refresh flag from the ON state to the OFF state.

Next, the control unit 1202 notifies the request source (host in this case) of the self-diagnosis process of the ICP uncorrectable cluster, and ends the self-diagnosis process for one logical block. In this case, the compaction unit 1210 performs compaction processing for moving the data of the logical block indicated by the logical block ID registered in step 310 to another block.

On the other hand, if the analysis result by the response analysis unit 1209 does not include one error response, that is, if the ECC error number N1 is zero (No in step 305), the self-diagnosis process proceeds to step 401. Further, even when the ECC error number N2 of the valid cluster is zero (No in step 307), the self-diagnosis process proceeds to step 401.

In step 401, the command progress determination unit 1205 determines whether the purge response is included (exists) in the command response analyzed by the response analysis unit 1209. That is, the command progress determination unit 1205 determines whether the command returned by the purge response (hereinafter referred to as a purge command) is included in the analyzed command response.

Here, on channels 14 and 15, the access processing requested by the host is prioritized, so the read commands C0000, C1000 simultaneously issued to channels 0,1, ..., 14,15 at time t1. It is assumed that the read command CE000, CF000 of, ..., CE000, CF000 has not been executed even after the time t2. In addition, it is assumed that a purge response is returned because an error occurred in the access processing via channels 14 and 15 requested by the host. The returned purge response includes read commands CE000, CE001, CE002, CF000, CF001, CF002 as purge commands (Yes in step 401).

In this case, it corresponds to the CH progress management unit 1204-14 of the command progress management unit 1204 corresponding to the channel 14 to which the read command CE000, CE001, CE002 is input, and the channel 15 to which the read command CF000, CF001, CF002 is input. The CH progress management unit 1204-15 of the command progress management unit 1204 updates the command progress information of channels 14 and 15 held by itself as follows. That is, the CH progress management units 1204-14 and 1204-15 update the command progress information (page number, plane-cluster number) of the channels of channels 14 and 15 so that the oldest position is shown (step 402). The oldest position corresponding to channels 14 and 15 is the position corresponding to the oldest purge command (unexecuted read command) CE000, CF000 (page 0, plane 0, cluster 0). In this case, the command progress information of channels 14 and 15 is updated to "000".

Further, in step 402, the CH progress management units (other CH progress management units) other than the CH progress management units 1204-14 and 1204-15 in the command progress management unit 1204 obtain the command progress information held by themselves as follows. Update to show location. Here, the other CH progress management unit updates the command progress information to "003" so that (page 0, plane 1, cluster 1) is shown, as is clear from FIG. Further, in step 402, the command progress management unit 1204 acquires the physical NAND cluster address for each channel based on the physical block ID acquired in step 302 and the current command progress information for each channel in the same manner as in step 303. To do.

In step 402, the command generation unit 1206 specifies read access to the position (page, plane, cluster) indicated by the physical NAND cluster address acquired by the command progress management unit 1204 for each channel in the same manner as in step 303. Generate 16 read commands. In step 402, the command generator 1206 simultaneously issues up to 16 generated read commands to the NAND interface 1201. In the example of FIG. 6, it is shown that 16 read commands C0003, C1003, ..., CE000, CF000 were issued at time t4. When step 402 is completed, the self-diagnosis process returns to step 304.

Next, it is assumed that the purge command is not included in the parsed command response (No in step 401). In this case, the command progress management unit 1204 increments the plane-cluster number s of the command progress information of channels 0 to 15 held by the command progress management unit 1204 (step 403). That is, the command progress management unit 1204 advances the command progress to the next position. In step S403, if the plane-cluster number s before the update is 3, the plane-cluster number s is set to 0. The plane-cluster number s is updated as 0 1 2 3 0.

Next, the command progress management unit 1204 determines whether one logical page has been completed for each channel based on the updated command progress information of channels 0 to 15 (step 404). Here, for example, if the plain-cluster number s of the command progress information of channel i is 0, one logical page for channel i (more specifically, all clusters corresponding to channel i in one logical page) is completed. It is judged.

If one logical page is not completed in any channel (No in step 404), the self-diagnosis process returns to step 303. In this step 303, as a result of executing step 403, the progress management unit 1203 determines whether the position indicated by the command progress information for each channel indicates the final cluster on the final page. The progress management unit 1203 holds the judgment result for each channel.

On the other hand, if one logical page is completed on any channel, for example channel i (Yes in step 404), the self-diagnosis process proceeds to step 405. In step 405, the command progress management unit 1204 increments the page number of the command progress information of the channel i for which one logical page is completed. That is, the command progress management unit 1204 advances the command progress of channel i to the next logical page. Here, since the plane-cluster number s was set to 0 in the most recent step 403, the command progress for channel i updated in step 405 indicates the first cluster on the next logical page. When step 405 is completed, the self-diagnosis process proceeds to step 408.

Next, the case where the ICP correction of the logical page j is successful (Yes in step 309) will be described. It is assumed that this ICP correction was made because an ECC error occurred in the access according to the read command submitted to channel i. In this case, the ICPCS management unit 1211 updates the ICP completion page bitmap to indicate the completion of the ICP correction on logical page j (step 406). Here, the bit j corresponding to the logical page j of the 64-bit length ICP completion page bitmap is set to 1 (ON state). Successful ICP correction of logical page j is equivalent to the normal completion of self-diagnosis processing of logical page j for all channels 0 to 15.

Therefore, when the ICP completion page bitmap is updated (step 406), the command progress management unit 1204 sets at least the command progress of channel i at the beginning of the logical page j + 1 next to the logical page j that succeeded in ICP correction. Proceed to the cluster (step 407). That is, the command progress management unit 1204 skips the logical page j at least regarding the command progress of channel i. In step 407, the command progress management unit 1204 also advances the command progress indicating that the logical page j is being processed among the command progresses of the remaining channels to the first cluster of the logical page j + 1. When step 407 ends, the self-diagnosis process proceeds to step 408 as if step S405 ended.

In step 408, the progress control management unit 1203 determines whether the command progress has progressed to the final cluster in the read target logical block on all channels 0 to 15 based on the information held by itself for each channel. That is, the progress control management unit 1203 determines whether the corresponding final cluster in the read target logical block is the read target for all channels 0 to 15. If there is a channel for which the final cluster is not read target (No in step 408), the self-diagnosis process returns to step 303.

On the other hand, if the corresponding final cluster in the read target logical block is the read target on all channels 0 to 15 (Yes in step 408), the self-diagnosis process proceeds to step 409. In step 409, the progress control management unit 1203 determines whether the processing of the read target logical block is completed (step 409). For this determination, the progress control management unit 1203 returns a command response (hereinafter referred to as the final command response) from all channels 0 to 15 according to the access to the corresponding final cluster in the read target logical block. Inquire the response analysis unit 1209 to see if it is correct.

If the final command response (success response or error response) is not returned from at least one channel, the progress control management unit 1203 determines that the processing of the read target logical block is incomplete (No in step 409). In this case, the progress management unit 1203 executes step 409 again after a predetermined time, for example.

On the other hand, if the final command response is returned from all channels 0 to 15, the progress control management unit 1203 determines the completion of the processing of the read target logical block (Yes in step 409). In this case, the control unit 1202 determines whether the refresh flag is in the ON state (step 410). If the refresh flag is in the ON state (Yes in step 410), the control unit 1202 registers the logical block ID of the read target logical block in the compaction unit 1210 as the logical block to be compacted (step). 411). In step 411, the control unit 1202 switches the refresh flag from the ON state to the OFF state. As a result, the control unit 1202 ends the self-diagnosis process for one logical block. On the other hand, if the refresh flag is in the OFF state (No in step 410), the control unit 1202 skips step 411 and ends the self-diagnosis process for one logical block.

The details of the procedure of the self-diagnosis process applied in the present embodiment have been described above. The patrol process or the refresh process, which is autonomously performed by the NAND controller 2 of the memory device 10 shown in FIG. 1, can also be performed in the same manner as the self-diagnosis process.

As described above, in the NAND controller 2 of the memory device 10 shown in FIG. 1, the command progress management unit 1204 manages the command progress status for each channel. In addition, the ICPCS management unit 1211 manages the ICP correction completion status for each logical page of the logical block. According to the memory device 10 of the present embodiment provided with the command progress management unit 1204 and the ICPCS management unit 1211, it is possible to execute a large-capacity read process in units of logical blocks at a higher speed without waste than in the past. It will be possible.

Further, according to the present embodiment, it is possible to improve the performance of the self-diagnosis process, the patrol process, or the refresh process, which is indispensable for ensuring the reliability of the memory device 10 provided with the NAND flash memory 11. Further, according to the present embodiment, even when the usage load for each channel varies, it is possible to reduce the redundancy of the command to be re-entered when the purge occurs or the ICP correction occurs.

According to at least one embodiment described above, a memory device having a multi-channel and a memory access method in the device, which can execute memory access processing in block units at high speed by management using a small capacity memory area, are provided. can do.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 ... Memory device, 11 ... NAND flash memory (memory), 12 ... NAND controller, 1201 ... NAND interface (memory interface), 1201a ... purge mechanism, 1201b ... channel error Correction mechanism (ICP correction mechanism), 1202 ... Control unit, 1203 ... Progress control department, 1204 ... Command progress management department, 1204-0 ~ 1204-15 ... Channel-specific command progress management department ( CH progress management unit), 1205 ... command progress judgment unit, 1206 ... command generation unit, 1207 ... table management unit, 1207a ... theory conversion table, 1208 ... response storage unit, 1209. .. Response analysis department, 1210 ... Compaction department, 1211 ... Interchannel error correction status management department (ICPCS management department).