Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a static memory cell.

As the technology examined by the present inventor, for example, in a semiconductor device having a static memory cell, the following technology can be considered.

For example, in SRAM (Static Random Access Memory) in which a plurality of static memory cells are arranged in a matrix (matrix), the selection terminals of the memory cells are combined with word lines in each row direction, and the memory cells are combined. Data input / output terminals are coupled to complementary data lines (also called complementary bit lines) in each column direction. Each complementary data line is commonly connected to the complementary common data line via a Y-selection switch circuit that includes a plurality of column selection switches that are one-to-one coupled to the complementary data line. In such SRAM, the power supply voltage supplied to the memory cell array is constant.

Examples of the technology related to such a semiconductor device include the technologies described in Patent Documents 1 and 2 and Non-Patent Document 1.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 2005-108307</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 06-314491</text></patcit><nplcit num="1"><text>S. Obayashi, et al., "A 65nm SoC Embedded 6T 6-Transistor Eslam Design for Manufacturing With Read and Light Stabilizing Circuits (A 65nm SoC Embedded 6T) -SRAM Design for Manufacturing with Read and Write Stabilizing Circuits), 2006 Symposium on VLSI Circuits Digest of Technical Papers, 2006</text></nplcit>

<p num="0005"> By the way, as a result of the present inventor's examination of the above-mentioned semiconductor device technology, the following has been clarified.</p><p num="0006"> With the miniaturization of devices, the fluctuation of the local threshold voltage (Vth) of the transistors that make up the SRAM memory cell increases, achieving both SNM (Static Noise Margin) and write margin (Write Margin) of SRAM within the Vth management range. It's getting harder to get. Note that SNM refers to a margin (margin) that allows the data stored in the memory cell to be retained without being inverted when the data in the memory cell is read. The write margin is a margin that can be written by inverting the data stored in the memory cell when writing the data in the memory cell.</p><p num="0007"> FIG. 23 shows the relationship between SNM and the write margin. In FIG. 23, the vertical axis represents the yield and the horizontal axis represents the threshold voltage (Vth) of the transistor of the SRAM memory cell. As shown in FIG. 23, SNM and the write margin are in a trade-off relationship. That is, when the temperature becomes high, the threshold voltage becomes low and the SNM deteriorates, and when the temperature becomes low, the threshold voltage becomes high and the write margin deteriorates.</p><p num="0008"> In Non-Patent Document 1, a high level V of the word line potential is provided by an always-on n-type MOS transistor connected to the word line._WLA method for improving the SNM margin by lowering the power supply voltage VDD is introduced. Figure 24 shows the high level voltage V of the word line WL._WLThe waveform of is shown. As shown in FIG. 24, the high level voltage V of the word line WL_WLIs lower than the power supply voltage VDD by ΔV.</p><p num="0009"> However, if the word line potential is lower than the power supply voltage, the write margin deteriorates at the same time, so that the operating margin with respect to the threshold voltage (Vth) of the transistor cannot be sufficiently widened. Figure 25 shows the high level voltage V of the word line WL._WLShows the relationship between SNM and write margin when is lower than the power supply voltage VDD by ΔV. In FIG. 25, the vertical axis represents the yield and the horizontal axis represents the threshold voltage (Vth) of the transistor of the SRAM memory cell. The solid line is the high level voltage V of the word line WL._WLIf is VDD, the dashed line is the high level voltage V of the word line WL_WLIndicates the case where is VDD-ΔV. As shown in Figure 25, the high level voltage V of the word line WL_WLSNM is improved (yield is improved) by setting VDD-ΔV. However, at the same time, the write margin deteriorates (yield decreases).</p><p num="0010"> In Non-Patent Document 1, this is solved by lowering the VDD potential (AR VDD) of the memory cell in the write cycle.</p><p num="0011"> However, if the VDD potential of the memory cell is lowered too much, there is a risk that the retention margin of the inactive cell on the same column deteriorates. Further, since it is necessary to lower AR VDD to a potential that can secure a write margin and then raise AR VDD to VDD within the write cycle, there arises a problem that the cycle frequency deteriorates. Therefore, there is a limit to securing both SNM and write margin at the same time. </p><p num="0012"> Therefore, an object of the present invention is to provide a technique capable of simultaneously securing both SNM and write margin in a semiconductor device having a static memory cell.</p><p num="0013"> The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.</p><p num="0014"> Based on the results of the invention, the applicant has conducted a prior art search from the viewpoint of "a SRAM that uses a temperature sensor to secure SNM and a write margin at the same time and controls the output voltage of the word line driver by its output". Was done. As a result, the above-mentioned Patent Documents 1 and 2 were extracted.</p><p num="0015"> In Patent Document 1, the temperature T0 such that "output voltage of temperature detection circuit = output voltage of reference voltage generation circuit" is detected, and in the low temperature region below this temperature T0, the reference voltage Vref is generated by the variable potential generation circuit. The value of is lowered by an arbitrary voltage V from the external power supply Vdd, and this lowered voltage (Vdd- V) is supplied to the word line WL of the memory cell through the word line driver as a variable potential power supply Vcp. Have been described. Patent Document 1 aims to stabilize data during data retention (during deactivation), and raises the potential of the non-selected word line when the temperature rises during data retention.</p><p num="0016"> Patent Document 2 describes SRAM in which the operating range is expanded by controlling the memory cell voltage based on the detection result of the temperature sensor. Patent Document 2 is intended to stabilize data retention at low temperatures, and has not been studied when it is active.</p>

<p num="0017"> A brief overview of typical examples disclosed in the present application is as follows.</p><p num="0018"> That is, the semiconductor device according to the typical embodiment is a semiconductor device having a static memory cell. Then, based on the memory cell array in which a plurality of static memory cells are arranged in a matrix, the temperature sensor circuit that detects the temperature in the semiconductor device, and the output of the temperature sensor circuit during the writing or reading operation of the memory cells. It has a voltage control circuit that controls the voltage supplied to the memory cell array.</p>

<p num="0019"> According to a typical embodiment, the yield can be secured in a wide threshold voltage Vth fluctuation range.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiment, in principle, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted. Unless otherwise specified, the symbol representing the terminal name also serves as the wiring name and signal name, and in the case of a power supply, also serves as the voltage value.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. There is a relationship of some or all modifications, details, supplementary explanations, etc. In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the first embodiment of the present invention.

First, an example of the configuration of the SRAM module in the semiconductor device of the first embodiment will be described with reference to FIG. The semiconductor device according to the first embodiment is not particularly limited, but is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The SRAM module according to the first embodiment is, for example, a memory array 5 in which a plurality of static memory cells (MC) 1 are arranged in a matrix (matrix) and a selection terminal of the memory cell 1. A word driver 2 for driving the connected word lines WL0 to WLn, a row decoder 3, a control logic 4 for controlling the write / read operation of the SRAM module, and a column decoder ( It consists of a Column Decoder (11), a column switch (Column Switch) 12, a write amplifier (Write Amp) 13, a Sense amplifier (Sense Amp) 14, and a temperature sensor circuit 6 that detects the temperature inside the semiconductor device. ..

The selection terminal of the memory cell 1 is connected to the word lines WL0 to WLn in each row direction, and the data input / output terminal of the memory cell 1 is connected to the complementary bit line in each column direction. Each complementary bit wire is connected to a column switch 12.

The address selection signals AX and AY are input to the low decoder 3 and the column decoder 11 via the control logic 4, and are decoded. The output of the low decoder 3 is input to the word driver 2 and activates one of the word lines WL0 to WLn.

On the other hand, the output of the column decoder 11 is input to the column switch (Column Switch) 12 to conduct a pair of the plurality of complementary bit lines in the memory cell array 5 with the light amplifier 13 and the sense amplifier 14.

In the read cycle, the signal REN is activated to a high level, the signal RENMR is activated to a high level via the control logic 4, and the sense amplifier 14 is activated. The data read from the memory cell 1 selected by the word line WL is amplified by the sense amplifier 14 via the complementary bit line and the column switch 12, and is output as read data (Read Data).

The read cycle includes a period until the sense amplifier is activated, the read data from the memory cell is output from the sense amplifier, and the sense amplifier is deactivated.

Further, the time of reading includes a period in which the word line connected to the memory cell to be read is activated when reading data from the memory cell.

In the write cycle, the signal DIC is activated to a high level, the signal DICMR is activated to a high level via the control logic 4, and the write amplifier 13 is activated. The data input as write data (Write Data) from the outside is transmitted to the complementary bit line by the write amplifier 13 via the column switch 12, and is written to the memory cell 1 selected by the word line WL. Further, the output signal TCNT of the temperature sensor circuit 6 is input to the word driver 2 that drives the word line WL.

The write cycle includes a period until the write amplifier (write driver) is activated, data is written to the memory cell, and the write amplifier is deactivated.

Further, the time of writing includes a period in which the word line connected to the memory cell to be written is activated when data is written to the memory cell.

FIG. 2 is a circuit diagram showing a configuration example of the word driver 2 shown in FIG. 1, and FIG. 3 is a high level voltage V of the word line WL which is the output of the word driver 2._WLIt is a figure which shows the temperature characteristic of.

When the corresponding word driver 2 is selected by the low decoder 3, the signal WS becomes low level, the n-type MOS transistor Mn1 is turned off, and the word line WL is raised to a high level by the p-type MOS transistor Mp1. At this time, if the signal TCNT is selected to a high level, the high level of the word line WL becomes a voltage (VDD-ΔV) lower than the power supply voltage VDD due to the current attraction of the p-type MOS transistor Mp1 and the n-type MOS transistor Mn2. ..

The temperature sensor circuit 6 has a characteristic that the signal TCNT becomes a low level (TCNT = L) at a low temperature and the signal TCNT becomes a high level (TCNT = H) at a high temperature. Therefore, as shown in FIG. 3, the high level voltage V of the word line WL_WLIs V at low temperatures_WL= VDD, V at high temperature_WLIt has the characteristic that = VDD-ΔV.

FIG. 4 is a circuit diagram showing an example of the configuration of the temperature sensor circuit 6 shown in FIG. 1, and FIG. 5 is a diagram showing the temperature characteristics of the output signal TCNT of the temperature sensor circuit 6.

As shown in FIG. 4, the temperature sensor circuit 6 includes a temperature sensor unit 61, a Schmitt trigger circuit 62, and the like. The temperature sensor unit 61 is composed of a differential amplifier 63, a current source 64, bipolar transistors Q1 and Q2, resistors R1 to R4, and the like.

The temperature sensor unit 61 amplifies the VBE voltage of the two stages of the bipolar transistors Q1 and Q2 by the differential amplifier 63, so that the output voltage VOUT becomes high at low temperature and low at high temperature as shown in FIG. It is possible to have a temperature gradient. The gradient of the output voltage VOUT and the temperature at which the output voltage VOUT intersects the reference voltage VREF can be achieved by appropriately setting the values of the resistors R1 to R4.

Since the output (signal TCNT) of the temperature sensor circuit 6 is distributed to a plurality of memory modules, it is convenient to convert an analog signal such as an output voltage VOUT to a digital signal level in consideration of noise immunity. Therefore, the Schmitt trigger circuit 62 converts the analog level output voltage VOUT into a digital signal TCNT. In the Schmitt trigger circuit 62, the threshold temperature at which the digital signal TCNT switches from low level (L) to high level (H) when the temperature changes from low temperature to high temperature is T2, and the signal TCNT changes from high level (H) when the temperature changes from high temperature to low temperature. A Schmitt trigger circuit having a hysteresis characteristic such that the threshold temperature for switching to the low level (L) is T1 is used. This is intended to prevent an increase in power consumption and noise due to frequent switching between high (H) and low (L) of the signal TCNT when the temperature is just near the judgment level.

Thus, the high level voltage V of the word line WL_WL, V at high temperature_WLSince = VDD-ΔV can be set, as shown in FIG. 6, the temperature characteristics of SNM can be compensated. Therefore, as shown in FIG. 8, the range of the threshold voltage Vth that can secure the yield is expanded. Is possible.

FIG. 6 shows the threshold voltage Vth of the n-type MOS transistor (Access-MOS, Driver-MOS) constituting the 6Tr-SRAM and the SRAM yield due to SNM in the first embodiment. In FIG. 6, the vertical axis shows the yield (SNM), and the horizontal axis shows the threshold voltage (Vth) of the transistor of the SRAM memory cell. Also, 101 is the high level voltage V of the word line WL._WLIf is VDD and the temperature is -40 degrees, 102 is the high level voltage V of the word line WL._WLIs VDD and the temperature is 125 degrees, 103 is the high level voltage V of the word line WL_WLIs VDD-ΔV and the temperature is 125 degrees.

In SNM, the higher the threshold voltage Vth of the n-type MOS transistor in the memory cell, the larger the margin and the higher the yield. Similarly, SNM has the property that the margin becomes smaller and the yield decreases at high temperatures (101 102). In the first embodiment, the high level voltage V of the word line WL when the temperature becomes high due to the output (signal TCNT) of the temperature sensor circuit 6._WLDecreases from VDD by ΔV (102 103). SNM is V_WLThe lower the value, the better the margin, so it is possible to compensate for the deterioration of SNM due to temperature characteristics.

FIG. 7 shows the threshold voltage Vth of the n-type MOS transistor constituting the 6Tr-SRAM and the SRAM yield due to the write margin in the first embodiment. In FIG. 7, the vertical axis shows the yield (write margin), and the horizontal axis shows the threshold voltage (Vth) of the transistor of the SRAM memory cell. Also, 201 is the high level voltage V of the word line WL._WLWhen is VDD-ΔV and the temperature is 125 degrees, 202 is the high level voltage V of the word line WL._WLIf is VDD-ΔV and the temperature is -40 degrees, 203 is the high level voltage V of the word line WL._WLIs VDD and the temperature is -40 degrees.

The write margin has characteristics that conflict with SNM. That is, the lower the threshold voltage Vth of the n-type MOS transistor, the larger the margin and the higher the yield. Similarly, as the light margin becomes lower, the margin becomes smaller and the yield decreases (201 202). Due to the output (signal TCNT) of the temperature sensor circuit 6, when the temperature becomes low, the high level voltage V of the word line WL_WLReturns from VDD-ΔV to VDD (202 203), so it is possible to compensate for the deterioration of the margin due to the temperature characteristics even for the write margin.

FIG. 8 is a diagram showing the SRAM yield with respect to the threshold voltage Vth of the n-type MOS transistor, which is the sum of the SNM and the write margin. Due to the temperature sensor circuit, V at high temperature_WLIs automatically adjusted from VDD to VDD-ΔV, so it is possible to expand the Vth range in which the yield can be secured.

(Embodiment 2) FIG. 9 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the second embodiment of the present invention, and FIG. 10 is a circuit diagram showing a configuration example of the word driver 2 shown in FIG.

In the second embodiment, in addition to the output of the temperature sensor circuit 6, a signal due to the blow / uncut of the fuse (FUSE) 7 is input to the word driver 2.

The signal TCNT &lt;0&gt; is the output signal of the temperature sensor circuit 6, and the signal TCNT &lt;1&gt; is the blow signal of the fuse 7. These signals are transmitted to the word driver 2, and the respective signals TCNT &lt;0&gt; and TCNT &lt;1&gt; are input to the gates of the n-type MOS transistors Mn2 and Mn3 connected to the word line WL. For example, the fuse 7 evaluates the threshold voltage Vth of the access MOS transistor (Access MOS) for each chip by a monitor circuit prepared inside the chip at the time of wafer test, and blows the fuse 7 when the threshold voltage Vth is lower than the reference. The signal TCNT &lt;1&gt; is fixed at a high level.

As a result, it is possible to improve the SNM of chips having low Vth and variation in the wafer, and it is possible to improve the SRAM yield in the wafer. Since this can be performed independently of the compensation of the temperature characteristics by the temperature sensor circuit, it is possible to secure the yield in a wide Vth range together with the yield improvement described in the first embodiment.

Further, in the configuration of FIG. 9, the output signal TCNT of the temperature sensor circuit 6 is once synchronized by the clock CK in the flip-flop in the SRAM module 10. Since the fluctuation of the signal TCNT due to the temperature fluctuation is asynchronous to the clock, if it is input to the word driver 2 as it is, the high level of the word line may change during the high level period of the word line WL, and the circuit It may make design and tester evaluation difficult. By synchronizing the signal TCNT with the clock CK, it becomes possible to handle it in the same way as the address selection signals AX, AY, etc.

(Embodiment 3) FIG. 11 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the third embodiment of the present invention, and FIG. 12 is a circuit diagram showing a configuration example of the word driver 2 and the driver power supply circuit 8 shown in FIG. Is.

In the configuration example of FIG. 11, the signal TCNT &lt;1: 0&gt; is input to the driver power supply circuit 8, and the power supply voltage VDDR is supplied as the power supply for the word driver 2. The voltage level of the power supply voltage VDDR output from the driver power supply circuit 8 is determined by the current inquiries of the p-type MOS transistors Mp1 and the p-type MOS transistors Mp2 and Mp3 selected by the signal TCNT &lt;1: 0&gt;. Since the high level of the word line WL is the power supply voltage VDDR of the word driver 2, the word is generated by the output of the temperature sensor circuit 6 and the blow signal of the fuse (FUSE) 7 as in the configuration example of FIG. 9 in the second embodiment. It is possible to change the high level voltage of the line WL.

(Embodiment 4) FIG. 13 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the fourth embodiment of the present invention, and FIG. 14 is a circuit diagram showing a configuration example of the word driver 2 and the driver power supply circuit 8 shown in FIG. , Fig. 15 shows the output voltage VOUT of the temperature sensor unit 61 and the high level voltage V of the word line WL._WLIt is a figure which shows the temperature characteristic of.

In the configuration example of FIG. 13, instead of the output signal TCNT of the CMOS level temperature sensor circuit 6 of FIG. 1, the output voltage VOUT of the analog level temperature sensor unit 61 is directly input to the driver power supply circuit 8. The temperature sensor unit 61 is a pre-stage portion of the temperature sensor circuit 6 shown in FIG. 4, and has a temperature characteristic such that the output voltage VOUT is high at a low temperature and low at a high temperature as shown in FIG. The VOUT is input to the gate of the p-type MOS transistor Mp2 of the word driver 2 in Fig. 14, and the output voltage VOUT decreases at high temperatures, so the current driving force of the p-type MOS transistor Mp2 increases, and the p-type MOS transistor Mp1 It is possible to lower the level of the power supply voltage VDDR, which is determined by the inquiry of the current with. When one temperature sensor unit can be mounted on one memory cell array, more accurate temperature compensation can be obtained as compared with the configuration example of FIG.

(Embodiment 5) FIG. 16 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the fifth embodiment of the present invention, FIG. 17 is a waveform diagram showing a writing operation to a memory cell using a write assist circuit, and FIG. 18 is a waveform diagram. , Is an enlarged view of FIG.

FIG. 16 shows a configuration example using the temperature sensor circuit 6 output for adjusting the write assist level of the memory array 5. FIG. 17 shows a write operation to a memory cell using the write assist circuit (Write Assist) 16.

The column selection signal YS0 that decodes the Y address goes high, and one side (DT) of the bit line pair of the selected memory cell array is lowered to low level by the write amplifier 13 via the column switch 12. At the same time, the word line signal WL0 whose X address is decoded becomes high level and inverts the internal node of the selected memory cell 1. At this time, the source voltage AR VDD of the p-type MOS transistor of the memory cell 1 is reduced to VDD-ΔVAR VDD by the write assist circuit 16. In the write assist circuit 16, the write enable signal WICMR becomes high level at the same time as the column selection signal YS0, and ARVDD0 is lowered, and ARVDD is lowered by turning on the p-type MOS transistor MP3. It stays at the level determined by the threshold voltage Vth of the p-type MOS transistors MP3 and MP4 of the write assist circuit 16.

By lowering AR VDD during the write operation in this way, the on-current of the p-type MOS transistor of the memory cell 1 becomes weaker, so that stable writing is performed to the memory cell 1 even when the threshold voltage Vth of the n-type MOS transistor is high. be able to. However, on the other hand, if AR VDD is lowered too much, there are side effects. In addition to the memory cell where the write operation is performed, other memory cells that are not accessed are connected to AR VDD, but if AR VDD drops too low, data corruption in the memory cell called data retention failure occurs. ..

The lower limit voltage of AR VDD at which such data retention failure occurs becomes higher as the temperature rises. Therefore, if ΔVAR VDD is increased at low temperature when the write margin is small and ΔVAR VDD is decreased at high temperature when the retention failure margin is small, both write and data retention margins can be achieved at the same time. In order to realize this, the threshold voltage Vth of the p-type MOS transistor MP5 is made low, the threshold voltage Vth of the p-type MOS transistor MP4 is made high, and the temperature sensor circuit 6 in which TCNT = L at low temperature is used as the p-type MOS transistor. Connect to the MP5 gate. Since AR VDD is determined by the threshold voltage Vth of the p-type MOS transistor MP5 at low temperature and ARVDD is determined by the threshold voltage Vth of the p-type MOS transistor MP4 at high temperature, ΔVAR VDD should be large at low temperature and ΔVARVDD should be small at high temperature as described above. Is possible.

(Embodiment 6) FIG. 19 is a block diagram showing a configuration example of a SRAM module in the semiconductor device according to the sixth embodiment of the present invention, and FIG. 20 is a circuit diagram and a diagram showing a configuration example of the step-down circuit (2) 17 shown in FIG. 21 is a diagram showing the temperature characteristics of the output voltage VDD1 of the step-down circuit (2) 17.

FIG. 19 shows another configuration example in which the word line voltage is changed by the temperature sensor circuit 6. The power supply voltage VDD supplied to the semiconductor device is stepped down to VDD-ΔV by the step-down circuit (1) and supplied as the power supply for each gate including the memory cell array, but the temperature sensor circuit 6 is used for the word driver 2. This is a configuration example in which VDD1 stepped down by the controlled step-down circuit (2) 17 is supplied as a power source.

Here, as shown in FIG. 21, the output TC of the temperature sensor circuit 6 is a 3-bit signal that switches in three stages of {011} {101} {110} within the temperature compensation range Tmin to Tmax of the semiconductor device. In the step-down circuit (2) 17 shown in FIG. 20, the output TC switches the voltage VR0 that divides the resistance from VDD1 and feeds it back to the differential amplifier. Since the differential amplifier adjusts the output voltage VDD1 so that VR0 and VR are equal, VDD1 is set high when the output TC is &lt;011&gt;, and VDD1 is lowered when the output TC is &lt;110&gt;.

On the other hand, the step-down circuit (1) has the same configuration as that of FIG. 20, and &lt;101&gt; is always selected. As a result, the high level (= VDD1) of the word line WL of the word driver 2 is higher than VDD-ΔV at low temperature and lower than VDD-ΔV at high temperature. Unlike the configuration example of FIG. 11 of the third embodiment, the word line voltage can be not only made lower than that of the memory cell array but also made higher than that of the memory cell array, so that it is possible to design a wider operating margin.

(Embodiment 7) FIG. 22 is a block diagram showing a configuration example of a SOC including a plurality of SRAM modules in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 22 shows a configuration example in which the present invention is applied to SOC (System On a Chip) 15. Normally, SOC has multiple memory modules with different capacities in the chip. The SOC 15 according to the seventh embodiment is equipped with a plurality of SRAM modules 10 described in the first to sixth embodiments. In FIG. 22, module1, module2, and module5 are large-capacity SRAM modules, module3 is a medium-capacity SRAM module, and module4 is a small-capacity SRAM module. These SRAM modules are a type of memory module. The memory module has a memory cell array composed of a plurality of memory cells, a sense amplifier, a driver, a decoder, other peripheral circuits, and the like, and functions independently as a memory.

As the memory capacity increases, it is more likely that SRAM memory cells with a large variation in threshold voltage Vth exist. Therefore, in a large-capacity module, the temperature sensor circuit 6 and the fuse 7 blown according to the Vth finish are used together to achieve a yield. It is necessary to secure it. On the other hand, the medium capacity module 3 can secure the yield only by the temperature sensor circuit 6, and the small capacity module 4 does not require a fuse or a temperature sensor circuit. In this way, the temperature sensor circuit 6 and the fuse 7 can be used properly according to the memory capacity of the memory module, and the memory module design can be facilitated.

In addition, module 5 is placed in a remote location in the chip with respect to other modules, but the temperature distribution in the chip may not be uniform, especially for products with a large die size. Therefore, a plurality of temperature sensor circuits 6 are mounted on the chip, and the memory module (module 5) uses the output of the temperature sensor circuit 6 closer to the chip.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

Therefore, for example, a part or all of each of the plurality of embodiments may be combined as appropriate.

The present invention is effective for a synchronous semiconductor memory equipped with a SRAM memory, and is particularly effective for a single SRAM product, a SOC product, and the like.

<figref num="1">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 1 of this invention.</figref><figref num="2">It is a circuit diagram which shows the configuration example of the word driver shown in FIG.</figref><figref num="3">In the semiconductor device according to the first embodiment of the present invention, the high level voltage V of the word line WL which is the output of the word driver._WLIt is a figure which shows the temperature characteristic of.</figref><figref num="4">It is a circuit diagram which shows the structural example of the temperature sensor circuit shown in FIG.</figref><figref num="5">It is a figure which shows the temperature characteristic of the output signal TCNT of the temperature sensor circuit in the semiconductor device by Embodiment 1 of this invention.</figref><figref num="6">It is a figure which shows the threshold voltage Vth of the n-type MOS transistor which constitutes 6Tr-SRAM, and the SRAM yield which is caused by SNM in the semiconductor device by Embodiment 1 of this invention.</figref><figref num="7">It is a figure which shows the threshold voltage Vth of the n-type MOS transistor which constitutes 6Tr-SRAM, and the SRAM yield which is caused by the write margin in the semiconductor device according to Embodiment 1 of this invention.</figref><figref num="8">It is a figure which shows the SRAM yield with respect to the threshold voltage Vth of the n-type MOS transistor which combined SNM and write margin in the semiconductor device by Embodiment 1 of this invention.</figref><figref num="9">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 2 of this invention.</figref><figref num="10">It is a circuit diagram which shows the configuration example of the word driver shown in FIG.</figref><figref num="11">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 3 of this invention.</figref><figref num="12">It is a circuit diagram which shows the structural example of the word driver and the driver power supply circuit shown in FIG.</figref><figref num="13">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 4 of this invention.</figref><figref num="14">It is a circuit diagram which shows the structural example of the word driver and the driver power supply circuit shown in FIG.</figref><figref num="15">In the semiconductor device according to the fourth embodiment of the present invention, the output voltage VOUT of the temperature sensor unit and the high level voltage V of the word line WL_WLIt is a figure which shows the temperature characteristic of.</figref><figref num="16">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 5 of this invention.</figref><figref num="17">FIG. 5 is a waveform diagram showing a write operation to a memory cell using a write assist circuit in the semiconductor device according to the fifth embodiment of the present invention.</figref><figref num="18">It is an enlarged view of FIG.</figref><figref num="19">It is a block diagram which shows the structural example of the SRAM module in the semiconductor device according to Embodiment 6 of this invention.</figref><figref num="20">It is a circuit diagram which shows the structural example of the step-down circuit (2) shown in FIG.</figref><figref num="21">It is a figure which shows the temperature characteristic of the output voltage VDD1 of the step-down circuit (2) in the semiconductor device according to Embodiment 6 of this invention.</figref><figref num="22">FIG. 5 is a block diagram showing a configuration example of a SOC including a plurality of SRAM modules in the semiconductor device according to the seventh embodiment of the present invention.</figref><figref num="23">It is a figure which shows the relationship between SNM and a write margin examined as the premise of this invention.</figref><figref num="24">It is a figure which shows the waveform of the high level voltage of a word line examined as the premise of this invention.</figref><figref num="25">It is a figure which shows the relationship between SNM and write margin when the high level voltage of a word line is lower than power supply voltage VDD by ΔV, which was examined as the premise of this invention.</figref>

Code description

1 Memory cell (MC) 2 word driver 3 Row Decoder 4 Control Logic 5 Memory Array 6 Temperature sensor circuit 7 FUSE 8 Driver power circuit 10 SRAM module 11 Column Decoder 12 Column Switch 13 Write Amp 14 Sense Amp 15 SOC (System On a Chip) 16 Write Assist Circuit 17 Step-down circuit (2) 61 Temperature sensor 62 Schmitt trigger circuit 63 Differential amplifier 64 current source AX, AY address selection signal CK clock Mn1 ~ Mn3 n-type MOS transistor Mp1 ~ Mp3, MP3 ~ MP5 p-type MOS transistors Q1, Q2 Bipolar transistor R1 ~ R4 resistors VOUT output voltage VREF reference voltage V_WLHigh level voltage of word line WL WL word line YS0 column selection signal