Technique and apparatus for depositing thin layers of semiconductors for solar cell fabricaton

0001Cross-reference to related applications This application claims the interests of earlier US Provisional Application No. 60 / 552,736 filed on March 15, 2004, which is incorporated herein by reference.

0002Field of invention The present invention relates to methods and devices for preparing semiconductor thin films for electromagnetic wave detectors and photoelectric conversion applications.

0003background A solar cell is a photoelectric conversion device that directly converts sunlight into electric power. The most common solar cell material is silicon in the form of single crystal or polycrystalline wafers. However, the cost of electricity generated by using silicon-based solar cells is higher than the cost of electricity generated by more traditional methods. Therefore, since the early 1970s, efforts have been made to reduce the cost of solar cells for use on the ground. One way to reduce the cost of solar cells is to develop low-cost thin-film growth methods that can deposit solar-quality absorbent materials on large-area substrates, and use these devices with high productivity and low-cost methods. To manufacture.

0004Group IBIIIAVIA (Cu, Ag, Au), Group IIIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table. Compound semiconductors are a good absorbent material for thin-film solar cell structures. In particular, CIGS (S), ie Cu (In, Ga) (S, Se)₂Or CuIn_1-xGa_x(S_ySe_1-y)_kThe compounds of Cu, In, Ga, Se and S commonly referred to (in the formula, 0 x 1, 0 y 1 and k is approximately 2) provide conversion efficiencies up to 20%. It has been used in solar cell structures so far. Absorption layers containing Group IIIA elements Al and / or Group VIA elements Te also demonstrated confirmation. Therefore, in summary, compounds containing at least one of i) Cu from Group IB, ii) In, Ga and Al from Group IIIA and iii) at least one of S, Se and Te from Group VIA are solar. It is of great interest to battery applications.

0005Cu (In, Ga, Al) (S, Se, Te)₂The structure of a conventional IBIIIAVIA group compound photoelectric cell such as the thin film solar cell of is shown in FIG. The device 10 is manufactured on a substrate 11 such as a sheet of glass, a metal sheet, an insulating foil or web, or a conductive foil or web. Cu (In, Ga, Al) (S, Se, Te)₂The absorbent membrane 12, which contains the materials in the family of, is already deposited on the substrate 11 and grows on the conductive layer 13 which acts as an electrical contact to the device. Various conductive layers, including Mo, Ta, W, Ti and stainless steel, are used in the solar cell structure of FIG. It is possible not to use the conductive layer 13 if the substrate itself is a properly selected conductive material. This is because the substrate 11 can then be used as an ohm contact with the device. After the absorption film 12 grows, a transparent layer 14 such as a CdS, ZnO or CdS / ZnO stack is formed on the absorption film. Electromagnetic waves 15 enter the device through the transparent layer 14. A metal grid (not shown) can also be deposited on the lucidum 14 to reduce the effective series resistance of the device. The preferred conductive type of the absorbing film 12 is p-type, and the preferred conductive type of the transparent layer 14 is n-type. However, n-type absorbent layers and p-type window layers can also be used. The preferred device structure of FIG. 1 is referred to as the "substraight" structure. The "super straight" structure also deposits a transparent conductive layer on a transparent super straight, such as glass or clear polymer foil, followed by Cu (In, Ga, Al) (S, Se, Te).₂It can be constructed by depositing an absorbent membrane and finally forming ohm contacts with the device by a conductive layer. In this super straight structure, light enters the device from the transparent super straight side. Different materials deposited by different methods can be used to provide different layers of the device shown in FIG.

0006For thin-film solar cells with IBIIIAVIA group compound absorption layers, battery efficiency is a clear function of the molar ratio of IB / IIIA. If more than one Group IIIA material is present in the composition, the relative or molar ratios of those IIIA elements also affect the properties. For example, Cu (In, Ga) (S, Se)₂For the absorbent layer, device efficiency is a function of the molar ratio of Cu / (In + Ga). In addition, some of the battery's key parameters such as open circuit voltage, short circuit current and fill factor change with the molar ratio of element IIIA, the Ga / (Ga + In) molar ratio. In general, the Cu / (In / + Ga) molar ratio is kept around 1.0 or below for good device performance. On the other hand, as the molar ratio of Ga / (Ga + In) increases, the optical bandgap of the absorption layer increases, thus increasing the open circuit voltage of the solar cell while typically decreasing the short circuit current. Can be done. It is important that the thin film deposition process has the ability to control both the molar ratio of IB / IIIA and the molar ratio of Group IIIA components in the composition. The chemical formula is often Cu (In, Ga) (S, Se)₂Although described as, the more accurate formula for the compound is Cu (In, Ga) (S, Se)._kNote that (in the equation, k is typically close to 2 and does not have to be exactly 2.). For simplicity, the inventor will continue to use the value of k as 2. Furthermore, the indication "Cu (X, Y)" in the chemical formula indicates all the chemical compositions of X and Y from (X = 0% and Y = 100%) to (X = 100% and Y = 0%). Please note that it means. For example, Cu (In, Ga) means all compositions from CuIn to CuGa. Similarly, Cu (In, Ga) (S, Se)₂Means the entire family of compounds having a molar ratio of Ga / (Ga + In) varying from 0 to 1 and a molar ratio of Se / (Se + S) varying from 0 to 1.

0007High quality Cu (In, Ga) Se for solar cell manufacturing₂The first technique to provide a film was the co-deposition of Cu, In, Ga and Se on a heated substrate in a vacuum chamber. However, low material utilization, high equipment costs, difficulties faced with large area deposition, and relatively low throughput are some of the challenges faced in the commercialization of co-deposition methods.

0008Cu (In, Ga) (S, Se) for solar cell applications₂Another technique for growing thin films of type compounds is Cu (In, Ga) (S, Se).₂It is a two-step process in which the metallic components of the material first deposit on the substrate and then react with S and / or Se in a high temperature annealing process. For example, CuInSe₂For growth, a thin layer of Cu and In is first deposited on the substrate, then this stack precursor layer reacts with Se at high temperatures. If the reaction atmosphere also contains sulfur, then CuIn (S, Se)₂Layers can grow. The addition of Ga to the precursor layer, i.e. the use of Cu / In / Ga stack membrane precursors, is Cu (In, Ga) (S, Se).₂Allows the growth of the absorption layer.

0009Sputtering and deposition techniques have been used in the prior art method to deposit layers containing Group IB and Group IIIA components of precursor stacks. For example, CuInSe₂In the case of growth, the Cu and In layers are sequentially sputtered and deposited on the substrate, as described in US Pat. No. 4,798,660, after which the stack film typically takes about 30 minutes or more. It was heated at high temperature for a long time in the presence of a gas containing Se. More recently, US Pat. No. 6,048,442 sputters and deposits a stack precursor film containing a Cu-Ga alloy layer and an In layer to form a Cu-Ga / In stack on a metal back electrode layer and then absorbs it. A method comprising reacting the precursor stack film with one of Se and S to form a layer is disclosed. U.S. Pat. No. 6,092,669 describes a sputtering apparatus for producing such an absorbent layer. While such techniques can result in good quality absorbent layers and efficient solar cells, they have the disadvantage that the main equipment is expensive and relatively slow to manufacture.

0010One prior art method described in US Pat. No. 4,581,108 utilizes a low cost electrodeposition method for the production of metal precursors. In this method, the Cu layer is first electrically deposited on the substrate. This is followed by electrodeposition of the In layer and heating of the deposited Cu / In stack in a reaction atmosphere containing Se. Although inherently low cost, this technology has poor adhesion to Mo contact layers CuInSe₂It is known to produce a membrane. In one publication ("Low Cost Thin Film Charcopilite Solar Cell", Bulletin of the 18th IEEE Photoelectric Conversion Experts Conference, 1985, p. 1429), electrodeposition of Cu / In and Cu / In / Ga layers And seleniumization is illustrated for CIS and CIGS growth. One problem has been identified as peeling of compound films during solar cell manufacturing. Later, according to another reference (Low Cost Methods for Manufacturing Semiconductor Films for CIS / CdS Solar Cells, Solar Cells, Vol. 21, p. 65, 1987), researchers Mo / CuInSe obtained by the above method₂Study the cross section of the interface and its CuInSe₂Has found poor adhesion to the Mo contact layer.

0011Regardless of the special method used in the two-step process, for example Cu (In, Ga) (S, Se)₂The growth of the absorbent film, the individual thickness of the layers forming the metal stack structure, is the above-mentioned two molar ratios, that is, the Cu / (In + Ga) ratio and the Ga / (Ga + In) ratio are large areas during operation. It needs to be controlled so that it can be kept under control on the substrate. If the reaction temperature is maintained below about 600 ° C, the molar ratio achieved with the metal stack structure is generally conserved on a macroscopic scale during the reaction phase. Therefore, the total molar ratio or the average molar ratio of the compound film obtained after the reaction step is substantially the same as the average molar ratio in the metal stack structure before the reaction step. In the prior art method, all Cu, In and / or Ga required for the final desired molar ratio deposit S and / or Se on the substrate prior to the reaction step. In other words, for example, Cu_0.8In_0.8Ga_0.2Se_xTo grow (where x is close to 2 in the equation), the prior art typically deposits a Cu / In / Ga stack, an In / Cu / Ga stack or a Cu-Ga / In stack. At this time, the Cu / (In + Ga) molar ratio of the stack is 0.8, and the Ga / (Ga + In) molar ratio of the stack is 0.2. The metal stack is then selenate at high temperatures to form a compound. One problem associated with such methods is that their precursors are relatively thick (500-1500 nm) and typically groups of In and Ga with low melting points of about 156 ° C and 30 ° C, respectively. It is rich in IIIB components, and they cause the microscopic heterogeneity described below.

0012Figures 2a-2c show the problem of microscopic heterogeneity that may be present in metal precursor layers, especially those with IB / IIIA molar ratios of 1 or less. Figure 2a schematically shows a typical Cu / In / Ga metal stack with a typical total molar ratio of Cu / (In + Ga) = 0.8 and Ga / (Ga + In) = 0.2 on the substrate. Shown. In this method, the contact film 21 is first deposited on the substrate 20 forming the substrate 22. The Cu layer 23 is then deposited on the contact membrane 21. The thickness of the Cu layer 23 can be, for example, about 200 nm. This Cu thickness and the desired molar ratio described require the deposition of an In layer with a thickness of about 440 nm and a Ga layer with a thickness of about 80 nm. These calculations can be made assuming that the densities of Cu, In and Ga are 8.96 g / cc, 7.31 g / cc and 5.91 g / cc, respectively, and the atomic weights are 63.54 g, 114.76 g and 69.72 g, respectively. Cu_0.8In_0.8Ga_0.2Se_1.9Using a density value of 5.75 g / cc and a molar weight of 306.66 grams for the selenium compound, the metal precursor in this example would result in a CIGS layer with a thickness of approximately 1880 nm, assuming 100% density. It is calculated. The optimum thickness of the CIGS layer for thin-film solar cell applications is in the range of 500 to 5000 nm, preferably 700 to 2000 nm, and is preferably thinner because it reduces material costs.

0013Returning to FIG. 2a, the deposition of Cu layer 23 with a thickness of about 200 nm is followed by the deposition of In layer 24 with a nominal thickness of 440 nm and Ga layer 25 with a thickness of 80 nm. The Cu layer 23 of the resulting metal precursor stack 26 is shown smooth and uniform, while the In and Ga layer surfaces are shown non-smooth. Although the surface morphology of these layers strongly depends on the deposition technique used, low melting point metals such as In and Ga are "ball-shaped" when deposited in thin film morphology, especially when deposited on top of each other. It is generally true that there is a tendency to "become". Note that the melting point of the (Ga + In) mixture is below the melting point of In, which is approximately 156 ° C.

0014The metal precursor layer 26 of FIG. 2a may have the desired Cu / (In + Ga) and Ga / (Ga + In) molar ratios in a broad sense or macroscopically. However, on a microscopic scale, the situation is quite different from what can be observed in FIG. 2b, which shows an enlarged view of region 27 in FIG. 2a. The local Cu / (In + Ga) ratio is point "B" because the In layer thickness "t1" at point "A" and its surroundings is much larger than the In layer thickness "t2" at point B. And its surroundings are much smaller than the point "A" and its surroundings. Furthermore, the Ga / (Ga + In) ratio also differs at these two points. That is, it is larger at point B than at point A. After the reaction step with Se, their microscopic heterogeneity of the molar ratio of metal components is mostly transferred to the compound, which is not due to changes in Cu / (In + Ga) and Ga / (Ga + In) ratios. It should be understood that it results in a CIGS layer with uniform compositional changes. This situation is schematically shown in FIG. 2c, which illustrates compound layer 29 obtained by reacting the precursor stack of FIG. 2b with Se. Region R1 in FIG. 2c roughly corresponds to the region around point A in FIG. 2b, and region R2 roughly corresponds to the region around point B in FIG. 2b. Therefore, region R1 is an In-rich region and region R2 is a Cu-rich region. Note that the boundaries between those regions may not be defined as suggested in Figure 2c. Boundaries are shown only to indicate points in their own right. In actual membranes, even the crystal structure of those regions may differ. The Cu-rich region after seleniumization can contain particles with large faces of Cu selenide, while the In or Ga-rich region can have smaller particles and be smooth. When the solar cell is built on compound layer 29 in Figure 2c, the copper-rich region R2 containing the highly conductive Cu selenide phase can increase leakage current and reduce voltage output throughout the device, while , In rich region R1 can increase its series resistance. Both effects are extreme If so, the efficiency of the solar cell can be deteriorated. Non-uniform surface morphology, such as that shown in FIGS. 2a-2c, varies between operations and between substrates, which can lead to poor repeatability of the solar cell manufacturing process for high efficiency large area device manufacturing. Yield can be low. A compound layer with macroscopic and microscopic compositional uniformity is required to ensure very good solar cell efficiency and high production volumes.

0015Note that the above example illustrates the problem of microscopic non-uniformity in the case of non-uniform or coarse Group IIIA layers deposited on smooth Group IB layers. However, similar problems are observed even when the morphology of the In and Ga layers is smooth as they are deposited. The reason is that even when the initial morphology of In and Ga is flat, the metal precursor is typically heated to temperatures above 350 ° C during the reaction process with VIA group materials such as Se. It is to be. When the heating process is performed, In and Ga begin to melt at temperatures above about 30 ° C prior to reaction with Group VIA materials, they dewet the substrate and on surfaces such as Cu surfaces. Accumulate in. This dewetting phenomenon forms a "ball" that produces a rough morphology similar to that shown in FIG. 2b. In addition, ball formation becomes more extensive as the amount of low melting point phase (In and / or Ga) in the stack increases or the thickness of the In and / or Ga layer increases.

0016FIG. 3a shows a typical metal precursor stack 36 deposited on a substrate 22, in which case the substrate 22 includes a substrate 20 and a contact membrane 21 as in FIG. 2a, and the metal precursor stack 36 It contains a substantially smooth Cu layer 33, a substantially smooth In layer 34 and a substantially smooth Ga layer 35, such that they maintain the substrate below room temperature by forced cooling during deposition. By using certain means, it can be deposited on the substrate 22 by various thin film deposition techniques such as vapor deposition, sputtering or electrodeposition. In this example, the individual Cu, In and Ga layers in stack 36 have a flat surface morphology. FIG. 3b shows the morphology of the precursor stack after heating to a temperature higher than the melting point of the In and (Ga + In) composition present on the Cu layer 33, for example 160 ° C. Since the (Ga + In) composition of our example is 20% Ga and 80% In, the melting point is in the range of 100-120 ° C according to the In-Ga binary phase diagram. The surface morphology of the (In + Ga) layer in FIG. 3b is extremely heterogeneous, with microscopic compositional heterogeneity in the compound layers prepared using the precursors described above with reference to FIGS. 2a, 2b and 2c. Can occur. Note that the interface between the Cu layer 33 and the (In + Ga) layer 36a in Figure 3b is shown to be sharp, but this interface can actually diffuse depending on the temperature of the heat treatment process. I want to be.

0017One way to address the problem of microscopic non-uniformity is described in US Pat. No. 5,567,469, obtained by Wada et al. In this method, portions or components of the low melting phase phase, such as indium, are introduced into the precursor layer in the form of compounds selected from the group consisting of oxides, seleniums and sulfides. Those compounds of In have a very high melting point. Therefore, when the precursor is heated to carry out the reaction step with the VIA group components, the melting and blotting of In is reduced. This is because at least part of In is in the form of refractory compounds.

0018The description so far has focused on the issue of microscopic compositional inhomogeneity in the metal precursor layer used in the prior art two-step process method. An even more important problem, namely the problem of adhesion, has been identified for the metal precursor layer obtained by the low cost electrodeposition method. Electroplating is attractive for use in terms of low cost, but as described below, it is a prior art for the production of metal IB and IIIA element stacks for the production of IBIIIAVIA group compound films. There are other limiting factors in using the electroplating method.

0019Cu, In and Ga have very different plating potentials. Cu / Cu in aqueous solution²⁺, In / In³⁺And Ga / Ga³⁺The molar standard electrode potentials of the metal / ion pair are approximately + 0.337V, -0.342V, and -0.52V, respectively. This means that Cu can be plated and deposited at low negative voltages. On the other hand, for In deposition, a larger negative voltage is required. Even greater negative voltages are required for Ga deposition. Therefore, in order to form a stack containing Cu, In and Ga, Cu is typically first electroplated. This is followed by the deposition of In and then Ga. On the other hand, while electroplating one species, the other species to be deposited can also be partially dissolved in the electrolyte. For example, if a Cu / Ga / In stack is electrically deposited, some Ga may dissolve in the In deposition solution while depositing In on Ga. This may result in inferior control over the Cu / (Ga + In) and Ga (Ga + In) molar ratios of the precursor and absorption layers after formation. Similarly, the deposition of the Cu layer on the In layer can result in the loss of In from the In layer to the Cu plating electrolyte during processing. Therefore, the prior art method uses electroplated Cu / In / Ga stacks in that order. However, after seleniumization, such stacks result in a compound layer with poor adhesion to the substrate or substrate. Moreover, the microscopic non-uniformity of composition, such as that described with reference to FIGS. 3a and 3b, makes it impossible to form a high quality IBIIIAVIA group suitable for the production of high efficiency solar cells. It should be understood that thin film deposition technology with adhesion problems cannot reliably scale the production of electronic devices, especially solar cells, which are expected to have a lifespan of more than 20 years.

0020As illustrated by the brief overview above, low cost deposition techniques need to be developed to produce high quality, dense and well-adhered IBIIIAVIA group compound thin films with macroscopic and microscopic compositional uniformity. It still exists.

0021Outline of the invention The present invention advantageously provides, in various embodiments, a low-cost deposition technique for producing high quality, dense, well-adhered IBIIIAVIA group compound thin films with macroscopic and microscopic compositional uniformity. ..

0022In one embodiment, a method of growing a group IBIIIAVIA semiconductor layer on a substrate is provided. In the method of the present invention, a step of depositing a film of a group IB material and a layer of at least one group IIIA material on a substrate, and a mixed layer of mixing a film of a group IB material and a layer of at least one group IIIA material are mixed. A step of forming a metal film containing at least one of a sublayer of a group IIIA material and a sublayer of a group IB material on the mixed layer.

0023In a preferred embodiment, the method of the present invention further comprises the step of reacting the mixed layer with a metal film having a Group VIA material to grow a desired semiconductor layer.

0024In various other embodiments, a particular combination of materials in different layers and multiple layers forming a stack are described, along with the various mixing and annealing combinations described.

0025In another aspect of the invention, there is provided a method of growing a group IBIIIAVIA semiconductor layer on a substrate. In this embodiment, a metal precursor containing a Group IB material is formed on the substrate, the metal precursor having a rough surface and microscopic compositional heterogeneity, followed by a Group IIIA material on the metal precursor. A stack is formed by electrodeposition on the surface, thereby substantially reducing the rough surface and obtaining a microscopic compositional uniformity of the stack.

0026Those and other aspects and features of the invention will be apparent to those skilled in the art by examining the following description of a particular embodiment of the invention, along with the accompanying drawings.

0027Detailed explanation The present invention overcomes the shortcomings of the prior art by addressing important manufacturability and yield issues such as microscopic composition control and adhesion of semiconductor absorbent membranes to substrates. The present invention also enables low-cost production of thin-film solar cells.

0028In one embodiment, the metal precursor production process is divided into at least two sub-steps, which enhances more intimate mixing and reaction between Group IB and Group IIIA materials, by means of the low melting point Group IIIA material phase. Keeps the substrate wet and reduces microscopic compositional heterogeneity. As shown in FIGS. 6a-6d, the first step of this metal precursor production method is the deposition or adhesion of the first layer 60 and the first thin film 61 on the substrate 22. The terms layer and membrane are used interchangeably herein. However, sometimes different terms are used simply because it is more convenient to have different words, but I would like you to interpret it as such. Similarly, layer deposition on a substrate is also referred to herein as layer growth on a substrate or attachment of a layer to a substrate. Note that the substrate 22 can be similar to the substrate shown in FIG. 3a. The layers in the substrate 22 simplify the drawings by not showing them so that the invention can be described more clearly.

0029Returning to FIG. 6a, the first layer 60 contains at least one Group IB material and the first film 61 contains at least one Group IIIA material. What is shown in FIG. 6a is the preferred deposition order of the first layer and the first film, but this order is changed, i.e. the first film 61 on the substrate 22 is first deposited. It is possible to deposit the first layer 60 on the first film 61. The preferred thickness for the first layer 60 is in the range of 10 to 150 nm, more preferably in the range of 50 to 100 nm. The preferred thickness of the first film 61 is in the range of 20 to 250 nm, more preferably in the range of 100 to 200 nm. The structure shown in FIG. 6a is treated in a first treatment step to facilitate mixing between the first layer 60 and the first film 61. The first treatment step may include heating the structure, microwave treatment, laser treatment, and the like. The treatment varies from 1 second for laser treatment to 30 minutes for annealing in the furnace, with a time range of 50 to 350 ° C, preferably 80 to 200 ° C in air or vacuum. It can be carried out in a reducing atmosphere containing, for example, hydrogen or carbon monoxide, or in a substantially inert atmosphere. Preferably, the treatment is carried out for 5 to 600 seconds, more preferably 5 to 300 seconds. The first treatment step results in a first mixed layer 62 on the substrate 22 shown in FIG. 6b. The mixed layer 62 contains a Group IBIIA solid solution and / or alloy and has a much flatter surface morphology compared to the layer illustrated in FIG. 3b. This is because the first thin film 61 containing the low melting point group IIIA material is thin. With a thinner Group IIIA material layer, the surface tension is lower, which makes the ball formation less severe.

0030The next step in this process is the deposition of a second layer 63 and a second membrane 64 on the first mixed layer 62 shown in FIG. 6c. The second layer 63 contains at least one Group IB material and the second film 64 contains at least one Group IIIA material. What is shown in FIG. 6c is the preferred order of deposition or adhesion of the second layer and the second film, which is the order in which the second film 64 is deposited on the first mixed layer 62. It is possible to change that and deposit the second layer 64 on the second membrane 64. The preferred thickness for the second layer 63 is in the range of 10 to 150 nm, more preferably 50 to 100 nm. The preferred thickness of the second film 64 is in the range of 20 to 250 nm, more preferably in the range of 100 to 200 nm. The structure shown in FIG. 6c is processed in the second processing step to facilitate mixing between the first mixing layer 62, the second layer 63 and the second membrane 64. The second treatment step may include heating the structure, microwave treatment, laser treatment, and the like. The treatment is carried out in an air, vacuum, reducing atmosphere or a substantially inert atmosphere at a temperature in the range of 50-350 ° C, preferably 80 ° C-200 ° C, from 1 second for laser treatment. The time can vary up to 30 minutes for the case of annealing in. Preferably, the treatment is carried out for 5 to 600 seconds, more preferably 3 to 300 seconds. The second treatment step results in a second mixed layer 65 on the substrate 22 as shown in FIG. 6d. The second mixed layer 65 contains a Group IBIIA solid solution and / or alloy and has a substantially flat surface morphology and a uniform microscopic composition.

0031Note that the deposition and treatment steps are repeated several times, preferably 2-5 times, to give a metal precursor of the desired thickness and composition with microscopic compositional uniformity. If more steps are used, the individual thickness of the deposited or adhered layers can be reduced and the surface morphology can be improved. As shown in FIG. 6d, after a desired thickness of IBIIIIA metal precursor is obtained, this precursor reacts with at least one VIA material, resulting in high density and good microscopicity. It is possible to form an IBIIIAVIA group compound layer having a uniform composition. With reference back to FIG. 6c, optionally, once the structure of this figure is obtained, the structure can react with the VIA group material without performing a second processing step. By this method, an IBIIIAVIA group compound layer having good microscopic composition uniformity can also be formed. With reference back to FIG. 6, this preferred embodiment of the present invention is microscopic with the surface morphology of the metal precursor by dividing the precursor deposition process into multiple steps and introducing a mixing and annealing steps. Improves composition uniformity. In this way, the heterogeneity of the individual mixed layers is minimized. Because they are thin. Even if there is heterogeneity in the first mixed layer formed on the substrate, the next mixed layer formed on the first layer will reduce the heterogeneity.

0032The present invention will now be Cu_0.8In_0.8Ga_0.2Se_1.9Described with an example of forming or growing a layer.

0033Example 1: A Mo-coated glass sheet can be used as the substrate. A 100 nm thick Cu layer can be deposited on the Mo layer. This is followed by a 220 nm thick In film and a 40 nm thick Ga layer. Anneal the stack for 5-600 seconds at a temperature of 80-200 ° C to promote alloying between Cu, In and Ga. 100 nm Cu, 220 nm In and 40 nm Ga are subsequently deposited or adhered on the alloyed layer. The precursor is seleniumized by a well-known method such as in hydrogen selenide gas or selenium vapor and Cu_0.8In_0.8Ga_0.2Se_1.9Form a compound. Seleniumization is a variety of other things such as depositing Se on metal precursors and heating the stack layer, heating the substrate in a Se-containing gas or liquid atmosphere for a time ranging from 5 to 60 minutes. It can be carried out by means.

0034Example 2: A Mo-coated glass sheet can be used as the substrate. A 100 nm thick Cu layer can be deposited on the Mo layer. This is followed by the deposition of a 220 nm thick In film and a 40 nm thick Ga layer. The stack is annealed at a temperature of 80-200 ° C for 5-600 seconds to increase alloying between Cu, In and Ga. Then, 100 nm Cu, 220 nm In and 40 nm Ga are deposited on the alloyed layer. The second annealing step is performed at 80-200 ° C for 5-600 seconds to promote further alloying between the layers of the metal precursor. The precursor so obtained is then seleniumized by a well-known method such as in hydrogen selenide or selenium vapor and Cu._0.8In_0.8Ga_0.2Se_1.9Form a compound. Seleniumization can be done in a variety of ways, such as depositing Se on a metal precursor and heating the stack layer, heating the substrate in a Se-containing gas or liquid atmosphere for a time ranging from 5 to 60 minutes. Note that it can be done by other means.

0035Example 3: The method in Example 1 or 2 is used except that the Cu, In and Ga layers can be deposited in 4 steps instead of 2 steps. Therefore, the thickness of Cu, In and Ga for each deposition process can be reduced to 50 nm, 110 nm and 20 nm, respectively. A smooth and uniform metal precursor is obtained by heat treating the layers after each deposition step, preferably for a time reduced to 2 to 300 seconds (except for the last case in Example 1). The seleniumization of this precursor is a high quality Cu with a uniform composition._0.8In_0.8Ga_0.2Se_1.9Provides a compound layer.

0036In another embodiment of the invention, the morphology of the deposited film is further improved and the microscopic compositional uniformity divides the metal precursor production process into at least two sub-steps and initially on the substrate. By selecting the composition of the sublayer deposited by the substep so that the sublayer deposited in the sublayer does not contain a significant amount of Group IIIA material separated after the treatment step to promote mixing and alloying of the metal components. It will be further enhanced. This method can now be explained by using the phase diagrams shown in FIGS. 4 and 5.

0037Figure 4 shows Cu₁₁In₉Shows a binary phase diagram for Cu-In (references: PR Subramanian and DE Laurin, Bulletin of Alloy Phase Diagrams, Vol. 10, No. 5, p. 554, 1989), including the positions of stable alloy phases in. From this phase diagram, if a film with a Cu / In ratio of less than 11/9 (1.22) is heated to a temperature above about 156 ° C, then the liquid phase of the In-rich solution is Cu.₁₁In₉Will separate from the Cu-rich phase and / or other Cu-rich Cu-In alloy phases with about 30-37% In. If the Cu / In ratio is greater than or equal to 1.22 but less than about 1.7 (region A in Figure 4) and the temperature is in the range 156 to 310 ° C, then Cu₁₁In₉Only the solid phase and corresponding to about 37% In will be present in the membrane under equilibrium conditions. If the Cu / In ratio exceeds about 1.7, then only the Cu-rich solid phase will be present at a temperature of about 550 ° C under equilibrium conditions.

0038Similarly, compositions with a Ga / Cu ratio greater than 2 can result in a Ga-rich liquid phase when heated to above 30 ° C. Cu-Ga dual phase diagram in Figure 5 (see: M. Hansen). , Structure of two-phase alloys, McGraw Hill, 1958, p. 583). In region B of the phase diagram (about 40-67% Ga, and temperatures up to 254 ° C), only the solid phase is present. For Ga content less than about 40%, only the solid phase will be present even at temperatures above 550 ° C.

0039This embodiment of the present invention is a process by carefully selecting the IB / IIIA group molar ratio of the sublayer deposited on the substrate, i.e. Cu / In, Cu / Ga or Cu / (In + Ga) molar ratio. Minimize liquid phase separation between mixing / alloying steps. In this way, dewetting and ball formation by the low melting point phase is minimized along with the microscopic compositional heterogeneity derived from them as described in the examples given below.

0040Example 4: CuInSe₂The phase can be formed on a Mo-coated glass substrate by performing the following steps. a) To deposit 200 nm Cu on the substrate. b) Deposit 360 nm In on Cu so that the Cu / In molar ratio is 1.22. c) Cu₁₁In₉Treating the stack for a time of preferably 5 to 600 seconds in the temperature range of 156 to 310 ° C to form an alloy layer that substantially contains the solid phase. d) Depositing 80 nm In on the alloy layer. And e) seleniumizing such obtained metal precursors already described. After the last In deposit, a low temperature annealing step, such as about 2 ~ 300 seconds at 100 ~ 200 ° C, is also performed before the selenium step, which may enhance the mixing between the alloyed layer and the last In layer. Please note that.

0041Example 5: The process in Example 4 has a Cu / In ratio greater than 1.22, but with more Cu (instead less In) in steps a) and b), as within region A in Figure 4. It can be changed to a method that can be deposited. In this case, after step c), the alloyed layer is Cu₁₁In₉The solid phase and the other solid phase shown in FIG. 4 with an In content of 37% or less to the left of region A are included. In this case, more In needs to be deposited in step d) to compensate for the larger Cu / In ratio of the alloyed layer. The rest of the process is similar to that described in Example 4. Note that the Cu / In ratio of the alloyed layer can be further increased by choosing the thickness of the Cu and In layers corresponding to less than about 37% In (relative to the left of region A). I want to. In this case, a much higher temperature range (up to about 600 ° C.) can be used during the treatment step c) without the formation of a liquid phase that causes dewetting and ball formation.

0042Example 6: CuInSe₂The layer can be formed on a Mo-coated glass substrate by performing the following steps. a) Deposit 100 nm Cu on the substrate. b) Deposit 180 nm In so that the Cu / In molar ratio is 1.22. c) Process Cu in a temperature range of 156 to 310 ° C, preferably for a time stack of 2 to 300 seconds.₁₁In₉Forming an alloyed layer that substantially contains a solid phase. d) Repeat steps a), b) and c). Then e) deposit 80 nm In. And f) to selenate the metal precursor thus obtained as described above. After the final In deposition step, a low temperature annealing step, such as at 100-200 ° C for about 2-300 seconds, is also performed before the selenium step to mix between the alloyed layer and the final In layer. Note that it increases.

0043Example 7: CuInSe₂The layers were adjusted in steps a), b) and d) so that the Cu and In film thicknesses resulted in a Cu / In molar ratio greater than 1.22, and the total Cu with an In layer thickness of 1 in step e). It can be formed on a Mo-coated glass substrate by performing the steps of Example 6 except that it is adjusted to provide a / In ratio. In this case, high temperatures up to about 600 ° C. can be used in a shorter time treatment step c) of 2-10 seconds, especially if the total In content of the alloyed layer is less than about 37%. ..

0044Example 8: CuGaSe₂The layer can be formed on a Mo-coated glass substrate by performing the following steps. a) To deposit 200 nm Cu on the substrate. b) Deposit 264 nm Ga so that the Cu / Ga molar ratio is about 1.5. c) The stack is processed in the temperature range of 30-600 ° C for preferably 5-600 seconds to form an alloyed layer that substantially contains a Cu-rich solid phase with a composition to the left of region B in FIG. To do. d) To deposit about 66 nm Ga on the alloyed layer to make the total Cu / Ga ratio about 1. Then, e) seleniumize the metal precursor thus obtained as described above. After the final Ga deposition step, low temperature (preferably <254 ° C) annealing is also performed for a short time, such as 2 to 300 seconds, before the seleniumization step to combine the alloyed layer with the final Ga layer. Thorough mixing between.

0045Examples 4 to 8 above are CuInSe.₂And CuGaSe₂Embodiments of the present invention will be described from the viewpoint of film growth. Those skilled in the art can use the same method to change the composition of Cu (In, Ga) Se.₂Or Cu (In, Ga) (SSe)₂Recognize that it can be used for layer growth and generally for the growth of many different IBIIIAVIA group compound layers. One specific embodiment described in the following example is to deposit a Cu and In-containing layer capable of alloy composition without a low melting point phase after the first treatment step, and after the second treatment step. It involves depositing Cu and Ga-containing layers that can form an alloy composition without a low melting phase. When formed on top of each other, the two layers form an entire metal precursor membrane with the desired composition on a macroscopic and microscopic scale.

0046Example 9: Cu with a k close to 2 (In)_0.69Ga_0.31) Se_kThe layer can be formed on a Mo-coated substrate by performing the following steps. a) To deposit a Cu layer on the Mo surface. b) To deposit the In layer on the Cu layer so that the Cu / In molar ratio is about 1.22. c) Process the Cu for a time stack of 5 to 600 seconds at a high temperature, preferably in the temperature range of 156 to 310 ° C.₁₁In₉Forming a first alloy layer that substantially contains a solid phase. d) To deposit a Cu layer on the alloyed layer. e) To deposit a Ga layer on the Cu layer so that the Cu / Ga ratio is about 0.5. f) Process the CuGa for a time stack of 5 to 600 seconds at a high temperature, preferably in the temperature range of 30 to 254 ° C.₂Forming a second alloyed layer that substantially contains the solid phase. g) Seleniumize the metal precursor thus obtained. Note that the thickness of Cu, In and Ga deposited in steps a), b), d) and e) can be adjusted to adjust the overall stoichiometry or composition. Cu thickness in step a), In thickness in step b), Cu thickness in step d) and Ga thickness in step e) is 1 mol.₁₁In₉And 2 moles of CuGa₂If selected to result in, the total composition of the metal precursor is Cu₁₁In₉Cu₂Ga₄And it's Cu₁₃In₉Ga₄That is, CuIn_0.69Ga_0.31Is equivalent to. When selenateized, this provides a compound layer with a Cu / (In + Ga) ratio of 1 and a Ga / (Ga + In) ratio of 0.31. This is a desirable composition for the production of high efficiency solar cells. The processing step f) may be skipped in the process sequence. The deposition order can also be changed. For example, steps d), e) and f) may be performed first. This is then followed by steps a), b) and optionally c). The entire precursor is then seleniumized as in step g). The deposition order can be further modified such that In is first and Cu is later and / or Ga is first and Cu is later. The method described in this example is unique in that it utilizes two alloy compositions, one of which is a Cu-In alloy (Cu).₁₁In₉) And the other Cu-Ga alloy (CuGa₂) Is a stable solid phase that does not melt at temperatures up to about 254 ° C, thus providing a uniform morphological and compositional metal precursor that can react with Group VIA materials to form a uniform Group IBIIIAVIA compound layer. .. From that point of view, CuGa having the above typical molar ratio₂/ Cu₁₁In₉Stack or Cu₁₁In₉/ CuGa₂The stack can be formed by any technique such as sputtering, vapor deposition, electroplating, etc., and then exposed to Se and / or S to form a good quality compound layer. Cu on the stack₁₁In₉Layer and CuGa₂Note that the interface between the layers is not expected to be very sharp, i.e. some reaction and mixing is expected at the interface between the two alloy phases during processing.

0047The Group IB and Group IIIA materials of the present invention can be deposited by various thin film deposition techniques such as sputtering, vapor deposition or electroless plating. One preferred method for carrying out the teachings of the present invention is a low cost electrodeposition method, which, when used in accordance with the techniques of the present invention, provides technical benefits that exceed the economic benefits already described. provide.

0048Cu (In, Ga) Se₂For thin film growth, the Cu, In and Ga layers are electrodeposited to a controlled thickness and the process alloying or mixing steps are furnace annealing, laser, microwave or RTP (fast heat treatment). It is done using. Cu_0.8In_0.8Ga_0.2Se_1.9Cu (In, Ga) Se with a typical composition of₂An example is given below to illustrate the use of electrodeposition to grow.

0049Example 10: A Mo-coated substrate can be used as the substrate. A Cu layer with a thickness of approximately 100 nm can be electrodeposited onto the Mo layer. This is followed by electrodeposition of an In film with a thickness of about 220 nm and a Ga layer with a nominal thickness of 40 nm. The stack is annealed at a temperature of 80-200 ° C for preferably 5-600 seconds to promote alloying between Cu, In and Ga. Then, 100 nm Cu, 220 nm In and 40 nm Ga are electrodeposited on the alloyed layer. The precursor is seleniumized by a well-known method such as hydrogen selenide or selenium vapor for a time of 5 to 60 minutes to Cu._0.8In_0.8Ga_0.2Se_1.9Form a compound. Seleniumization can be performed by various other means such as depositing Se on the metal precursor, heating the stack layer, heating the substrate in a Se-containing gas or liquid atmosphere, and the like. Please note.

0050Example 11: A Mo-coated substrate can be used as the substrate. A Cu layer with a thickness of approximately 100 nm can be electrodeposited on the Mo layer. This is followed by electrodeposition of an In film with a thickness of about 220 nm and a Ga layer with a nominal thickness of 40 nm. The stack is annealed at a temperature of 80-200 ° C for preferably 2-300 seconds to promote alloying between Cu, In and Ga. Nominal 100 nm Cu, nominal 220 nm In and about 40 nm Ga are then electrodeposited onto the alloyed layer. The second annealing step is performed at 80-200 ° C., preferably for 2-300 seconds, to further promote alloying between the metal precursor layers. The precursor thus obtained is then seleniumized for 5 to 60 minutes by a well-known method such as hydrogen selenide or selenium vapor to Cu._0.8In_0.8Ga_0.2Se_1.9Form a compound. Seleniumization can be performed by various other means such as depositing Se on the metal precursor and heating the stack layer, heating the substrate in a Se-containing gas or liquid atmosphere, and the like. Please note that.

0051The present invention has the unique ability to enable efficient use of low cost electrodeposition methods for the deposition of metal components Cu, In and Ga. In general, Cu, In and Ga have very different plating potentials. Therefore, the Cu layer is typically first electroplated to form a metal precursor stack containing Cu, In and Ga. This is then followed by the deposition of all required Ins, followed by all required Ga deposits. On the other hand, even if one type is electroplated, the other type in which the deposition is carried out may be partially dissolved in the electrolytic solution, resulting in very poor composition control.

0052In one embodiment of the invention, Cu and at least one Group IIIA component are first electrodeposited on the substrate. The treatment step is then used to promote the alloying and formation of at least one IBIIIIA group alloy and / or solid solution. The plating potential of Group IIIA materials in Group IBIIIA alloys and / or solid solutions changes, and the amount of Group IIIA materials on the surface of Group IBIIIIA alloys and / or solid solution films also decreases. Both of these factors allow for efficient electrodeposition of the next stack without dissolving the substance of the Group IIIA material in the plating solution of the next step. For example, the precursor layer can be formed on the substrate as follows. The Cu layer is first electrodeposited on the substrate. This is followed by electrodeposition of the Ga layer. A treatment process such as heat treatment forms an alloyed Cu-Ga layer. The In layer is electrodeposited on the Cu-Ga layer. By diffusing Ga in the Cu layer and chemically bonding Ga to the Cu-Ga alloy composition or Cu in the solid solution, the electrode potential of Ga in the alloy is compared to the electrode potential of pure Ga. It varies and therefore the electrodeposition of In on the Cu-Ga alloy is achieved without significant loss of Ga to the In plating solution. Moreover, the Ga content on the surface of the Cu-Ga alloy or solid solution layer is much lower than the Ga content on the surface of the Cu / Ga stack initially electroplated on the substrate. Therefore, the Ga content available on this surface for possible removal during the In deposition process is dramatically reduced by the use of the alloying process of the present invention. Another advantage of the method of the present invention is the fact that Ga diffuses into Cu and / or Cu diffuses into Ga during alloying. The result is that Ga is brought close to the interface between the metal precursor membrane and the substrate without compromising compositional control. Bringing Ga near the substrate improves the adhesion of the IBIIIAVIA group compound layer to the substrate after the seleniumization and / or sulfidation steps. This claim is possible for all alloyed layers obtained through the steps of the present invention, including all Cu-In and Cu-Ga alloys.

0053Adhesion to the base material can also be improved by directly plating the base material with a Cu-Ga mixture or an alloy layer. In a preferred embodiment of the invention, the Cu-Ga alloy layer 25 is electrodeposited onto the conductor 22 from a suitable electrolyte as shown in FIG. The substrate 23 can be a metal or glass sheet or a hard or flexible conductor or insulator material such as metal or insulating foil. Metal foils include Ti, stainless steel or Mo foils. Insulating foils include those made from high temperature materials and polymers such as polyimide and mica. The conductor 22 contains a material that allows good ohm contact with the absorbent layer after it is fully formed. Such ohm contact materials include Ti, Mo, W, Ta and their nitrides. The Cu-Ga alloy layer 25 may contain 5 to 50 atomic% Ga, preferably 10 to 30 atomic% Ga. The thickness of the Cu-Ga alloy layer 25 will be in the 100-500 nm range. Electrodeposition can be carried out using a glycerin-based electrolyte containing Ga and Cu ions. The gallium and copper ion sources can be metal salts such as copper chloride and gallium chloride, which are dissolved in glycerin solution with a weak acid such as citric acid or tartaric acid. Electrodeposition can be carried out at room temperature or in a cooled electrolyte maintained at 5-15 ° C. Plating current density is 0.5-40mA / cm²Range, preferably 1-20mA / cm²Will be in the range of. The gallium to Cu ratio in the electrolyte can vary from 0.5 to 5 to control the Ga / Cu ratio of the deposited membrane. The deposited layer is Cu₉Ga₄, Cu₃Ga₂And CuGa₂Can include at least one of the alloy species such as. In one preferred embodiment, the Cu-Ga layer is Cu_(1-x)Ga_xIncludes solid solutions that can be represented by the chemical formula (where x is less than or equal to about 2.0). Gallium is tightly bound to Cu in this solid solution composition, which improves the stability and repeatability of the methods disclosed in the present invention. It is important that the Cu-Ga alloy layer is substantially free of free Ga phases. To avoid such a situation, after the deposition of the Cu-Ga layer on the substrate 24 (Fig. 7), the structure is annealed for an appropriate time to ensure the complete alloying of Cu and Ga. obtain. For example, after electrodeposition of the Cu-Ga layer on the substrate, the "base / Cu-Ga layer" structure is in the temperature range of 50-500 ° C, preferably 100-200 ° C for 1 second to 15 minutes. It can preferably be annealed for 5 seconds to 1 minute. Annealing can be performed in an air, vacuum, inert gas or reducing atmosphere using a furnace, oven or fast heating annealing system. Laser annealing or microwave annealing can also be used. In laser annealing, the Cu-Ga layer is a short CO for a few seconds.₂Exposure to large area rays of lasers such as lasers, YAG lasers or Ar lasers promotes alloying.

0054After annealing, the Cu-Ga alloy layer 25 is completely formed, and the In layer 26 is electroplated on the Cu-Ga alloy layer 25. Indium plating can be performed using established electrolytes such as In sulfamate electrolytes commercially available from Indium Corporation of the United States. Plating current density is 10-100mA / cm for this process², Preferably 20 ~ 50mA / cm²Is in the range of. The thickness of the In layer can be in the range of 200 to 1000 nm depending on the thickness of the Cu-Ga alloy layer and the desired Cu / (In + Ga) and Ga / (Ga + In) molar ratios. Once the structure of FIG. 7 is obtained, it can react with Group VIA materials to form the aforementioned compound layer.

0055Returning to the issue of micro-heterogeneity, it forms a first metal precursor sublayer containing at least one Group IB material, followed by a substantially flat surface for the entire metal precursor. Placing a second metal group IIIA rich precursor sublayer on top of the first sublayer in a manner that provides surface topography has certain advantages. FIG. 8a shows a typical first metal precursor sublayer 83 formed on a substrate 82 containing a substrate 80 and a contact film 81. The first metal precursor sublayer has surface topography with thick regions 84 and thin regions 85. As mentioned above with reference to FIG. 2b, such non-uniform surfaces are such that a Group IIIA rich film is deposited on a film containing at least one Group IB material or is observed in FIG. 3b. It may be brought about by the dewetting or boring phenomenon when such a surface can be formed during heat treatment of metal precursors containing Group IB and Group IIIA materials. Sublayer 83 may be brought about by annealing the Cu-Ga layer of FIG. 7 as described above. The average thickness of the sublayer is in the range of 200-2000 nm, and the local variation in thickness can be as large as +/- 70% of the average thickness. For example, a typical sublayer with an average thickness of 600 nm may have a thin region as thin as 180 nm and a thick region as thick as 1020 nm. Whatever the origin, such heterogeneity is detrimental to the microscopic compositional uniformity of the precursor membranes and compound layers obtained using them. Moreover, as mentioned above, the thick region 84 is usually richer for low melting point group IIIA materials compared to the thin region 85. To overcome this problem, FIG. 8b shows the process of depositing a second metal group IIIA rich precursor sublayer 86 on top of the first sublayer 83 in a manner that defines surface topography. In this method, the thick Group IIIA rich layer is deposited on the thin region 85 of the first sublayer 83, and the thin Group IIIA rich layer is deposited on the thick region 84 of the first sublayer 83. If thin and thick areas are each for Group IIIA materials

0056The electrodeposition method and the electroless plating method are wet processing methods that give a unique quality for carrying out the present invention already disclosed. The solution or electrolyte used for the technique can be formulated to obtain a "flattened" deposit on a rough surface. Various organic and inorganic additives can be utilized in such electrolytes to enhance sedimentation at valleys or low surfaces on the substrate while suppressing deposition at peaks or high places. Thus, if the Group IIIA rich sublayer is electroplated, for example, on the first metal sublayer 83 of FIG. 8a, the plating is thickened on the thin region 85 and suppressed on the thick region 84. It results in a metal group IIIA rich sublayer 86 with a surface profile similar to that shown in FIG. 8b. Many different types of additives can be used in electrolytes or solutions to achieve the flattening effect. Accelerators containing chemicals such as thiourea, polyethylene glycol, polyether sulfides, mercapto compounds, coumarins, aromatic sulfone amides, saccharin, bissodium sulfopropyl disulfides, amines or high molecular weight polymers with amide functional groups. , Inhibitors, leveling agents, surfactants and the like. Valleys as narrow as 10-100 nm or even narrower are preferentially filled and flattened with an electrolytic plating material such as a Group IIIA rich sublayer with such additives in the electroplating solution. ..

0057It should be noted that the electroplating or electroless plating of the Group IIIA rich surface film on the substantially metal precursor layer already prepared has the following advantages. i) After the formation of the IBIIIAVIA group layer and the solar cell device, coating and adjusting the composition of any region that may contain excess IB group material causing short circuits and reduced device performance. ii) Flattening the surface morphology of the entire precursor layer and compound film after reaction with Group VIA materials such that good quality bonding is formed by the deposited CdS layer or other bonding forming material. iii) Dense the surface layer of the entire precursor layer so that better bonding after compound formation is produced using such compound layers. Their advantages are also applicable to the problem of fixation by precursor layers deposited by other techniques. In this case, the electrodeposition step of adhering the Group IIIA rich layer on the already formed precursor layer improves the surface morphology, increases the density, and improves the microscopic composition uniformity. Can be considered to be.

0058For example, FIG. 9 shows a metal precursor that can be formed on a substrate 92 by a nanoparticle deposition method such as spraying or doctor blade manipulation of Cu, or Cu-In or Cu-Ga or Cu-In-Ga-containing nanoparticle ink. Shows body layer 93. The nanoparticles in this case are < It can be 200 nm, and they are dispersed in a solvent such as water, alcohol or ethylene glycol, assisted by well-known organic surfactants and dispersants, to form inks. The precursor layer 93 can be present in a deposited form, or it is 100-400 for the purpose of at least partially melting the nanoparticles to each other and to the contact film 91 of the substrate 92. It can be subjected to processing steps such as annealing steps at high temperatures such as ° C. Instead, in general, the precursor layer 93 is any substantially metallic precursor with inferior surface morphology and / or inferior microscopic composition uniformity made by either method. Can be a layer. For example, in the precursor layer, first, an ink of oxide particles containing Cu, In and Ga is deposited on a substrate to form an oxide film, and then the oxide film is reduced to form, for example, Cu. It can be obtained by obtaining a substantially metal film containing more than 90 mol% of the metal component containing In and Ga. As can be seen from this figure, the top surface of the precursor layer 93 is rough due to the granular nature of the nanoparticles or the heat treatment or reduction steps typically used to form the precursor layer. There are many gaps, which are micron or less than micron in size at or near the surface. As an example, the precursor layer can have a thickness of 200-2000 nm and its surface roughness can be in the 50-500 nm range. The Group IIIA rich layer 94 is electrodeposited on the rough surface of the precursor layer 93 to form the entire precursor layer 96 having a surface 95 with virtually no roughness and porosity. For example, the surface 95 may have a roughness in the 5-10 nm range. This is achieved because the plating solution has the ability to penetrate the smallest cavities or pores and fills them as described in the context of FIG. 8b. The precursor layer 93 can be Cu-rich, i.e. Cu / In, or Cu / Ga or Cu / (In + Ga) ratio is> It is 1. In this case, the Group IIIA rich layer 94 may contain In and / or Ga and may be plated with an electrolytic solution containing a flattening or gap filling additive. Group IIIA rich layers can also contain multiple layers such as In and Ga layers. The thickness of the Group IIIA rich layer is adjusted to provide the desired stoichiometry or overall composition for the entire precursor layer 96. Alternatively, the precursor layer 93 may have a Cu / In or Cu / Ga or Cu / (In + Ga) ratio of 1 or <1. In this case, a thinner Boron Group IIIA rich layer would be needed. The precursor layer 93 can also be made substantially from Cu particles. In this case, In and / or Ga are electrodeposited onto this coarsely porous Cu layer, adjusting the overall composition to the desired Cu / In, Cu / Ga or Cu / (In + Ga) ratio, and at the same time. The pores are filled and after reaction with at least one VIA group material, the surface of the entire precursor layer is flattened for the formation of a high quality compound film.

0059FIG. 10 shows a schematic view of an apparatus 40 that can be used for the electrodeposition step of the processing step of the present invention. The device is described by taking up the electrodeposition of Cu-Ga and In as an example. It will be apparent to those skilled in the art that the general design of the apparatus of FIG. 10 can be used to carry out all of the embodiments related to electroplating of the present invention. Device 40 in FIG. 10 is an in-line system with a plurality of stations. The device 40 processes a substrate 40a, which may be in the form of flexible foil or a rigid sheet. The deposition is carried out on the conductor 41, which is already coated on one surface of the substrate 40a. First, the Cu-Ga layer is deposited on the conductor 41 in the Cu-Ga electroplating station 42a. The copper-Ga electroplating station 42a comprises an electroplating chamber 45, where the enclosure 52 receives the electroplating solution through the inlet 50 and delivers it onto the surface of the conductor 41 through the opening 51. The electroplating solution flows in the direction indicated by arrow 48. The anode 47 is located towards the enclosure 52, which is made of an insulating material such as polypropylene. The anode 47 can be made of an inert material such as Pt or Pt-coated Ti, or the anode can be a Cu or Cu-Ga alloy anode. Anode 47 may have pores or openings in it to allow the plating solution to flow. The electrical contact 46 is installed so as to softly touch the surface of the conductor 41. Note that if the process is carried out in in-line mode, the substrate 40a will move continuously in the direction "P" when the Cu-Ga layer is deposited. Thus, the first contact 46a touches the surface of the conductor 41 prior to plating, while the second contact 46b touches the surface of the Cu-Ga layer deposited on the conductor 41 through the opening 51. In that regard, scratching the Cu-Ga surface by the second contact 46b should be avoided by using a lightly contacting spring load or roller-type contact. .. It is also possible to eliminate the second contact 46b and use only one set of contacts (first contact 46a). Although the two contacts are schematically shown in FIG. 4, it should be understood that any number of contacts can be used as long as they are outside the area defined by the opening 51. If the substrate 40a is conductive, then electrical contacts can be made on the back surface 40b, which eliminates any problems with scratching the deposited layer.

0060During electrodeposition, a voltage is applied between the contact 46 and the anode 47 to make the conductive surface of the contact and substrate more cathodic. This causes deposition on the conductive surface of the substrate. The plating solution is injected onto the surface of the conductor 41 through the opening 51 and then flows outward of the enclosure 52 for recovery, regeneration and recirculation. The opening 51 may exist in the form of a rectangular slit. The plating current density used, the width of the slit in direction P, and the speed used for substrate movement determine the thickness of the Cu-Ga layer obtained in the portion of the substrate moving over the opening 51. The length of the slit (perpendicular to P) determines how large the substrate is machined and what the output of device 40 is. The width of the opening 51 or slit can be in the range of 1-10 cm, while its length can be in the range of 30-120 cm.

0061Since the surface of the conductor 41 is coated with a Cu-Ga layer, it moves to the rinsing / drying station 43 where the surface of the Cu-Ga layer is rinsed and chemical residues are removed. After rinsing, the surface can be dried by blowing air or nitrogen against it. After rinsing and drying, a portion of the surface already covered with Cu-Ga is transferred to the annealing station 44. As mentioned above, the use of the annealing station 44 is optional, but it is preferable to ensure good composition control. If the electrodeposition process performed at Cu-Ga electroplating station 42a results in a fully alloyed Cu-Ga layer, the need for annealing station 44 may be eliminated. At the annealing station 44, the newly deposited Cu-Ga layer is exposed to heat from the heat source 55. The heat source 55 may be a resistant heating element, a collection of heating lamps, a laser beam, or the like as described above. The Cu-Ga layer is annealed in the annealing station 44 to ensure substantial alloying of Cu and Ga and formation of the Cu-Ga alloy layer. Once the Cu-Ga alloy layer is formed on the surface of the conductor 41, it moves to the In electroplating station 42b to deposit the In layer and is a precursor such as that shown in FIG. 7 or 8b. The structure is obtained. The In electroplating station can be very similar to the Cu-Ga electroplating station, therefore its details are not shown in FIG. The anode in this case can be an inert anode or an In anode. The width of the aperture and the plating current density are selected to provide the desired In layer thickness and the desired overall Cu / (In + Ga) and Ga / (Ga + In) ratios. Since the preferred mode of operation of device 40 in FIG. 10 is "in-line", the speed of substrate 40a in direction P is the same for all steps performed in series mode. Therefore, the thickness of the various layers electroplated is controlled by the plating current density used in each process station. obtain. It should be understood that the various steps of the invention can also be performed within different parts of the device. For example, Cu-Ga electroplating and annealing can be performed in one device, and In electroplating can be performed in another device. Although four process stations are shown in FIG. 10, a large number of process stations can be added to the equipment of FIG. For example, multiple Cu-Ga electroplating stations and In electroplating stations and annealing stations can be used to increase power output. Two or more units shown in FIG. 10 may be added in series to carry out the invention described in FIGS. 6a-6d. Even selenium / sulfidation stations can be added to the termination to react a newly deposited Cu-Ga / In precursor stack with VIA material to form a compound layer as described below.

0062In another preferred embodiment of the present invention, the Cu-Ga alloy layer is formed by reacting the Cu layer with the Ga-supported layer. FIG. 11a shows a substrate 240 coated with a Cu layer 300. The Cu layer 300 is preferably deposited on the conductor 220 through electrodeposition. However, other well-known membrane deposition techniques can also be used. After the deposition of the Cu layer 300, the Ga-supporting layer 310 is deposited on the Cu layer 300 as shown in FIG. 11b. The Ga-supporting layer is preferably a Ga layer, but may also contain a Ga-In alloy. The Ga-supported layer is preferably deposited using electroplating. However, other thin film deposition techniques may also be used. Ga and Ga-In alloys are < Since it melts at a low temperature of 156 ° C, techniques such as melt spraying or dipping can also be utilized for the deposition of those materials. In dipping techniques, the substrate is immersed in a melt that can be a melt of Ga or Ga and In and then removed from it. In this case, a small amount of Cu (1 to 10%) is also included in the melt to prevent Cu from seeping out from the electrodeposited Cu layer 300 to the melt. Once the stack of Cu layer 300 and Ga-supporting layer 310 is formed as shown in FIG. 11b, the stack is annealed as described above to form the Cu-Ga alloy layer 320 as shown in FIG. 11c. To do. If the Ga-supported layer 310 contains In, the Cu-Ga alloy layer may also contain some In in the form of elemental In or Cu-In alloy or In-Ga alloy. The atomic% of In in the Ga-supported layer is preferably in the range of 0 to 20%. Therefore, the melting point of the Ga-supported layer is preferably less than 30 ° C. After the annealing step and the formation of the Cu-Ga alloy layer 320, the In layer is preferably deposited on the Cu-Ga layer by electrodeposition to obtain a structure similar to that in FIG. The preferred process flow of the present invention using the low cost large area deposition method is a) electrodeposition of the Cu layer on the substrate, b) electrodeposition of the Ga layer on the Cu layer, and c) formation of the Cu-Ga alloy layer. Annealing of the Cu / Ga stack for, and d) electrodeposition of the In layer on the Cu-Ga layer to form the precursor layer as shown in FIG. The device of FIG. 10 can be easily formed and it can carry out those process steps. Electrodeposition of In from an electrolytic solution with flattening ability can be present in the Cu-Ga alloy layer described above in connection with FIGS. 8a and 8b, with rough formation problems and microscopic compositional inhomogeneity. Address the problem.

0063Reactions of metal precursors with Group VIA materials can be accomplished in a variety of ways. In one embodiment, the precursor layer is exposed to high temperature Group VIA vapors. Their techniques are well known in the art and they are solid Se, solid S, solid Te, H in the temperature range of 350-600 ° C.₂Se gas, H₂It involves heating the precursor layer for a time ranging from 5 minutes to 1 hour in the presence of at least one of Se vapor, S vapor, and Te vapor provided from a source such as S gas. In another embodiment, one or more layers of Group VIA material are deposited on the precursor layer, and the stack layer is then heated in a furnace, such as in a fast thermal annealing furnace. Group VIA materials can be deposited, sputtered or plated on the precursor layer. Alternatively, inks containing Group VIA nanoparticles can be prepared, and those inks can be deposited on the precursor layer to form a Group VIA material layer containing Group VIA nanoparticles. Such layers can be deposited using dipping, spraying, doctor blade processing or printing techniques with ink. The reaction can be carried out at elevated temperatures for 1 to 30 minutes depending on the temperature. As a result of the reaction, IBIIIAVIA group compounds are formed from the precursor. It should also be noted that the reaction chamber can be added to the equipment of Figure 10 and the entire process can be carried out in-line.

0064Solar cells can be made on the compound layers of the invention using materials and methods well known in the art. For example, a thin (<0.1 micron) CdS layer can be deposited on the surface of the compound layer using a chemical immersion method. A transparent window of ZnO can be deposited on the CdS layer using MOCVD or sputtering techniques. A metal finger pattern is optionally deposited on ZnO to complete the solar cell.

0065Although the present invention has been described in connection with certain preferred embodiments, modifications to it will be apparent to those skilled in the art.

0066<figref num="1">It is sectional drawing of the solar cell using the IBIIIAVIA group absorption layer.</figref><figref num="2a">Shown is a prior art Cu / In / Ga metal precursor stack deposited on a substrate exemplifying the non-uniform surface morphology of the In and Ga layers by "balling".</figref><figref num="2b">An enlarged view of the region 27 in FIG. 2a is shown.</figref><figref num="2c">The prior art IBIIIAVIA group compound membrane with microscopic compositional heterogeneity obtained by reacting the metal precursor layer shown in FIG. 2b with a group VIA material is shown.</figref><figref num="3a">A Cu / In / Ga metal precursor stack deposited on a substrate is shown, exemplifying a uniform surface morphology in the as-deposited form.</figref><figref num="3b">The metal precursor of FIG. 3a after heating to high temperature is shown, exemplifying the formation of non-uniform surface morphology due to the melting of the Group IIIA phase.</figref><figref num="4">The Cu-In binary phase diagram is shown.</figref><figref num="5">The Cu-Ga binary phase diagram is shown.</figref><figref num="6">The preferred process sequence of the present invention is shown.</figref><figref num="7">A preferred precursor stack containing a Cu-Ga alloy and an In layer is shown.</figref><figref num="8a">Shows a first metal precursor sublayer with uneven surface topography.</figref><figref num="8b">It shows a second metal sublayer deposited on the non-flat surface of the first metal sublayer that forms a flat surface topography.</figref><figref num="9">Shown shows a total precursor layer having a flat surface with a porous and rough precursor film in a flattened state and an electroplating layer deposited on it.</figref><figref num="10">A device for electroplating, cleaning, and annealing a thin layer is shown.</figref><figref num="11a">The Cu layer deposited on the base material is shown.</figref><figref num="11b">The stack of Cu / (Ga-supporting film) deposited on the substrate is shown.</figref><figref num="11c">The alloy layer formed on the substrate by reacting the stack of FIG. 11b is shown.</figref>