Display substrate and display panel having the same

The present invention relates to a display board and a display panel having the display board. More specifically, the present invention relates to a display board that alleviates the gate signal delay and a display panel having the display board.

Generally, the liquid crystal display panel includes an array substrate having a thin film transistor and a pixel electrode, a color filter having a color filter and a common electrode, and a liquid crystal layer interposed between the array substrate and the color filter substrate. Here, the array substrates are perpendicularly intersected with each other and further include gate wiring and data wiring defining a plurality of unit pixels, and the thin film transistor and the pixel electrode are generally formed in the unit pixel.

The image quality of the image displayed on the liquid crystal display panel is greatly affected by the normal transmission of signals applied to the gate wiring and the data wiring.

In particular, when the screen of the liquid crystal display panel is enlarged, the length of the gate signal wiring increases, the time constant increases, and when the resolution becomes high, the conduction time of the thin film transistor decreases relatively. Therefore, the larger the size and the higher the resolution of the liquid crystal display panel, the more the gate signal delay increases and the output of the gate IC becomes insufficient unless the time constant of the gate signal wiring is sufficiently small. Due to the larger screen of the liquid crystal display panel and the demand for high resolution image quality, the gate signal delay becomes more problematic when using the conventional drive method of displaying an image at a signal frequency of 120 Hz with 60 Hz drive. ..

The gate signal delay increases as the resistance of the gate wiring increases and the parasitic capacitor formed in the gate wiring increases. Therefore, in order to reduce the gate signal delay, research on low resistance metal used as a material for gate wiring is continuing, and a design is made to suppress the generation of parasitic capacitors.

On the other hand, recently, in order to improve the side viewing angle of the liquid crystal display panel, the PVA mode in which the pixel electrodes are patterned to divide the unit pixel region into a plurality of domains and the patterned pixel electrodes are electrically separated from each other. An SPVA mode liquid crystal display panel that divides into sub-electrodes has been developed. In particular, in the SPVA mode, when the sub-electrodes formed in one unit pixel region are connected to different gate wirings, the gate signal delay becomes a major obstacle to normal image display.

<p num="0007"> The technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is a display in which the parasitic capacitance of a capacitor formed in a gate wiring is reduced to reduce a signal delay. To provide a substrate.</p><p num="0008"> Another object of the present invention is to provide a display panel including a display board in which the parasitic capacitance of a capacitor formed in a gate wiring is reduced to reduce signal delay.</p>

<p num="0009"> In order to realize the above-mentioned object of the present invention, the display substrate according to the embodiment of the present invention includes a base substrate, a gate wiring, a data wiring, a pixel electrode, and a shield electrode. The base substrate contains a plurality of unit pixel regions arranged in a matrix shape. The gate wiring is extended between the unit pixel regions and the data wiring intersects the gate wiring and is extended between the unit pixel regions. The pixel electrodes are arranged within the unit pixel region and are electrically connected to the output terminals of the switching element that are electrically connected to the gate wiring and the data wiring. The shield electrode is formed on the upper part of the gate wiring and the data wiring. An opening is formed in the shield electrode to expose a part of the gate wiring.</p><p num="0010"> The shield electrode is formed of the same substance in the same layer as the pixel electrode. The inner edge of the shield electrode formed by the opening overlaps the gate wiring. The shield electrode has a width larger than that of the gate wiring, covers the gate wiring, and is arranged so as to be separated from the pixel electrode. The width of the gate wiring and the width of the data wiring are reduced at the intersections that intersect each other. A domain division pattern is formed on the pixel electrodes.</p><p num="0011"> In order to realize the other object of the present invention described above, the display panel according to the embodiment of the present invention has a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. including. The first substrate includes a gate wiring arranged on the lower substrate, a data wiring intersecting the gate wiring, a pixel electrode arranged in the unit pixel area defined by the gate wiring and the data wiring, and the gate wiring and data. It includes a switching element for switching wiring to a pixel electrode and a shield electrode. The shield electrode is formed above the gate wiring and the data wiring, and the shield electrode is formed with a first opening that partially exposes the gate wiring. The second substrate includes an upper substrate facing the lower substrate and a common electrode formed on the upper substrate facing the pixel electrodes.</p><p num="0012"> In one embodiment, the first substrate further comprises a protective insulating film covering the gate wiring, the data wiring, and the switching element. The pixel electrode and the shield electrode are formed on the protective insulating film. The inner edge of the shield electrode formed by the first opening overlaps the gate wiring, and the outer edge of the shield electrode is located between the edge of the pixel electrode and the edge of the gate wiring. A second opening corresponding to the first opening is formed in the common electrode. The inner edge of the common electrode formed by the second opening is arranged between the inner edge and the outer edge of the shield electrode. The second substrate further includes a light blocking pattern, a color filter, and an overcoat film. The light blocking pattern is formed on the upper substrate corresponding to the gate wiring, the data wiring, and the switching element. The color filter is formed corresponding to the unit pixel area. The protective film covers the light blocking pattern and the color filter, and the common electrode is formed on the protective film. A first domain division pattern is formed on the pixel electrode, and a second domain division pattern is formed on the common electrode, which is alternately arranged with the first domain division pattern.</p><p num="0013"> According to the display board of the present invention and the display panel having the same, it is possible to reduce the gate delay and realize a good quality image in the display panel having a large size and high resolution.</p>

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display board will be described below with reference to FIGS. 1 to 3. FIG. 1 is a plan view of a display board according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the display board illustrated in FIG. 1 cut along the line II ́.

Referring to FIGS. 1 and 2, the display board 100 includes a base board 110, a gate wiring GL, a pair of data wirings DL1, DL2, a pixel electrode PE, and a shield electrode SC.

The base substrate 110 may be formed of optically isotropic glass. A plurality of unit pixel regions arranged in a matrix shape are arranged on the base substrate 110. The unit pixel area is arranged by a certain arrangement method such as a matrix shape and a mosaic shape.

The gate wiring GL extends between the unit pixel regions on the base substrate 110. The data wiring DL1 and DL2 are arranged on the base substrate 110 on which the gate wiring GL is formed in a state of being insulated from the gate wiring GL. The data wiring DL1 and DL2 intersect the gate wiring GL and are extended between the unit pixel areas. The gate wiring GL may be formed of, for example, aluminum (Al), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), silver (Ag), or the like.

In order to reduce the delay of the control signal applied to the gate wiring GL, the gate wiring GL is preferably formed of a metal having a small resistance value, and the gate wiring GL preferably has a large cross-sectional area. However, if the line width of the gate wiring GL is very large, the aperture ratio of the unit pixel area decreases, and if the thickness of the gate wiring GL is very thick, the formation of other layers formed on the upper part of the gate wiring GL is formed. It won't be easy. In this embodiment, the gate wiring GL has a first width. On the other hand, in order to reduce the overlapping area between the gate wiring GL and the data wiring DL, the width of the gate wiring GL is reduced at the intersection intersecting the data wiring DL, and the width of the data wiring DL is increased. It is preferable to reduce at the intersection where the gate wiring GL intersects.

A thin film transistor is formed in each unit pixel region. The thin film transistor is electrically connected to the gate wiring GL and the data wirings DL1 and DL2. Each thin film is arranged along each gate wiring GL or each data wiring DL1 and DL2, is electrically connected to the gate wiring GL and data wiring DL1 and DL2, and is electrically connected to the data wiring DL1 by a control signal applied from the gate wiring GL. , Outputs the pixel voltage applied from DL2.

In this embodiment, one gate wiring GL and two data wirings DL1 and DL2 correspond to one unit pixel area. Therefore, the thin film transistor will be described focusing on the unit pixel region. The two data wiring DL1 and DL2 corresponding to the unit pixel area are defined as the first data wiring DL1 and the second data wiring DL2, respectively. The thin film transistor connected to the first data wiring DL1 is defined as the first thin film transistor TFT1, and the thin film transistor connected to the second data wiring DL2 is defined as the second thin film transistor TFT2. Since the layered structures of the first and second thin film transistors TFT1 and TFT2 are the same, the layered structure will be described centering on the first thin film transistor TFT1 illustrated in FIGS. 1 and 2 for convenience of explanation.

As shown in FIGS. 1 and 2, the first thin film transistor TFT1 includes a first gate electrode GE1, a gate insulating film 120, a first active layer AL1, a first ohmic contact layer OL1, a first source electrode SE1, and a first drain. Includes electrode DE1.

The first gate electrode GE1 protrudes from the gate wiring GL. The gate insulating film 120 is formed on the base substrate 110 on which the gate wiring GL is formed. The first active layer AL1 is made of a semiconductor such as amorphous silicon and is formed on the gate insulating film 120 corresponding to the first gate electrode GE1.

The first source electrode SE1 is a portion of the first data wiring DL1 that overlaps with the first active layer AL1 and has a U-shape as an example. The first drain electrode DE1 is formed in the same layer as the first source electrode SE1 so as to be separated from the first source electrode SE1. As an example, the first drain electrode DE1 is arranged in the middle of the first source electrode SE1 having a U shape. Therefore, the first drain electrode DE1 partially overlaps with the first active layer AL1 and extends along the first data wiring DL1. The first ohmic contact layer OL1 is made of, for example, amorphous silicon doped with n-type impurities, between the first active layer AL1 and the first source electrode SE1, and between the first active layer AL1 and the first drain electrode. Formed with DE1 respectively.

The display substrate 100 further includes a passivation layer 130 and a protective insulating film 140.

The passivation layer 130 covers the first thin film transistor TFT1, the second thin film transistor TFT2, the first data wiring DL1, the second data wiring DL2, and the gate insulating film 120.

The protective insulating film 140 is formed on the passivation layer 130 to flatten the surface. In this embodiment, the protective insulating film 140 is an organic insulating film 140 that maintains the hue of the light incident on the base substrate 110 as it is. In another embodiment different from this, the protective insulating film 140 may be a color filter having different hues for each unit pixel area. Here, any one of the passivation layer 130 and the protective insulating film 140 may be omitted.

The pixel electrode PE is formed in a unit pixel region on the organic insulating film 140. The pixel electrode PE is made of a transparent conductive material, and, for example, is made of indium tin oxide (ITO), indium zinc oxide (IZO), amorphous indium tin oxide (a-ITO), and the like.

In this embodiment, the pixel electrode PE includes a first sub-electrode SPE1 and a second sub-electrode SPE2 that are electrically separated from each other. A domain division pattern DDP is formed on the first sub-electrode SPE1 and the second sub-electrode SPE2. In this embodiment, the domain division pattern DDP is an opening pattern in which a part of the first sub-electrode SPE1 and the second sub-electrode SPE2 is removed in a V shape. In another embodiment different from this, the domain division pattern DDP may be a protrusion pattern.

The first sub-electrode SPE1 is electrically connected to the first drain electrode DE1 of the first thin film transistor TFT1 through the first contact hole 142 formed in the organic insulating film 140, and the second sub-electrode SPE2 is passed through the second contact hole 144. It is electrically connected to the second drain electrode DE2 of the second thin film transistor TFT2.

The display board 100 further includes a storage wiring STL. The storage wiring STL may be formed in the same layer as the gate wiring GL and may be arranged parallel to the gate wiring GL so as to cross the unit pixel area. The width of the portion of the storage wiring STL corresponding to the unit pixel region increases to form the storage electrode STE.

FIG. 3 is a cross-sectional view of the display board illustrated in FIG. 1 cut along the II-II ́ line.

With reference to FIGS. 1, 2, and 3, the shield electrode SC is formed of the same substance as the pixel electrode PE on the organic insulating film 140, similarly to the pixel electrode PE. The shield electrode SC is formed correspondingly between the unit pixel regions. Therefore, the shield electrode SC is formed on the gate wiring GL and the data wirings DL1 and DL2. The shield electrode SC corresponding to the gate wiring GL has a second width W2 larger than the first width W1 of the gate wiring GL and completely covers the gate wiring GL. The outer edge of the shield electrode SC is arranged between the edge of the pixel electrode PE and the edge of the gate wiring GL.

In this embodiment, the gate wiring GL and the pixel electrode PE and the data wiring DL1 and DL2 and the pixel electrode PE are not overlapped on the plan view, but are formed close to each other on a number to several tens of microscales. Therefore, a first parasitic capacitor is formed between the gate wiring GL and the pixel electrode PE using the gate insulating film 120, the passivation film 130, and the organic insulating film 140 as dielectrics, and the data wirings DL1, DL2 and the pixel electrode PE A second parasitic capacitor is formed between them.

Since the shield electrode SC is formed on the gate wiring GL and the data wirings DL1 and DL2, a third parasitic is formed between the shield electrode SC and the gate wiring GL and between the shield electrode SC and the data wirings DL1 and DL2. A capacitor is formed. When the third parasitic capacitor is formed, the size of the first parasitic capacitor and the second parasitic capacitor becomes very small. Therefore, the degree to which the pixel voltage applied to the pixel electrode PE by the first parasitic capacitor and the second parasitic capacitor is distorted and the degree to which the data signal is distorted are reduced.

On the other hand, in order to reduce the gate signal delay, it is preferable that the parasitic capacitor formed in the gate wiring GL is small. Therefore, it is preferable to reduce the third parasitic capacitor as well.

In this embodiment, the shield electrode SC formed on the upper part of the gate wiring GL is formed with an opening OP from which a part of the shield electrode SC is removed. The opening OP extends long along the gate wiring GL and has a third width W3 that is smaller than the first width W1 of the gate wiring GL. The opening OP is formed so as to completely overlap the gate wiring GL. That is, the inner edge of the shield electrode SC formed by the opening OP overlaps with the gate wiring GL. That is, the third width W3 (overall width) of the opening OP is arranged directly on the first width W1 of the gate wiring GL. Therefore, even if an opening OP is formed in the shield electrode SC, a part of the shield electrode SC overlaps with the gate wiring GL, so that a third parasitic capacitor is formed, and as a result, the first parasitic capacitor and the second parasitic capacitor are formed. The effect of blocking the formation of the capacitor remains.

The larger the overlapping area between the shield electrode SC and the gate wiring GL, the smaller the separation interval between the shield electrode SC and the gate wiring GL, and the dielectric constant of the gate insulating film 120, the passage film 130, and the organic insulating film 140. The larger the value, the more the third parasitic capacitor increases.

In this embodiment, the opening OP formed on the shield electrode SC significantly reduces the third parasitic capacitor. Further, even if the line width of the gate wiring GL is increased, the third parasitic capacitor hardly increases due to the opening OP formed in the shield electrode SC. Therefore, the line width of the gate wiring GL can be increased to reduce the resistance of the gate wiring GL, and the opening OP formed in the shield electrode SC reduces the third parasitic capacitor and reduces the gate signal delay. it can.

The display panel will be described below with reference to FIGS. 4 to 9. FIG. 4 is a plan view of a display panel according to an embodiment of the present invention.

Referring to FIG. 4, the display panel 500 includes a first substrate 501, a second substrate 601 and a liquid crystal layer LC interposed between the first substrate and the second substrate 601. The first substrate 501 is substantially the same as the display substrate 100 illustrated in FIGS. 1 to 3.

Therefore, when observing with reference to the unit pixel area, the first substrate 501 has the lower substrate 510, the gate wiring GL arranged on the lower substrate 510, the first data wiring DL1 and the second data intersecting with the gate wiring GL. The wiring DL2, the gate wiring GL, the pixel electrode PE arranged in the unit pixel area defined by the first data wiring DL1 and the second data wiring DL2, the gate wiring GL, the first data wiring DL1, and the second data. It includes a first thin film transistor TFT1 and a second thin film transistor TFT2 for switching the wiring DL2 to the pixel electrode PE, and a shield electrode SC formed between the unit pixel regions.

The shield electrode SC is formed above the gate wiring GL, the first data wiring DL1 and the second data wiring DL2, and the first opening OP1 is formed in the shield electrode SC corresponding to the gate wiring GL.

The lower substrate 510, the first domain division pattern DDP1 formed on the pixel electrode PE, and the first opening OP1 formed on the shield electrode SC are the base substrate 110, the domain division pattern DDP, and the domain division pattern DDP shown in FIGS. 1 to 3. Corresponds to each opening OP.

FIG. 5 is a plan view of the second substrate of the display panel illustrated in FIG. FIG. 6 is a cross-sectional view of the display panel illustrated in FIG. 4 cut along the line III-III ́. FIG. 7 is a cross-sectional view of the display panel illustrated in FIG. 4 cut along the IV-IV ́ line.

With reference to FIGS. 5, 6 and 7, the second substrate 601 includes an upper substrate 610 facing the lower substrate 510 of the first substrate 501, a light blocking pattern BM, a color filter 620, an overcoat film 630, and common. Includes electrode 640.

The light blocking pattern BM is formed in the first region (plane) of the upper substrate 610 facing the lower substrate 510. As shown in FIG. 4, the light blocking pattern BM includes a boundary region between unit pixel regions, a first thin film transistor TFT1, a second thin film transistor TFT2, a gate wiring GL, a first data wiring DL1, a second data wiring DL2, and a storage wiring. Cover STL. The light blocking pattern BM defines an opening having a shape corresponding to a unit pixel region. The light blocking pattern BM preferably contains an organic substance, but may also contain an inorganic substance such as chromium (Cr).

The color filter 620 is formed in the opening and partially overlaps with the light blocking pattern BM. The color filter 620 is one of a red color filter, a green color filter, and a blue color filter. The red color filter, the green color filter, and the blue color filter are arranged by a predetermined arrangement method such as a stripe type and a mosaic type.

Unlike this embodiment, when the color filter 620 is formed on the first substrate 501 instead of the organic insulating film 540 formed on the passivation film 530, the color filter may be omitted on the second substrate 601. ..

The overcoat film 630 covers and protects the color filter 620 and the light blocking pattern BM, and flattens the surface of the second substrate 601. The overcoat film 630 is preferably made of a transparent organic substance.

The common electrode 640 is formed on the overcoat film 630 with the same material as the pixel electrode PE. A second domain division pattern DDP2, for example, an aperture pattern is formed on the common electrode 640 corresponding to the unit pixel region. The first domain division pattern DDP1 and the second domain division pattern DDP2 are arranged alternately. As a result, the unit pixel area is divided into a plurality of domains. Here, the domain is defined as a region divided by a position where the arrangement direction of the liquid crystal changes discontinuously as a boundary.

When the gate wiring GL and the common electrode 640 overlap, a fourth parasitic capacitor is formed in the gate wiring GL, and the fourth parasitic capacitor increases the gate signal delay. In this embodiment, in order to reduce the overlapping area between the gate wiring GL and the common electrode 640, a part of the common electrode 640 corresponding to the gate wiring GL is removed to form the second opening OP2. .. The second opening OP2 corresponds to the first opening OP1 formed on the shield electrode SC.

As shown in FIG. 6, the liquid crystal layer LC is interposed between the first substrate 501 and the second substrate 601. The liquid crystal molecules contained in the liquid crystal layer LC in the domains adjacent to each other are arranged in different directions. This increases the viewing angle of the light emitted from one unit pixel area.

FIG. 8 is an enlarged view of the first region illustrated in FIG. FIG. 9 is a cross-sectional view taken along the VV ́ line illustrated in FIG.

With reference to FIGS. 8 and 9, the gate wiring GL has a first width W1. The shield electrode SC covering the gate wiring GL has a second width W2 larger than the first width W1 and is separated from the pixel electrode PE. Therefore, the outer edge of the shield electrode SC is arranged between the edge of the pixel electrode PE and the edge of the gate wiring GL.

The shield electrode SC corresponding to the gate wiring GL is formed with a first opening OP1 extending long along the gate wiring GL. The first opening OP1 has a third width W3 that is smaller than the first width W1. The first opening OP1 completely overlaps with the gate wiring GL. Therefore, the inner edge of the shield electrode SC formed by the first opening OP1 overlaps the gate wiring GL.

By forming the first opening OP1, the number of third parasitic capacitors formed between the shield electrode SC and the gate electrode is significantly reduced. By forming the third parasitic capacitor, the formation of the first parasitic capacitor is suppressed between the pixel electrode PE and the gate wiring GL, and the distortion of the pixel voltage applied to the pixel electrode PE and the gate signal delay are reduced.

On the other hand, as described above, the second opening OP2 is formed on the common electrode 640 in the region corresponding to the gate wiring GL, and the formation of the fourth parasitic capacitor formed between the gate wiring GL and the common electrode 640 is suppressed. .. In order to suppress the formation of the fourth parasitic capacitor, it is preferable that the common electrode 640 and the gate wiring GL do not overlap.

In this embodiment, the second opening OP2 has a fourth width W4 that is larger than the first width W1 of the gate wiring GL and extends along the gate wiring GL longer than the first opening OP1. That is, the third width W3 (overall width) of the first opening OP1 is arranged directly on the first width W1 of the gate wiring GL, and the overall width of the gate wiring GL is the fourth of the second opening OP2. Placed directly under width W4. Therefore, the first opening OP1 is arranged inside the second opening OP2 on the plan view, and the inner edge of the common electrode 640 formed by the second opening OP2 is the edge of the gate wiring GL and the outer edge of the shield electrode SC. It is placed between and.

Even if the line width of the gate wiring GL is increased, the third parasitic capacitor is hardly increased by the first opening OP1, and the formation of the fourth parasitic capacitor is suppressed by the second opening OP2.

As described in detail above, according to the present invention, the gate wiring formed on the display panel in order to suppress signal interference between the pixel electrode and the gate wiring and between the pixel electrode and the data wiring. And a shield electrode separated from the pixel electrode is formed on the upper part of the data wiring. An opening is formed in the shield electrode and the common electrode corresponding to the gate wiring, and the size of the parasitic capacitor formed in the gate wiring can be significantly reduced. As a result, the line width of the gate wiring can be increased without increasing the parasitic capacitor, and the gate signal delay can be significantly reduced.

The present invention has been described in detail by way of examples of the present invention, but the present invention is not limited to this, and any person who has ordinary knowledge in the technical field to which the present invention belongs can keep the idea and spirit of the present invention. The present invention can be modified or modified.

<figref num="1">It is a top view of the display board according to one Example of this invention.</figref><figref num="2">It is sectional drawing which cut | cut the display board illustrated in FIG. 1 along the line II ́.</figref><figref num="3">It is sectional drawing which cut | cut the display board illustrated in FIG. 1 along the II-II ́ line.</figref><figref num="4">It is a top view of the display panel according to one Example of this invention.</figref><figref num="5">It is a top view of the 2nd substrate of the display panel illustrated in FIG.</figref><figref num="6">It is sectional drawing which cut | cut the display panel illustrated in FIG. 4 along the line III-III ́.</figref><figref num="7">It is sectional drawing which cut | cut the display panel illustrated in FIG. 4 along the IV-IV ́ line.</figref><figref num="8">It is an enlarged view of the 1st region illustrated in FIG.</figref><figref num="9">It is sectional drawing which cut | cut the display panel illustrated in FIG. 4 along the VV ́ line.</figref>

Code description

100 display board 110 base board 120 Gate insulating film 130 Passion membrane 140 Organic insulating film 500 display panel 620 color filter 630 Overcoat film 640 Common electrode GL gate wiring DL data wiring STL storage wiring TFT thin film transistor PE pixel electrode SPE sub-electrode OP opening BM light blocking pattern DDP domain split pattern SC shield electrode