Semiconductor Integrated Circuit Device

The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique useful for being applied to a semiconductor integrated circuit device including a CDR (Clock and Data Recovery) circuit.

For example, Patent Document 1 discloses a clock data recovery circuit that makes jitter tolerance and the like expandable. In this clock data recovery circuit, the edge of the data and the edge of the clock are compared, and when the interval falls below the reference value, the clock is regenerated by controlling the edge of the clock to move away from the edge of the data. There is.

Further, Non-Patent Document 1 describes a configuration of a transmission system using a duo binary transmission method. In this transmission system, binary data (1,0) from the transmitting side is transmitted to a receiving circuit by using a duo binary transmission method, and the clock signal and the data signal are reproduced in the receiving circuit. The reproduction of the clock signal is performed by the clock recovery circuit detecting the cross point at the intermediate amplitude level of the input signal. The reproduction of the data signal is performed by comparing and judging the amplitude of the input signal and the two reference voltages (intermediate amplitude level ± Vref) at the timing of the reproduced clock signal. Then, the ternary data (2,1,0) is obtained by this comparison judgment, and the original binary data (1,0) is reproduced by decoding this.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2004-180188</text></patcit><nplcit num="1"><text>12Gb / s Duobinary Signaling with x2 Oversampled Edge Equalization, 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 7, 2005, p.70-71</text></nplcit>

<p num="0004"> In recent years, as the transmission speed of inter-LSI or inter-board communication has rapidly increased, both data and clock are superimposed and transmitted on one signal line instead of the conventional parallel transmission method using a translational clock. The serial transmission method is widespread. In the serial transmission method, it is necessary to dramatically increase the transmission speed per signal line, but along with this, the attenuation of the high frequency component of the transmission signal becomes large due to the skin effect of the transmission line conductor or the dielectric loss of the insulating material. On the receiving side, the input waveform has a dependency on a code sequence called ISI (Inter Symbol Interference), and the signal quality deteriorates. Then, the eye pattern on the receiving side narrows in both the time axis direction (width) and the amplitude direction (height), which causes a reception error.</p><p num="0005"> As a method for realizing high-speed transmission while allowing the occurrence of such ISI, a duo binary transmission method as shown in Non-Patent Document 1 can be mentioned. FIG. 18 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device examined as the premise of the present invention. This semiconductor integrated circuit device reflects the characteristics of the receiving circuit shown in Non-Patent Document 1. The semiconductor integrated circuit apparatus shown in FIG. 18 includes a clock data reproduction circuit CDR, and the CDR is composed of a data reproduction circuit DR, a clock reproduction circuit CR, and a clock signal generation circuit CLK_GEN.</p><p num="0006"> The clock reproduction circuit CR latches the input data signal DIN by using the rising and falling edges of the clock signal CLK from CLK_GEN, and controls CLK_GEN by comparing the latch results. CLK_GEN outputs CLK with an appropriate phase based on the comparison result in CR. The data reproduction circuit DR sets different threshold values for DIN by the threshold value setting circuits VTSET_H and VTSET_L, and latches the outputs of VTSET_H and VTSET_L at the rising edge of CLK. Then, the data signal DATA is reproduced by outputting either of these two latch results via the selector circuit SEL. At this time, the value of the previous data signal DATA is used to select the SEL.</p><p num="0007"> FIG. 19 illustrates an example of the operation using the semiconductor integrated circuit device of FIG. 18, (a) is a waveform diagram showing the operation of the data reproduction circuit with respect to the input data signal, and (b) is the clock reproduction. It is a waveform diagram which shows the operation of a circuit. For example, when the duo binary transmission method as described above is used, the input data signal DIN in FIG. 18 has a waveform (eye pattern) as shown in FIG. 19 (a). However, the duobinary eye pattern associated with the duobinary transmission method may refer to a pattern in which the eye that is slightly open around the threshold value VT_C is closed in Fig. 19 (a). Those with small eyes open are sometimes called EE (Edge Equalize) -NRZ eye patterns. Since the embodiments described below are similarly applicable to both of these eye patterns, an eye pattern as shown in FIG. 19 (a) is referred to as a bipolar NRZ eye pattern in the present specification without distinguishing between them. I will decide.</p><p num="0008"> In the bipolar NRZ eye pattern, bits (signs) adjacent to each other in the time axis direction interfere with each other (that is, ISI occurs), so that the trajectory of the waveform differs depending on the bit pattern (code string). For example, in the data cycle t [-1], t [0], t [1] for 3 bits, if the'L'level is continuous for 3 bits, the trajectory from t [0] to t [1]. Is the lower straight orbit indicated by (LLL). At this time, there are two types of orbits from t [-1] to t [0], an orbit that passes through the lower straight line and an orbit that descends to the right. It depends on the value of the bit in 2].</p><p num="0009"> In addition, when the'L'level becomes the'H'level after 2 bits in a row, the orbit from t [0] to t [1] is the orbit that rises upward as shown by (LLH). Become. In this case as well, as in the case of (LLL), the orbit from t [-1] to t [0] is determined by the value of the bit at t [-2]. In this way, the other bit patterns also follow the orbits shown in (LHL), (LHH), ..., (HHH) in FIG. 19 (a), respectively.</p><p num="0010"> In such an eye pattern, it is desirable to determine the value of each bit using two threshold values VT_H and VT_L. That is, when focusing on t [0], when the bit value of t [-1] is at the'H'level, the eye opens in a relatively wide area surrounded by the thick dotted line in Fig. 19 (a). Even at the'L'level, the eye opens in a relatively wide area surrounded by a dashed line. Therefore, if the bit value of t [-1] is at the'H'level, the sign of'H'/' L'is determined based on VT_H, which is larger than the intermediate level threshold VT_C at t [0]. If the level is'L', the judgment margin can be sufficiently secured by performing the code judgment based on VT_L smaller than VT_C at t [0].</p><p num="0011"> Therefore, in the configuration of FIG. 18, the threshold value VT_H is set by the threshold value setting circuit VTSET_H, and VT_L is set by VTSET_L. Specifically, different offset voltages are applied to DIN with VTSET_H and VTSET_L, and these outputs are latched by latch circuits FF181 and FF182 with the same threshold voltage, respectively, to determine the code at different thresholds. Has been realized. The output of FF181 and the output of FF182 are input to the selector circuit SEL, and the selection of this SEL is performed by adding the delay to the output of the SEL (that is, the reproduced data signal DATA) by the one-cycle delay circuit DLY181. This makes it possible to select either the output of FF181 (latch result at VT_H) or the output of FF182 (latch result at VT_L) according to the previous code.</p><p num="0012"> On the other hand, the latch timing in the latch circuits FF181 and FF182 is determined by the clock signal CLK controlled by the clock reproduction circuit CR. In CR, the operation as shown in Fig. 19 (b) is performed. In FIG. 19 (b), as shown in Non-Patent Document 1, the edge of DIN is detected at the intermediate level threshold value VT_C in the eye pattern of FIG. 19 (a), and the phase of CLK is adjusted. There is. That is, as can be seen from FIG. 19A, the latch timing at FF181 and FF182 should be the timing at the point where a plurality of waveform trajectories cross on VT_C. Therefore, in order to match the rising timing TGe of CLK with this cross point, as shown in FIG. 19 (b), the rising timing TGe of CLK and the falling timings TGd and TGf on both sides thereof are used.</p><p num="0013"> In the example of FIG. 19 (b), when the DIN code is determined using VT_C as the reference voltage, it is determined to be'L'at the rising timing TGe of CLK, and it is also determined to be'L'at the falling timing TGd to the left of it. It is judged as'H'at the falling edge TGf on the right side. Therefore, it can be seen that there is a cross point (DIN edge) between TGe judged to have a different code and TGf to the right of it, and the phase of CLK should be shifted to the right so as to match this edge. I understand. In this specification, the method of adjusting to the edge in this way is referred to as an edge matching method.</p><p num="0014"> Further, in the present specification, as shown in FIG. 21, when there is an edge of the data signal between the clock timing TG2 to be matched and the clock timing TG1 for phase comparison located to the left of the clock timing TG2, the phase is It is assumed that the comparison signal EARLY is generated. On the other hand, if there is an edge of the data signal between TG2 and the clock timing TG3 for phase comparison located to the right of TG2, it is assumed that the phase comparison signal LATE is generated. In the example of FIG. 19 (b), since the edge of DIN exists between TGe and TGf, LATE is generated, and CLK is corrected to the right in response to this.</p><p num="0015"> In order to realize such an operation, in the configuration of FIG. 18, the DIN in which the threshold value is not set is latched by the latch circuit FF184 at the rising edge of CLK, and by the latch circuit FF183 at the falling edge of CLK. Then, by comparing the output of FF184 and the output of FF183 with the EXOR circuit EOR181, the latch result of DIN at the rising timing TGe in FIG. 19 (b) and the falling timing TGf to the right of it is compared. In addition, by comparing the output of FF184 and the signal delayed by the one-cycle delay circuit DLY182 with the EXOR circuit EOR182, the latch result of DIN at the rising timing TGe and the falling timing TGd to the left of it can be obtained. I'm comparing. The clock signal generation circuit CLK_GEN reflects these comparison results and generates a phase-corrected CLK.</p><p num="0016"> However, in such a configuration, there is a possibility that sufficient resistance (margin) to DIN waveform variation cannot be secured. FIG. 20 is a waveform diagram showing an actual state of the eye pattern shown in FIG. 19 (a). As can be seen from FIG. 20, each waveform trajectory shown in FIG. 19 (a) actually has a variation, and in particular, at the cross point on VT_C where most of the waveform trajectories intersect, the variation overlaps and is relative. Large variations will occur. Therefore, when trying to match the rising edge of CLK with respect to this cross point using the clock reproduction circuit CR of FIG. 18, the phase of CLK output from CLK_GEN also fluctuates greatly, and along with this, the DR There is a risk that the correct DATA cannot be played back, or the proper CLK cannot be played back by CR.</p><p num="0017"> Therefore, one of the objects of the present invention is to provide a semiconductor integrated circuit device having a sufficient margin with respect to variations in input waveforms. The above-mentioned and other purposes and novel features of the present invention will be clarified from the description and the accompanying drawings of the present specification.</p>

<p num="0018"> A brief description of typical inventions disclosed in the present application is as follows.</p><p num="0019"> The semiconductor integrated circuit device of the present invention includes a clock data reproduction circuit. The clock data reproduction circuit latches the input data signal with a plurality of threshold values different depending on the clock signal as a logic criterion, and processes the latch result to select a candidate consisting of a combination of the reproduction data signal and the phase comparison signal. It includes a second circuit that outputs two types and a third circuit that selects and outputs one of these two types of candidates. The third circuit is characterized in that which candidate is selected in the data cycle of interest is determined based on the code of the reproduced data signal in the previous data cycle.</p><p num="0020"> In this way, not only the reproduced data signal but also the phase comparison signal in the data cycle of interest is selected and determined based on the code of the reproduced data signal in the previous data cycle, so that the phase comparison signal can be selected as in the conventional case. It is possible to improve the margin for the variation of the input waveform as compared with the case where there is no child (for example, when it is determined only by the latch result at one threshold value).</p>

<p num="0021"> Briefly explaining the effects obtained by typical inventions disclosed in the present application, it is possible to realize a semiconductor integrated circuit device including a clock data reproduction circuit having a sufficient margin for variations in input waveforms. It becomes.</p>

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. There is a relationship of some or all modifications, details, supplementary explanations, etc. In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of a component or the like, the shape is substantially the same unless otherwise specified or when it is considered that it is not apparent in principle. Etc., etc. shall be included. This also applies to the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiment, in principle, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a block diagram showing an example of the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention. The semiconductor integrated circuit apparatus of the first embodiment includes a clock data reproduction circuit CDR. The CDR is composed of a clock data determination circuit CD_JGE and a clock signal generation circuit CLK_GEN. CD_JGE is composed of a plurality of threshold setting circuits VTSET1 to VTSETn (n 2), a logic circuit LOG, a selector circuit SEL, and a one-cycle delay circuit DLY1. CD_JGE determines the code of the input data signal DIN at the timing of the clock signal CLK, outputs the reproduced data signal DATA, compares and determines whether the phase of CLK is appropriate for the phase of DIN, and compares the phase as a result. Output signals EARLY and LATE toward CLK_GEN. CLK_GEN outputs a phase-corrected CLK based on EARLY and LATE. This CLK is input to the LOG and is also used as a reproduction clock signal.

VTSET1 to VTSETn set different threshold voltages for DIN. LOG latches the signals for which these threshold voltages are set by CLK, performs various judgments and other processes on the latch results, and performs two types of signal groups consisting of a combination of data signals and phase comparison signals { Output (DATA1, EARLY1, LATE1) and (DATA0, EARLY0, LATE0)} as candidates. SEL selects and outputs one of these two candidates. This selected data signal becomes the reproduced data signal DATA, and the selected phase comparison signals EARLY and LATE become the output signal toward CLK_GEN. Here, the SEL is selected with the value obtained by delaying the reproduced data signal DATA by one cycle by DLY1. That is, the reproduced data signal DATA and the phase comparison signals EARLY and LATE in the data cycle of interest are determined based on the values of the reproduced data signal DATA in the previous data cycle.

This configuration is different from the configuration of FIG. 18 described above, and the phase comparison signals EARLY and LATE in addition to the reproduced data signal DATA of the data cycle of interest are also determined based on the value of the reproduced data signal DATA of the previous data cycle. Is the main feature. This makes it possible to improve the margin for waveform variation of the input data signal DIN, which will be described in detail later.

FIG. 2 is a circuit diagram showing a detailed configuration example of the semiconductor integrated circuit device of FIG. In the semiconductor integrated circuit device shown in FIG. 2, the clock data determination circuit CD_JGE2 is composed of two threshold setting circuits VTSET_H and VTSET_L, a logic circuit LOG2, a selector circuit SEL, and a one-cycle delay circuit DLY1. There is. LOG2 receives the output of VTSET_H and makes various comparison judgments, and outputs the signal group (DATA1, EARLY1, LATE1). The comparison circuit CMP21 and the signal group (DATA0, EARLY0, LATE0) which also receives the output of VTSET_L The output comparison circuit CMP22 is included.

VTSET_H and VTSET_L are, for example, circuits that apply different offset voltages to the input data signal DIN. Here, it is assumed that VTSET_H has a smaller offset voltage value than VTSET_L. When the output from VTSET_H and the output from VTSET_L are judged at the same voltage level, judging the output of VTSET_H is equivalent to judging at the threshold voltage relatively high with respect to DIN, and the output of VTSET_L is determined. Judgment is equivalent to judging at a threshold voltage that is relatively low relative to DIN.

The comparison circuit CMP21 is composed of latch circuits FF20 to FF22 and EXOR circuits EOR20 and 21. The FF20 latches the output of VTSET_H at the rising timing of the clock signal CLK_0 from CLK_GEN. FF21 latches the output of VTSET_H at the rising timing of the clock signal CLK_90 from CLK_GEN, and FF22 latches the output of VTSET_H at the falling timing of CLK_90. Note that CLK_90 is 90 degrees out of phase with CLK_0. The EOR20 performs an EXOR operation on the output of FF20 and the output of FF21, and outputs the result as a phase comparison signal EARLY1. EOR21 performs EXOR calculation on the output of FF20 and the output of FF22, and outputs the result as the phase comparison signal LATE1. The output of FF20 is the data signal DATA1.

The comparison circuit CMP22 also has the same configuration as the CMP21 except that the input / output destinations are different, and is composed of the latch circuits FF23 to FF25 and the EXOR circuits EOR22 and 23. FF23 latches the output of VTSET_L at the rising timing of CLK_0. The FF24 latches the output of VTSET_L at the rising timing of CLK_90, and the FF25 latches the output of VTSET_L at the falling timing of CLK_90. The EOR22 performs an EXOR operation on the output of FF23 and the output of FF24, and outputs the result as a phase comparison signal EARLY0. EOR23 performs EXOR calculation on the output of FF23 and the output of FF25, and outputs the result as the phase comparison signal LATE0. The output of FF23 is the data signal DATA0.

FIG. 3 illustrates an operation example of the semiconductor integrated circuit device of FIG. 2, (a) is a waveform diagram showing the operation of data reproduction and clock reproduction with respect to an input data signal, and (b) is a waveform diagram showing the operation of clock reproduction. It is a waveform diagram which shows a more detailed operation. In the configuration of FIG. 2, as shown in FIG. 3 (a), the threshold value VT_H is higher than the intermediate level and lower in the data cycle t [-1], t [0], t [1] for 3 bits. Code determination and phase comparison are performed at both thresholds VT_L. Then, which of the judgment / comparison result in VT_H and the judgment / comparison result in VT_L is used is determined according to the value of the reproduction data (that is, the sign judgment result) of the previous data cycle.

For example, if t [0] is the data cycle of interest, if the sign judgment result at t [-1] is'H', the judgment / comparison result at VT_H is selected, and if it is'L'. Selects the judgment / comparison result in VT_L. Here, as the phase comparison method, unlike the edge matching method described in FIG. 19, a method as described in Patent Document 1 described above (referred to as an eye track method in the present specification) is used. In the eye track method, as shown in Fig. 3 (a), only a predetermined time (here, 1/4 of the data cycle time (= phase 90 degrees)) is set from the latch timing ( mark) TGb for code determination. Latch timings (x mark) TGa and TGc for phase comparison are provided at separated positions, and the clock phase is controlled so that the latch results at these three timings are all the same.

To explain this conceptually, when t [0] is the data cycle of interest, as described in FIG. 19, when the sign determination result at t [-1] is'H', it is indicated by a thick dotted line. The eye opens, but control is performed so that all ( marks) and (x marks) on VT_H are included in this eye. Similarly, if the sign judgment result at t [-1] is'L', the eye indicated by the alternate long and short dash line opens, but the ( mark) and (x mark) on VT_L are in this eye. Control to enter everything.

In order to perform such an eye-track phase comparison, in the configuration example of FIG. 2, the operation as shown in FIG. 3B is performed using two clock signals CLK_0 and CLK90. In the example of FIG. 3B, for example, assuming that the sign determination result of the previous data cycle is'H', the phase comparison is performed at the position of VT_H in the data cycle of interest. Specifically, with VT_H as the threshold value, DIN latch is performed between the rising timing TGa of CLK_90, the next falling timing TGc, and the rising timing TGb of CLK_0. In this example, the latch result on TGa is'L', the latch result on TGb is'H', and the latch result on TGc is'H'. Therefore, the clock signals CLK_0 and CLK90 are controlled to be shifted to the right so that all of these latch results are'H'.

In the comparison circuit CMP21 of FIG. 2, the latch result at TGa corresponds to the output of FF21, the latch result at TGb corresponds to the output of FF20, and the latch result at TGc corresponds to the output of FF22. If the comparison result of EOR20 between the output of FF20 and the output of FF21 is different, EARLY1 becomes'H'. EARLY in the eye track method means that the timing TGb and the like in FIGS. 3 (a) and 3 (b) are too biased to the left. Therefore, if the sign determination result of the previous data cycle is'H'and the'H' of this EARLY1 is output to EARLY via the selector circuit SEL, CLK_GEN controls to shift CLK_0 and CLK90 to the right. Is done.

On the other hand, if the comparison result of EOR21 between the output of FF20 and the output of FF22 is different, LATE1 becomes'H'. LATE in the eye track method means that the timing TGb and the like in FIGS. 3 (a) and 3 (b) are too biased to the right. Therefore, if the sign determination result of the previous data cycle is'H'and the'H' of LATE1 is output to LATE via the selector circuit SEL, CLK_GEN controls to shift CLK_0 and CLK90 to the left. Is done. When the data of the previous data cycle is'H', the output of FF20 (the latch result of the timing TGb in FIG. 3) is output as the reproduced data signal DATA via the SEL. In the edge alignment method as described in FIG. 19B, the control is performed so as to shift the clock signal to the right when LATE occurs, but in the eye track method, the control direction is reversed.

Similarly, in the comparison circuit CMP22, the latch results at TGa, TGb and TGc correspond to the outputs of FF24, FF23 and FF25, respectively. If the comparison result of EOR22 of FF23 and FF24 is different, EARLY0 becomes'H', and if the comparison result of EOR23 of FF23 and FF25 is different, LATE0 becomes'H'. Therefore, when the data of the previous data cycle is'L'and the'H' of EARLY0 or LATE0 is output to EARLY or LATE via SEL, the phase control as described above is performed by CLK_GEN. When the data of the previous data cycle is'L', DATA0 from FF23 is output as the reproduced data signal DATA via SEL.

As described above, by using the configurations and operations as shown in FIGS. 2 and 3, it is possible to improve the margin for the waveform variation of the input data signal DIN. That is, for example, when the sign determination result at t [-1] in FIG. 3 (a) is'H', at t [0], it corresponds to the eye shown by the thick dotted line at the position of the threshold value VT_H. The phase comparison result may be generated for a limited number of waveform trajectories. Therefore, the amount of variation of the waveform orbits related to this phase comparison is relatively small compared to the amount of variation at the cross point on VT_C where almost all the waveform orbits intersect, as described in FIGS. 19 and 20. , The phase variation of the reproduction clock signal (CLK_0, CLK_90) output from CLK_GEN is also small.

Further, in the phase comparison method shown in FIGS. 2 and 3, as can be seen from FIG. 3 (a) and the like, the eye indicated by the thick dotted line is targeted at the position of VT_H, and the eye indicated by the dashed line is indicated at the position of VT_L. The phase of the clock signal is adjusted to the timing at which the code can be accurately determined while actually monitoring each eye. On the other hand, the phase comparison method as described in FIGS. 19 and 20 can be said to be a method of adjusting the phase of the clock signal without actually monitoring the eye. Therefore, as compared with the phase comparison method as described with reference to FIGS. 19 and 20, it is possible to match the phase of the clock signal with the timing at which the sign can be determined more accurately.

Furthermore, by using the configurations and operations shown in FIGS. 2 and 3, the threshold values VT_H and VT_L in FIG. 3 can be easily set at any position in each eye where the margin becomes large. Become. For example, in the case of VT_H, ideally, the setting value with the largest margin in the time axis direction (horizontal axis) is the position where the (HHL) orbit and the (LHH) orbit intersect as shown in FIG. It is a set value that passes. However, in this case, for example, when the (HHL) trajectory varies in the voltage direction (vertical axis), the margin may decrease with respect to this vertical axis. In such a case, the set value of VT_H may be slightly lowered to approach the intermediate level (VT_C). In the configuration and operation of FIGS. 2 and 3, if the threshold value VT_H is set by VTSET_H, the clock signal CLK is automatically adjusted at the timing when a margin can be secured in the time axis direction at the threshold value. Therefore, any threshold value can be easily set.

Therefore, even if the DIN has a certain amount of waveform variation, the correct data signal or the correct clock signal can be reproduced, and the margin for the DIN waveform variation can be improved.

Next, an application example of the semiconductor integrated circuit device (clock data reproduction circuit CDR) of FIG. 1 will be described. FIG. 13 is a schematic view showing a configuration example of a transmission system to which the semiconductor integrated circuit device of FIG. 1 is applied. The transmission system shown in FIG. 13 is composed of a transmission circuit LSI_tx, a reception circuit LSI_rx, and a transmission line MS connecting them. LSI_tx is composed of, for example, one semiconductor chip, and transmits the transmission code string (transmission data) DATA_tx in synchronization with the clock signal CLK_tx from the transmission oscillation circuit PLL_tx. At this time, the transmission side equalization (Feed Forward Equalization) is often performed by the transmission side equalizer EQ. The signal subjected to this equalization processing is sent to the MS via the driver circuit DRV and the output pin Ptx.

On the other hand, LSI_tx is composed of, for example, one semiconductor chip, and receives a signal transmitted via the MS from the input pin Prx. At this time, the received signal from Prx becomes the bipolar NRZ eye pattern as described in FIG. 19 and the like. This received signal is amplified by the amplifier circuit AMP and input to the clock data reproduction circuit CDR. This CDR has the configuration as shown in FIG. 1 described above, and generates a reproduction data signal DATA and a reproduction clock signal CLK using one input data signal DIN. These generated signals are input to, for example, a FIFO (First In First Out) circuit (not shown), where synchronization with the internal clock signal of LSI_tx is performed.

Further, for the CDR, a plurality of clock signals CLK_φ1 to CLK_φ16 having different phases (here, 16 phases) are input from the receiving oscillation circuit PLL_rx. Here, the oscillation frequencies of PLL_tx and PLL_rx do not always exactly match. Therefore, the CDR reproduces the clock signal CLK by sequentially selecting an appropriate one phase based on DIN from the multi-phase clock signals CLK_φ1 to CLK_φ16 output by PLL_rx. At the same time, DIN code determination (that is, reproduction of data signal DATA) is also performed.

FIG. 14 is a perspective view showing an example of an implementation form of the transmission system shown in FIG. FIG. 14 shows an example of the internal configuration of a system such as a server, RAID (Redundant Array of Inexpensive Disks), and a router. It includes multiple daughter card CRDs, etc. that are connected to multiple connector CNs. One of the daughter card CRDs is equipped with a transmission circuit LSI_tx, and the other is equipped with a reception circuit LSI_rx, which transmits data from LSI_tx to LSI_rx via a transmission line on the MB. The length of this transmission line may reach, for example, about 1 m.

In such a case, high-speed communication can be realized by using the transmission method for receiving the bipolar NRZ eye pattern described above on the receiving circuit LSI_rx side. Furthermore, by applying the configuration shown in FIG. 1 to the clock data reproduction circuit CDR in LSI_rx, it is possible to improve the margin for jitter and the like of the transmission waveform, and it is possible to further increase the speed. Here, data transmission using the backplane main board MB is taken as an example, but of course, the data transmission is not limited to this, and for example, data between LSIs on the same printed board using a transmission line extending about 30 cm. A beneficial effect can be obtained even when applied to transmission or data transmission using a coaxial cable extending up to about 10 m.

FIG. 15 is a block diagram showing a configuration example of the clock data reproduction circuit in the transmission system of FIG. The clock data reproduction circuit CDR shown in FIG. 15 is phase-compared with the clock data determination circuit CD_JGE that receives the input data signal DIN and the reproduction clock signal CLK and outputs the reproduction data signal DATA and the phase comparison signals EARLY and LATE. It is composed of a clock signal generation circuit CLK_GEN that receives a signal and corrects CLK. This CD_JGE has the configuration and operation as shown in Fig. 1 and the like. Here, an example of the detailed configuration and operation of CLK_GEN included in FIG. 1 and the like will be described.

CLK_GEN is composed of a majority decision circuit M_JGE, a phase selection circuit PH_SEL, a clock signal selection circuit CK_SEL, a clock delay circuit CK_DLY, and the like. The majority decision circuit M_JGE aggregates the phase comparison signals EARLY and LATE output from CD_JGE for each data cycle for a plurality of data cycles, and outputs the phase control signal UP or DOWN by making a majority decision. For example, when the number of occurrences of EARLY is greater than the number of occurrences of LATE, DOWN, which is a control signal for delaying the phase of CLK, is output. In the opposite case, UP is output as a control signal that accelerates the phase of CLK.

The phase selection circuit PH_SEL is composed of, for example, a 16-bit shift register and performs operations such as right shift when UP is input and left shift when DOWN is input. One of the 16-bit selection signals S1 to S16 output by PH_SEL is activated, but the position of the activated selection signal moves according to a right shift or a left shift. The clock signal selection circuit CK_SEL selects a one-phase clock signal corresponding to the selection signals S1 to S16 from the 16-phase clock signals CK_φ1 to CK_φ16 from the reception oscillation circuit PLL_tx in FIG. 13, and selects the playback clock signal CLK. Output as. Further, for example, when two clock signals CLK_0 and CLK_90 are input to CD_JGE as shown in FIG. 2, the clock delay circuit CK_DLY adds a predetermined delay to the reproduction clock signal CLK. Supply to CD_JGE.

FIG. 16 is a schematic diagram illustrating an example of the operation of the clock signal generation circuit in the clock data reproduction circuit of FIG. The clock data reproduction circuit CLK_GEN receives the phase comparison signals EARLY and LATE and performs an operation of selecting one phase from the multiphase clock signals CK_φ1 to CK_φ16 so that the sign can always be determined at the center of the eye. In CK_φ1 to CK_φ16, CLK_φ [n + 1] is shifted in the same direction with respect to CLK_φ [n] by a predetermined phase (here, 22.5 (360/16) degrees). In the following, a case of performing phase comparison by the eye track method as described in FIG. 3 will be described as an example.

In the eye track method, when the rising timing of the reproduction clock signal CLK (that is, the timing of sign determination) and the edge in the input data signal waveform (DIN waveform) are too close to each other, the polyphase clock signal is sequentially shifted so as to move away from the edge. While selecting. In the example of FIG. 16, the clock signal CLK_φ1 is selected first. After that, in ST160, when the rising timing of the reproduction clock signal CLK and the rising edge of DIN approach each other, EARLY is output from CD_JGE and DOWN is output from M_JGE. As a result, CK_SEL selects the clock signal CLK_φ2 via PH_SEL and outputs CLK_φ2 as the reproduction clock signal CLK.

After that, also in ST161, it is determined that the rising timing of CLK and the rising edge of DIN are close to each other. Similarly, CK_SEL selects the clock signal CLK_φ3 and outputs CLK_φ3 as the reproduction clock signal CLK. On the other hand, in ST162, when the rising timing of CLK and the falling edge of DIN approach each other, LATE is output from CD_JGE and UP is output from M_JGE. As a result, CK_SEL selects the clock signal CLK_φ2 via PH_SEL and outputs CLK_φ2 as the reproduction clock signal CLK.

In FIG. 16, for ease of explanation, the operation is such that the result of phase comparison in one data cycle (bit rate Tc) is immediately reflected, but in reality, for example, as shown in FIG. It becomes an operation. FIG. 17 is an explanatory diagram that supplements the operation of FIG. In FIG. 17, a plurality of data cycles (plurality of bit rates Tc) are set as a phase detection period Tp, and the phase comparison results of each data cycle are averaged within this period. This corresponds to the operation of the majority decision circuit M_JGE in FIG. Further, the averaged result will be reflected in the reproduction clock signal CLK after the time required for reselecting the clock signal CK (clock delay Td) has passed. Therefore, the phase of the reproduction clock signal CLK is corrected for each clock control interval Tg which is Tp + Td.

As described above, by using the semiconductor integrated circuit device of the first embodiment, it is possible to improve the margin for the waveform variation of the input data signal. Further, by applying the semiconductor integrated circuit device of the first embodiment to a transmission system, high-speed transmission can be realized.

(Embodiment 2) In the second embodiment, a detailed configuration example different from that of FIG. 2 will be described in the semiconductor integrated circuit apparatus shown in FIG. In FIG. 2 described above, a configuration called a full rate is shown in which code determination or the like is performed using the rising timing of the clock signal CLK_0 in each data cycle. Unlike this, the semiconductor integrated circuit apparatus of the second embodiment is characterized in that it uses a configuration called a half rate. In the half-rate configuration, the frequency of the clock signal is reduced to half, and the sign determination or the like is performed using both the rising and falling timings.

FIG. 4 shows the details of FIG. 1 in the semiconductor integrated circuit apparatus according to the second embodiment of the present invention, (a) is a circuit diagram showing a configuration example thereof, and (b) is a selector logic in (a). It is explanatory drawing which shows the logical content of a circuit. FIG. 5 is a waveform diagram illustrating an operation example of code determination and phase comparison when a half-rate configuration is used in the semiconductor integrated circuit apparatus according to the second embodiment of the present invention, and FIG. 5A is an operation of FIG. An example is shown, and (b) shows other operation examples.

First, in order to facilitate understanding, the operation when the half-rate configuration is used will be described with reference to FIG. In the half-rate configuration, as shown in the bipolar NRZ eye pattern of the input data signal DIN in FIG. 5 (a), the operation is performed as if the phase comparison is partially omitted. In the full rate configuration shown in Fig. 3 (a), the phase comparison between the threshold VT_H side and the threshold VT_L side is performed in all data cycles t [-1], t [0], t [1]. On the other hand, in FIG. 5 (a), the phase comparison on the VT_H side is performed by t [-1] and t [1], and the phase comparison on the VT_L side is performed by t [0]. That is, the phase comparison at each threshold value is performed every other data cycle, and the phase comparison is performed at only one of the threshold values for each data cycle.

Further, as shown in the clock signal CLK_0 in FIG. 5 (a), the frequency of the clock signal is half that in the cases of FIGS. 2 and 3. For example, at t [-1], the sign determination latch is performed at the rising timing, and then At t [0] of, the code determination latch is performed at the falling timing. When such a half-rate configuration is used, the internal operating speed is halved as compared with the full-rate configuration, so that it is possible to save power and, in some cases, area. Further, by partially omitting the phase comparison, further power saving and area saving can be achieved.

FIG. 5 (b) shows an operation in which the phase comparison is partially omitted from FIG. 5 (a). With respect to FIG. 5 (a), the phases on the VT_H side and the VT_L side in each data cycle are shown. The comparison latches are omitted one by one. Further, at each threshold value, the front phase comparison latch and the rear phase comparison latch are alternately omitted for each data cycle, and are omitted for each threshold value in each data cycle. The position of the latch is different. As a result, on the VT_H side, t [-1] is used to compare only EARLY, t [0] is used to compare only LATE, and on the VT_L side, t [-1] is used to compare only LATE. At t [0], only EARLY is compared.

As a configuration for realizing such an operation, FIG. 5 (a) is represented here, and an example of the configuration will be described with reference to FIG. The semiconductor integrated circuit device shown in FIG. 4 is composed of a clock data determination circuit CD_JGE4 and a clock signal generation circuit CLK_GEN. CD_JGE4 includes a threshold setting circuit VTSET_H, VTSET_L, a logic circuit LOG4, a selector logic circuit SEL_LOG, a bus signal selection circuit IND_SEL41, and a one-cycle delay circuit DLY1. VTSET_H and VTSET_L are the same as those in the first embodiment.

The logic circuit LOG4 includes twelve latch circuits FF40 to FF51 and four EXOR circuits EOR40 to EOR43. The FF40 latches the output of VTSET_H at the rising edge of the clock signal CLK_0 from CLK_GEN, and outputs the latch result to SEL_LOG as the signal DATA_H1. The FF41 latches the output of VTSET_H at the falling edge of CLK_0, retakes the latching result at the rising edge of CLK_0 by FF48, and outputs the latching result of FF48 to SEL_LOG as a signal DATA_H0. FF42 latches the output of VTSET_L at the rising edge of CLK_0, and outputs the latch result to SEL_LOG as the signal DATA_L1. The FF43 latches the output of VTSET_L at the falling edge of CLK_0, retakes the latching result at the rising edge of CLK_0 by FF49, and outputs the latching result of FF49 as a signal DATA_L0 to SEL_LOG.

The FF44 latches the output of VTSET_H at the rising edge of the clock signal CLK_45N from CLK_GEN, and outputs the latch result to EOR40. The FF45 latches the output of VTSET_H at the rising edge of the clock signal CLK_45P from CLK_GEN, and outputs the latch result to EOR41. The FF46 latches the output of VTSET_L at the falling edge of CLK_45N, regains the latching result at the rising edge of CLK_0 by FF50, and outputs the latching result of FF50 to EOR42. The FF47 latches the output of VTSET_L at the falling edge of CLK_45P, regains the latching result at the rising edge of CLK_0 by FF51, and outputs the latching result of FF51 to EOR43.

The EOR40 performs an EXOR operation on the latch result of FF40 and the latch result of FF44, and outputs the operation result to SEL_LOG as a signal EARLY_H1. The EOR41 performs an EXOR operation on the latch result of FF40 and the latch result of FF45, and outputs the operation result to SEL_LOG as the signal LATE_H1. The EOR42 performs an EXOR operation on the latch result of FF49 and the latch result of FF50, and outputs the operation result to SEL_LOG as a signal EARLY_L0. The EOR43 performs an EXOR operation on the latch result of FF49 and the latch result of FF51, and outputs the operation result to SEL_LOG as a signal LATE_L0.

Each such input signal to SEL_LOG corresponds to each latch location shown in FIG. 5 (a). First, "H0" such as DATA_H0 means that "H" means the threshold value VT_H side, and "0" is a data cycle latched by the falling edge of CLK_0 (t [-2], t [0], It means t [2], ...). In addition, "L1" such as DATA_L1 means that "L" means the threshold value VT_L side, and "1" is a data cycle (t [-1], t [1], t that is latched at the rising edge of CLK_0. It means [3], ...).

In FIG. 5A, since the code determination is performed on the VT_H side and the VT_L side in all data cycles, DATA_H0 and DATA_L0 are output in the falling data cycle of CLK_0, and DATA_H1 and DATA_L1 are output in the rising data cycle of CLK_0. Is output. On the other hand, since the phase comparison is partially omitted as described above, EARLY_L0 and LATE_L0 corresponding to the phase comparison result only on the VT_L side are output in the falling data cycle of CLK_0, and in the rising data cycle of CLK_0. EARLY_H1 and LATE_H1 corresponding to the phase comparison result only on the VT_H side are output.

In addition, EARLY_L0 and LATE_L0 are the latch result at the falling edge of CLK_0 (for example, corresponding to the mark on the VT_L side of t [0]) and the latch at the falling edge of CLK_45N and CLK_45P whose phases are shifted by 45 degrees on both sides of the latch result. It can be obtained by comparing the results (for example, corresponding to the x mark on the VT_L side of t [0]). Similarly, EARLY_H1 and LATE_H1 are the latch result at the rising edge of CLK_0 (for example, corresponding to the mark on the VT_H side of t [1]) and the latch result at the rising edge of CLK_45N and CLK_45P (for example, the VT_H side of t [1]). It can be obtained by comparing and calculating (corresponding to the x mark).

The selector logic circuit SEL_LOG in FIG. 4A receives such an input signal and performs various selection operations, etc., and performs various selection operations, etc., and reproduce data signal DATA [0: 1] and phase comparison signal EARLY [0: 1], LATE. Output [0: 1]. DATA [0], EARLY [0], LATE [0] correspond to the sign judgment result and phase comparison result in the falling data cycle of CLK_0, and correspond to DATA [1], EARLY [1], LATE [1]. Corresponds to the sign determination result and phase comparison result in the rising data cycle of CLK_0.

Here, the operation such as selection in SEL_LOG is performed based on the sign determination result of the previous data cycle as in the first embodiment. In FIG. 5 (a), regarding the code determination, for example, if the code determination result (PRE) at t [-1] is'H', the code determination result at t [0] (DATA [0]] ) Is DATA_H0, and conversely, if it is'L', DATA [0] is DATA_L0. Also, if the sign judgment result at t [0], that is, the DATA [0] just determined is'H', the sign judgment result at t [1] (DATA [1]) is DATA_H1, and conversely. If'L', DATA [1] is DATA_L1.

On the other hand, regarding the phase comparison, for example, if the sign determination result at t [-1], that is, DATA [1] in the previous clock cycle is'H', the phase comparison is not performed at t [0]. Outputs'L'as EARLY [0] and LATE [0]. Conversely, if the sign determination result at t [-1], that is, DATA [1] in the previous clock cycle is'L', phase comparison is performed at t [0], and EARLY_L0 is set as EARLY [0]. Is output as LATE [0] and LATE_L0. If the sign determination result at t [0], that is, DATA [0] in this clock cycle is'H', phase comparison is performed at t [1], and EARLY_H1 is set as EARLY [1] and LATE [1]. ] To output LATE_H1. Conversely, if the sign determination result at t [0], that is, DATA [0] in this clock cycle is'L', then EARLY [1] and LATE [1] without performing phase comparison at t [1]. Outputs'L'as.

In order to perform such an operation, in SEL_LOG, as shown in Fig. 4 (a), only DATA [1] is selected from DATA [0: 1] by IND_SEL41, and the signal PRE delayed by 1 clock cycle by DLY1 is selected. It is used to perform operations such as selection.

FIG. 4 (b) shows the operation (logical content) of the selector logic circuit SEL_LOG as described above. The signal PRE is a signal obtained by delaying DATA [1] by DLY1. First, SEL_LOG outputs DATA [0] = DATA_H0, EARLY [0] = LATE [0] ='L' when PRE is'H', and DATA [0] = DATA_L0, when PRE is'L'. Outputs EARLY [0] = EARLY_L0 and LATE [0] = LATE_L0. Next, SEL_LOG outputs DATA [1] = DATA_H1, EARLY [1] = EARLY_H1, LATE [1] = LATE_H1 when the determined DATA [0] is'H', and when it is'L', SEL_LOG outputs. Outputs DATA [1] = DATA_L1 and EARLY [1] = LATE [1] ='L'.

As described above, by using the semiconductor integrated circuit apparatus of the second embodiment, it is possible to improve the margin for the waveform variation of the input data signal even in the half-rate configuration as in the first embodiment. Further, by applying the semiconductor integrated circuit device of the second embodiment to a transmission system, high-speed transmission can be realized. Needless to say, the application is not limited to the full-rate configuration and the half-rate configuration described so far, but is also applicable to a quad-rate configuration using a frequency half of the half-rate configuration.

(Embodiment 3) In the third embodiment, a detailed configuration example different from that of FIG. 2 will be described in the semiconductor integrated circuit apparatus shown in FIG. The semiconductor integrated circuit device of the third embodiment generates the code determination result and the phase comparison result of the data cycle of interest by using the latch results of the data cycle of interest and the data cycle of interest in addition to the code determination result of the pre-data cycle. Is the main feature.

FIG. 6 shows the details of FIG. 1 in the semiconductor integrated circuit apparatus according to the third embodiment of the present invention, (a) is a circuit diagram showing a configuration example thereof, and (b) is a determination process in (a). It is explanatory drawing which shows the logical content of a circuit. Compared with the semiconductor integrated circuit device shown in FIG. 2, the semiconductor integrated circuit device shown in FIG. 6 has a clock signal CLK_45P inside the logic circuit LOG6 included in the clock data determination circuit CD_JGE6 and a clock signal generation circuit CLK_GEN. It is different to generate CLK_45N. Other than that, it is the same as in FIG. 2, and detailed description thereof will be omitted.

The logic circuit LOG6 is composed of four latch circuits FF60 to FF63, four one-cycle delay circuits DLY60 to DLY63, and a determination processing circuit JGE6. The FF60 latches the output of the threshold setting circuit VTSET_H at the rising edge of CLK_45N, and transmits the latch result to the JGE6 as a signal H0F via the DLY60. The FF61 latches the output of VTSET_H at the rising edge of CLK_45P, and transmits the latch result to JGE6 as a signal H1R as it is, and also transmits the latch result to JGE6 as a signal H0R via DLY61.

The FF62 latches the output of the threshold setting circuit VTSET_L at the rising edge of CLK_45N, and transmits the latch result to the JGE6 as a signal L0F via the DLY62. The FF63 latches the output of VTSET_L at the rising edge of CLK_45P, and transmits the latch result to JGE6 as a signal L1R as it is, and also transmits the latch result to JGE6 as a signal L0R via DLY63. JGE6 receives these signals H0F, H0R, H1R, L0F, L0R, L1R, performs the judgment processing as shown in Fig. 6 (b), and performs two types of candidates consisting of a combination of data signal and phase comparison signal { Output (DATA1, EARLY1, LATE1) or (DATA0, EARLY0, LATE0)}.

Figure 8 shows the figure<u style="single">6</u>It is a waveform diagram which shows the operation example of the semiconductor integrated circuit apparatus of the above, and (a) and (b) explain the operation of the code determination and the phase comparison with respect to the said waveform. The signals H0F, H0R, H1R, L0F, L0R, L1R in FIG. 6 (a) correspond to the latch results at the positions shown in FIG. 8 (a).

For example, "H" in H0F means the threshold value VT_H side, "0" means the data cycle t [0], and "F" means the timing on the front side (timing TGh in FIG. 8 (a)). means. For example, "L" in L1R means the threshold value VT_L side, "1" means the data cycle t [1], and "R" means the timing on the rear side (timing in FIG. 8 (a)). It means TGj). The same meaning applies to other signals. Here, TGh is in a position shifted to the left by 45 degrees with respect to TGi, which corresponds to the rising timing of CLK_45N in FIG. 6 (a). On the other hand, TGj is in a position shifted to the right by 45 degrees with respect to TGi, which corresponds to the rising timing of CLK_45P in FIG. 5 (a).

By the way, the code string having the highest band in the bipolar NRZ eye pattern is (LLHLLH ...) or (HHLHHL ...). Therefore, as shown in FIG. 8B, if random jitter is input from, for example, the transmission oscillation circuit PLL_tx, the pulse width of such a code string is likely to be narrower than the original width. On the other hand, for pulses with a low band such as (HHHLLLHHH), there is a high possibility that the pulse width will widen if random jitter is applied. So, for example, if the latch results of H0F and H0R are different on the VT_H side of t [0], is the pulse width of (HHLHHL ...) narrowed or the pulse width of (HHHLLLLHHH) widened? Can be determined using the latch result at t [1]. For example, using L1R at t [1], if the latch result here is'H', it is judged that the pulse width of (HHLHHL ...) is narrowed, and if it is'L', the pulse of (HHHLLLLHHH) is judged. Judge that the width has expanded.

Using this way of thinking, the sign determination result and phase comparison result at t [0] can be defined as follows.

First, the condition in the data cycle t [-1] is "the sign judgment result in t [-1] is'H'" (condition 1) or "the sign judgment result in t [-1] is'L'". Divide into (Condition 2). Next, in the case of (Condition 1), at t [0], "the front and rear latch results (H0F and H0R latch results) are the same" (Condition 1-1) or "the front and rear latch results (H0F and H0R)". Latch result) is different (Condition 1-2). Similarly, in the case of (Condition 2), at t [0], "the front and rear latch results (latch results at L0F and L0R) are the same" (Condition 2-1) or "before and after latch results (L0F and L0R)". (Latch result in) is different (Condition 2-2). As described in FIG. 1 and the like, when (Condition 1) is satisfied, the latch result (L0F, L0R) at VT_L is not used in t [0], and when (Condition 2) is satisfied, t [ In 0], the latch result (H0F, H0R) at VT_H is not used.

Under such conditions, if (Condition 1) and (Condition 1-1) are satisfied, the sign determination result can be the latch result at H0F (or H0R), and the phase comparison signals EARLY1 and LATE1 Does not have to occur. On the other hand, when (Condition 1) and (Condition 1-2) are satisfied, as can be seen from the above explanation, if the latch result of t [1] at L1R is'H', it is regarded as the sign determination result (DATA1). Outputs'L'and EARLY1 ='H' as the phase comparison result. On the contrary, if the latch result in L1R is'L',' H'is output as the code determination result (DATA1) and LATE1 ='H' is output as the phase comparison result.

Further, when (Condition 2) and (Condition 2-1) are satisfied, the sign determination result can be the latch result at L0F (or L0R), and the phase comparison signals EARLY0 and LATE0 need not be generated. On the other hand, when (Condition 2) and (Condition 2-2) are satisfied, as can be seen from the above explanation, if the latch result of t [1] at H1R is'H', it is regarded as the sign determination result (DATA0). Outputs'L'and LATE0 ='H' as the phase comparison result. On the contrary, if the latch result in H1R is'L',' H'is output as the sign determination result (DATA0) and EARLY0 ='H' is output as the phase comparison result.

In order to perform such an operation, the figure<u style="single">6</u>In (a) and (b), (Condition 1) and (Condition 2) are separated by the selector circuit SEL and the 1-cycle delay circuit DLY1, and (Condition 1-1) and (Condition 1-2) are separated and (Condition 1-2) are separated. Logic circuit JGE to separate condition 2-1) and (condition 2-2)<u style="single">6</u>I'm going at. JGE<u style="single">6</u>Then, for example, when the above-mentioned (Condition 1) and (Condition 1-2) are satisfied, as shown in FIG. 6 (b), the inverted signal of L1R is used as DATA1, the inverted signal of L1R is used as EARLY1, and the inverted signal of L1R is used as LATE1. You can output it. Similarly, when (Condition 2) and (Condition 2-2) are satisfied, the inverted signal of H1R may be output as DATA0, the inverted signal of H1R as EARLY0, and H1R as LATE0.

As described above, in the semiconductor integrated circuit apparatus of FIG. 6, the code determination result and the phase comparison result in the data cycle t [0] of interest are added to the code determination result in the previous data cycle t [-1], and the attention is paid. It is determined using the latch results in the data cycle t [0] and the post-data cycle t [1]. Therefore, in addition to the margin expansion by using the sign determination result of the pre-data cycle as described in the first embodiment, it is possible to further expand the margin by using the latch result in the post-data cycle. It becomes. That is, if the code judgment result in the pre-data cycle and the latch result in the post-data cycle are known, the code in the data cycle of interest can be determined more accurately, so that the waveform of the received code string (input data signal) is in its own band. Therefore, it is possible to generate accurate code determination results and phase comparison results even when the fluctuations are relatively large.

By the way, in the configuration of FIG. 6 and the operation of FIG. 8, the latch results of H1R and L1R in the post-data cycle t [1] were used, but instead, as shown in FIG. 8 (b), of t [1]. The latch result at C1R located at the intermediate level threshold VT_C may be used. The configuration in this case is shown in FIG. 7A and 7B show a modification of FIG. 6, where FIG. 7A is a circuit diagram showing a configuration example thereof, and FIG. 7B is an explanatory diagram showing the logical contents of the determination processing circuit in FIG. 6A.

The clock data determination circuit CD_JGE7 shown in FIG. 7A adds a threshold setting circuit VTSET_C and a latch circuit FF74 that latches the output to CD_JGE6 in FIG. The logical content has been slightly changed. Since the other configurations are the same as those in FIG. 6, detailed description thereof will be omitted. VTSET_C is a circuit that sets an intermediate level threshold value VT_C between VT_H and VT_L as shown in Fig. 8 (b). The FF74 latches the output of VTSET_C with the clock signal CLK_45P, and outputs the latch result to JGE7 as the signal C1R.

As shown in Fig. 7 (b), the logical content of JGE7 is that L1R and H1R in JGE6 in Fig. 6 (b) are replaced with C1R. When the configuration using three threshold values is used in this way, the circuit area increases with VTSET_C, but as can be seen from Fig. 8 (b), H1R and L1R are configured using two threshold values. The determination margin in the voltage axis (vertical axis) direction can be expanded as compared with the case of using. Therefore, it is possible to generate a more accurate code determination result and phase comparison result.

As described above, by using the semiconductor integrated circuit device of the third embodiment, it is possible to improve the margin for the waveform variation of the input data signal. Further, by applying the semiconductor integrated circuit device of the third embodiment to a transmission system, high-speed transmission can be realized.

(Embodiment 4) In the fourth embodiment, a detailed configuration example different from that of FIG. 2 will be described in the semiconductor integrated circuit apparatus shown in FIG. The main feature of the semiconductor integrated circuit device of the fourth embodiment is that the phase comparison is performed by the edge matching method instead of the eye track method as shown in the first embodiment and the like. In terms of phase comparison operation performance, the eye track method is considered to be superior to the edge alignment method, but the edge alignment method can be realized even with a one-phase clock signal, so the area efficiency is higher than that of the eye track method. It is considered to be excellent.

FIG. 9 is a circuit diagram showing a detailed configuration example of FIG. 1 in the semiconductor integrated circuit apparatus according to the fourth embodiment of the present invention. Compared with the semiconductor integrated circuit device shown in FIG. 2, the semiconductor integrated circuit device shown in FIG. 9 has only the clock signal CLK_0 inside the logic circuit LOG9 included in the clock data determination circuit CD_JGE9 and the clock signal generation circuit CLK_GEN. Is different in that it occurs. Other than that, it is the same as in FIG. 2, and detailed description thereof will be omitted.

The logic circuit LOG9 receives the output of VTSET_H and makes various comparison judgments, and outputs the signal group (DATA1, EARLY1, LATE1). The comparison circuit CMP91 and the signal group (DATA0, EARLY0, LATE0) also receives the output of VTSET_L. ) Is included in the comparison circuit CMP92. The CMP91 is composed of two latch circuits FF90 and FF91, a one-cycle delay circuit DLY90, and two EXOR circuits EOR90 and EOR91.

The FF90 latches the output of VTSET_H at the rising edge of CLK_0, and outputs the latch result to the selector circuit SEL as a data signal DATA1. The FF91 latches the output of VTSET_H at the falling edge of CLK_0 and outputs the latch result to EOR90 and EOR91. The EOR90 performs an EXOR operation on the latch result of FF90 and the latch result of FF91, and outputs the calculation result to the SEL as a phase comparison signal LATE1. The EOR91 performs an EXOR operation on the signal obtained by delaying the latch result of FF90 by DLY90 and the latch result of FF91, and outputs the calculation result to the SEL as a phase comparison signal EARLY1.

The CMP92 also has the same configuration as the CMP91, and is composed of two latch circuits FF92 and FF93, a one-cycle delay circuit DLY91, and two EXOR circuits EOR92 and EOR93. FF92 latches the output of VTSET_L at the rising edge of CLK_0, and outputs the latch result to SEL as a data signal DATA0. The FF93 latches the output of VTSET_L at the falling edge of CLK_0 and outputs the latch result to EOR92 and EOR93. The EOR92 performs an EXOR operation on the latch result of FF92 and the latch result of FF93, and outputs the calculation result to the SEL as a phase comparison signal LATE0. The EOR93 performs an EXOR operation on the signal obtained by delaying the latch result of FF92 by DLY91 and the latch result of FF93, and outputs the calculation result to the SEL as a phase comparison signal EARLY0.

FIG. 10 is a waveform diagram illustrating an operation example of code determination and phase comparison in the semiconductor integrated circuit apparatus of FIG. The semiconductor integrated circuit device of FIG. 9 performs phase comparison using the edge matching method as described with reference to FIG. In FIG. 10, the threshold value VT_H is set at the voltage level at the intersection of the waveform trajectories (HHL) and (LHH), and the threshold value VT_L is set at the voltage level at the intersection of (LLH) and (HLL). Then, the falling timing of CLK_0 is adjusted to these intersections (marked with x in FIG. 10) by using the edge matching method, and the sign determination is performed at the rising timing of CLK_0 (marked with in FIG. 10).

For example, in the data cycle t [0], the latch result of FF90 in Fig. 9 (for example, corresponding to the mark on the VT_H side of t [0] in Fig. 10) is output as DATA1, and the latch result of FF90 and FF91 The latch result (for example, corresponding to the x mark on the VT_H side between t [-1] and t [0]) is compared at EOR90. In addition, the latch result of FF91 and the output of DLY90 in Fig. 9 (for example, corresponding to the mark on the VT_H side of t [-1] in Fig. 10) are compared by EOR91.

If the latch result of FF90 and the latch result of FF91 are different signs (that is, if there is a DIN edge between these latch timings), EOR90 outputs LATE1 ='H'. On the other hand, if the output of DLY90 and the latch result of FF91 have different signs, EOR91 outputs EARLY1 ='H'. When the sign determination result in the data cycle t [-1] is'H', these signal groups (DATA1, EARLY1, LATE1) are output via SEL. The clock signal generation circuit CLK_GEN corrects the phase of CLK_0 to the left based on the'H'level of EARLY, and corrects the phase of CLK_0 to the right based on the'H' level of LATE.

As described above, by applying the semiconductor integrated circuit device of the fourth embodiment to the transmission system, high-speed transmission can be realized.

(Embodiment 5) In the fifth embodiment, a configuration example in which the configuration of FIG. 9 in the fourth embodiment is modified will be described. The main feature of the semiconductor integrated circuit device of the fifth embodiment is that, in addition to the configuration shown in FIG. 9, a function of performing phase comparison only when a specific code string is input is added. ..

FIG. 11 is a circuit diagram showing a configuration example obtained by modifying FIG. 9 in the semiconductor integrated circuit device according to the fifth embodiment of the present invention. Compared with the semiconductor integrated circuit device shown in FIG. 9, the semiconductor integrated circuit device shown in FIG. 11 has a code string judgment circuit SBL_JGE added to the output of the selector circuit SEL included in the clock data judgment circuit CD_JGE11. It's different. Other than that, it is the same as in FIG. 9, and detailed description thereof will be omitted.

The code sequence determination circuit SBL_JGE is composed of three 1-cycle delay circuits DLY2 to DLY4, two EXOR circuits EOR1 and EOR2, and three AND circuits AND1 and AND2 in addition to the one-cycle delay circuit DLY1 shown in FIG. Will be done. EOR2 performs EXOR operation on the data signal DATA output from SEL and the signal via DLY1. EOR1 EXORs the signal via DLY1 and the signal via DLY2 from there. The output of EOR2 is input to one of AND3, the output of EOR1 is inverted and input to the other of AND3, and the AND operation result by AND3 is output as an enable signal EN. As a result, EN becomes'H'when (output of DATA, DLY1, output of DLY2) is (L, H, H) or (H, L, L). That is, it becomes'H'when the code string is (HHL) or (LLH).

EN is input to one of AND1 and one of AND2. On the other side of AND1, the phase comparison signal LATE, which is the output of SEL, is input via DLY3. On the other side of AND2, the phase comparison signal EARLY, which is the output of SEL, is input via DLY4. Then, the outputs of AND1 and AND2 are input to CLK_GEN. Therefore, the'H'of EARLY or LATE will be transmitted to CLK_GEN only when the code string is (HHL) or (LLH). Note that DLY3 and DLY4 are for adjusting the number of clock stages.

12 (a) and 12 (b) are waveform diagrams illustrating an operation example of code determination and phase comparison in the semiconductor integrated circuit apparatus of FIG.

FIG. 12A shows a case where the threshold values VT_H and VT_L are set to positions closer to the intermediate level by ΔV1 than the threshold values in FIG. 10 in the semiconductor integrated circuit apparatus of the fourth embodiment. .. At this time, the timing of the code determination latch deviates from the timing of the code determination latch in FIG. 10 by, for example, ΔT1 = (bit rate Tc × 1/4 (= phase 90 degrees)) (FIG. 12 (FIG. 12 (Fig. 12)). It is best to place it at the mark) in a). As a result, as described in the first embodiment, it is possible to easily expand the margin with respect to the variation in the vertical axis direction of the waveform. The effect of shifting such a threshold value can be obtained not only in this embodiment but also in other embodiments. However, in the semiconductor integrated circuit apparatus shown in the fourth embodiment, for example, since the waveform orbit (HHL) and (LHH) are not distinguished on the VT_H side, the falling timing of CLK_0 is the waveform orbit (HHL). It will settle at the midpoint of (LHH), that is, the position marked with x in FIG. 12 (a), and the optimum point cannot be achieved. Therefore, in the fourth embodiment, it is essential to set the threshold values VT_H and VT_L to the threshold values shown in FIG.

In this embodiment 5, in order to eliminate this drawback of the fourth embodiment, as shown in FIG. 12 (b), only the waveform trajectories (HHL) and (LLH) are targeted, and (HHL) and VT_H are used. An operation is performed such that the falling edge of the clock signal CLK_0 is adjusted to the intersection and the intersection of (LLH) and VT_L. By doing so, it is possible to match the timing of the fall of CLK_0 with the waveform trajectories (HHL) and (LLH), so that the margin for variations in the threshold values VT_H and VT_L can be expanded.

As described above, by using the semiconductor integrated circuit device of the fifth embodiment, it is possible to improve the margin for the waveform variation of the input data signal. Further, by applying the semiconductor integrated circuit device of the fifth embodiment to a transmission system, high-speed transmission can be realized.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof.

For example, in the above-described embodiment, a configuration example in which an offset voltage is applied in a threshold setting circuit and latched by a latch circuit is shown, but this is a circuit parameter or process parameter of the latch circuit in the first stage of input. The same can be achieved by adjusting the above or devising the configuration of this first-stage latch circuit.

The semiconductor integrated circuit device of the present invention is widely applicable to, for example, a serial transmission system that receives a bipolar NRZ eye pattern and reproduces a data signal or a clock signal.

<figref num="1">It is a block diagram which shows an example of the structure in the semiconductor integrated circuit apparatus by Embodiment 1 of this invention.</figref><figref num="2">It is a circuit diagram which shows the detailed configuration example of the semiconductor integrated circuit apparatus of FIG.</figref><figref num="3">An operation example of the semiconductor integrated circuit device of FIG. 2 will be described. FIG. 2A is a waveform diagram showing the operation of data reproduction and clock reproduction with respect to an input data signal, and FIG. 2B is a more detailed operation of clock reproduction. It is a waveform diagram which shows.</figref><figref num="4">It is an operation diagram for demonstrating the modification of the structure of FIG. 2, and (a) and (b) show different operation respectively.</figref><figref num="5">FIG. 5 is a waveform diagram illustrating an operation example of code determination and phase comparison when a half-rate configuration is used in the semiconductor integrated circuit apparatus according to the second embodiment of the present invention, and FIG. 4A shows an operation example of FIG. And (b) shows other operation examples.</figref><figref num="6">In the semiconductor integrated circuit apparatus according to the third embodiment of the present invention, the details of FIG. 1 are shown, (a) is a circuit diagram showing a configuration example thereof, and (b) is the logical content of the determination processing circuit in (a). It is explanatory drawing which shows.</figref><figref num="7">A modified example of FIG. 6 is shown, (a) is a circuit diagram showing a configuration example thereof, and (b) is an explanatory diagram showing the logical contents of the determination processing circuit in (a).</figref><figref num="8">Figure<u style="single">6</u>It is a waveform diagram which shows the operation example of the semiconductor integrated circuit apparatus of the above, and (a) and (b) explain the operation of code determination and phase comparison with respect to the said waveform.</figref><figref num="9">It is a circuit diagram which shows the detailed configuration example of FIG. 1 in the semiconductor integrated circuit apparatus according to Embodiment 4 of this invention.</figref><figref num="10">FIG. 5 is a waveform diagram illustrating an operation example of code determination and phase comparison in the semiconductor integrated circuit apparatus of FIG.</figref><figref num="11">FIG. 5 is a circuit diagram showing a configuration example obtained by modifying FIG. 9 in the semiconductor integrated circuit device according to the fifth embodiment of the present invention.</figref><figref num="12">In the semiconductor integrated circuit apparatus of FIG. 11, it is a waveform diagram explaining the operation example of the code determination and the phase comparison, and (a) and (b) explain the operation of the code determination and the phase comparison with respect to the said waveform. ..</figref><figref num="13">It is the schematic which shows the structural example of the transmission system to which the semiconductor integrated circuit apparatus of FIG. 1 is applied.</figref><figref num="14">It is a perspective view which shows an example of the implementation form of the transmission system shown in FIG.</figref><figref num="15">It is a block diagram which shows the structural example of the clock data reproduction circuit in the transmission system of FIG.</figref><figref num="16">It is the schematic explaining an example of the operation of the clock signal generation circuit in the clock data reproduction circuit of FIG.</figref><figref num="17">It is explanatory drawing which supplements the operation of FIG.</figref><figref num="18">It is a circuit diagram which shows an example of the structure in the semiconductor integrated circuit apparatus examined as the premise of this invention.</figref><figref num="19">An example of the operation using the semiconductor integrated circuit device of FIG. 18 will be described. FIG. 18A is a waveform diagram showing the operation of the data reproduction circuit with respect to the input data signal, and FIG. 18B is an operation of the clock reproduction circuit. It is a waveform diagram which shows.</figref><figref num="20">It is a waveform diagram which shows the actual state of the eye pattern shown in FIG. 19 (a).</figref><figref num="21">It is explanatory drawing which shows the definition of a phase comparison signal.</figref>

Code description

CDR clock data playback circuit CD_JGE Clock data judgment circuit LOG logic circuit VTSET threshold setting circuit SEL selector circuit DLY 1 cycle delay circuit CLK_GEN Clock signal generation circuit CMP comparison circuit EOR EXOR circuit SEL_LOG selector logic circuit JGE judgment processing circuit AND AND circuit SBL_JGE code string judgment circuit LSI_tx transmitter circuit LSI_rx receiver circuit EQ transmitter equalizer PLL oscillator circuit DRV driver circuit Ptx output pin Prx input pin MS transmission line AMP amplifier circuit MB backplane main board CS housing CN connector CRD daughter card M_JGE majority decision circuit PH_SEL phase selection circuit CK_SEL clock signal selection circuit CK_DLY clock delay circuit DR data playback circuit CR clock playback circuit IND_SEL bus signal selection circuit