Semiconductor device, and control method thereof

0001The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device that simultaneously writes or reads data from a plurality of non-volatile memory cells and a control method thereof.

0002Patent Document 1 discloses a non-volatile semiconductor storage device in which the time for reading control information during the initial setting period at power-on or reset is shortened. According to this, the same 1-bit control information is stored in a plurality of non-volatile memory cells (hereinafter referred to as active cells) connected to one bit line or one word line. When reading the control information, each bit is read from a plurality of active cells at the same time, so that a data current several times higher than usual can be obtained. As a result, the drive capability of the read path is strengthened, so that voltage amplification is not required to read the control information, and the read time in the initial setting period at the time of power-on or reset can be shortened, and the read time can be shortened quickly and normally. It is possible to shift to the access operation of.

0003Patent Document 2 discloses a non-volatile semiconductor storage device in which a dummy source line is provided in a cell array in order to prevent a voltage rise in the source line. Further, Patent Document 3 discloses a non-volatile semiconductor storage device in which a bulk bias contact structure is provided in a cell array in order to adjust the bulk voltage.<patcit num="1"><text>WL2007 / 004253 A1</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 11-307746</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2001-110920</text></patcit>

<p num="0004"> As shown in Patent Document 1, when data is read or written to a plurality of active cells connected to one bit line or one word line at the same time, the plurality of active cells are one bit. Since the line or one source line is shared, there is a problem that a large current several times larger than usual flows and the operation of reading or writing data becomes unstable.</p><p num="0005"> An object of the present invention is to provide a semiconductor device having improved stability of data read / write operation and a control method thereof when reading or writing to a plurality of memory cells storing data at the same time. To do.</p>

<p num="0006"> The present invention includes a plurality of bit lines provided in a memory cell area, a plurality of word lines provided intersecting the plurality of bit lines, and a plurality of spreads provided along the plurality of word lines. Data provided at an intersection of a source line and the plurality of bit lines and the plurality of word lines and connected to the plurality of bit lines, the plurality of word lines, and the plurality of diffusion source lines. A plurality of non-volatile active cells to be stored and a control unit for writing or reading data to at least two or more active cells among the plurality of active cells at the same time are provided, and the number of the plurality of active cells is provided. Is a semiconductor device characterized in that the number of intersections is smaller than the number of the intersections. According to the present invention, when data is written or read to two or more active cells at the same time, the magnitude of the current flowing through the bit line and the diffusion source line can be reduced, so that data can be written or read. The stability of operation can be improved.</p><p num="0007"> In the above configuration, the control unit may be configured to write or read the same 1-bit data to at least two or more active cells among the plurality of active cells at the same time.</p><p num="0008"> In the above configuration, the semiconductor device includes a plurality of the memory cell areas, and the control unit is simultaneously the same as the active cells in at least two or more of the plurality of memory cell areas. It can be configured to write or read 1-bit data. According to this, the same 1-bit data can be stored in the active cell in two or more memory cell areas, and can be read or written at the same time.</p><p num="0009"> In the above configuration, among the intersections, the intersections where the plurality of active cells are not provided may be provided with dummy cells which are not connected to the plurality of bit lines.</p><p num="0010"> In the above configuration, the number of the plurality of active cells connected to one of the plurality of bit lines is less than the number of the intersections in the bit line, and the number of the plurality of active cells is connected to one of the plurality of word lines. The number of the plurality of active cells may be smaller than the number of the intersections in the word line. According to this, the magnitude of the current flowing through one bit line or the diffusion source line can be further reduced, so that the stability of the data writing or reading operation can be further improved.</p><p num="0011"> In the above configuration, the number of the plurality of active cells connected to one of the plurality of bit lines is 1 or less, and the number of the plurality of active cells connected to one of the plurality of word lines. Can be configured to be 1 or less. According to this, the magnitude of the current flowing through one bit line or the diffusion source line can be further reduced, so that the stability of the data writing or reading operation can be further improved.</p><p num="0012"> In the above configuration, the number of the plurality of active cells connected to one of the plurality of diffusion source lines may be 1 or less. According to this, since the magnitude of the current flowing through one diffusion source line can be further reduced, the stability of the data writing or reading operation can be further improved.</p><p num="0013"> In the above configuration, a word line that is not connected to the active cell of the plurality of word lines may be provided between the word lines connected to the active cell of the plurality of word lines. it can. According to this, since the magnitude of the current flowing through one diffusion source line can be further reduced, the stability of the data writing or reading operation can be further improved.</p><p num="0014"> In the above configuration, a metal source line provided between the plurality of bit lines along the plurality of bit lines and connected to the plurality of diffusion source lines can be provided. According to this, since the magnitude of the current flowing through one metal source line can be reduced, the stability of the data writing or reading operation can be further improved.</p><p num="0015"> In the above configuration, the plurality of bit lines connected to each of the active cells may be provided with the plurality of bit lines not connected to each of the active cells. According to this, between the bit lines used for writing or reading data, a dummy bit line that is not used for writing or reading data is provided, so that interference during writing or reading data is prevented. It can be suppressed.</p><p num="0016"> In the above configuration, the same data can be stored in the plurality of active cells in the memory cell area.</p><p num="0017"> In the above configuration, different data may be stored in the plurality of active cells in the memory cell area.</p><p num="0018"> In the above configuration, the plurality of active cells may be configured to store control information read at the time of power-on or at the time of initial setting after reset.</p><p num="0019"> The present invention includes a plurality of bit lines provided in a memory cell area, a plurality of word lines provided intersecting the plurality of bit lines, and a plurality of spreads provided along the plurality of word lines. Data provided at an intersection of a source line and the plurality of bit lines and the plurality of word lines, and connected to the plurality of bit lines, the plurality of word lines, and the plurality of diffusion source lines. A method for controlling a semiconductor device, comprising a plurality of non-volatile active cells to be stored, wherein the number of the plurality of active cells is smaller than the number of the intersections, and the plurality of active cells. Among the steps, the step of simultaneously storing the same 1-bit data in at least 2 or more active cells and the same 1-bit data from the at least 2 or more active cells in which the same 1-bit data is stored. It is a control method of a semiconductor device characterized by having a step of simultaneously reading out. According to the present invention, when data is written or read to two or more active cells at the same time, the magnitude of the current flowing through the bit line and the diffusion source line can be reduced, so that data can be written or read. The stability of operation can be improved.</p>

<p num="0020"> According to the present invention, when writing or reading data to two or more active cells storing data at the same time, the magnitude of the current flowing through the bit line and the diffusion source line can be reduced, so that the data can be reduced. It is possible to improve the stability of the writing or reading operation of.</p>

0021Hereinafter, examples according to the present invention will be described with reference to the drawings.

Comparative example

00221 to 3 show semiconductor devices according to a comparative example. In addition, all the following examples are examples in which the present invention is used in a non-volatile memory cell area outside the main storage area. The memory cell area outside the main storage area is a storage area provided outside the main storage area of the semiconductor device, and stores various control information read during the initial setting period after the power is turned on or reset, for example. Refers to the area.

0023FIG. 1 is a block diagram showing a configuration of a semiconductor device common to Comparative Examples and Examples. The semiconductor device includes a main control unit 200 that controls the entire operation, a main storage area 202 for storing data, a main input / output circuit 204 for exchanging data with the outside, and an address of a cell in the main storage area 202. Address storage area 206 for storing data, main booster circuit 208 for applying voltage required for writing or reading, and various control information read during the initial setting period at power-on or reset. It includes a control information storage area 210 and a main address decoder 212 for reading or writing to a predetermined cell in the main storage area 202.

0024FIG. 2 is a block diagram showing the configuration of the control information storage area 210. The control information storage area 210 is a memory cell control unit 220 for controlling the control information storage area 210, a memory cell area 100 for storing control information, and data exchange between the memory cell area 100 and the main control unit 200. It consists of an input / output circuit 224 for reading data, a booster circuit 228 for applying a voltage when writing or reading data, and an address decoder 230 for accessing a predetermined cell in the memory cell area 100. These operations will be described in Example 1.

0025FIG. 3 is a top view schematically showing the configuration of the memory cell area 100 according to the comparative example. The memory cell area 100 is provided with eight bit lines BL in the vertical direction and eight word lines WL in the horizontal direction. In addition, four diffusion source lines (not shown, see FIG. 4) are provided along the word line WL. A metal source line MSL is provided along the bit line BL on the outside of the bit line BL, and the diffusion source line is connected to the metal source line MSL. At the intersection of the bit line BL and the word line WL, an active cell AC, which is a memory cell for storing data, is provided. The active cell AC is a non-volatile memory cell, and stores control information read during the initial setting period after power-on or reset, for example. The memory cell control unit 220 (FIG. 2) can write or read to a plurality of active cell ACs at the same time.

00264 and 5 are circuit diagrams showing a part of the memory cell area 100 (area 10 in FIG. 3). The active cell AC is connected to the bit line BL, the word line WL, and the diffusion source line VSL, respectively. The diffusion source line VSL is connected to the metal source line MSL. Further, in order to reduce the area of the memory cell area 100, the active cell AC connected to the two word lines WL shares one diffusion source line VSL. For example, the eight active cell ACs connected to the wordline WL1 and the eight active cell ACs connected to the wordline WL2 are all connected to the diffusion source line VSL1. When writing data to the active cell AC, by applying a high voltage (for example, 12V) to the bit line BL and word line WL and a low voltage (for example, 0V) to the source line VSL, high energy is applied to the floating gate described later. The electrons are injected and the data is stored. When reading data from the active cell AC, a high voltage (for example, 6V) is applied to the bit line and word line, and a low voltage (for example, 0V) is applied to the source line VSL, and the flowing current is converted into a voltage signal. Read the data. In either case, current flows from the bit line BL to the source line VSL via the active cell AC.

0027With reference to Fig. 4, the same 1-bit data is stored in 8 active cells AC1 to AC8 (AC5 to AC8 are not shown) connected on one word line WL1, and writing or reading is performed at the same time. I will explain the issues when doing so. When data is written or read, a large current 22 of 8 cells flows through the diffusion source line VSL1. The diffusion source line VSL1 has a relatively large resistance value, and the potential rises when a large current flows, which makes the data writing or reading operation unstable.

0028With reference to Fig. 5, the same 1-bit data is stored in 8 active cells AC1 and AC9 to AC15 (AC12 to AC15 are not shown) connected on one bit line BL1 and written or written at the same time. The problem when reading is described. When data is written or read, a large current 20 equivalent to 8 cells flows through the bit line BL1. At this time, since the bit line BL1 is very thin, it may exceed the current density standard. Further, since the voltage of the bit line BL1 drops and a sufficient voltage cannot be supplied for writing or reading data, the data writing or reading operation becomes unstable.

0029In this way, when writing or reading to a plurality of active cell ACs arranged in a row at the same time, a large current flows through one bit line BL or one source line VSL, so that the write or read operation is performed. There was a problem that it became unstable.

0030Example 1 shows the basic configuration of the present invention. The configuration of the semiconductor device (FIGS. 1 and 2) is the same as that of the comparative example except that the configuration of the memory cell area 100 is different. FIG. 6 is a top view schematically showing the configuration of the memory cell area 101 in the semiconductor device according to the first embodiment. The description of the configuration common to the comparative example (Fig. 3) will be omitted. The memory cell area 101 is provided with eight bit lines BL, eight word lines WL, and four diffusion source lines (not shown, see FIG. 7). A metal source line MSL is provided on the outside of the bit line BL and is connected to the diffusion source line. Eight active cells AC are diagonally provided at the intersection where the bit line BL and the word line WL intersect. That is, one bit line BL is provided with one active cell AC, and one word line WL is provided with one active cell AC. A dummy cell DC is provided at the intersection where the active cell is not provided. Unlike the active cell AC, the dummy cell DC is a cell that does not store data.

0031FIG. 7 is a circuit diagram showing a part of the memory cell area 101 (area 11 in FIG. 6) according to the first embodiment. The active cell AC1 is connected to the bit line BL1 and the word line WL1. Similarly, the active cells AC2 to AC4 are also connected to the bit lines BL2 to BL4 and the word lines WL2 to WL4, respectively. The active cells AC1 and AC2 are connected to the diffusion source line VSL1, and the active cells AC3 and AC4 are connected to the diffusion source line VSL2, respectively. The diffusion source lines VSL1 and VSL2 are provided along the word line WL and are connected to the metal source lines MSL1 and MSL2, respectively. On the other hand, the dummy cell DC is not connected to the bit line BL. Therefore, data cannot be read or written to the dummy cell DC.

0032FIG. 8 is a top view of the region 11. The word lines WL1 to WL4 and the diffusion source lines VSL1 to VSL2 are provided in parallel. A bit line BL is provided above the word line WL and the diffusion source line VSL in a direction intersecting the word line WL and the diffusion source line VSL. The active cell AC1 is provided at the intersection of the bit line BL1 and the word line WL1 and is arranged so as to straddle the diffusion source line VSL1 and the drain region described later. The same applies to the active cells AC2 to AC4. Dummy cell DC is provided at the other intersections. A bit line contact 30 is formed in the bit line BL provided with the active cell AC.

0033FIG. 9 (a) is a schematic cross-sectional view of the active cell AC1 along the line AA1 in FIG. 8, and FIG. 9 (b) is a cross-sectional view of the dummy cell DC along the line B-B1 in FIG. With reference to FIG. 9A, an n-type source region 41 for supplying electrons and an n-type drain region 42 for discharging electrons are provided in a substrate 40 made of a p-type silicon semiconductor. A floating gate 44 for storing electrons is provided on the upper surface of the substrate 40 via a tunnel oxide film 43. A control gate 46 for applying a bias voltage is provided on the upper surface of the floating gate 44 via an interlayer dielectric film 45. The source area 41 corresponds to the diffusion source line VSL1 and the control gate 46 corresponds to the word line WL1. The drain region 42 is connected to the bit line BL1 by the bit line contact 30. With reference to FIG. 9B, the bit line contact 30 is not formed in the drain region 42 of the dummy cell DC, and the dummy cell DC and the bit line BL2 are not connected.

0034A control method for the semiconductor device according to the first embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a diagram showing a flow of data writing operation. With reference to FIGS. 2 and 10, first, in step S10, the memory cell control unit 220 specifies the address of the active cell AC to be written to the address decoder 222. As a result, the active cell AC to be written is selected. Next, in step S12, the memory cell control unit 220 conducts the bit line BL and the word line WL to which the voltage should be applied to the address decoder 222. As a result, the data writing route is selected. Next, in step S14, the memory cell control unit 220 causes the booster circuit 228 to apply a voltage to the selected active cell AC. As a result, the same 1-bit data fetched from the main control unit 200 via the input / output circuit 224 is simultaneously stored in the selected active cell AC.

0035FIG. 11 is a diagram showing a flow of data reading operation. First, in step S20, the memory cell control unit 220 specifies the address of the active cell AC to be read to the address decoder 222 with reference to FIGS. 2 and 11. As a result, the active cell AC to be read is selected. Next, in step S22, the memory cell control unit 220 conducts the bit line BL and the word line WL to which the voltage should be applied to the address decoder 222. As a result, the data read route is selected. Next, in step S24, the memory cell control unit 220 causes the booster circuit 228 to apply a voltage to the selected active cell. As a result, the same 1-bit data is simultaneously read from the selected active cell AC. Next, in step S26, the memory cell control unit 220 causes the input / output circuit 224 to output the read data to the main control unit 200.

0036When writing or reading to eight active cell ACs in the memory cell area 101 at the same time with reference to FIGS. 6 and 7, the current 20 for one cell in the bit line BL and the current 20 for two cells in the diffusion source line VSL Current 22 flows. On the other hand, in the comparative example, a current of 8 cells flows through one bit line BL or one word line WL. Therefore, according to the configuration of the first embodiment, the current flowing through the bit line BL and the diffusion source line VSL can be reduced. As a result, it is possible to prevent the magnitude of the current from exceeding the current density reference of the bit line BL and the diffusion source line VSL. Further, by suppressing the potential drop of the bit line BL and suppressing the potential rise of the diffusion source line VSL, it is possible to supply a sufficient voltage for writing or reading data. From the above, when data is written or read to a plurality of active cell ACs at the same time, the stability of the write or read operation can be improved.

0037Further, in the first embodiment, a dummy cell DC is provided at the intersection of the bit line BL and the word line WL where the active cell AC is not provided. The difference between the active cell AC and the dummy cell DC is the presence or absence of the bit line contact 30, and the configurations of both are almost the same. As a result, substantially the same structure appears repeatedly in the memory cell area 101, so that the memory cell area 101 can be easily miniaturized even when the same exposure technique is used. Further, since the layout of the memory cell array of the main storage area 202 can be diverted to the memory cell area 101, the design and development of the semiconductor device becomes easy.

0038In the first embodiment, the memory cell control unit 220 writes or reads simultaneously to eight active cell ACs that store the same 1-bit data, but at least two or more active cells of the plurality of active cell ACs are active. Other configurations and control methods may be used as long as the same 1-bit data is written or read to the cell AC at the same time. For example, the same 1-bit data may be stored in the active cells AC1 to AC4, and other same 1-bit data may be stored in the remaining active cells (AC5 to AC8).

0039In the first embodiment, the number of active cell ACs that the memory cell control unit 220 writes or reads at the same time is set to 8, but the number is smaller than the number of intersections between the bit line BL and the word line WL in the memory cell area 101. If so, it may be a number other than 8. For example, the number of active cell ACs connected to one bitline BL is less than the number of intersections in one bitline BL, and the number of active cell ACs connected to one wordline WL is The configuration may be less than the number of intersections in one wordline WL. In addition, the number of active cells connected to one bit line is 1 or less (one active cell is connected to one bit line, or no active cell is connected), and the number of active cells is one or less. , The number of active cells connected to one wordline is 1 or less (one active cell is connected to one wordline, or no active cell is connected). Good. In either case, since the number of active cells connected to one bit line or one source line is smaller than that in the comparative example, the current flowing when writing or reading data can be reduced. Thereby, the stability of the data writing or reading operation can be improved.

0040The second embodiment is an example in which active cells are provided every other word line. FIG. 12 is a top view schematically showing the configuration of the memory cell area 102 in the semiconductor device according to the second embodiment. The description of the configuration common to that of the first embodiment (FIG. 6) will be omitted. The memory cell area 102 is provided with eight bit lines BL, 16 word lines WL, and eight diffusion source lines (not shown, see FIG. 13). Eight active cells AC are diagonally provided at the intersection of the bit line BL and the word line WL. That is, one active cell AC is provided for each bit line BL, and a word line WL provided with one active cell AC and a word line WL not provided with an active cell AC alternate. It is provided in. Of the intersections of the bit line BL and the word line WL, a dummy cell DC is provided at the intersection where the active cell AC is not provided.

0041FIG. 13 is a circuit diagram showing a part of the memory cell area 102 (area 12 in FIG. 12). The description of the configuration common to that of the first embodiment (FIG. 7) will be omitted. The active cell AC1 is connected to the bit line BL1, the word line WL1, and the diffusion source line VSL1. The active cell AC2 is connected to the bit line BL2, the word line WL3, and the diffusion source line VSL2. Unlike the first embodiment, the active cell AC is not connected to the word lines WL2 and WL4. In the semiconductor device according to the first and second embodiments, in order to reduce the area of the memory cell area, a cell (active cell AC or dummy cell DC) connected to two word lines WL is one diffusion source. It shares the line VSL. Therefore, by alternately providing the word line WL to which the active cell AC is connected and the word line WL to which the active cell AC is not connected as in the second embodiment, the word line WL is connected to one diffusion source line VSL. The number of active cells AC will be one.

0042When data is written or read to eight active cell ACs in the memory cell area 102 at the same time with reference to FIGS. 12 and 13, the current 20 for one cell in the bit line BL becomes 1 in the diffusion source line VSL. The current 22 for the cell flows. In the first embodiment, the size of the current 22 flowing through the diffusion source line VSL was two cells, so that the current flowing through one diffusion source line VSL is smaller in the second embodiment. In this way, the wordline WL to which the active cell AC is connected and the wordline WL to which the active cell AC is not connected are alternately provided, and the number of active cell ACs connected to the diffusion source line VSL is reduced to one. By doing so, the current flowing through the diffusion source line VSL becomes the size of one cell, so that the current flowing through the diffusion source line VSL can be further reduced. As a result, the potential rise of the diffusion source line VSL can be further suppressed, and the stability of the data writing or reading operation can be further improved.

0043In the second embodiment, the word line WL to which the active cell AC is connected and the word line WL to which the active cell AC is not connected are alternately provided, but the active cell AC connected to one diffusion source line VSL is provided. If the number is one, other configurations may be used. For example, it is possible to have a configuration in which eight word lines WL and eight diffusion source lines VSL are alternately provided in parallel in the memory cell area 102.

0044Example 3 is an example in which a metal source line is provided between the bit lines. FIG. 14 is a top view schematically showing the configuration of the memory cell area 103 in the semiconductor device according to the third embodiment. The description of the configuration common to that of the second embodiment (FIG. 12) will be omitted. The memory cell area 103 is provided with eight bit lines BL, 16 word lines WL, and eight diffusion source lines (not shown, see FIG. 15). In addition, nine metal source line MSLs are provided along the bit line BL between and outside the bit line BL. At the intersection of the bit line BL and the word line WL, eight active cell ACs are diagonally provided as in the case of the second embodiment. That is, one active cell AC is provided for each bit line BL, and a word line WL provided with one active cell AC and a word line WL not provided with an active cell AC alternate. It is provided in. Of the intersections of the bit line BL and the word line WL, a dummy cell DC is provided at the intersection where the active cell AC is not provided. Neither the active cell AC nor the dummy cell DC is provided at the intersection of the word line WL and the metal source line MSL.

0045FIG. 15 is a circuit diagram showing a part of the memory cell area 103 (area 13 in FIG. 14). The active cell AC1 is connected to the bit line BL1, the word line WL1, and the diffusion source line VSL1. The active cell AC2 is connected to the bit line BL2, the word line WL3, and the diffusion source line VSL2. The diffusion source lines VSL1 and VSL2 are connected to the metal source lines MSL1 to MSL3, respectively.

0046FIG. 16 is a top view of the region 13. The drain region (not shown) of the active cell AC and the bit line BL are connected by a bit line contact 30. The diffusion source line VSL and the metal source line MSL are connected by a source line contact 32. The diffuse source line VSL is straight, but the word line WL is curved near the source line contact 32 (region 18) to avoid contact with the source line contact 32.

0047When data is written or read to the active cell AC at the same time with reference to FIG. 15, the current 22a flowing from the active cell AC1 to the diffusion source line VSL1 is transferred to the metal source lines MSL1 and MSL2 to which the diffusion source line VSL1 is connected. The current 22b flowing from the active cell AC2 to the diffusion source line VSL2 flows to the metal source lines MSL2 and MSL3 to which the diffusion source line VSL2 is connected. The same applies to the other active cell ACs with reference to FIG. That is, the magnitude of the current flowing through the metal source line MSL is one cell or less.

0048In Example 2 (FIGS. 12 and 13), the number of diffusion source lines VSL was eight, whereas the number of metal source line MSLs was two, so that the flow flows into one metal source line MSL. The magnitude of the current was 4 cells. The metal source line MSL has a smaller resistance value than the diffusion source line VSL and can carry a large current, but it is preferable that the load due to the current is small. In Example 3, a metal source line MSL is provided between the bit lines BL, and since the number of metal source line MSLs is 9 for 8 diffusion source line VSLs, one metal source line MSL is used. The magnitude of the flowing current is smaller than that of one cell. As a result, the magnitude of the current flowing through the metal source line can be reduced, the load of the current on the metal source line can be reduced, and the potential rise in the metal source line can be suppressed.

0049The fourth embodiment is an example in which the same 1-bit data is stored in active cells provided in a plurality of memory cell areas. FIG. 17 is a diagram schematically showing the configuration of the memory cell area according to the fourth embodiment. The memory cell area 104 is composed of eight memory cell areas 104a to 104h continuously provided in the direction of the word line WL. The memory cell areas 104a to 104h share a word line WL and a diffusion source line (not shown).

0050FIG. 18 is a diagram schematically showing the configuration of the memory cell area 104a of FIG. The description of the configuration common to that of the second embodiment (FIG. 12) will be omitted. The memory cell area 104a is provided with 16 bit lines BL, 16 word lines WL, and 8 source lines (not shown, see FIG. 19). Eight active cells AC are diagonally provided at the intersection of the bit line BL and the word line WL. That is, a bit line BL having one active cell AC and a bit line BL not having an active cell are alternately provided, and a word line WL having one active cell AC and an active cell are provided. No wordline WLs are provided alternately.

0051FIG. 19 is a circuit diagram showing a part of the memory cell area 104a (area 14 in FIG. 18). The active cell AC1a is connected to the bit line BL1a, the word line WL1, and the diffusion source line VSL1. The active cell AC2a is connected to the bit line BL3a, the word line WL3, and the diffusion source line VSL2. No active cell AC is connected to the bit lines BL2a and BL4a, which are so-called dummy lines.

0052FIG. 20 is a top view of the region 14. The drain region of the active cell AC1a (not shown) and the bit line BL1a, and the drain region of the active cell AC2a (not shown) and the bit line BL3a are connected by a bit line contact 30, respectively. Since the active cell AC is not provided in the bit lines BL2a and BL4a, the bit line contact 30 is not formed. Compared with FIG. 16 of the third embodiment, since the source line contact 32 is not formed and the word line WL is provided in a straight line in FIG. 20, the distance between the bit lines BL and the word line WL becomes smaller. ing.

0053With reference to FIG. 17, in the memory cell areas 104a to 104h, the same 1-bit data is stored in the active cells AC1a to AC1h connected to the word line WL1. Similarly, the active cells AC2a to AC2h (not shown) store other identical 1-bit data. The memory cell control unit 220 (FIG. 2) can simultaneously write or read data to a cell in which the same 1-bit data is stored. With reference to FIGS. 17 to 19, when data is written or read simultaneously to the active cells AC1a to AC1h and AC2a to AC2h in the memory cell areas 104a to 104h, a current of 20 is generated in the bit line BL and a diffusion source is generated. A current of 22 flows through each line VSL.

0054According to the configuration of the fourth embodiment, the same 1-bit data can be stored in the active cell AC in two or more memory cell areas, and can be read or written at the same time.

0055Further, in the fourth embodiment, different 1-bit data are stored in the active cells AC1a and AC2a (FIG. 19) in the memory cell area 104a. Here, if the distance between the active cells AC1a and AC2a is small, the voltages applied to the two active cells may interfere with each other when writing or reading data, and the writing or reading of data may become unstable. In the fourth embodiment, the bit line to which one active cell is connected and the bit line to which the active cell is not connected are alternately provided, and the word line to which one active cell is connected and the active cell are connected. Word lines that are not used are provided alternately. As a result, between the bit line BL used for writing or reading data, a bit line BL (dummy line) that is not used for writing or reading data is provided, so that when writing or reading data, Interference can be suppressed.

0056The above effect can be obtained by providing a metal source line between the bit lines as in Example 3 (FIG. 15). However, in Example 3 (FIG. 16), since the word line WL is curved near the source line contact 32 (area 18), the distance between the bit lines BL and the word line WL becomes large, and the memory cell area 103 The area of is large. In the fourth embodiment, the bit line BL (dummy line) to which the active cell AC is not connected is used instead of the metal source line MSL. As a result, the distance between the bit lines BL and the word lines WL can be reduced as compared with the case where the metal source line MSL is provided between the bit lines BL, and the area of the memory cell area 104a can be reduced.

0057In the fourth embodiment, the number of the memory cell areas 104 is eight, but any number may be used as long as it is two or more. Also, the same 1-bit data is stored in 8 active cell ACs that share one wordline WL, but the combination of 2 or more active cell ACs that store the same 1-bit data is other. It may be a thing.

0058In the fourth embodiment, the bit line BL in which the active cell AC is not provided is provided with the dummy cell DC, but the bit line BL may be configured not to be provided with the dummy cell DC. As a result, the distance between the bit lines BL can be further reduced, so that the area of the memory cell area 104a can be further reduced.

0059Although the preferred examples of the present invention have been described in detail above, the present invention is not limited to the specific examples, and various modifications are made within the scope of the gist of the present invention described in the claims. Can be changed.

0060<figref num="1">FIG. 1 is a block diagram showing a comparative example and a configuration of a semiconductor device according to Examples 1 to 4.</figref><figref num="2">FIG. 2 is a block diagram showing the configuration of the control information storage area in FIG.</figref><figref num="3">FIG. 3 is a top view schematically showing the configuration of the semiconductor device according to the comparative example.</figref><figref num="4">FIG. 4 is a circuit diagram showing the details of the region 10 in FIG.</figref><figref num="5">FIG. 5 is a circuit diagram showing the details of the region 10 in FIG.</figref><figref num="6">FIG. 6 is a top view schematically showing the configuration of the semiconductor device according to the first embodiment.</figref><figref num="7">FIG. 7 is a circuit diagram showing the details of the region 11 in FIG.</figref><figref num="8">FIG. 8 is a top view showing the structure of the region 11 in FIG.</figref><figref num="9">FIG. 9 (a) is a cross-sectional view taken along line A-A1 in FIG. 8, and FIG. 9 (b) is a cross-sectional view taken along line B-B1 in FIG.</figref><figref num="10">FIG. 10 is a flowchart showing the flow of control of the semiconductor device according to the first embodiment.</figref><figref num="11">FIG. 11 is a flowchart showing the flow of control of the semiconductor device according to the first embodiment.</figref><figref num="12">FIG. 12 is a top view schematically showing the configuration of the semiconductor device according to the second embodiment.</figref><figref num="13">FIG. 13 is a circuit diagram showing the details of the region 12 in FIG.</figref><figref num="14">FIG. 14 is a top view schematically showing the configuration of the semiconductor device according to the third embodiment.</figref><figref num="15">FIG. 15 is a circuit diagram showing the details of the region 13 in FIG.</figref><figref num="16">FIG. 16 is a top view showing the structure of the region 13 in FIG.</figref><figref num="17">FIG. 17 is a top view schematically showing the configuration of the semiconductor device according to the fourth embodiment.</figref><figref num="18">FIG. 18 is a top view schematically showing the configuration of the memory cell area 104a in FIG.</figref><figref num="19">FIG. 19 is a circuit diagram showing the details of the region 14 in FIG.</figref><figref num="20">FIG. 20 is a top view showing the structure of the region 14 in FIG.</figref>

Code description

006110 Area on memory cell area 20, 22 current 30 bit line contact 32 Source line contacts 40 board 41 Source area 42 drain area 43 Tunnel oxide film 44 Floating gate 45 interlayer dielectric film 46 Control Gate 100 ~ 104 Memory cell area 200 Main control unit 202 Main storage area 204 Main input / output circuit 206 Primary address storage area 208 Main booster circuit 210 Control information storage area 212 Main address decoder 220 Memory cell control unit 222 address decoder 224 I / O circuit 228 Booster circuit