Power supply unit

The present invention relates to a power supply device, for example, a technique effective in applying to a switching power supply device that converts a high voltage into a low voltage.

For example, in Patent Document 1, n inductors connected in parallel to a common capacitor, n output switch devices connected to each inductor, and n devices for driving each output switch device by PWM control. A multi-phase back converter consisting of a phase output device and a phase control device that supplies a common control signal to each phase output device is described (Fig. 1). The phase control device supplies a phase timing signal such as a triangular wave and a PWM control signal for determining the PWM duty to n phase output devices. This triangular wave is determined by each of the n phase output devices at a different voltage level, whereby n different phase timing signals are generated for each of the n phase output devices (Fig. 12d). Each of the n phase output devices drives the corresponding output switch device in its own phase with a PWM duty based on the PWM control signal described above.

Further, Patent Document 2 describes n inductors connected in parallel to a common capacitor, n transistor pairs connected to each inductor, and n phases for driving each transistor pair by PWM control. A multi-phase converter consisting of an IC and a control IC that supplies a common control signal to each phase IC is described (Figs. 1 and 2). The control IC generates a clock signal, a phase-out signal (pulse signal), an error amplifier signal for determining the PWM duty, and the like. The first phase IC receives the phase-out signal from the control IC as a phase-in signal, delays it by one clock, and then outputs it to the second phase IC as a phase-out signal. The second phase IC receives the phase-out signal from the first phase IC as a phase-in signal, delays it by one clock, and then outputs it as a phase-out signal to the third phase IC, and so on. Finally, the phase-out signal from the nth phase IC is fed back as the phase-in signal of the control IC. Each phase IC drives the corresponding transistor pair with PWM duty according to the error amplifier signal based on the timing of its own phase-in signal.

Further, Patent Document 3 describes a semiconductor device in which a power MOSFET, a drive circuit for driving the power MOSFET, and a control circuit for transmitting a switching control signal to the drive circuit are mounted in one package (FIG. 6). 1, Fig. 2). This semiconductor device detects an error amplifier signal (judgment reference level) that reflects the detected voltage from an external capacitor coupled to the power MOSFET, and a signal that detects the current flowing through the power MOSFET and converts the voltage (lamp signal). A peak current control method is used in which the PWM duty is determined based on the comparison results (Figs. 8 and 9). Further, this semiconductor device has a built-in oscillation circuit, and the output of the oscillation circuit and the error amplifier signal described above can be shared with other semiconductor devices via an external terminal (Fig. 17).

Further, in Non-Patent Document 1, six inductors connected in parallel to a common capacitor, six transistor pairs connected to each inductor, and six transistor pairs driven by PWM control are described. A 6-phase back converter consisting of a driver IC and a control IC that controls each driver IC is described. The control IC consists of 6 pairs of external input terminals (plus and minus) for detecting the current flowing through the 6 inductors, and 6 external outputs that supply PWM signals with different phases to the 6 driver ICs. It is equipped with terminals and multiple external input terminals for externally setting the set voltage of the common capacitor.<patcit num="1"><text>Special Table 2005-520475</text></patcit><patcit num="2"><text>JP-A-2007-135390</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2008-17620</text></patcit><nplcit num="1"><text>"ISL6327 Data Sheet", [online], [Searched on February 12, 2008], Internet &lt;URL: http://www.intersil.com/data/fn/FN9276.pdf&gt;</text></nplcit>

<p num="0006"> For example, in various electronic devices and electric devices represented by personal computers (hereinafter, PCs), a desired DC voltage (for example, 12V, 5V, 3.3V, etc.) is generated from an AC voltage (for example, 100V, etc.) that is a commercial power source. It is equipped with an AC / DC converter (for example, ATX power supply). Further, in a notebook type PC or the like, a specific value of DC voltage is supplied by a battery. For example, various semiconductor components used in PCs and the like require a stable power supply voltage, and in some cases, multiple power supply voltage values are required. Therefore, the voltage generated by this AC / DC converter or battery is It is supplied to various semiconductor components after being converted to a predetermined voltage and a stable voltage by a step-down DC / DC converter (back converter). These are generally called POL (point of load) converters, etc. For example, in the case of a PC, various information units (CPU (Central Processing Unit), GPU) are placed on the motherboard and various expansion boards (graphic boards, etc.). (Graphics Processing Unit), memory, etc.)</p><p num="0007"> As such a back converter, a switching type back converter that can obtain high power efficiency is usually used. When the switching method is used, it is particularly important to reduce the ripple voltage caused by switching and to cope with the increase in current. That is, with respect to the latter, when the amount of load current increases, the on-resistance loss and heat generation of the switching transistor due to this increase cannot be ignored. In order to solve such a problem, for example, as described in Patent Documents 1 and 2 and Non-Patent Document 1, a plurality of inductors are connected in parallel to a common capacitor, and each inductor has a current in a different phase. It is beneficial to use a multi-phase technology that allows the current to flow. When the multi-phase technology is used, in principle, the ripple voltage is reduced as the number of phases is increased, and the load current amount needs to be distributed and supplied from each inductor (each switching transistor). Correspondence becomes easy. Moreover, since the value of the inductor can be reduced, high-speed response can be achieved.</p><p num="0008"> However, when the techniques of Patent Documents 1 and 2 and Non-Patent Document 1 are used, a master IC (phase control device of Patent Document 1, control IC of Patent Document 2, control IC of Non-Patent Document 1) is always provided. It is necessary to connect multiple slave ICs to. Therefore, it is not possible to reduce the cost in terms of mounting area and IC cost. For example, when a multi-phase power supply smaller than 6 phases is realized by using the technology of Non-Patent Document 1, the circuit for realizing the remaining phases and the like are wasted. On the other hand, for example, when the techniques of Patent Documents 1 and 2 are used, slave ICs may be provided according to the number of phases to be realized, but in addition, a master IC must be provided, so the number of phases to be realized is particularly high. The smaller the number, the lower the cost performance. In particular, since the mounting area is limited in notebook PCs and various mobile devices, it is desired to reduce the mounting components and the connection wiring between the mounted components as much as possible.</p><p num="0009"> Therefore, one of the objects of the present invention is to provide a power supply device capable of realizing a multi-phase power supply at low cost. The above-mentioned and other purposes and novel features of the present invention will be clarified from the description and the accompanying drawings of the present specification.</p>

<p num="0010"> The outline of typical embodiments of the invention disclosed in the present application will be briefly described as follows.</p><p num="0011"> The power supply device according to the embodiment of the present invention includes a plurality of semiconductor devices, a plurality of inductors coupled to the plurality of semiconductor devices, and an output capacitor commonly coupled to the plurality of inductors. .. Each semiconductor device starts from the first input terminal and the first output terminal, the first circuit that delays the trigger pulse signal input from the first input terminal and transmits it to the first output terminal, and this trigger pulse signal. It includes a control circuit that controls switching of the built-in transistor and supplies current to the corresponding inductor. Then, the plurality of semiconductor devices are coupled to each other in a ring shape by coupling their first output terminals to the first input terminals of any one semiconductor device other than themselves, thereby forming a multi-phase power supply. It is characterized by performing operations.</p><p num="0012"> With such a configuration, it is not necessary to provide a master IC as in the prior art, so that multi-phase power supply operation can be realized at low cost. In order to realize multi-phase power supply operation with such a configuration, more specifically, for example, any one of a plurality of semiconductor devices needs to generate a trigger pulse signal only once at startup. Therefore, each semiconductor device has a function of generating a trigger pulse signal at the time of activation according to an external setting. This external setting may be performed, for example, depending on whether or not an external resistor is connected to the first input terminal or the first output terminal. As a result, the number of terminals can be reduced as compared with the case where a dedicated terminal is separately provided, and the cost can be reduced.</p><p num="0013"> In addition, each of the above-mentioned semiconductor devices is provided with an error amplifier circuit for setting the switching time of the transistor, and receives an error amplifier signal from a second output terminal that outputs an error amplifier signal from this error amplifier circuit and an error amplifier signal from other than itself. It is desirable to have a second input terminal that can also receive. Thereby, for example, any one of the plurality of semiconductor devices can generate an error amplifier signal, and the other semiconductor devices can share the error amplifier signal. As a result, the number of wires and the like can be reduced, so that the cost can be reduced, and since the setting standard of the switching time is the same in each semiconductor device, switching control with little variation in each phase becomes possible. In particular, when the peak current control method is used for this switching control, it is advantageous because the current for each phase can be easily equalized. In this case, by detecting the current for each phase by the current of the transistor in each semiconductor device, the number of wires and the like can be reduced as compared with the case where the current of the inductor is detected, and the cost can be reduced. Become.</p><p num="0014"> Further, the power supply device according to the embodiment of the present invention is further provided with one semiconductor device for monitoring and setting in addition to the semiconductor device as described above. The semiconductor device for this monitoring setting includes, for example, a plurality of first setting terminals for setting the voltage value of the output capacitor and an error amplifier circuit as described above. In this case, this error amplifier circuit generates an error amplifier signal based on the detection voltage of the output capacitor and the information of the plurality of first setting terminals. Then, this error amplifier signal is input from the second input terminal of the plurality of semiconductor devices as described above, and is shared by the plurality of semiconductor devices. Since a plurality of first setting terminals generally have a large number of terminals, it is possible to realize a low-cost power supply device as a whole by separating them into different semiconductor devices. It should be noted that such a semiconductor device for monitoring setting can be equipped with, for example, a so-called droop function.</p>

<p num="0015"> Briefly explaining the effects obtained by typical inventions disclosed in the present application, a multi-phase power supply can be realized at low cost.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the same members are, in principle, given the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, when it is necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one of them. Is related to some or all of the other modifications, details, supplementary explanations, and the like.

In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number. Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of a component or the like, the shape is substantially the same unless otherwise specified or when it is considered that it is not apparent in principle. Etc., etc. shall be included. This also applies to the above numerical values and ranges.

(Embodiment 1) FIG. 1 shows a basic concept of a power supply device according to a first embodiment of the present invention, (a) is a schematic diagram showing a configuration example thereof, and (b) is an explanatory diagram showing an operation example of (a). is there. The power supply device shown in FIG. 1 (a) has a configuration that realizes an n (n 2) phase multi-phase power supply, and n semiconductor devices (semiconductor devices or semiconductor ICs) DEV [1] to DEV [ n], n inductors L1 to Ln, output capacitor Cv, etc.

Each of DEV [1] to DEV [n] includes a trigger input terminal TRG_IN, a trigger output terminal TRG_OUT, and a timer circuit TM. The TM takes the TRG_IN signal as an input, delays it based on the capacitor Ctm connected to the delay time setting terminal CT, and outputs the delayed signal from TRG_OUT. Although analog delay based on the capacitor Ctm is used here, it is not limited to this, and can be replaced with various general delay circuits such as digital delay using a flip-flop circuit or a counter circuit. Is.

TRG_IN and TRG_OUT of each semiconductor device DEV [1] to DEV [n] are connected in a ring shape as a whole by combining TRG_OUT of one semiconductor device with TRG_IN of another semiconductor device. That is, the TRG_OUT of the first stage DEV [k] (1 k (n-1)) is combined with the TRG_IN of the second stage DEV [k + 1], and the TRG_OUT of the final stage DEV [n] is the highest. It is combined with TRG_IN of DEV [1] which is the previous stage. One end of the inductors L1 to Ln is coupled to DEV [1] to DEV [n], and the other end is commonly coupled to one end of the output capacitor Cv. Further, DEV [1] to DEV [n] operate when the enable signal EN is activated.

In such a configuration, each of DEV [1] to DEV [n] performs PWM (Pulse Width Modulation) operation starting from the input signal to its own TRG_IN as shown in Fig. 1 (b), and itself. Supply current to the inductor corresponding to. Therefore, DEV [1] performs PWM operation, DEV [2] performs PWM operation after the delay time based on TM (referred to as Td) elapses, and then DEV [n] performs PWM operation in the same manner. After passing Td from, DEV [1] will perform PWM operation again. As a result, the switching frequency f (= (Td × n))^-1) [Hz] can realize n-phase multi-phase power supply operation.

By the way, in such a ring-coupled loop system, once a pulse signal is input, this pulse signal will circulate automatically after that, but this first pulse signal must be generated in some way. It doesn't become. Therefore, in the configuration example of FIG. 1A, DEV [1] sets the start trigger terminal ST to, for example, a fixed voltage (here, the ground voltage GND), so that a pulse is generated only once when the enable signal EN is activated. Generate. The other DEV [2] to DEV [n] do not generate this first pulse signal by setting ST to open, for example.

As described above, when the power supply device as shown in FIG. 1 is used, an n-phase multi-phase power supply can be realized by n semiconductor devices without the need for a separate master IC as in the conventional technology. As a result, the cost of the power supply device can be reduced in terms of the cost of the semiconductor device itself and the mounting cost thereof. In addition, it is possible to facilitate the design of the power supply device as compared with the conventional technique. That is, when using a master IC, it is necessary to provide compatible master ICs and n slave ICs, and in principle extend n wires from the master IC to n slave ICs. Complex design (wiring design, etc.) is required. On the other hand, the power supply device shown in FIG. 1 is easy to design because it is sufficient to provide semiconductor devices having the desired number of phases and connect TRG_OUT of one semiconductor device to TRG_IN of another semiconductor device on a one-to-one basis. Further, the semiconductor device in the power supply device of FIG. 1 can operate by itself by connecting its own TRG_IN to its own TRG_OUT, and can also be used as a single-phase power supply. With these, when it is desired to construct a power supply device having various phases, it can be flexibly dealt with, and it can be realized easily and at low cost.

FIG. 2 is a block diagram showing a more detailed configuration example of the power supply device of FIG. FIG. 3 is a waveform diagram showing an operation example of the power supply device of FIG. The power supply device shown in FIG. 2 is an example of realizing a two-phase multi-phase power supply, and further, a configuration example of a main part of the semiconductor device DEV is shown. Each of the semiconductor devices DEV [1] and [2] shown in FIG. 2 performs a PWM operation called a peak current control method as shown in Patent Document 3 described above.

DEV [1] contains 9 external terminals. ON / OFF [1] is the device operation enable setting terminal, CS [1] is the current sense terminal (current sense signal), EO_IN [1] is the error amplifier input terminal, and EO [1] is the error amplifier output terminal. Moreover, TRG_IN [1] is a trigger input terminal (trigger input signal), and TRG_OUT [1] is a trigger output terminal (trigger output signal). Furthermore, VIN [1] is a power supply voltage input terminal, SW [1] is a switch terminal, and FB [1] is an output power supply voltage detection terminal. Similarly, DEV [2] also has 9 external terminals (ON / OFF [2], CS [2], EO_IN [2], EO [2], TRG_IN [2], TRG_OUT [2], VIN [ 2], SW [2], FB [2]) are included.

The enable signal EN is input to ON / OFF [1] and [2]. Resistors Ri1 and Ri2 for current detection are connected to CS [1] and CS [2], respectively. EO [1] is combined with EO_IN [1] and EO_IN [2] respectively. TRG_OUT [1] is bound to TRG_IN [2] and TRG_OUT [2] is bound to TRG_IN [1]. In addition, the resistor Rs for the start trigger is connected to TRG_OUT [1]. The input power supply voltage Vin is input to VIN [1] and [2]. SW [1] is coupled to one end of the output capacitor Cv via the inductor L1, and SW [2] is coupled to one end of the Cv via the inductor L2. The voltage at one end of this Cv becomes the output power supply voltage Vout, and this Vout becomes the power supply voltage of a predetermined load LD such as a CPU. This Vout is also input to FB [1].

Each of the semiconductor devices DEV [1] and [2] has a timer circuit TM, a pulse generation circuit PGEN, a comparison circuit VC1, a flip-flop circuit FFp, an error amplifier circuit EA, a current detection circuit ACS, a blanking circuit BK, and a control logic. It is equipped with circuits LGC, driver circuits DV1 and DV2, and transistors Qh and Ql. Taking DEV [1] as an example, PGEN receives the trigger input signal from TRG_IN [1] and outputs the reset signal RES. FFp receives RES as a reset input, receives VC1 output as a set input, and outputs a PWM signal from (/ Q). In response to this PWM signal, the LGC drives the Qh gate via DV1 and the Ql gate via DV2.

For Qh, the drain is connected to VIN [1] and the source is connected to SW [1]. For Ql, the drain is connected to SW [1] and the source is connected to the ground voltage GND. ACS detects the current flowing through the drain of Qh, masks it with BK for a certain period of time, and then outputs it to CS [1]. Since the resistor Ri1 is connected to CS [1], this detected current is converted to voltage by CS [1]. In addition, the EA compares the output power supply voltage Vout detected by FB [1] with the reference voltage Vref to generate an error amplifier signal that serves as a determination reference for the PWM duty. This error amplifier signal is input again from EO_IN [1] via EO [1]. Then, VC1 compares the amount of current detected by CS [1] with reference to the error amplifier signal of EO_IN [1], and transmits the result to the set input of FFp.

On the other hand, the trigger input signal from TRG_IN [1] is also transmitted to the timer circuit TM. The timer circuit TM delays this trigger input signal by a predetermined delay time Td, and outputs it from TRG_OUT [1]. In addition, the TM includes a start trigger discriminant circuit STJG. This STJG determines whether the resistor Rs for the start trigger is connected to TRG_OUT [1]. When connected, the TM generates a pulse signal only once when the enable signal EN is input via ON / OFF [1], and outputs it from TRG_OUT [1]. Note that STJG of DEV [2] does not generate this pulse signal because Rs is not connected to its own TRG_OUT [2].

The power supply device of FIG. 2 operates as shown in FIG. First, DEV [1] receives the trigger input signal from TRG_IN [1] and generates the reset signal RES. This RES then drives Qh to the'H'level (ie on) and Ql to the'L'level (ie off). Actually, it is necessary to set a dead time at the switching timing between Qh and Ql, but this is omitted here. When Qh is driven on, the input power supply voltage Vin from VIN [1] is transmitted to SW [1].

Since the voltage of this SW [1] is applied to the inductor L1, a lamp wave-shaped current that rises with a predetermined slope flows through Qh. This current is converted to voltage by CS [1]. Here, the blanking circuit BK in FIG. 2 provides a constant mask time from when Qh is turned on until a voltage is generated in CS [1], but this causes a malfunction due to detecting the spike current due to switching. This is to prevent it. Although not shown, this spike current is associated with the recovery current of the body diode connected to the Ql. DEV [1] drives Qh to the'L'level (ie off) when the voltage of this CS [1] reaches the voltage level of the error amplifier signal input from EO_IN [1], and Ql To the'H'level (ie on). When Ql is turned on (Qh is off), the energy stored in L1 keeps the current flowing through L1 through this Ql. As a result, the current IL1 flowing through the inductor L1 rises with a predetermined slope while Qh is on (Ql is off), and decreases with a predetermined slope while Ql is on (Qh is off).

Further, when a trigger input signal is input from TRG_IN [1], DEV [1] adds a delay time Td to it and outputs it from TRG_OUT [1]. The trigger output signal from this TRG_OUT [1] is input to TRG_IN [2] as a trigger input signal of DEV [2]. After receiving the trigger input signal from this TRG_IN [2] and generating the reset signal RES, the DEV [2] performs the same operation as in the case of the DEV [1] described above. Further, DEV [2] outputs a trigger output signal from TRG_OUT [2] like DEV [1], and this is input to TRG_IN [1] as a trigger input signal of DEV [1]. The operation like that is repeated.

As a result of such an operation, the current IL2 of the inductor L2 is generated with a delay of half a cycle from the current IL1 of the inductor L1 described above. The output capacitor Cv receives the IL1 and IL2 to generate a predetermined output power supply voltage Vout, and the load LD uses this Vout as the power supply voltage and IL1 and IL2 as the power supply current to perform the desired operation. Although not particularly limited, the input power supply voltage Vin is 12V, the output power supply voltage Vout is 1.2V, and each of IL1 and IL2 is several tens of A and the like.

As described above, the power supply device of FIG. 2 includes a feedback loop for feeding back the output power supply voltage Vout, and a feedback loop for monitoring and feeding back the input current IL, and the error amplifier signal generated by the feedback loop of this voltage ( It is a method of controlling the peak current of the input current IL based on the judgment level). When such a peak current control method is used, as described in Patent Document 3, the unstable element of the feedback loop system can be canceled to facilitate phase compensation, and the output power supply voltage Vout associated with the load LD can be used. It is possible to respond to fluctuations in high speed.

Further, the power supply device of FIG. 2 shares the error amplifier signal generated by the error amplifier circuit EA of DEV [1] between DEV [1] and DEV [2] via EO_IN [1] and EO_IN [2]. It is composed. In the multi-phase power supply, a well-balanced and stable power supply can be realized by making the current flowing in each phase more equal. For example, when each of DEV [1] and DEV [2] uses its own EA to generate its own error amplifier signal (judgment level), the judgment level may vary slightly due to process fluctuations and the like. is there. On the other hand, in the power supply device of FIG. 2, since this determination level is unified, it is possible to further equalize the current IL1 and the current IL2.

Furthermore, by constructing a multi-phase power supply using the semiconductor device as described in FIG. 2, the number of wirings can be reduced as the number of phases increases. That is, for example, in the above-mentioned Patent Documents 1 and 2 and Non-Patent Document 1, the current is detected by wiring n pairs from the master IC and the slave IC to n inductors for n phases. , The number of wires increases as the number of phases increases. On the other hand, in the power supply device of FIG. 2, since the current is detected inside each of the semiconductor devices DEV [1] and [2], such wiring is unnecessary. From the above, it can be said that the power supply device of FIG. 2 has a configuration suitable for realizing a multi-phase power supply, in addition to the various effects described in FIG. Although an example of two phases is shown here, it is easy to understand that the same configuration and operation can be obtained in three or more phases, and the same effect can be obtained.

As described above, by using the power supply device of the first embodiment, it is possible to typically realize a low-cost multi-phase power supply.

(Embodiment 2) In the second embodiment, a more detailed configuration example of the semiconductor device DEV described in the first embodiment will be described. FIG. 4 is a block diagram showing a detailed configuration example of a semiconductor device used in the power supply device according to the second embodiment of the present invention. FIG. 5 is a plan view showing an example of the package form of the semiconductor device of FIG. The configuration example shown in FIG. 4 is a further embodiment of the configuration example of FIG. 2 described above, and the rough configuration and operation thereof are the same as those in FIGS. 2 and 3. Here, the description will be given focusing on the parts that are further embodied from the configuration example of FIG.

The semiconductor device (semiconductor device, semiconductor IC) DEV shown in FIG. 4 is roughly classified into a transistor Qh which is a high-side transistor (for example, MOSFET), a transistor Ql which is a low-side transistor (for example MOSFET), and these transistors. It is composed of various control circuits that control. A diode D1 is installed between the source and drain of Qh, and a Schottky diode SBD1 is installed between the source and drain of Ql. By providing this SBD1, it is possible to reduce the voltage drop of the current path on the Ql side, especially during the dead time from turning off Qh to turning on Ql.

As shown in FIG. 5, the transistor Qh and the diode D1 are formed on the semiconductor chip HSCP, the transistor Ql and the Schottky diode SBD1 are formed on the semiconductor chip LSCP, and various other control circuits are formed on the semiconductor chip CTLCP. Is formed in. That is, the semiconductor device DEV shown in FIG. 5 is a multi-chip module SiP (System in Package) or (MCM: Multi Chip Module) in which three semiconductor chips are mounted in one package. This semiconductor device DEV is not particularly limited, but is realized by, for example, an 8 mm × 8 mm QFN (Quad Flat Non-leaded package) having 56 external terminals.

In this package, LSCP is mounted in about half of the mounting area, and HSCP and CTLCP are mounted in the area that divides the remaining area into about two equal parts, respectively. That is, the transistor area of the low-side transistor Ql is designed to be about twice as large as the transistor area of the high-side transistor Qh. As explained in FIGS. 2 and 3, for example, when converting a 12V input power supply voltage Vin to a 1.2V output power supply voltage Vout, the time to turn on Ql is longer than the time to turn on Qh. Becomes longer. Therefore, by increasing the transistor area of Ql, the on-resistance can be lowered and the power efficiency of the power supply device can be improved. The details are shown in Fig. 4, but various external terminals connected to Qh are arranged around HSCP, various external terminals connected to Ql are arranged around LSCP, and various external terminals connected to Ql are arranged around CTLCP. Is arranged with external terminals for various control signals that control Qh and Ql.

In FIG. 4, the drain of Qh is connected to the power supply voltage input terminal VIN and the source is connected to the switch terminal SW, and the drain of Ql is connected to the SW and the source is connected to the ground voltage terminal PGND. This PGND is a terminal dedicated to Qh and Ql, and is provided separately from the ground voltage of various control circuits so as not to give switching noise to other various control circuits. An output capacitor Cv is connected to the SW via the inductor L, and the voltage of this Cv becomes the output power supply voltage Vout.

Although not shown, the current detection circuit ACS is realized, for example, by forming a 1/18500 size transistor in the HSCP that is connected to the transistor Qh in a current mirror. Then, with the current of Qh as IL, the current of IL / 18500 detected by this ACS is supplied to the current sense terminal (current sense signal) CS via the mask period (for example, several tens of ns) by the blanking circuit BK. To. An external resistor Ri for current detection is connected to the CS, which converts the current into a voltage. A bias current source IB2 is connected to the CS to stabilize the operation.

The driver circuits DV1 and DV2 drive Qh and Ql, respectively, based on the control from the control logic circuit LGC. The input power supply voltage Vin is supplied to the power supply terminal VCIN in the same manner as the power supply voltage input terminal VIN. The power supply voltage from this VCIN is supplied to the regulator circuits VREG1 and VREG2 via the voltage detection circuit UVLOC. The voltage detection circuit UVLOC detects that the input power supply voltage is equal to or higher than a predetermined voltage, and in that case, enables the operation of VREG1 and VREG2. VREG1 and VREG2 receive an input power supply voltage such as 12V and generate an internal power supply voltage such as about 5V. VREG1 supplies the generated internal power supply voltage to various control circuits and outputs it to the internal power supply terminal REG5. VREG2 supplies the generated internal power supply voltage to DV1 and DV2, and outputs it to the internal power supply terminal DRV5. Capacitors C4 and C5 for voltage stabilization are connected to the internal power supply terminals REG5 and DRV5, respectively.

Here, since the driver circuits DV1 and DV2 drive Qh and Ql, they require a relatively large current and generate a lot of noise. On the other hand, since many other analog circuits such as voltage comparison circuits are included in other various control circuits, it is necessary to reduce power supply noise. Therefore, these power supplies are individually generated by two regulator circuits VREG1 and VREG2. Further, the regulator voltage monitoring circuit SV monitors the internal power supply voltage generated by VREG1 and VREG2, and outputs an internal power supply enable signal REGGD when it is within a predetermined range.

The boot terminal BOOT supplies the power supply voltage of the driver circuit DV1. The BOOT is connected to the DRV5 via the Schottky diode SBD2, and is connected to the SW via the external boost capacitor Cb and the external resistor Rb. When Ql is on, an internal supply voltage (DRV5) is applied to this Cb via SBD2 and BOOT. After that, when Qh is turned on, Vin transmitted to SW is boosted by this Cb and supplied to DV1. This allows DV1 to generate a voltage above the Qh threshold.

In addition to the internal power supply enable signal REGGD described above, the control logic circuit LGC has a PWM signal from the flip-flop circuit FFp, an ON / OFF signal from the device operation enable setting terminal (ON / OFF), and an excess current detection circuit OCPC. It operates by receiving the excess current detection signal OCP and the excess voltage detection signal OVP from the excess voltage detection circuit OVPC. The LGC uses PWM signals to control DV1 and DV2 when the ON / OFF signal (device operation enable signal) is on (that is, the enabled state) and the REGGD, OCP, and OVP are all normal.

An enable signal (not shown) is input from the outside to the device operation enable setting terminal (ON / OFF), and the transistor Q20 is connected. The transistor Q20 is driven on by the OR20 when the temperature detection circuit TSD detects abnormal heat generation or when the excess voltage detection circuit OVPC detects the excess voltage detection signal OVP. In this case, the ON / OFF signal is forcibly turned off (that is, the operation disabled state) regardless of the enable signal from the outside. The excess voltage detection circuit OVPC monitors the output power supply voltage Vout by the output power supply voltage detection terminal FB, and outputs OVP when an excessive voltage occurs. The excess current detection circuit OCPC is connected to the CS via the comparison circuit VC3, and outputs the OCP when an excessive voltage is generated in the CS (that is, an excessive current flows).

The pulse generation circuit PGEN receives the trigger input signal from the trigger input terminal TRG_IN and outputs the reset signal RES and the max duty signal MXD. The reset signal RES becomes the reset input of the flip-flop circuit FFp, and the MXD becomes the set input of FFp via the OR1 circuit. The MXD forces the PWM when the maximum allowable on-duty value is reached to prevent the inductor L from saturating and damaging the device if the on-duty of the PWM signal is too large. It is a signal for lowering the signal. Further, the output of the comparison circuit VC1 is connected to the other input of the OR circuit OR1. VC1 compares the error amplifier signal input from the error amplifier input terminal EO_IN with the signal obtained by adding a predetermined offset voltage (0.1V) to the CS voltage.

The control logic circuit LGC forcibly drives Qh and Ql off when the excess current detection signal OCP or the excess voltage detection signal OVP is input. The output power supply voltage monitoring circuit PWGD detects that the output power supply voltage Vout detected by the output power supply voltage detection terminal FB is equal to or higher than a predetermined value. That is, it is detected that the Vout generation operation is normally performed. When detected, the PWGD drives the transistor Q21 and outputs a detection signal to the power good terminal PG.

The error amplifier circuit EA generates an error amplifier signal by extracting the difference between the reference voltage Vref and the output power supply voltage detection terminal FB, and outputs it from the error amplifier output terminal EO. The output power supply voltage Vout of the output capacitor Cv is input to the FB via the resistance voltage dividers of the external resistors R1 and R2. The error amplifier signal output from the EO is returned to EO_IN via the resistance voltage dividers of the external resistors R5 and R6 after the bandwidth of the power supply circuit is set by the external resistor R4 and the external capacitor C2.

The EA is also connected to the soft start terminal TRKSS. An external resistor R3, an external capacitor C1, and a transistor Q14, which is an internal transistor, are connected to TRKSS. Q14 is set through the OR2 circuit when the ON / OFF signal is off (that is, the operation is disabled), the internal power supply enable signal REGGD is disabled, or the excess current detection signal OCP is activated. Drive TRKSS to ground voltage GND. In this case, the output (EO) of the EA becomes the GND level, and the switching operation stops. Conversely, when the OCP is inactive, the ON / OFF signal is on, and REGGD is enabled, Q14 is turned off and charge is accumulated in C1 from the internal power supply terminal REG5 via R3. As a result, the voltage of TRKSS rises slowly, and a soft start is executed in which the on-duty of the PWM signal is gradually increased. The ground voltage terminal SGND is different from the above-mentioned PGND for various control circuits operated by the internal power supply (REG5).

Although the details will be described later, the timer circuit TM operates under the control of the ON / OFF signal and the internal power supply enable signal REGGD, receives the trigger input signal from the trigger input terminal TRG_IN, and adds a predetermined delay time to the trigger. Output from the output terminal TRG_OUT. The delay time at this time is set by the external capacitor Ctm and the external resistor Rtm connected to the delay time setting terminal CT. Further, TM includes a start trigger discrimination circuit STJG, and STJG generates a pulse signal only once at the start of operation after the power is turned on when a resistor is connected to TRG_OUT.

FIG. 6 is a wiring diagram showing a configuration example of a power supply device when a multi-phase power supply is realized by using the semiconductor devices of FIGS. 4 and 5. Here, a two-phase power supply device is taken as an example, but of course, it can be similarly expanded to three or more phases. Most of the external resistors and external capacitors connected to the external terminals of the semiconductor devices DEV [1] and DEV [2] are the same as those described in FIG. Here, the explanation will be limited to the characteristic points of constructing the multi-phase power supply.

First, TRG_OUT of DEV [1] is connected to TRG_IN of DEV [2], and TRG_OUT of DEV [2] is connected to TRG_IN of DEV [1]. Is done. That is, as described in FIG. 3, a current is supplied from the SW of DEV [1] to the inductor L1 at a certain cycle, and a current is supplied from the SW of DEV [2] to the inductor L2 in a form deviated from this by half a cycle. The output power supply voltage Vout is generated by inputting these currents to the output capacitor Cv. Here, an external resistor Rs is connected between TRG_OUT of DEV [1] and the ground voltage GND in order to generate a pulse signal only once at the start of operation after the power is turned on (at startup or at startup). Will be done. On the other hand, this external resistor is not connected to TRG_OUT of DEV [2].

Vout is input to the FB of DEV [1] via the resistance voltage dividers of the external resistors R1 and R2. On the other hand, the FB of DEV [2] is connected to the ground voltage GND. That is, as described in FIGS. 2 and 3, DEV [1] generates an error amplifier signal corresponding to Vout, and this is shared by DEV [1] and DEV [2]. Specifically, the EO of DEV [1] is connected to the EO_IN of DEV [1] via the resistance voltage divider by the external resistors R51 and R61, and the DEV is connected to the resistance voltage divider by the external resistors R52 and R62. Connected to EO_IN in [2]. As a result, the current balance of each phase can be equalized as described in FIGS. 2 and 3. Here, the EO of DEV [1] is connected to the EO_IN of DEV [2] via R52 and R62, but even if the EO_IN of DEV [1] is connected to the EO_IN of DEV [2] as it is. Good.

The enable signal EN is commonly input to ON / OFF of DEV [1] and DEV [2] via the external resistor R9. In addition, TRKSS of DEV [1] and TRKSS of DEV [2] are also connected in common. This makes it possible to match the startup and shutdown timings between DEV [1] and DEV [2].

7A and 7B show the details of the timer circuit TM of the semiconductor device DEV of FIG. 4, where FIG. 7A is a circuit diagram showing a configuration example thereof, and FIG. 7B is a waveform diagram showing an operation example thereof. The timer circuit TM shown in FIG. 7 is composed of a flip-flop circuit FF1, a transistor Q1, an OR circuit OR1, OR2, a comparison circuit CMP1, a start trigger discrimination circuit STJG, and the like. FF1 controls Q1 with the inverting output node (/ Q) with TRG_IN as the set input and the OR2 output as the reset input. On the other hand, an external resistor Rtm is connected between the delay time setting terminal CT and the internal power supply voltage (REG5), and an external capacitor Ctm is connected between the CT and the ground voltage GND. Q1 is provided between this CT and the ground voltage GND.

That is, when a set input is made to FF1, Q1 is turned off and Ctm is charged, and when a reset input is made, Q1 is turned on and Ctm is discharged. The inverted signal of the ON / OFF signal and the inverted signal of REGGD are input to OR1, and the calculation result is transmitted to the reset input of FF1 via one input of OR2. That is, the reset input is performed when the operation is disabled or the internal power supply is disabled, and the reset input is not performed when the internal power supply is not in the normal operating state.

CMP1 compares the CT voltage with the reference voltage Vref_CT and generates a timer output signal TM_OUT when the CT voltage is higher than Vref_CT. This TM_OUT is output to the start trigger discrimination circuit STJG and becomes the other input of OR2. Therefore, as shown in FIG. 7 (b), the Ctm is charged by receiving the trigger input signal from TRG_IN, and the discharge operation is performed when the CT voltage reaches Vref_CT. Then, when transitioning from this charging operation to the discharging operation, TM_OUT is output, and the TM delay time Td is from the input to TRG_IN to the output of TM_OUT.

This delay time Td [sec] is given by Eq. (1) using the capacitance value of Ctm, the resistance value of Rtm, and the voltage values of Vref_CT and REG5. Td = -Ctm Rtm Ln {1-(Vref_CT) / REG5} (1) Further, when the multi-phase power supply operation as shown in FIG. 6 is performed by using such a timer circuit TM, the switching frequency f [Hz] is given by Eq. (2). f = (Td × number of phases)^-1 (2) The switching frequency f is not particularly limited, but is set to, for example, several hundred k [Hz]. When the switching frequency f is determined, Td is determined according to the number of phases to be realized, and Ctm and Rtm that realize this Td are determined. If there is a variation in accuracy between Ctm and Rtm, the phase difference between each phase will shift. For example, Ctm and Rtm with an absolute accuracy of 1% or 2%, which are generally used, are used. If is used, there will be almost no problem in actual use.

FIG. 8 is a circuit diagram showing a detailed configuration example of the start trigger discrimination circuit STJG in the timer circuit TM of FIG. 7. The start trigger discrimination circuit STJG shown in FIG. 8 includes a clocked inverter circuit CIV, a current mirror circuit CM, an inverter circuit IV3, IV5, a logical product circuit AD1, an inverting logical product circuit ND1, a one-shot pulse generation circuit OSPG, and a one-shot delay pulse. It is composed of the generation circuit OSPG_DLY, the AND circuit OR3, and so on. The CIV is connected to the gates of the MOSFETs Q11 and Q12 connected in series between the internal power supply (REG5) and the output node Nb, the NMOS transistors Q13 and Q14 connected in series between Nb and the ground voltage GND, and the gate of Q11. It is equipped with the inverter circuit IV4.

The current mirror circuit CM consists of current sources IB12 and MIMO transistors Q15 and Q16 provided on one current path from the internal power supply (REG5) to GND, and current sources IB11 and MIMO provided on the other current path. It includes a transistor Q17 and an MIMO transistor Q18 that controls activation / deactivation of CM. The current I2 from IB12 flows to the common source node via diode-connected Q15 and Q16, and from here to GND via Q18. On the other hand, the current I1 from IB11 flows to the common source node via Q17, and then flows to GND via Q18. The Q17 has its gate and source connected in common with the gate and source of the Q16 and has the same transistor size as the Q16.

The output node Nb of CIV and the connection node of IB12 and Q15 in CM are both connected to TRG_OUT. The AD1 receives the internal power supply enable signal REGGD and the ON / OFF signal (device operation enable signal), and drives Q11 and Q14 of the CIV based on the logical product result. This activates the CIV when both internal power and device operation are enabled, and deactivates the CIV when one of them is disabled. Also, the output of AD1 is connected to Q18 in CM via IV3. As a result, contrary to CIV, the CM is deactivated when both the internal power supply and the device operation are enabled, and the CM is activated when one of them is disabled.

ND1 takes the connection node Na of IB11 and Q17 in CM and the output of IV3 as inputs, and outputs the inverse AND operation result to OSPG_DLY. OSPG_DLY receives the transition to the'H'level of ND1 and generates a one-shot pulse signal, which is delayed for a certain period of time (for example, 10 μs) and output to one input of OR3. The timer output signal TM_OUT described in FIG. 7 is input to the other input of OR3. OR3 outputs the OR operation result of these inputs to OSPG. Following the transition to the'H'level of OR3, OSPG generates a one-shot pulse signal and transmits it via IV5 to the gates of Q12 and Q13 in CIV.

In such a configuration, the CIV functions as an output buffer, and the CM functions as a determination circuit for whether or not external resistors Rs are connected. Both CIV and CM are connected to TRG_OUT, but they act complementaryly so that while one is activated, the other is inactive, so they do not affect each other. That is, for example, while the determination is being made by the CM, the CIV does not affect this determination operation.

To explain the operation concretely, first, in the state before startup, the ON / OFF signal is at the'L'level and / or the REGGD is at the'L' level, so the CIV is inactive (Q11 and Q14 are off). Then, the CM becomes active (Q18 is on). Then, one input of ND1 (output of IV3) becomes'H'level. In such a state, when an external resistor Rs (for example, 27 kΩ) is connected to TRG_OUT, the current I2 (for example, 10 μA) of IB12 flows to the Rs side, and the applied voltage of Q15 and Q16 is less than the threshold voltage. Therefore, it is turned off. This turns off Q17 and puts node Na at the'H'level. As a result, the output of ND1 is at the'L'level. On the other hand, when the external resistor Rs is not connected to TRG_OUT, the current I2 (for example, 10 μA) of IB12 flows through Q15 and Q16. As a result, the current of I2 also flows in Q17, but since this is larger than the current I1 of IB11 (for example, 5 μA), the node Na becomes the'L'level. As a result, the output of ND1 is at the'H'level.

After that, when the startup is performed, the ON / OFF signal becomes the'H'level and the REGGD becomes the'H' level, so the CIV becomes the active state (Q11 and Q14 are on) and the CM becomes the inactive state (Q18 is off). ). As a result, one input of ND1 (output of IV3) transitions from the'H'level to the'L'level. Here, when Rs is connected to TRG_OUT, the output of ND1 receives the'L'level transition of one of the inputs and transitions from the'L'level to the'H'level. Conversely, if Rs is not connected to TRG_OUT, the output of ND1 remains at the'H'level.

Therefore, OSPG_DLY outputs a one-shot pulse signal only when Rs is connected to TRG_OUT. This one-shot pulse signal is input to the OSPG via OR3, the OSPG outputs the one-shot pulse signal again, and this signal is output to TRG_OUT via IV5 and the active CIV. Also, when OR3 receives the timer output signal TM_OUT, OSPG outputs a one-shot pulse signal, and this signal is output to TRG_OUT via IV5 and CIV. Since the CM is in an inactive state during the operation period after the start-up, the one-shot pulse signal is not affected. Furthermore, during this operating period, the output of ND1 is fixed at the'H'level by the output of IV3 regardless of the node Na in the CM, and OSPG_DLY will not operate again.

As described above, by using the timer circuit TM and the start trigger discrimination circuit STJG described in FIGS. 7 and 8, each semiconductor device receives the trigger input signal from TRG_IN, adds the delay time Td to it, and starts from TRG_OUT. The trigger output signal can be output. Further, a semiconductor device in which an external resistor Rs is connected to TRG_OUT can output a trigger output signal from TRG_OUT only once at its startup (startup). In this case, for example, in FIG. 6, the power switching operation is first started by the DEV [2] that has received the TRG_OUT of the DEV [1] at the time of startup, and then the DEV [1] is the power supply. The switching operation will be started.

In summary, the configuration example shown in FIG. 7 is a means for determining the presence or absence of external resistors Rs (current mirror circuit CM) and, if present, a start signal (REGGD, ON /) in the one-shot pulse signal generation circuit. It is equipped with means (ND1, OSPG_DLY, etc.) that reflect the transition of (OFF) and do not reflect the transition of the start signal when there is none. As long as the configuration is provided with such means, of course, the configuration is not limited to the configuration example shown in FIG. 7, and various changes can be made. Of course, it is also possible to make a determination based on the presence / absence of a connection to TRG_IN instead of the determination based on the presence / absence of a connection to TRG_OUT.

Further, the determination is not limited to the external resistance Rs, and for example, the determination can be made by setting the external terminal to the power supply voltage level or the ground voltage level. However, in this case, the number of external terminals is increased by one pin, and from this point of view, it is desirable to use a method of determining by external resistance Rs. Since Rs has a high resistance such as 27 kΩ, it has almost no effect on the trigger output signal from TRG_OUT.

As described above, by using the power supply device of the second embodiment, it is possible to realize a typically low-cost multi-phase power supply as in the case of the first embodiment.

(Embodiment 3) In the third embodiment, an example in which a single-phase power supply is realized by using the semiconductor device DEV described in the second embodiment (FIG. 4 or the like) will be described. FIG. 9 is a wiring diagram showing a configuration example of the power supply device according to the third embodiment of the present invention. The semiconductor device DEV [1] shown in FIG. 9 is connected to an external resistor and an external capacitor similar to the DEV of FIG. 4 and the DEV [1] of FIG. The difference is that the trigger output terminal TRG_OUT of DEV [1] is connected to its own trigger input terminal TRG_IN, and the external resistor Rs is connected to this TRG_OUT. Other than that, it is the same as the DEV in Fig. 4 and the DEV [1] in Fig. 6, so detailed explanation is omitted.

Since the semiconductor device DEV described in Fig. 4 and the like does not require a master IC as in the conventional technology and is a configuration example in which it can operate independently, a single-phase power supply can be obtained by making the connection as shown in Fig. 9. Can operate as. In this case, DEV [1] detects the external resistance Rs at startup, generates a trigger output signal from TRG_OUT, and starts the power supply switching operation when it is input to TRG_IN as a trigger input signal. The switching frequency f [Hz] when the configuration example of FIG. 9 is used is f = (Td) based on the above equation (2), where the delay time of the trigger input signal and the trigger output signal is Td.^-1Will be.

In this way, by using the semiconductor device DEV described in FIG. 4 and the like, not only the multi-phase power supply but also the single-phase power supply can be easily realized or at low cost, and the flexibility when designing the power supply of the system is increased. Can be improved. That is, by using 1 to n semiconductor devices, a 1 to n phase power supply can be realized.

(Embodiment 4) FIG. 10 shows the basic concept of the power supply device according to the fourth embodiment of the present invention, (a) is a schematic diagram showing a configuration example thereof, and (b) is an explanatory diagram showing an operation example of (a). is there. Similar to the power supply device of FIG. 1, the power supply device shown in FIG. 10 realizes an n-phase multi-phase power supply by connecting n semiconductor devices DEVd [1] to DEVd [n] in a ring shape. It has become. In the configuration example of FIG. 1 (a), the interval between each phase is determined in an analog manner using the timer circuit TM, whereas in the configuration example of FIG. 10 (a), the reference clock signal is used to digitally determine the interval. The main feature is that the interval between each phase is set.

In FIG. 10A, the phase output terminal (phase output signal) PH_OUT [1] of DEVd [1] is connected to the phase input terminal (phase input signal) PH_IN [2] of DEVd [2]. PH_OUT [2] of DEVd [2] is connected to PH_IN [3] of DEVd [3], and so on, PH_OUT [n] of DEVd [n] is connected to PH_IN [1] of DEVd [1]. Will be done. Here, as shown in FIG. 10B, each of DEVd [1] to DEVd [n] generates such a phase output signal in synchronization with the reference clock signal SYNC. In this example, DEVd [n-1] generates PH_OUT [n-1] in synchronization with the falling edge of SYNC, and DEVd [n] that receives this is specified in synchronization with the next rising edge of SYNC. The PWM operation (SW [n]) of is started, and the operation to generate PH_OUT [n] is performed in synchronization with the next fall.

Here, this reference clock signal SYNC is generated by DEVd [1] in which the capacitor Cf is connected to the frequency setting terminal CTF, and is output from the reference clock signal terminal SYNC [1] of DEVd [1]. On the other hand, the CTF of DEVd [2] to DEVd [n] is the ground voltage. In this case, the reference clock signal terminals SYNC [2] to SYNC [n] of DEVd [2] to DEVd [n] behave as input terminals, and by receiving the reference clock signal SYNC from DEVd [1], DEVd [2] A common reference clock signal SYNC can be used from 1] to DEVd [n]. Such behavior of the reference clock signal terminal can be realized by using the technique described in Patent Document 3.

FIG. 11 shows an example around the phase input signal and the phase output signal in the semiconductor device of FIG. 10, where (a) is a schematic configuration diagram of a master device, (b) is a schematic configuration diagram of a slave device, and (c). ) Is an explanatory diagram showing an example of the operation. The semiconductor device DEVd [1] shown in FIG. 11 (a) includes an oscillation circuit OSC, a reference clock control unit SYNC_CTL, a disjunction circuit OR30, a logical product circuit AD30, a flip-flop circuit FF30, a one-shot pulse generation circuit OSPG1, OSPG2, and the like. Includes. As described in FIG. 10, this device is a master device that generates a reference clock signal.

OSC generates a reference clock signal SYNC at a frequency corresponding to the capacitor Cf connected to the frequency setting terminal CTF. This SYNC is output from the reference clock signal terminal SYNC [1] via SYNC_CTL. The phase input terminal PH_IN [1] is connected to the set input of the FF30 via one of the inputs of the OR30. Therefore, when the phase input signal is input, the FF30 is in the set state and its output (Q) is at the'H'level. The output (Q) of this FF30 is transmitted to one input of the AD30. SYNC is transmitted to the other input of the AD30. Therefore, when FF30 is set along with the phase input signal, SYNC is output from AD30.

The output of this AD30 is input to OSPG2. OSPG2 receives the falling edge of SYNC, generates a one-shot pulse signal, and outputs this as a phase output signal from PH_OUT [1]. As a result, as shown in FIG. 11 (c), the phase input signal synchronized with the falling edge of SYNC is received from the previous stage, and the phase output signal is output at the next falling edge. On the other hand, the one-shot pulse signal of this OSPG2 becomes the reset input of FF30. As a result, as shown in FIG. 11 (c), only one'H'pulse signal in SYNC is output from AD30. The'H'pulse signal from this AD30 is transmitted to the internal circuit as a PWM enable signal PWM_EN, and the internal circuit synchronizes with this rising edge and sends a transistor (that is, Qh, Ql in Fig. 2) with a predetermined PWM duty. Drive.

The reference clock signal SYNC from OSC is also input to OSPG1. OSPG1 generates a start-up pulse signal only once when the reference clock signal SYNC from the OSC stabilizes after the device starts up. This start-up pulse signal becomes the set input of the FF30 via the other input of the OR30. Then, the phase output signal and the PWM_EN are generated in the same manner as in the case of the phase input signal shown in FIG. 11 (c). In this case, unlike the case of the second embodiment, this master device first starts the switching operation. That is, in the second embodiment, the master device generates the trigger output signal only once at the beginning, but in the fourth embodiment, the master device generates the trigger input signal only once at the beginning. It is a configuration example to be performed.

Further, the semiconductor device DEVd [n] shown in FIG. 11 (b) also has the same configuration as that of DEVd [1] in FIG. 11 (a). However, the operation of DEVd [n] is slightly different from that of DEVd [1] because its frequency setting terminal CTF is the ground voltage GND. That is, the reference clock signal terminal SYNC [n] of DEVd [n] behaves as an input terminal, and the reference clock signal SYNC input from here performs the operation as shown in FIG. 11 (c). In this case, OSC is not operating and OSPG1 is not operating, so the start pulse signal is not generated.

As described above, by using the power supply device of the fourth embodiment, it is possible to realize a typically low-cost multi-phase power supply as in the case of the first embodiment and the like. Further, since the multi-phase power supply operation is performed in synchronization with the reference clock signal SYNC, the variation in the phase difference between each phase can be easily reduced as compared with the case where the analog delay described in the second embodiment or the like is used. it can.

(Embodiment 5) In the fifth embodiment, an example of a power supply device in which the semiconductor devices as described above are used and the functions are further expanded will be described. FIG. 12 is a schematic view showing an example of the configuration of the power supply device according to the fifth embodiment of the present invention. The power supply device shown in FIG. 12 is provided with a monitoring setting device DEV_SVC in addition to n semiconductor devices DEV [1] to DEV [n] connected to each other by a ring as described in FIG. 1, for example. It is a feature. It is assumed that each of DEV [1] to DEV [n] includes, for example, the configuration example shown in FIG.

Although the details will be described later, the monitoring setting device DEV_SVC has a function of changing the judgment level of the error amplifier mainly based on a plurality of output power supply voltage setting terminals VIDs, thereby setting the value of the output power supply voltage Vout of the output capacitor Cv. .. That is, for example, as shown in FIG. 6, in the conventional embodiments, the error amplifier signal (EO) from DEV [1] is shared by the error amplifier input terminals EO_IN of DEV [1] to DEV [n]. An example is shown. On the other hand, in the configuration example of FIG. 12, the error amplifier signal from DEV_SVC is shared by the error amplifier input terminals EO_IN of DEV [1] to DEV [n].

Since such an output power supply voltage setting terminal VID requires a large number of pins, when the same function is realized by the configuration example of the previous embodiments (that is, the power supply device of the same device only), all of them are used. You need to provide this VID for your device. Therefore, by realizing this function with another chip as shown in the configuration example of FIG. 12, the cost can be reduced as a whole. In this case, since at least an error amplifier is provided in DEV_SVC, the error amplifier (EA in FIG. 4) in DEV [1] to DEV [n] becomes unnecessary in some cases. However, the EA does not require a large area, and it is better to have it in DEV [1] to DEV [n] from the viewpoint of maintaining the independent operation function of DEV [1] to DEV [n].

Further, in the configuration example of FIG. 12, the soft start terminal TRKSS of the monitoring setting device DEV_SVC is connected to the external resistor R3, the external capacitor C1, and the TRKSS of DEV [1] to DEV [n]. This is because, as shown in FIG. 4, the information of the ON / OFF signal, the internal power supply enable signal REGGD, and the excess current detection signal OCP in DEV [1] to DEV [n] is reflected in the TRKSS of DEV_SVC.

FIG. 13 is a block diagram showing a detailed configuration example of the monitoring setting device DEV_SVC in the power supply device of FIG. The monitoring setting device DEV_SVC shown in Fig. 13 has output power supply voltage detection terminals SN, SP, FB, output power supply voltage setting terminals VID1 to VID7, soft start terminal TRKSS, device operation enable setting terminal (ON / OFF), and error amplifier output terminal. It is equipped with EO, power good terminal PG, droop terminal DROOP, differential output terminal DFO, etc.

The SN is connected to, for example, the ground voltage node of the load LD (not shown) connected to the output capacitor Cv, and the SP is connected to the output power supply voltage Vout of the Cv. The differential amplifier circuit AMP_DF amplifies the potential difference between the SN and SP, and outputs the differential amplification signal DFS to the DFO. That is, the voltage detection is performed with higher accuracy than the case where the voltage is detected by the FB as described in the previous embodiments. This DFO is connected to the FB via an external resistor R50. The digital-to-analog conversion circuit DAC converts the output power supply voltage setting signals from VID1 to VID7 into analog values. The variable voltage generation circuit VR generates a voltage corresponding to this analog value and outputs it to the error amplifier circuit EA.

The error amplifier circuit EA amplifies the potential difference between VR and FB, and outputs the result to EO. As a result, the EA can generate an error amplifier signal (EO) according to VID1 to VID7. In addition, the EA receives the voltage of TRKSS to which the external resistor R3, the external capacitor C1 and the built-in transistor Q41 are connected, and performs a soft start. Q41 connects TRKSS to the ground voltage GND while the ON / OFF signal of the device operation enable setting terminal (ON / OFF) is OFF (operation disable state), and when it is ON, it is in the open state. It becomes. When it is turned on, the TRKSS voltage gradually rises and a soft start is performed.

The EO is connected to the FB via the external resistor R4 and the external capacitor C2. R4 and C2 are responsible for setting the bandwidth of the power circuit. Further, the EO is connected to the EO_IN of DEV [1] to DEV [n] as shown in FIG. On the other hand, the output of the EA (that is, the voltage of the EO) is input to the droop control circuit DROOPC via the low-pass filter circuit LPF. The DROOPC controls the variable current source IR by the value of the external resistor R51 connected to the droop terminal DROOP and the output voltage of the EA. This IR current is supplied to the FB. The output power supply voltage monitoring circuit PWGD detects that the voltage value of the differential amplification signal DFS is equal to or higher than a predetermined value. That is, it is detected that the output power supply voltage Vout is generated. When detected, the PWGD drives the transistor Q40 and outputs a detection signal to the power good terminal PG.

Here, the droop is known as a function of controlling the output power supply voltage and the output power supply current in inverse proportion, for example, reducing the output power supply voltage as the output power supply current increases. In the peak current control method, the output voltage of the error amplifier circuit EA is proportional to the output power supply current. Therefore, by changing the IR value according to the output voltage of the EA, the output power supply voltage Vout can be changed as a result. Specifically, the IR current value is controlled to increase as the voltage of the error amplifier signal from the EA increases. IR increases in proportion to the output (EO) of the EA, and its proportionality constant is determined by the value of the external resistor R51. The value of the decrease in the output power supply voltage Vout at this time is expressed by Eq. (3). ΔVout = IR × R50 (3) As described above, by using the power supply device of the fifth embodiment, it is possible to realize a typically low-cost multi-phase power supply as in the case of the first embodiment and the like. That is, when it is desired to add a droop function or an output power supply voltage setting function, it is possible to realize a low-cost multi-phase power supply as a whole by providing these functions as separate devices. Specifically, for example, as can be seen from FIG. 13, the monitoring setting device DEV_SVC can be realized in a small area, and the wiring between DEV_SVC and DEV [1] to DEV [n] is small, so that the device Both cost and mounting cost can be reduced.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof.

For example, in the previous embodiments, a configuration example of a semiconductor device provided with a peak current control method has been shown, but this embodiment has a main feature in a method for realizing a multi-phase power supply by ring connection, and is not necessarily required. It is not limited to the peak current control method. For example, as is widely known, it is also possible to use a voltage control method for generating a PWM signal using a triangular wave generation circuit. However, in a multi-phase power supply, it is desirable to pass an even current for each phase, and from this viewpoint, the peak current control method facilitates the control.

Further, in the embodiments so far, a configuration example in which a switching operation is performed starting from a trigger input signal has been shown, but in short, since the switch operation may be performed in phases at regular intervals, the trigger is not limited to the trigger input signal. It is also possible to start from the output signal.

The power supply device according to the embodiment of the present invention is a useful technique particularly applied to a multi-phase DC-DC converter, and is not limited to this, and can be widely applied to a power supply device in general.

<figref num="1">The basic concept of the power supply device according to the first embodiment of the present invention is shown, (a) is a schematic diagram showing a configuration example thereof, and (b) is an explanatory diagram showing an operation example of (a).</figref><figref num="2">FIG. 5 is a block diagram showing a more detailed configuration example of the power supply device of FIG.</figref><figref num="3">It is a waveform diagram which shows the operation example of the power supply device of FIG.</figref><figref num="4">FIG. 5 is a block diagram showing a detailed configuration example of a semiconductor device used in the power supply device according to the second embodiment of the present invention.</figref><figref num="5">It is a top view which shows an example of the package form of the semiconductor device of FIG.</figref><figref num="6">It is a wiring diagram which shows the configuration example of the power-source device when the multi-phase power source is realized by using the semiconductor device of FIG. 4 and FIG.</figref><figref num="7">The details of the timer circuit of the semiconductor device of FIG. 4 are shown, (a) is a circuit diagram showing a configuration example thereof, and (b) is a waveform diagram showing an operation example thereof.</figref><figref num="8">FIG. 5 is a circuit diagram showing a detailed configuration example of the start trigger discrimination circuit in the timer circuit of FIG. 7.</figref><figref num="9">It is a wiring diagram which shows the structural example of the power-source device according to Embodiment 3 of this invention.</figref><figref num="10">The basic concept of the power supply device according to the fourth embodiment of the present invention is shown, (a) is a schematic diagram showing a configuration example thereof, and (b) is an explanatory diagram showing an operation example of (a).</figref><figref num="11">An example around the phase input signal and the phase output signal in the semiconductor device of FIG. 10 is shown. (A) is a schematic configuration diagram of a master device, (b) is a schematic configuration diagram of a slave device, and (c) is its operation. It is explanatory drawing which shows an example.</figref><figref num="12">It is the schematic which shows an example of the structure in the power-source device according to Embodiment 5 of this invention.</figref><figref num="13">It is a block diagram which shows the detailed configuration example of the monitoring setting device in the power supply device of FIG.</figref>

Code description

ACS current detection circuit AD logical product circuit AMP_DF differential amplifier circuit BK blanking circuit BOOT boot terminal C capacitor Cv output capacitor CIV clocked inverter circuit CMP comparison circuit CM current mirror circuit CS current sense terminal CTF frequency setting terminal CT delay time setting terminal D diode DAC digital-to-analog conversion circuit DEV_SVC monitoring configuration device DEV, DEVd semiconductor device DFO differential output terminal DFS differential amplification signal DROOPC droop control circuit DROOP droop terminal DRV5 internal power supply terminal DV driver circuit EA error amplifier circuit EN enable signal EO_IN error amplifier input terminal EO error amplifier output terminal FB output power supply voltage detection terminal FF flip-flop circuit GND ground voltage HSCP, LSCP, CTLCP semiconductor chip IR variable current source IV Inverter circuit IB current source L inductor LD load LGC control logic circuit LPF low-pass filter circuit MXD max duty signal ND inverting logical product circuit OCPC excess current detection circuit OCP excess current detection signal ON / OFF device operation enable setting terminal OR OR circuit OSC oscillator circuit OSPG_DLY One-shot delay pulse generation circuit OSPG one-shot pulse generation circuit OVPC overvoltage detection circuit OVP overvoltage detection signal PGEN pulse generation circuit PGND ground voltage terminal PG power good terminal PH_IN phase input terminal PH_OUT phase output terminal PWGD output power supply voltage monitoring circuit PWM_EN PWM enable signal Q transistor REG5 internal power supply terminal REGGD internal power enable signal RES reset signal R external resistor SBD Schottky diode SGND Ground voltage terminal SN, SP output power supply voltage detection terminal STJG start trigger discrimination circuit ST start trigger terminal SV regulator voltage monitoring circuit SW switch terminal SYNC [n] Reference clock signal terminal SYNC reference clock signal SYNC_CTL Reference clock control unit TM_OUT timer output signal TM timer circuit TRG_IN trigger input terminal TRG_OUT trigger output terminal TRKSS soft start terminal TSD temperature detection circuit UVLOC voltage detection circuit VC comparison circuit VCIN power terminal VID output power supply voltage setting terminal VIN power supply voltage input terminal VREG regulator circuit VR variable voltage generation circuit Vin input power supply voltage Vout output power supply voltage Vref, Vref_CT Reference voltage