Information processor and its control method

The present invention relates to a data transmitting device, an information processing device having a data receiving device for receiving data output by the data transmitting device, and a control method of the information processing device.

FIG. 1 shows a configuration example of a computer system. This computer system includes a system board (SB) # 0 to # 7, an input / output unit (IOU) # 0 to # 7, a memory system interconnection board 101, and a management board 102.

Each SB # i (i = 0 ~ 7) is equipped with a memory 111, a central processing unit (CPU) 112, and a chipset 113, and each IOU # i (i = 0 ~ 7) is a PCI (Peripheral Components Interconnect). ) Card 131, hard disk device 132, and chipset 133 are installed.

The memory system interconnection board 101 is equipped with a chipset 121 and connects SB # 0 to # 7 and IOU # 0 to # 7 to each other. The management board 102 mounts a controller 141 connected to each of the chipsets 113, 133, and 121, and controls the system. The controller 141 is implemented as firmware, for example.

Chipsets 113, 133, and 121 are control LSIs (Large Scale Integration). The chipset 113 includes the transmitter / receiver 114, the chipset 121 includes the transmitter / receiver 122 and 123, and the chipset 133 includes the transmitter / receiver 134. These chipsets are connected to each other via a transmission / reception unit, and data is transmitted / received between the chipsets.

FIG. 2 shows a configuration example of a conventional transmitting chip and receiving chip. The transmitting chip 201 corresponds to the transmitting / receiving unit on the transmitting side, and the receiving chip 202 corresponds to the transmitting / receiving unit on the receiving side. The transmitting chip 201 and the receiving chip 202 are connected to the clock signal line by N data signal lines (N is a positive integer).

The transmission chip 201 includes a phase-locked loop (PLL) 211, a clock output circuit 212, a pattern generation circuit 213, a data selection circuit 214-1 to 214-N, a flip-flop circuit 215-1 to 215-2N, and 216-1 to 216. -N, bit selection circuits 217-1 to 217-N, data output circuits 218-1 to 218-N, and transmitter control circuit 219 are provided.

The transmitter control circuit 219 outputs the pattern selection signal to the pattern generation circuit 213 and outputs the data selection signal to the data selection circuits 214-1 to 214-N according to the training start instruction signal from the controller 141.

The PLL 211 generates a clock signal and outputs it to the clock output circuit 212, the flip-flop circuits 215-1 to 215-N, 216-1 to 216-N, and the bit selection circuits 217-1 to 217-N. The clock output circuit 212 outputs a clock signal to the receiving chip 202.

The pattern generation circuit 213 generates a 2-bit training pattern [1: 0] according to the pattern selection signal and outputs it to the data selection circuits 214-1 to 214-N. The training pattern [1: 0] is a predetermined data string between chips and is used at the time of phase adjustment.

Each data selection circuit 214-j (j = 1 to N) selects either a 2-bit transmission data [1: 0] or a training pattern [1: 0] signals according to the data selection signal. Then, the values of bits 0 and 1 of the selected signal are output to the flip-flop circuits 215-j and 216-j, respectively.

Each flip-flop circuit 215-j latches the value of bit 0 in synchronization with the clock signal and outputs it to the bit selection circuit 217-j. Each flip-flop circuit 216-j latches the value of bit 1 in synchronization with the clock signal and outputs it to the bit selection circuit 217-j.

Each bit selection circuit 217-j selects an output signal of either the flip-flop circuit 215-j or 216-j according to the value of the clock signal, and outputs the output signal to the data output circuit 218-j. In this example, when the clock signal is logic "1", the output signal of the flip-flop circuit 215-j is selected, and when the clock signal is logic "0", the output signal of the flip-flop circuit 216-j is selected. .. Each data output circuit 218-j is out of the bit selecting circuits 217-j outputs a force signal, the reception chip 202 as a data signal.

The receiving chip 202 includes a clock input circuit 221, a clock adjustment circuit 222-1 to 222-N, a clock adjustment control circuit 223-1 to 223-N, a pattern detection circuit 224-1 to 224-N, and a data input circuit 225-1. It includes ~ 225-N, flip-flop circuits 226-1 to 226-N, 227-1 to 227-N, 221-1 to 228-N, and a receiver control circuit 229.

The receiver control circuit 229 outputs the clock adjustment instruction signal to the clock adjustment control circuits 223-1 to 223-N according to the training start instruction signal from the controller 141. The clock signal output from the transmission chip 201 is input to the clock input circuit 221 and the clock input circuit 221 outputs the input clock signal to the clock adjustment circuits 222-1 to 222-N.

Each clock adjustment circuit 222-j delays the phase of the clock signal according to the TAP value j from the clock adjustment control circuit 223-j, and generates an adjusted clock signal j. Then, the adjusted clock signal j is output to the clock adjustment control circuit 223-j and the flip-flop circuits 226-j, 227-j, and 228-j.

The data signal output from the data output circuit 218-j of the transmission chip 201 is input to the data input circuit 225-j, and the data input circuit 225-j inputs the input data signal to the flip flop circuits 226-j and 228-. Output to j.

The flip-flop circuit 226-j latches the data signal in synchronization with the inverted signal of the adjusted clock signal j, and outputs the data signal to the flip-flop circuit 227-j. The flip-flop circuit 227-j latches the output signal of the flip-flop circuit 226-j in synchronization with the adjusted clock signal j, and outputs it as the value of bit 0 of the received data. The flip-flop circuit 228-j latches the data signal in synchronization with the adjusted clock signal j and outputs it as the value of bit 1 of the received data. In this way, 2-bit received data j [1: 0] is generated.

The pattern detection circuit 224-j detects the pattern of the received data j [1: 0], outputs the adjustment pattern detection signal j to the clock adjustment control circuit 223-j, and outputs the end pattern detection signal j to the receiver control circuit 229. Output to.

Each clock adjustment control circuit 223-j starts phase adjustment according to the clock adjustment instruction signal, and increases or decreases the TAP value j according to the adjustment pattern detection signal j from the pattern detection circuit 224-j. Then, the TAP value j is output to the clock adjustment circuit 222-j.

In data transmission between chips, it is necessary to align the edge of the clock signal with the center of the data waveform and input the clock signal to the flip-flop circuits 226-j, 227-j, and 228-j in order to secure a margin. Therefore, the phase adjustment of the clock signal is usually performed using a known training pattern [1: 0]. At the time of phase adjustment, the transmission chip 201 selects and outputs the training pattern [1: 0]. Then, the receiving chip 202 receives the training pattern [1: 0] while changing the TAP value j, and calculates the TAP value corresponding to the center of the data waveform according to the pattern detection result.

FIG. 3 shows a configuration example of the pattern generation circuit 213 of FIG. The pattern generation circuit 213 includes an adjustment pattern storage unit 301, an end pattern storage unit 302, and a pattern selection circuit 303.

The adjustment pattern storage unit 301 stores the 2-bit adjustment pattern '10' and outputs the adjustment pattern to the pattern selection circuit 303. The end pattern storage unit 302 stores the 2-bit end pattern '11' and outputs the end pattern to the pattern selection circuit 303. The pattern selection circuit 303 selects one of the patterns according to the pattern selection signal from the transmitter control circuit 219, and outputs it as a training pattern [1: 0].

FIG. 4 shows a configuration example of the pattern detection circuit 224-j of FIG. The pattern detection circuit 224-j includes an adjustment pattern storage unit 401, an end pattern storage unit 402, and comparators 403 and 404.

The adjustment pattern storage unit 401 stores the adjustment pattern '10' and outputs the adjustment pattern to the comparator 403. The end pattern storage unit 302 stores the end pattern '11' and outputs the end pattern to the comparator 404.

The comparator 403 compares the received data j [1: 0] with the adjustment pattern '10', and if they match, the adjustment pattern detection signal j (for example, logic 1"" indicates that the pattern detection result is OK. ) Is output. On the other hand, if they do not match, the adjustment pattern detection signal j (for example, logic 0) indicating that the pattern detection result is NG is output.

The comparator 404 compares the received data j [1: 0] with the end pattern '10', and if they match, the end pattern detection signal j (for example, logic 1"" indicates that the pattern detection result is OK. ) Is output. On the other hand, if they do not match, the end pattern detection signal j (for example, logic 0) indicating that the pattern detection result is NG is output.

FIG. 5 shows a configuration example of the clock adjustment circuit 222-j of FIG. The clock adjustment circuit 222-j includes a delay line and a decoder 502. The delay line consists of buffer circuits 501-0 to 501-6, switches sw0 to sw6, and capacitors 503-0 to 503-6.

The decoder 502 changes the load capacitance of the delay line by turning on / off the switches sw0 to sw6 according to the TAP value j from the clock adjustment control circuit 223-j. As a result, the delay amount of the delay line is controlled, and the phase of the input clock signal changes.

FIG. 6 shows the correspondence between the TAP value j and the switching signal output from the decoder 502 to the switches sw0 to sw6. The switch swk (k = 0 to 6) turns on when the input switching signal is logic 1 and turns off when the logic 0. The greater the number of switches that are turned on, the greater the load capacitance and the greater the amount of delay. Conversely, the greater the number of switches that are turned off, the smaller the load capacitance and the smaller the amount of delay. In this example, any of the eight-step delay amount can be set by the 3-bit TAP value j [2: 0] representing any value from 0 to 7.

FIG. 7 shows a configuration example of the clock adjustment control circuit 223-j of FIG. The clock adjustment control circuit 223-j includes an incrementer 701, a decrementer 702, a TAP value selection circuit 703, a flip-flop circuit 704, 705, 706, an addition circuit 707, a division circuit 708, and a TAP control circuit 709.

The TAP control circuit 709 starts the phase adjustment according to the clock adjustment instruction signal from the receiver control circuit 229. Then, in response to the adjustment pattern detection signal j from the pattern detection circuit 224-j, the TAP value selection signal is output to the TAP value selection circuit 703, and the TAP value set signal is output to the flip-flop circuits 705 and 706.

The incrementer 701 adds 1 to the TAP value output from the flip-flop circuit 704 and outputs it to the TAP value selection circuit 703, and the decrementer 702 subtracts 1 from the TAP value output from the flip-flop circuit 704. Output to the TAP value selection circuit 703.

The TAP value selection circuit 703 selects one of the TAP values output from the flip-flop circuit 704, the incrementalr 701, the decrementer 702, or the division circuit 708 according to the TAP value selection signal, and outputs the TAP value to the flip-flop circuit 704.

The flip-flop circuit 704 latches the TAP value output from the TAP value selection circuit 703 in synchronization with the adjusted clock signal j, and outputs it as the TAP value j. The flip-flop circuit 705 latches the TAP value j in synchronization with the adjusted clock signal j and outputs it to the adder circuit 707 as an upper limit value. The flip-flop circuit 706 latches the TAP value j in synchronization with the adjusted clock signal j and outputs it to the adder circuit 707 as the lower limit value. Further, the flip-flop circuits 705 and 706 hold the upper limit value and the lower limit value according to the respective TAP value set signals.

The adder circuit 707 adds the upper limit value output from the flip-flop circuit 705 and the lower limit value output from the flip-flop circuit 706, and outputs the addition result to the division circuit 708. The division circuit 708 outputs half the value of the addition result to the TAP value selection circuit 703.

FIG. 8 is a flowchart of the operation of the TAP control circuit 709. When the TAP control circuit 709 receives the clock adjustment instruction signal from the receiver control circuit 229 (step 801), the TAP control circuit 709 outputs a TAP value selection signal for selecting the TAP center value 4 (step 802).

Next, the pattern detection result is determined based on the adjustment pattern detection signal j from the pattern detection circuit 224-j (step 803). If the pattern detection result is OK, the TAP value selection signal for selecting the smaller TAP value is output (step 804). As a result, the TAP value output from the decrementer 702 is output to the clock adjustment circuit 222-j as the TAP value j.

Next, the pattern detection result is determined based on the adjustment pattern detection signal j (step 805), and if the pattern detection result is OK, the operation of step 804 is repeated. Then, when the pattern detection result becomes NG, the TAP value set signal is output to the flip-flop circuit 706 (step 808). As a result, the current TAP value j is set in the flip-flop circuit 706 as the lower limit value.

On the other hand, if the pattern detection result is NG in step 803, a TAP value selection signal for selecting a larger TAP value is output (step 806). As a result, the TAP value output from the incremental 701 is output to the clock adjustment circuit 222-j as the TAP value j.

Next, the pattern detection result is determined based on the adjustment pattern detection signal j (step 807), and if the pattern detection result is NG, the operation of step 806 is repeated. Then, when the pattern detection result is OK, the TAP value set signal is output to the flip-flop circuit 706 (step 808).

When the lower limit value is set in step 808, the TAP value selection signal for selecting a larger TAP value is output (step 809), and the pattern detection result is determined based on the adjustment pattern detection signal j (step 810). ). If the pattern detection result is OK, the operation of step 809 is repeated, and if the pattern detection result is NG, the TAP value set signal is output to the flip-flop circuit 705 (step 811). As a result, the current TAP value j is set in the flip-flop circuit 705 as an upper limit value.

Next, the TAP value selection signal for selecting the optimum TAP value is output (step 812). As a result, the average value of the set upper limit value and lower limit value is selected and output to the clock adjustment circuit 222-j as the TAP value corresponding to the center of the data waveform.

FIG. 9 is a flowchart of the phase adjustment operation by the controller 141, the transmission chip 201, and the reception chip 202 of FIG. The transmitter control circuit 219 and the receiver control circuit 229 start the phase adjustment by an instruction from the outside at the time of initialization, and start the phase adjustment periodically by the timer at the time of operation.

When the computer system is turned on (step 901), the controller 141 outputs a training start instruction signal to the transmitter control circuit 219 and the receiver control circuit 229.

The transmitter control circuit 219 outputs a pattern selection signal for selecting an adjustment pattern to the pattern generation circuit 213, and outputs a data selection signal for selecting a training pattern [1: 0] to the data selection circuits 214-1 to 214-N. To do. As a result, the adjustment pattern is transferred to the receiving chip 202 as the training pattern [1: 0] (step 902).

The receiver control circuit 229 outputs the clock adjustment instruction signal to the clock adjustment control circuits 223-1 to 223-N. As a result, the operation shown in FIG. 8 is started, and the phase of the clock signal is adjusted (step 903).

Then, when the phase adjustment is completed (step 904), the transmitter control circuit 219 outputs a pattern selection signal for selecting the end pattern to the pattern generation circuit 213, and initializes the timer. As a result, the end pattern is transferred to the receiving chip 202 as the training pattern [1: 0] (step 905).

The pattern detection circuits 224-1 to 224-N output end pattern detection signals 1 to N indicating that the phase adjustment has been completed to the receiver control circuit 229, and the receiver control circuit 229 initializes the timer ( Step 906). As a result, normal operation using the adjusted clock signals 1 to N is performed until the timer count operation of the transmitter control circuit 219 and the receiver control circuit 229 is completed (step 907).

Then, when the timer counting operations of the transmitting unit control circuit 219 and the receiving unit control circuit 229 are completed (step 908), the operations after step 902 are repeated. In this way, the transmitter control circuit 219 and the receiver control circuit 229 perform the operations of steps 902 to 905 not only at the time of initialization but also at the time of operation to readjust the phase of the clock signal.

FIG. 10 is a timing chart showing an example of the phase adjustment operation in the receiving chip 202 of FIG. At the time of phase adjustment, the adjustment pattern '10' is repeatedly output from the data output circuit 218-j of the transmitting chip 201, and the repeating pattern such as '010101 ...' Is repeatedly output to the data input circuit 225-j of the receiving chip 202. Entered.

At this time, the output waveforms of the clock input circuit 221 and the data input circuit 225-j are as shown in (1). The expected behavior is to receive the data '0' at the down edge of the clock signal and the data '1' at the up edge.

When the phase of the clock signal is slightly advanced by the clock adjustment circuit 222-j, the adjusted clock signal j, received data j [1], received data j [0] (FF1 stage), received data j [0] (FF2 stage) The waveforms of the eye) and the adjustment pattern detection signal j are as shown in (2). The received data j [1] represents the output signal of the flip-flop circuit 228-j, and the received data j [0] (FF 1st stage) and the received data j [0] (FF 2nd stage) are the flip-flop circuits 226, respectively. Represents the output signals of -j and 227-j.

In this case, the flip-flop circuit 226-j receives the data '0' at the down edge of the adjusted clock signal j, and the flip-flop circuit 228-j receives the data '1' at the up edge of the adjusted clock signal j. I'm receiving. Therefore, the received data j [1: 0] matches the adjustment pattern '10'. Therefore, the adjustment pattern detection signal j indicates OK.

When the phase of the clock signal is further advanced by the clock adjustment circuit 222-j, the waveform of each signal becomes as shown in (3). In this case, the down edge of the adjusted clock signal j is before the data '0', and the data '1' is received at the down edge. Similarly, the up edge of the adjusted clock signal j is before the data '1', and the data '0' is received at the up edge. Therefore, the received data j [1: 0] becomes '01' and does not match the adjustment pattern '10'. Therefore, the adjustment pattern detection signal j indicates NG.

On the other hand, when the phase of the clock signal is delayed by the clock adjustment circuit 222-j, the waveform of each signal becomes as shown in (4). In this case, the down edge of the adjusted clock signal j is later than the data '0', and the data '1' is received at the down edge. Similarly, the up edge of the adjusted clock signal j is later than the data '1', and the data '0' is received at the up edge. Therefore, the received data j [1: 0] becomes '01' and does not match the adjustment pattern '10'. Therefore, the adjustment pattern detection signal j indicates NG.

As shown in (1) to (4), each phase is compared with the adjustment pattern '10' by comparing the received data [1: 0] with the adjustment pattern '10' while changing the phase of the clock signal by the clock adjustment circuit 222-j. The pattern detection result (OK or NG) for is found. Since the center value of the TAP value range for which the pattern detection result is OK corresponds to the center of the data waveform, the phase adjustment is completed by calculating the center value. The waveform of each signal after the phase adjustment is completed is shown in (5).

In addition to the phase adjustment of the clock signal as described above, a technique for performing phase correction between bits of parallel data is known (see, for example, Patent Documents 1 and 2). However, the above-mentioned conventional phase adjustment method has the following problems. (1) Since the phase relationship between the clock signal and the data signal changes with time due to temperature fluctuations, power supply voltage fluctuations, clock fluctuations due to PLL jitter, etc., the phase gradually deviates from the optimum phase. For this reason, readjustment is required even during operation before a deviation that cannot be transmitted occurs. When performing phase adjustment, it is usually necessary to temporarily stop the data transfer and transmit the training pattern, so that the data transfer performance is deteriorated. In particular, as the transmission speed increases, it is necessary to readjust the data frequently, which has a large effect on the data transfer performance. (2) As described above, since the phase adjustment is performed only periodically, the edge of the clock signal does not always follow the center of the data waveform, and a certain degree of deviation is allowed. Therefore, when the fluctuation of the phase relationship between the clock signal and the data signal is large, the error frequency increases.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 5-145537</text></patcit><patcit num="2"><text>Special Table 2004-531117</text></patcit>

An object of the present invention is to adjust the phase relationship between the clock signal and the data signal without stopping the transfer of normal data between the data transmitting device and the data receiving device. The disclosed information processing device includes a data transmitting device and a data receiving device connected to the data transmitting device and receiving data output by the data transmitting device.

The data transmission device includes a reference clock generator, a selection circuit, and a transmission data synchronization output circuit. The reference clock generation unit generates a reference clock, and the selection circuit inputs transmission target data and phase adjustment data, and selects either transmission target data or phase adjustment data. The transmission data synchronization output circuit synchronizes the data selected by the selection circuit with the reference clock and outputs it as transmission data.

The data receiving device includes a clock phase adjusting circuit, a received data output unit, a data adjusting circuit, an adjusted receiving data output unit, and a comparison unit. The clock phase adjustment circuit inputs a reference clock and outputs a clock whose phase of the reference clock is delayed based on the clock phase adjustment value. The reception data output unit inputs transmission data, synchronizes the input transmission data with the delayed clock, and outputs it as reception data.

The data adjustment circuit inputs the transmission data and outputs the adjustment target received data in which the transmission data is delayed based on the data phase adjustment value. The adjustment reception data output unit inputs the adjustment target reception data, synchronizes the input adjustment target reception data with the delayed clock, and outputs the adjustment reception data as the adjustment reception data. The comparison unit inputs the received data and the adjusted received data, compares the received data with the adjusted received data, and outputs it as a data phase adjustment value based on the comparison result.

According to such a configuration, the phase adjustment of the transmission data output from the data transmission device to the data reception device is performed while using the clock whose phase is adjusted based on the clock phase adjustment value. This makes it possible to reflect the data phase adjustment result in the clock phase adjustment, and for example, the clock phase adjustment value can be updated based on the comparison result by the comparison unit. Since the data phase adjustment is performed by comparing the received data with the adjusted received data, the received data does not have to be a training pattern and may be normal data.

The reference clock corresponds to, for example, the clock signal output by the PLL 1011 described later, and the transmission target data corresponds to, for example, any of transmission data 1 [1: 0] to transmission data N [1: 0] described later. .. The phase adjustment data corresponds to, for example, the training pattern [1: 0] output by the pattern generation circuit 1013 described later.

The clock phase adjustment value corresponds to, for example, any of the TAP values 1 to TAP value N described later, and the data phase adjustment value corresponds to, for example, any of the TAP2 values 1 to TAP2 value N described later. The adjustment target reception data corresponds to, for example, a data signal output by any of the data adjustment circuits 1031-1 to 1031-N described later, and the adjustment reception data is, for example, the adjusted reception data 1 [1: 0] described later. ] ~ Corresponds to any of the adjusted received data N [1: 0].

According to another aspect, the data transmission device includes a reference clock generator, a first selection circuit, a second selection circuit, a first transmission data synchronization output circuit, and a second transmission data synchronization output circuit. Further, the data receiving device includes a first clock phase adjusting circuit, a second clock phase adjusting circuit, a first received data output unit, a second received data output unit, a first data adjusting circuit, and a second data. It has an adjustment circuit, a first adjustment reception data output unit, a second adjustment reception data output unit, a first comparison unit, and a second comparison unit.

The reference clock generator generates a reference clock. The first selection circuit inputs the first transmission target data and the phase adjustment data, and selects one of the first transmission target data and the phase adjustment data. The first transmission data synchronous output circuit synchronizes the data selected by the first selection circuit with the reference clock and outputs the data as the first transmission data.

The second selection circuit inputs the second transmission target data and the phase adjustment data, and selects either the second transmission target data or the phase adjustment data. The second transmission data synchronization output circuit synchronizes the data selected by the second selection circuit with the reference clock and outputs it as the second transmission data.

The first clock phase adjustment circuit inputs the reference clock and outputs the first clock whose phase of the reference clock is delayed based on the first clock phase adjustment value. The first received data output unit inputs the first transmitted data, synchronizes the input first transmitted data with the first clock, and outputs the input as the first received data.

The first data adjustment circuit inputs the first transmission data and outputs the first adjustment target reception data in which the first transmission data is delayed based on the first data phase adjustment value. The first adjustment reception data output unit inputs the first adjustment target reception data, synchronizes it with the first clock, and outputs it as the first adjustment reception data. The first comparison unit inputs the first received data and the first adjusted received data, compares the first received data with the first adjusted received data, and based on the result of the comparison, the first data phase. Output as an adjustment value.

The second clock phase adjustment circuit inputs the reference clock and outputs the second clock whose phase of the reference clock is delayed based on the second clock phase adjustment value. The second received data output unit inputs the second transmitted data, synchronizes the input second transmitted data with the second clock, and outputs the second received data as the second received data.

The second data adjustment circuit inputs the second transmission data, and outputs the second adjustment target reception data in which the second transmission data is delayed based on the second data phase adjustment value. The second adjustment reception data output unit inputs the second adjustment target reception data, synchronizes it with the second clock, and outputs it as the second adjustment reception data. The second comparison unit inputs the second received data and the second adjusted received data, compares the second received data with the second adjusted received data, and based on the result of the comparison, the second data phase. Output as an adjustment value.

According to such a configuration, the first output from the data transmitting device to the data receiving device is used while using the first and second clocks whose phases are adjusted based on the first and second clock phase adjustment values. And the phase adjustment of the second transmission data is performed.

This makes it possible to reflect the data phase adjustment result in the clock phase adjustment. For example, the first and second clock phase adjustment values are updated based on the comparison result by the first and second comparison units. Can be done. Since the data phase adjustment is performed by comparing the first and second received data with the first and second adjusted received data, the first and second received data do not have to be training patterns and are normal data. It may be.

The reference clock corresponds to, for example, the clock signal output by the PLL 1011 described later, and the first and second transmission target data are, for example, transmission data 1 [1: 0] to transmission data N [1: 0] described later. Corresponds to any of. The phase adjustment data corresponds to, for example, the training pattern [1: 0] output by the pattern generation circuit 1013 described later.

The first and second clock phase adjustment values correspond to, for example, any of the TAP values 1 to N described later, and the first and second data phase adjustment values correspond to, for example, the TAP2 values 1 to described later. Corresponds to one of the TAP2 values N. The first and second adjustment target received data correspond to, for example, a data signal output by any of the data adjustment circuits 1031-1 to 1031-N described later, and the first and second adjustment reception data are, for example, , Corresponds to any of the adjusted received data 1 [1: 0] to the adjusted received data N [1: 0], which will be described later.

According to the disclosed information processing apparatus, it is possible to constantly adjust the phase of the clock signal without stopping the transfer of normal data. Therefore, the phase adjustment performance and the data transfer performance are improved.

<figref num="1">It is a block diagram of a computer system.</figref><figref num="2">It is a block diagram of the conventional transmission chip and reception chip.</figref><figref num="3">It is a block diagram of the conventional pattern generation circuit.</figref><figref num="4">It is a block diagram of the conventional pattern detection circuit.</figref><figref num="5">It is a block diagram of the conventional clock adjustment circuit.</figref><figref num="6">It is a figure which shows the output of the conventional decoder.</figref><figref num="7">It is a block diagram of the conventional clock adjustment control circuit.</figref><figref num="8">It is a flowchart of the operation of the conventional TAP control circuit.</figref><figref num="9">It is a flowchart of the conventional phase adjustment operation.</figref><figref num="10">It is a timing chart of the conventional phase adjustment operation.</figref><figref num="11">It is a block diagram of the transmission chip and the reception chip of embodiment.</figref><figref num="12">It is a block diagram of the clock adjustment control circuit of an embodiment.</figref><figref num="13">It is a flowchart of the operation at the time of initialization of the TAP control circuit of an embodiment.</figref><figref num="14">It is a flowchart of operation at the time of operation of the TAP control circuit of embodiment.</figref><figref num="15">It is a block diagram of the data adjustment circuit of an embodiment.</figref><figref num="16">It is a figure which shows the output of the decoder of an embodiment.</figref><figref num="17">It is a block diagram of the data adjustment control circuit of embodiment.</figref><figref num="18">It is a flowchart of operation of the TAP2 control circuit of embodiment.</figref><figref num="19">It is a flowchart of the phase adjustment operation of an embodiment.</figref><figref num="20">It is a timing chart of the phase adjustment operation of an embodiment.</figref>

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 11 shows a configuration example of the transmitting chip and the receiving chip of the embodiment. The transmitting chip 1001 and the receiving chip 1002 are connected by a clock signal line and N data signal lines.

The transmission chip 1001 includes a phase-locked loop (PLL) 1011, a clock output circuit 1012, a pattern generation circuit 1013, a data selection circuit 1014-1 to 1014-N, a flip flop circuit 1015-1 to 1015-N, and 1016-1 to 1016. -N, bit selection circuits 1017-1 to 1017-N, data output circuits 1018-1 to 1018-N, and transmitter control circuit 1019 are provided.

The receiving chip 1002 includes a clock input circuit 1021, a clock adjustment circuit 1022-1 to 1022-N, a clock adjustment control circuit 1023-1 to 1023-N, a pattern detection circuit 1024-1 to 1024-N, and a data input circuit 1025-1. ~ 1025-N, flip flop circuit 1026-1 ~ 1026-N, 1027-1 ~ 1027-N, 1028-1 ~ 1028-N, receiver control circuit 1029, and constant adjustment unit 1030-1 ~ 1030-N Be prepared.

Of these, the pattern generation circuit 1013 has the same configuration as in FIG. 3, the pattern detection circuits 1024-1 to 1024-N have the same configurations as in FIG. 4, and the clock adjustment circuits 1022-1 to 1022-N have the same configuration. It has the same configuration as in FIG. The operation of circuits other than the transmitter control circuit 1019, the receiver control circuit 1029, the clock adjustment control circuits 1023-1 to 1023-N, and the constant adjustment units 1030-1 to 1030-N is shown in FIG. Is similar to.

The transmitter control circuit 1019 outputs the pattern selection signal to the pattern generation circuit 1013 and outputs the data selection signal to the data selection circuits 1014-1 to 1014-N according to the training start instruction signal from the controller 141.

Each constant adjustment unit 1030-j (j = 1 to N) includes a data adjustment circuit 1031-j, a flip-flop circuit 1032-j, 1033-j, 1034-j, and a data adjustment control circuit 1035-j.

The receiver control circuit 1029 outputs the clock adjustment instruction signal to the clock adjustment control circuits 1023-1 to 1023-N according to the training start instruction signal from the controller 141. Then, at the time of constant phase adjustment after the start of operation, the data adjustment instruction signal is output to the data adjustment control circuits 1035-1 to 1035-N.

Each data adjustment circuit 1031-j delays the phase of the data signal output from the data input circuit 1025-j according to the TAP2 value j from the data adjustment control circuit 1035-j, and flip-flops the delayed data signal. Output to circuits 1032-j and 1034-j.

The flip-flop circuit 1032-j latches the data signal in synchronization with the inverted signal of the adjusted clock signal j, and outputs the data signal to the flip-flop circuit 1033-j. The flip-flop circuit 1033-j latches the output signal of the flip-flop circuit 1032-j in synchronization with the adjusted clock signal j, and outputs it as the value of bit 0 of the adjusted received data. The flip-flop circuit 1034-j latches the data signal in synchronization with the adjusted clock signal j and outputs it as the value of bit 1 of the adjusted received data. In this way, the 2-bit adjusted reception data j [1: 0] is generated and output to the data adjustment control circuit 1035-j.

Each data adjustment control circuit 1035-j starts phase adjustment of the data signal according to the data adjustment instruction signal, and TAP2 according to the comparison result of the received data j [1: 0] and the adjusted received data j [1: 0]. Increase or decrease the value j. Then, the TAP2 value j is output to the data adjustment circuit 1031-j, and the TAP update instruction signal j and the TAP update difference j are output to the clock adjustment control circuit 1023-j.

Each clock adjustment control circuit 1023-j starts phase adjustment of the clock signal according to the clock adjustment instruction signal, and the TAP update instruction signal j, the TAP update difference j, and the adjustment pattern detection signal j from the pattern detection circuit 1024-j. Increase or decrease the TAP value j according to. Then, the TAP value j is output to the clock adjustment circuit 1022-j.

At the time of initial adjustment such as immediately after the power of the computer system is turned on, the phase adjustment of the clock signal is performed using the training pattern output by the pattern generation circuit 1013. However, during operation, the phase of the clock signal is adjusted without using the training pattern.

During operation, the transmission chip 1001 always outputs transmission data j [1: 0] as normal data. Then, the receiving chip 1002 receives the normal data while changing the TAP2 value j, and compares the normal data received based on the TAP2 value j with the normal data received based on the TAP value j to obtain the data waveform. Calculate the TAP value corresponding to the center.

In this case, since the received data itself is used as the expected value, it cannot be determined whether or not reception is possible if there is no change in the data pattern. However, since scrambling such as 8B10B or PRBS (Pseudo-Random Bit Sequence) is usually performed, the data The pattern changes and it is possible to judge whether reception is possible.

Note that some or all of the TAP values 1 to N may be the same value, or all may be different values. FIG. 12 shows a configuration example of the clock adjustment control circuit 1023-j of FIG. The clock adjustment control circuit 1023-j includes the TAP update circuit 1101, the incremental 1102, the decrementer 1103, the TAP value selection circuit 1104, the flip flop circuit 1105, 1106, 1107, the addition circuit 1108, the division circuit 1109, and the TAP control circuit 1110. Be prepared.

The TAP control circuit 1110 starts the phase adjustment according to the clock adjustment instruction signal from the receiver control circuit 1029. Then, the TAP value selection signal is output to the TAP value selection circuit 1104 according to the TAP update instruction signal j from the data adjustment control circuit 1035-j and the adjustment pattern detection signal j from the pattern detection circuit 1024-j, and the TAP is output. The value set signal is output to the flip-flop circuits 1106 and 1107.

The TAP update circuit 1101 subtracts the TAP update difference j from the data adjustment control circuit 1035-j from the TAP value output from the flip-flop circuit 1105, and outputs the subtraction result to the TAP value selection circuit 1104 as the TAP update value. .. The incrementer 1102 adds 1 to the TAP value output from the flip-flop circuit 1105 and outputs it to the TAP value selection circuit 1104, and the decrementer 1103 subtracts 1 from the TAP value output from the flip-flop circuit 1105. Output to the TAP value selection circuit 1104.

The TAP value selection circuit 1104 selects one of the TAP values output from the flip-flop circuit 1105, the TAP update circuit 1101, the incrementer 1102, the decrementer 1103, or the division circuit 1109 according to the TAP value selection signal, and the flip-flop circuit Output to 1105.

The flip-flop circuit 1105 latches the TAP value output from the TAP value selection circuit 1104 in synchronization with the adjusted clock signal j, and outputs the TAP value as the TAP value j. The flip-flop circuit 1106 latches the TAP value j in synchronization with the adjusted clock signal j and outputs it to the adder circuit 1108 as an upper limit value. The flip-flop circuit 1107 latches the TAP value j in synchronization with the adjusted clock signal j, and outputs the TAP value j as the lower limit value to the adder circuit 1108. Further, the flip-flop circuits 1106 and 1107 hold the upper limit value and the lower limit value according to the respective TAP value set signals.

The adder circuit 1108 adds the upper limit value output from the flip-flop circuit 1106 and the lower limit value output from the flip-flop circuit 1107, and outputs the addition result to the division circuit 1109. The division circuit 1109 outputs half the value of the addition result to the TAP value selection circuit 1104.

FIG. 13 is a flowchart of the operation of the TAP control circuit 1110 at the time of initialization. The operation of steps 1201 to 1212 is the same as the operation of steps 801 to 812 in FIG.

FIG. 14 is a flowchart of the update operation of the TAP control circuit 1110 during operation. When the TAP control circuit 1110 receives the TAP update instruction signal j from the data adjustment control circuit 1035-j (step 1301), the TAP control circuit 1110 outputs a TAP value selection signal for selecting the TAP update value (step 1302). As a result, the TAP update value output from the TAP update circuit 1101 is output to the clock adjustment circuit 1022-j as the TAP value j.

FIG. 15 shows a configuration example of the data adjustment circuit 1031-j of FIG. The data adjustment circuit 1031-j includes a delay line and a decoder 1402. The delay line consists of buffer circuits 1401-0 to 1401-14, switches sw0 to sw14, and capacitors 1404-0 to 1404-14.

The decoder 1402 changes the load capacitance of the delay line by turning on / off the switches sw0 to sw14 according to the TAP2 value j from the data adjustment control circuit 1035-j. As a result, the delay amount of the delay line is controlled, and the phase of the input data signal changes.

FIG. 16 shows the correspondence between the TAP2 value j and the switching signals output from the decoder 1402 to the switches sw0 to sw14. The switch swk (k = 0 to 14) turns on when the input switching signal is logic 1 and turns off when the logic 0. In this example, any of the 16 levels of delay can be set by the 4-bit TAP2 value j [3: 0], which represents any value from -8 to 7.

FIG. 17 shows a configuration example of the data adjustment control circuit 1035-j of FIG. The data adjustment control circuit 1035-j includes an incrementer 1501, a decrementer 1502, a TAP2 value selection circuit 1503, a flipflop circuit 1504, 1505, 1506, an adder circuit 1507, a division circuit 1508, a comparator 1509, and a TAP2 control circuit 1510.

The comparator 1509 transfers the received data j [1: 0] from the flip-flop circuits 1027-1 and 1028-1 and the adjusted received data j [1: 0] from the flip-flop circuits 1033-1 and 1034-1. The comparison is performed and the data comparison result is output to the TAP2 control circuit 1510.

The TAP2 control circuit 1510 starts the phase adjustment of the data signal according to the data adjustment instruction signal from the receiver control circuit 1029. Then, according to the data comparison result from the comparator 1509, the TAP2 value selection signal is output to the TAP2 value selection circuit 1503, and the TAP2 value set signal is output to the flip-flop circuits 1505 and 1506.

The incrementer 1501 adds 1 to the TAP2 value output from the flip-flop circuit 1504 and outputs it to the TAP2 value selection circuit 1503, and the decrementer 1502 subtracts 1 from the TAP2 value output from the flip-flop circuit 1504. Output to TAP2 value selection circuit 1503.

The TAP2 value selection circuit 1503 selects either the TAP2 value output from the flip-flop circuit 1504, the incrementer 1501, or the decrementer 1502, or 0 (TAP2 center value) according to the TAP2 value selection signal, and flip-flops. Output to circuit 1504.

The flip-flop circuit 1504 latches the TAP2 value output from the TAP2 value selection circuit 1503 in synchronization with the adjusted clock signal j, and outputs the TAP2 value as the TAP2 value j. The flip-flop circuit 1505 latches the TAP2 value j in synchronization with the adjusted clock signal j and outputs it to the adder circuit 1507 as an upper limit value. The flip-flop circuit 1506 latches the TAP2 value j in synchronization with the adjusted clock signal j and outputs it to the adder circuit 1507 as the lower limit value. Further, the flip-flop circuits 1505 and 1506 hold the upper limit value and the lower limit value according to the respective TAP2 value set signals.

The adder circuit 1507 adds the upper limit value output from the flip-flop circuit 1505 and the lower limit value output from the flip-flop circuit 1506, and outputs the addition result to the division circuit 1508. The division circuit 1508 outputs half the value of the addition result as the TAP update difference j to the clock adjustment control circuit 1023-j, and also outputs the TAP update instruction signal j to the clock adjustment control circuit 1023-j.

FIG. 18 is a flowchart of the operation of the TAP2 control circuit 1510 during operation. When the TAP2 control circuit 1510 receives the data adjustment instruction signal from the receiver control circuit 1029 (step 1601), the TAP2 control circuit 1510 outputs a TAP2 value selection signal for selecting the TAP2 center value 0 (step 1602). As a result, 0 is output to the data adjustment circuit 1031-j as the TAP2 value j.

It then outputs a TAP2 value selection signal that selects a smaller TAP2 value (step 1603). As a result, -1 output from the decrementer 1502 is output to the data adjustment circuit 1031-j as the TAP2 value j.

Next, the data comparison result from the comparator 1509 is determined (step 1604). If the received data j [1: 0] and the adjusted received data j [1: 0] match, the data comparison result is determined to be OK, and if they do not match, it is determined to be NG.

If the data comparison result is OK, the operation of step 1603 is repeated, and if the data comparison result is NG, the TAP2 value set signal is output to the flip-flop circuit 1506 (step 1605). As a result, the current TAP2 value j is set in the flip-flop circuit 1506 as the lower limit value.

It then outputs a TAP2 value selection signal that selects the TAP2 center value 0 (step 1606), followed by a TAP2 value selection signal that selects a larger TAP2 value (step 1607). As a result, the +1 output from the incremental 1501 is output to the data adjustment circuit 1031-j as the TAP2 value j.

Next, the data comparison result from the comparator 1509 is determined (step 1608), and if the data comparison result is OK, the operation of step 1607 is repeated. Then, when the data comparison result becomes NG, the TAP2 value set signal is output to the flip-flop circuit 1505 (step 1609). As a result, the current TAP2 value j is set in the flip-flop circuit 1505 as the upper limit value, and the average value of the upper limit value and the lower limit value is output to the clock adjustment control circuit 1023-j as the TAP update difference j (step 1610).

FIG. 19 is a flowchart of a phase adjustment operation by the controller 141, the transmitting chip 1001 and the receiving chip 1002 of FIG. The transmitter control circuit 1019 and the receiver control circuit 1029 start phase adjustment by an external instruction at the time of initialization. On the other hand, during operation, the transmitter control circuit 1019 does not perform the phase adjustment operation, and the receiver control circuit 1029 instructs the data adjustment control circuits 1035-1 to 1035-N to adjust the data.

The operation of steps 1701 to 1705 at the time of initialization is the same as the operation of steps 901 to 905 of FIG. When the end pattern is transmitted from the transmission chip 1001 to the reception chip 1002, the pattern detection circuits 102-1 to 1024-N send end pattern detection signals 1 to N indicating that the phase adjustment is completed to the receiver control circuit 1029. Output. Then, the receiving unit control circuit 1029 outputs the data adjustment instruction signal to the data adjustment control circuits 1035-1 to 1035-N. As a result, normal operation using the adjusted clock signals 1 to N is performed (step 1706), and the TAP values 1 to N are continuously updated by the constant adjustment unit 1030-1 to 1030-N (step 1707). ).

FIG. 20 is a timing chart showing an example of the phase adjustment operation during operation of the receiving chip 1002 of FIG. During operation, transmission data j [1: 0] is output from the data output circuit 1018-j of the transmission chip 1001, and a data string such as'ABCDEFG ...'is output to the data input circuit 1025-j of the reception chip 1002. Is entered.

At this time, the output waveforms of the clock input circuit 1021 and the data input circuit 1025-j, the adjusted clock signal j, the received data j [1], the received data j [0] (FF1 stage), and the received data j [0 ] (FF 2nd stage) waveform is as shown in (1). The received data j [1] represents the output signal of the flip-flop circuit 1028-j, and the received data j [0] (FF 1st stage) and the received data j [0] (FF 2nd stage) are the flip-flop circuit 1026, respectively. Represents the output signals of -j and 1027-j.

The expected behavior is to receive data'A',' C',' E',' G', etc. at the up edge of the clock signal and data'B',' D',' F', etc. at the down edge. Is to receive. Here, it is assumed that the TAP value is set to 5.

For example, if the phase of the data signal is slightly advanced by the data adjustment circuit 1031-j with the TAP2 value = -1, the adjusted data signal, the adjusted received data j [1], and the adjusted received data j [0] (FF1 stage). (Eyes), the adjusted received data j [0] (FF 2nd stage), and the waveform of the data comparison result are as shown in (2).

The adjusted data signal represents the output signal of the data adjusting circuit 1031-j, and the adjusted received data j [1] represents the output signal of the flip-flop circuit 1034-j. The adjusted reception data j [0] (FF 1st stage) and the adjusted reception data j [0] (FF 2nd stage) represent the output signals of the flip-flop circuits 1032-j and 1033-j, respectively. The data comparison result represents the output signal of the comparator 1509.

In this case, the flip-flop circuit 1032-j receives the adjusted data'B',' D',' F', etc. at the down edge of the adjusted clock signal j. Further, the flip-flop circuit 1034-j receives the adjusted data'A',' C',' E',' G'and the like at the up edge of the adjusted clock signal j. Therefore, the adjusted received data j [1: 0] matches the received data j [1: 0]. Therefore, the data comparison result shows OK.

When the phase of the data signal is further advanced by the data adjustment circuit 1031-j with the TAP2 value = -3, the waveform of each signal becomes as shown in (3). In this case, the down edge of the adjusted clock signal j will be later than the adjusted data'B',' D',' F', etc., and the adjusted data'B',' D',' F'at the up edge. 'Etc. is being received. Similarly, the up edge of the adjusted clock signal j is later than the adjusted data'A',' C',' E',' G', etc., and the adjusted data'C',' E'at the down edge. Received',' G', etc. Therefore, the adjusted received data j [1: 0] does not match the received data j [1: 0]. Therefore, the data comparison result shows NG.

On the other hand, when the phase of the data signal is delayed by the data adjustment circuit 1031-j with the TAP2 value = +5, the waveform of each signal becomes as shown in (4). In this case, the down edge of the adjusted clock signal j is before the adjusted data'B',' D',' F', etc., and the adjusted data'Z',' B',' at the up edge. Receives D','F', etc. Similarly, the up edge of the adjusted clock signal j is before the adjusted data'A',' C',' E',' G', etc., and the adjusted data'A',' at the down edge. Receives C',' E', etc. Therefore, the adjusted received data j [1: 0] does not match the received data j [1: 0]. Therefore, the data comparison result shows NG.

As shown in (1) to (4), the adjusted received data j [1: 0] is compared with the received data j [1: 0] while changing the phase of the data signal in the data adjusting circuit 1031-j. By doing so, the data comparison result (OK or NG) for each phase is found. Since the center value of the TAP2 value range for which the data comparison result is OK corresponds to the optimum delay amount, the optimum TAP update difference j can be obtained by calculating the average value of the upper and lower limits of the TAP2 value. can get.

For example, if the upper limit of the TAP2 value is +5 and the lower limit is -3, the TAP update difference j is ((+ 5) + (-3)) / 2 = + 1. Therefore, the phase adjustment is completed by subtracting 1 from the current TAP value 5 and setting the TAP value to 4 by the clock adjustment control circuit 1023-j. As a result, the phase of the adjusted clock signal j is advanced by the amount corresponding to the TAP value 1, and the waveform of the adjusted clock signal j is shown in (5).

As described above, by providing the constant adjustment unit in each data path, the phase adjustment can be performed without using the training pattern. As a result, it is not necessary to stop the normal data transfer during operation, so that the data transfer performance does not deteriorate. Further, since the phase can be adjusted at all times, the edge of the clock signal follows the center of the data waveform even when the fluctuation of the phase relationship between the clock signal and the data signal is large, and stable data transfer becomes possible.

The adjustment pattern '10' and end pattern '11' shown in FIGS. 3 and 4, the output of the TAP2 value j and the decoder shown in FIG. 16, and the output of the TAP value j and the decoder shown in FIG. 6 are merely examples. , Other patterns and values may be used.