Branch prediction device and method that breaks accessing a pattern history table into multiple pipeline stages
22 claims: 6 independent, 16 dependent
- 1分岐命令に関する分岐予測情報をグループ化した分岐予測グループを各々記憶し、前記分岐予測情報を蓄積処理する分岐予測情報蓄積処理手段と、 要求に基づいて、各々の前記分岐予測グループの中から少なくとも一つの前記分岐予測グループを選択制御する第1の選択制御処理と、前記第1の選択制御処理にて選択された前記分岐予測グループの中から一又は複数の前記分岐予測情報を選択制御する第2の選択制御処理と、前記第2の選択制御処理にて選択された前記分岐予測情報に基づいて分岐予測結果を生成処理する予測結果生成処理と、を含む処理をパイプライン処理により行い、前記分岐予測情報蓄積処理手段に対してアクセスする制御を行うパイプラインアクセス制御手段と、 を有すると共に、 前記パイプラインアクセス制御手段は、 前記分岐予測情報蓄積処理手段の前記分岐予測情報又は前記分岐予測グループを選択するためのインデックス情報の値に関し、分岐予測生成に関する前記パイプライン処理を行う分岐予測生成パイプラインの一期間において、前記一期間の以降に実行される他の期間での前記インデックス情報の値を先行して計算し、前記分岐予測生成パイプラインの各期間での各処理に必要な各々のインデックス情報を供給する制御を行うインデックス情報制御手段と、 前記インデックス情報制御手段にて計算された前記一期間に対応する前記インデックス情報の値に基づいて、前記第1の選択制御処理を行選択により行う第1の選択制御手段と、 前記インデックス情報制御手段にて計算された前記他の期間に対応する前記インデックス情報の値に基づいて、同一分岐命令の分岐予測に対しては前記第1の選択制御処理が行われる前記一期間と異なる前記他の期間に前記第2の選択制御処理を列選択により行う第2の選択制御手段と、 を含むことを特徴とする分岐予測装置。
- 2請求項1に記載の分岐予測装置において、 前記インデックス情報制御手段は、 前記分岐命令に先行する他の分岐命令に対応するものであって前記一期間に実行される前記予測結果生成処理にて生成された前記分岐予測結果に基づいて、前記他の期間における前記インデックス情報の値を計算すること、 を特徴とする分岐予測装置。
- 3請求項1又は請求項2に記載の分岐予測装置において、 前記インデックス情報制御手段は、 N個前の前記分岐命令から分岐予測ターゲットとなる分岐命令までに実行され通過したN個の分岐命令のパスの情報に関する実行パス履歴情報に基づいて、前記分岐予測ターゲットとなる分岐命令に対応する前記インデックス情報の値の計算を行うこと、 を特徴とする分岐予測装置。
- 4請求項1乃至請求項3のうちいずれか一項に記載の分岐予測装置において、 前記インデックス情報制御手段は、 拡張―Folded―Index―レジスタユニットを構成するシフトレジスタの出力の所定の部分を、前記第1の選択制御手段による行選択の入力とする構成を含むものであることを特徴とする分岐予測装置。
- 5請求項1乃至請求項4のうちいずれか一項に記載の分岐予測装置において、 前記第2の選択制御手段は、 前記インデックス情報の値に基づいて、一つの分岐予測グループの中から少なくとも2つの各分岐予測情報を選択する第1の列選択手段、 を含むことを特徴とする分岐予測装置。
- 6請求項5に記載の分岐予測装置において、 前記第1の列選択手段は、 拡張―Folded―Index―レジスタユニットを構成するシフトレジスタの一部の値が複製されることで前記インデックス情報のうちの列選択情報が格納される列選択情報一時格納部と、 前記第1の選択制御手段にて選択された一つの分岐予測グループに関する情報を一時格納する分岐予測グループ情報一時格納部と、 前記列選択情報一時格納部の列選択情報の値と、前記分岐予測グループ情報一時格納部の一つの分岐予測グループに関する情報とに基づいて、前記一つの分岐予測グループの中から少なくとも2つの各分岐予測情報を選択する第1の列選択論理回路部と、 を含むことを特徴とする分岐予測装置。
- 7請求項5に記載の分岐予測装置において、 前記第2の選択制御手段は、 前記予測結果生成処理により生成された分岐予測結果情報に基づいて、前記第1の列選択手段にて選択された各分岐予測情報のうち一つの分岐予測情報を選択する第2の列選択手段、 含むことを特徴とする分岐予測装置。
- 8分岐命令に関する分岐予測情報をグループ化した分岐予測グループを各々記憶し、前記分岐予測情報を蓄積処理する分岐予測情報蓄積処理手段を含み、前記分岐予測情報蓄積処理手段に対してパイプライン処理によるアクセスが可能なパイプライン化分岐履歴情報蓄積処理ユニットと、 前記分岐予測情報又は前記分岐予測グループの選択を行うためのインデックス情報の値に関し、分岐予測生成に関する前記パイプライン処理を行う分岐予測生成パイプラインの一期間において、前記一期間の以降に実行される他の期間での前記インデックス情報の値を先行して計算し、前記分岐予測生成パイプラインの各期間での各処理に必要な各々のインデックス情報を供給する制御を行い、プロセッサパイプラインのフェッチステージで処理を行うための第1のインデックス情報制御ユニットと、 前記インデックス情報を制御し、プロセッサパイプラインのコミットステージで処理を行うための第2のインデックス情報制御ユニットと、 を含み、 前記パイプライン化分岐履歴情報蓄積処理ユニットは、 前記第1のインデックス情報制御ユニットにて計算された前記一期間に対応する前記インデックス情報の値に基づいて、 各々の前記分岐予測グループの中から少なくとも一つの前記分岐予測グループを選択制御する 第1の選択制御処理を行選択により行う第1の選択制御手段と、 前記第1のインデックス情報制御ユニットにて計算された前記他の期間に対応する前記インデックス情報の値に基づいて、同一分岐命令の分岐予測に対しては前記第1の選択制御処理が行われる前記一期間と異なる前記他の期間に 、前記第1の選択制御処理によって選択された前記分岐予測グループの中から一又は複数の前記分岐予測情報を選択制御する 第2の選択制御処理を列選択により行う第2の選択制御手段と、 前記第2の選択制御手段にて選択された前記分岐予測情報に基づいて、分岐予測結果を生成処理する予測結果生成手段と、 を含み、 前記第1のインデックス情報制御ユニットは、 前記第1の選択制御手段による第1の選択制御処理と、前記第2の選択制御手段による第2の選択制御処理と、前記予測結果生成手段による予測結果生成処理とを含む処理をパイプライン処理する制御を行うこと、 を特徴とするハイブリッド分岐予測装置。
- 9請求項8に記載のハイブリッド分岐予測装置において、 前記第1のインデックス情報制御ユニットは、 前記フェッチステージにて投機実行に利用され、前記フェッチステージにて利用された命令キャッシュインデックスと、前記予測結果生成手段の出力とに基づいて制御すること、 を特徴とするハイブリッド分岐予測装置。
- 10請求項8又は請求項9に記載のハイブリッド分岐予測装置において、 前記第2のインデックス情報制御ユニットは、 前記コミットステージにて、前記フェッチステージに利用された命令キャッシュインデックスと、実行ステージでの結果とに基づいて制御し、前記分岐予測情報による分岐予測が失敗し、プロセッサパイプラインの巻き戻しが行われる際に、前記コミットステージにて巻戻先保存処理に利用されること、 を特徴とするハイブリッド分岐予測装置。
- 11請求項8乃至請求項10のうちいずれか一項に記載のハイブリッド分岐予測装置において、 前記第2のインデックス情報制御ユニットは、 実行ステージでの実行結果と予測結果とが異なり、前記コミットステージにてプロセッサパイプライン処理の巻き戻し処理が行われる際に、前記インデックス情報を、前記第1のインデックス情報制御ユニットにコピーする処理を行うこと、 を特徴とするハイブリッド分岐予測装置。
- 12請求項8乃至請求項11のうちいずれか一項に記載のハイブリッド分岐予測装置において、 前記パイプライン化分岐履歴情報蓄積処理ユニット、前記第1のインデックス情報制御ユニット、及び前記第2のインデックス情報制御ユニットは、それぞれ複数形成され、 各々の各前記第1のインデックス情報制御ユニットは、 それぞれ異なる長さの分岐履歴をハッシュし、各前記パイプライン化分岐履歴情報蓄積処理ユニットの各々の各分岐予測情報の各インデックス情報を各々生成すること、 を特徴とするハイブリッド分岐予測装置。
- 13請求項12に記載のハイブリッド分岐予測装置において、 各々の各前記第2のインデックス情報制御ユニットは、 それぞれ異なる長さの分岐履歴をハッシュし、各前記パイプライン化分岐履歴情報蓄積処理ユニットの各々の各分岐予測情報の各インデックス情報を各々生成すること、 を特徴とするハイブリッド分岐予測装置。
- 14請求項12に記載のハイブリッド分岐予測装置において、 各々の各前記第1のインデックス情報制御ユニットは、 各々異なる命令数分の分岐履歴情報と、分岐命令キャッシュインデックス情報とに基づいて制御されること、 を特徴とするハイブリッド分岐予測装置。
- 15命令に基づいて各ステージを順次移行するプロセッサパイプライン処理を実行する複数のプロセッサパイプライン処理装置と、 前記プロセッサパイプライン処理における分岐命令の分岐予測を行う、請求項1乃至請求項7のうちいずれか一項に記載の分岐予測装置と、 前記各装置を制御する制御装置と、 を含むことを特徴とするプロセッサ。
- 16命令に基づいて各ステージを順次移行するプロセッサパイプライン処理を実行する複数のプロセッサパイプライン処理装置と、 前記プロセッサパイプライン処理における分岐命令の分岐予測を行う、請求項8乃至請求項14のうちいずれか一項に記載のハイブリッド分岐予測装置と、 前記各装置を制御する制御装置と、 を含むことを特徴とするプロセッサ。
- 17分岐命令に関する分岐予測を行う分岐予測装置が、前記分岐命令に関する分岐予測情報をグループ化した分岐予測グループを各々記憶し前記分岐予測情報を蓄積処理する分岐予測情報蓄積処理手段を参照し、前記分岐命令に関する分岐予測結果を生成して分岐予測を行う分岐予測方法であって、 少なくとも一つの前記分岐命令に関し、前記分岐予測情報蓄積処理手段の各々の前記分岐予測グループの中からいずれか一つの前記分岐予測グループを選択制御する第1の選択制御処理と、 前記第1の選択制御処理にて選択された前記分岐予測グループの中から一又は複数の前記分岐予測情報を選択制御する第2の選択制御処理と、 前記第2の選択制御処理にて選択された分岐予測情報に基づいて、前記分岐命令に関する分岐予測結果を生成する分岐予測結果生成処理と、 を含み、 前記第1の選択制御処理と、前記第2の選択制御処理と、前記分岐予測結果生成処理とについてのパイプライン処理を各分岐命令に関して行うと共に、 前記第1の選択制御処理は、 前記分岐予測グループを行選択により選択制御する行選択処理、 を含み、 前記第2の選択制御処理は、 一又は複数の前記分岐予測情報を列選択により選択制御する列選択処理、 を含み、 前記分岐予測情報蓄積処理手段の前記分岐予測情報又は前記分岐予測グループを選択するためのインデックス情報の値に関し、分岐予測生成に関する前記パイプライン処理を行う分岐予測生成パイプラインの一期間において、前記一期間の以降に実行される他の期間での前記インデックス情報の値を先行して計算し、前記分岐予測生成パイプラインの各期間での各処理に必要な各々のインデックス情報を供給する制御を行うインデックス情報制御ステップを含み、 第1の期間に、第1の分岐命令に関し、 前記インデックス情報制御ステップにて計算された前記第1の期間に対応する前記インデックス情報の値に基づいて、 前記分岐予測グループを選択する第1の行選択処理を行う第1のステップと、 前記第1の期間の後の第2の期間に、前記第1の分岐命令に関し 、前記インデックス情報制御ステップにて計算された前記第2の期間に対応する前記インデックス情報の値に基づいて、 一又は複数の前記分岐予測情報を選択する第1の列選択処理と、前記第1の分岐命令の次に処理される第2の分岐命令に関し前記分岐予測グループを選択する第2の行選択処理と、を並行して処理を行う第2のステップと、 前記第2の期間の後の第3の期間に、前記第1の分岐命令に関して前記第1の列選択処理にて選択された前記分岐予測情報に基づいて、前記第1の分岐命令に関する分岐予測結果を生成する第1の分岐予測結果生成処理と、前記第2の分岐命令に関し一又は複数の前記分岐予測情報を選択する第2の列選択処理と、前記第2の分岐命令の次に処理される第3の分岐命令に関し前記分岐予測グループを選択する第3の行選択処理と、を並行して処理を行う第3のステップと、 を含むことを特徴とする分岐予測方法。
- 18請求項17に記載の分岐予測方法において、 前記第3のステップでは、 前記第3の行選択処理の後に、前記第1の分岐予測結果生成処理にて生成された第1の分岐予測結果情報に基づいて、前記第3の期間の後の第4の期間における第4のステップに処理されるべき前記分岐予測情報蓄積処理手段のインデックス情報の値を先行して計算する処理を行うこと を特徴とする分岐予測方法。
- 19請求項18に記載の分岐予測方法において、 前記第3のステップでは、 計算された前記インデックス情報の値に基づいて、前記第4の期間に処理されるべき第3の列選択処理のためのインデックス情報の値を抽出し、特定の列選択情報一時格納部に保持する処理を行うこと、 を特徴とする分岐予測方法。
- 20請求項18に記載の分岐予測方法において、 前記第3のステップでは、 計算された前記インデックス情報の値を、前記第4の期間に処理されるべき第4の行選択処理のためのインデックス情報の値として保持する処理を行うこと、 を特徴とする分岐予測方法。
- 21請求項19に記載の分岐予測方法において、 前記第4のステップでは、 前記第2の分岐命令に関して生成される第2の分岐予測結果情報を生成する第2の分岐予測結果生成処理と、 前記第3の行選択処理にて各々の前記分岐予測グループの中から選択されたいずれか一つの前記分岐予測グループと、前記列選択情報一時格納部の値と、に基づいて、少なくとも2つの各分岐予測情報を選択する第3の列選択第1処理と、 前記第2の分岐予測結果生成処理にて生成された前記第2の分岐予測結果情報に基づいて、前記第3の列選択第1処理にて選択された各前記分岐予測情報のうち、一つの分岐予測情報を選択する第3の列選択第2処理と、 を行うことを特徴とする分岐予測方法。
- 22分岐命令に関する分岐予測を行う分岐予測装置が、前記分岐命令に関する分岐予測情報をグループ化した分岐予測グループを各々記憶し前記分岐予測情報を蓄積処理する分岐予測情報蓄積処理手段を参照し、前記分岐命令に関する分岐予測結果を生成して分岐予測を行うための分岐予測制御プログラムであって、 前記分岐予測装置に、 少なくとも一つの前記分岐命令に関し、前記分岐予測情報蓄積処理手段の各々の前記分岐予測グループの中からいずれか一つの前記分岐予測グループを選択制御する第1の選択制御処理と、 前記第1の選択制御処理にて選択された前記分岐予測グループの中から一又は複数の前記分岐予測情報を選択制御する第2の選択制御処理と、 前記第2の選択制御処理にて選択された分岐予測情報に基づいて、前記分岐命令に関する分岐予測結果を生成する分岐予測結果生成処理と、 を含む処理を実行させ、 前記分岐予測装置に、 前記第1の選択制御処理と、前記第2の選択制御処理と、前記分岐予測結果生成処理とについてのパイプライン処理を各分岐命令に関して実行させると共に、 前記第1の選択制御処理は、 前記分岐予測グループを行選択により選択制御する行選択処理、 を含み、 前記第2の選択制御処理は、 一又は複数の前記分岐予測情報を列選択により選択制御する列選択処理、 を含み、 前記分岐予測装置に、 前記分岐予測情報蓄積処理手段の前記分岐予測情報又は前記分岐予測グループを選択するためのインデックス情報の値に関し、分岐予測生成に関する前記パイプライン処理を行う分岐予測生成パイプラインの一期間において、前記一期間の以降に実行される他の期間での前記インデックス情報の値を先行して計算し、前記分岐予測生成パイプラインの各期間での各処理に必要な各々のインデックス情報を供給する制御を行うインデックス情報制御ステップを実行させると共に、 第1の期間に、第1の分岐命令に関し、 前記インデックス情報制御ステップにて計算された前記第1の期間に対応する前記インデックス情報の値に基づいて、 前記分岐予測グループを選択する第1の行選択処理を行う第1のステップと、 前記第1の期間の後の第2の期間に、前記第1の分岐命令に関し 、前記インデックス情報制御ステップにて計算された前記第2の期間に対応する前記インデックス情報の値に基づいて、 一又は複数の前記分岐予測情報を選択する第1の列選択処理と、前記第1の分岐命令の次に処理される第2の分岐命令に関し前記分岐予測グループを選択する第2の行選択処理と、を並行して処理を行う第2のステップと、 前記第2の期間の後の第3の期間に、前記第1の分岐命令に関して前記第1の列選択処理にて選択された前記分岐予測情報に基づいて、前記第1の分岐命令に関する分岐予測結果を生成する第1の分岐予測結果生成処理と、前記第2の分岐命令に関し一又は複数の前記分岐予測情報を選択する第2の列選択処理と、前記第2の分岐命令の次に処理される第3の分岐命令に関し前記分岐予測グループを選択する第3の行選択処理と、を並行して処理を行う第3のステップと、 を含む処理を実行させることを特徴とする分岐予測制御プログラム。
Independent claims22
210 paragraphs, as filed
The present invention relates to a branch prediction device, a hybrid branch prediction device, a processor, a branch prediction method, and a branch prediction control program.
Branch Prediction in a computer architecture is a function in a processor that predicts whether or not a conditional branch instruction branches in the program execution process. The processor fetches and executes an instruction by the branch prediction function before it is actually decided whether or not to branch. In particular, the pipeline processing processor fetches instructions one after another so as not to interrupt the pipeline, so branch prediction is required.
Examples of the related technology of the branch prediction device that performs this kind of branch prediction include the first related technology (Non-Patent Document 1) and the second related technology (Patent Document 1) shown below.
The first related technique discloses an example of a configuration of a branch prediction device of a dynamic branch prediction method. This first related technology is shown in FIG. FIG. 15 is a block diagram showing an example of the first related technology of the branch prediction device.
In the branch prediction device 700 shown in the figure, the branch prediction result is generated by using the reading results of the pattern history tables 720-1, 720-2, and 720-3. Specifically, the index information of the pattern history tables 720-1, 720-2, 720-3 is generated by using the hash logic circuit units 710-1, 710-2, 710-3 (Non-Patent Document No. 1). Pages 7-8). In the figure, the hash logic circuit units 710-1, 710-2, and 710-3 are branches corresponding to the global branch history information from the global branch history (information storage unit) 702 and the target instruction from the instruction counter 740. Performs hash logic operations based on the instruction address.
The branch prediction device 700 of the first related technology includes multiple types of pattern history table 720-1 (Meta: global branch prediction device), pattern history table 720-2 (G1: "e-gskew" type branch prediction device), and Each branch prediction result by the pattern history table 720-3 (G1: "e-gskew" type branch prediction device) and the pattern history table 720-3 (BIM: bimodal branch prediction device) is finally selected by the prediction result generation logic 730. It constitutes a "2Bc-gskew" type hybrid branch prediction device that outputs branch prediction results.
In the second related technique (Patent Document 1), the branch prediction device includes an XOR circuit as a hash logic circuit unit immediately before the tagged PHT (Pattern History Table) unit which is a pattern history table (Patent Document 1). Figure 2). The XOR circuit calculates the exclusive OR of the branch instruction address to be executed indicated by the program counter and the contents of the GHR unit. The GHR (Global History Register) unit is a register that records the history of whether or not a recently executed branch instruction has branched. The calculated exclusive OR is supplied as an index to the tagged PHT (Pattern History Table) unit. The tagged PHT unit is RAM that stores the tag and the count value for each index that is the output of the XOR circuit. When the count values are 0 and 1, it is predicted that it will not branch, and when the count values are 2 and 3, it is predicted that it will branch.<nplcit num="1"><text>Andre Seznec, et al, "Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor", In proceedings of the 29th IEEE-ACM International Symposium on Computer Architecture, 25-29 may 2002</text></nplcit><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-5956</text></patcit>
<p> However, since both the first related technology and the second related technology have a hash logic circuit unit immediately before the pattern history table, there is a delay in the processing related to branch prediction when accessing the pattern history table. There was a point to be improved that the processing speed of the processor was reduced.</p><p> Further, in the branch prediction device of the first related technology, when the hash logic circuit units 710-1, 710-2, and 710-3 perform an operation based on the branch instruction address from the instruction counter 740, the instruction counter Since the branch instruction address from 740 is not known until just before the fetch stage, the operations of the hash logic circuit units 710-1, 710-2, and 710-3 are performed ahead of schedule prior to the fetch stage of processor pipeline processing. The existence of the hash logic circuits 710-1, 710-2, and 710-3 themselves hindered the increase in processing speed.</p><p> In addition, after the fetch stage of the processor pipeline processing is started, the hash logic circuit units 710-1, 710-2, and 710-3 perform complicated hash logic operations based on the branch instruction address after the finding. , The arithmetic processing takes time, and the delay due to the arithmetic of the hash logic circuit unit exacerbates the delay of branch prediction including the access processing to the pattern history table, which leads to the delay of the fetch stage itself, and as a result, the delay of the processor is exacerbated. Therefore, since the branch prediction delay includes the delays of the hash logic circuits 710-1, 710-2, and 710-3, the branch prediction delay limits the clock cycle of the entire processor, which adversely affects the processing speed of the processor. There was a point to be improved that it exerts.</p><p> The present invention has been made as an object to solve the points to be improved in the related technology described above, and the purpose of the present invention is to provide a processor without providing a hash logic circuit unit immediately before the pattern history table. It is an object of the present invention to provide a branch prediction device, a hybrid branch prediction device, a processor, a branch prediction method, and a branch prediction control program capable of preventing a branch prediction delay that adversely affects the processing speed of the above.</p>
<p> The above object is achieved by a combination of the features described in the primary independent claims, and the sub-claims provide for further advantageous embodiments of the invention. The outline of the present invention does not list all the necessary features, and therefore independent claims and sub-claims not described here and subcombinations of these feature groups can also be inventions.</p><p> The branch prediction device of the present invention is a branch prediction information storage processing means that stores branch prediction groups that group branch prediction information related to branch instructions and stores the branch prediction information. A first selection control process that selectively controls at least one branch prediction group from each branch prediction group based on a request, and a branch prediction group selected by the first selection control process. A second selection control process that selectively controls one or more of the branch prediction information, and<u style="single">A prediction result generation process that generates a branch prediction result based on the branch prediction information selected in the second selection control process, and a prediction result generation process.</u>A pipeline access control means that performs processing including the above by pipeline processing and controls access to the branch prediction information storage processing means.<u style="single">With</u><u style="single">The pipeline access control means</u><u style="single">Regarding the value of the branch prediction information of the branch prediction information storage processing means or the index information for selecting the branch prediction group, in one period of the branch prediction generation pipeline that performs the pipeline processing related to the branch prediction generation, the above-mentioned one. The value of the index information in other periods executed after the period is calculated in advance, and control is performed to supply each index information required for each process in each process of the branch prediction generation pipeline. Index information control means and</u><u style="single">A first selection control means that performs the first selection control process by row selection based on the value of the index information corresponding to the one period calculated by the index information control means.</u><u style="single">Based on the value of the index information corresponding to the other period calculated by the index information control means, the first selection control process is performed for the branch prediction of the same branch instruction. A second selection control means that performs the second selection control process by column selection in different other periods.</u> It is characterized by including.</p><p> The hybrid branch prediction device of the present invention includes a branch prediction information storage processing means that stores branch prediction groups that group branch prediction information related to branch instructions and stores the branch prediction information, and the branch prediction information storage process. Regarding the branch history information storage processing unit that can access the means by pipeline processing and the value of the branch prediction information or the index information for selecting the branch prediction group, the pipe related to branch prediction generation. In one period of the branch prediction generation pipeline that performs line processing, the value of the index information in other periods executed after the one period is calculated in advance, and in each period of the branch prediction generation pipeline. The first index information control unit for controlling the supply of each index information required for each process of the above and performing the process at the fetch stage of the processor pipeline, controlling the index information, and committing the processor pipeline. The pipelined branch history information storage processing unit includes a second index information control unit for performing processing in the stage, and the pipelined branch history information storage processing unit corresponds to the one period calculated by the first index information control unit. Based on the value of the index information<u style="single">Select and control at least one branch prediction group from each branch prediction group.</u>Same branch based on the first selection control means that performs the first selection control process by row selection and the value of the index information corresponding to the other period calculated by the first index information control unit. For the branch prediction of the instruction, in the other period different from the one period in which the first selection control process is performed.<u style="single">, Select and control one or a plurality of the branch prediction information from the branch prediction group selected by the first selection control process.</u>A second selection control means that performs the second selection control process by column selection, and a prediction result generation means that generates a branch prediction result based on the branch prediction information selected by the second selection control means. The first index information control unit includes, the first selection control process by the first selection control means, the second selection control process by the second selection control means, and the prediction result. It is characterized in that it controls the pipeline processing of the processing including the prediction result generation processing by the generation means.</p><p> The processor of the present invention has a plurality of processor pipeline processing devices that execute processor pipeline processing that sequentially shifts each stage based on instructions, and the branch prediction described above that performs branch prediction of branch instructions in the processor pipeline processing. It is characterized by including a device or a hybrid branch prediction device and a control device that controls each of the devices.</p><p> In the branch prediction method of the present invention, the branch prediction device that performs branch prediction related to a branch instruction stores each branch prediction group in which branch prediction information related to the branch instruction is grouped, and stores the branch prediction information. A branch prediction method that refers to a processing means, generates a branch prediction result related to the branch instruction, and performs branch prediction. The branch prediction group of each of the branch prediction information storage processing means with respect to at least one branch instruction. A first selection control process that selectively controls any one of the branch prediction groups, and one or more branch prediction information from the branch prediction group selected by the first selection control process. Includes a second selection control process that selectively controls the above, and a branch prediction result generation process that generates a branch prediction result related to the branch instruction based on the branch prediction information selected in the second selection control process. , The first selection control process, the second selection control process, and the branch prediction result generation process are performed for each branch instruction, and the first selection control process is the branch. The second selection control process includes a row selection process of selecting and controlling a prediction group by row selection, and the second selection control process includes a column selection process of selecting and controlling one or more branch prediction information by column selection.<u style="single">Regarding the value of the branch prediction information of the branch prediction information storage processing means or the index information for selecting the branch prediction group, in one period of the branch prediction generation pipeline that performs the pipeline processing related to the branch prediction generation, the above-mentioned one. The value of the index information in other periods executed after the period is calculated in advance, and control is performed to supply each index information required for each process in each process of the branch prediction generation pipeline. Including index information control step</u>Regarding the first branch instruction in the first period<u style="single">Based on the value of the index information corresponding to the first period calculated in the index information control step.</u>Regarding the first branch instruction in the first step of performing the first row selection process for selecting the branch prediction group and in the second period after the first period.<u style="single">, Based on the value of the index information corresponding to the second period calculated in the index information control step.</u>A first column selection process for selecting one or more branch prediction information, and a second row selection process for selecting the branch prediction group for a second branch instruction processed after the first branch instruction. And, in the second step of processing in parallel, and in the third period after the second period, the branch selected in the first column selection process with respect to the first branch instruction. A first branch prediction result generation process that generates a branch prediction result for the first branch instruction based on the prediction information, and a second branch prediction information that selects one or more branch prediction information for the second branch instruction. A third step of processing the column selection process and the third row selection process for selecting the branch prediction group for the third branch instruction processed after the second branch instruction in parallel. , Is included.</p><p> In the branch prediction program of the present invention, the branch prediction device that performs branch prediction related to a branch instruction stores each branch prediction group in which branch prediction information related to the branch instruction is grouped, and stores the branch prediction information. A branch prediction control program for generating a branch prediction result related to the branch instruction and performing branch prediction by referring to the processing means. The branch prediction device stores the branch prediction information for at least one branch instruction. Among the first selection control process that selectively controls any one of the branch prediction groups from each of the branch prediction groups of the processing means and the branch prediction group selected by the first selection control process. A branch prediction result related to the branch instruction is generated based on the second selection control process that selectively controls one or a plurality of the branch prediction information and the branch prediction information selected by the second selection control process. A process including a branch prediction result generation process is executed, and the branch prediction device is subjected to a pipeline process for the first selection control process, the second selection control process, and the branch prediction result generation process. The first selection control process includes a row selection process that selectively controls the branch prediction group by row selection, and the second selection control process includes one or more of the above. Includes a column selection process that selects and controls branch prediction information by column selection.<u style="single">A branch prediction generation pipeline that performs the pipeline processing related to branch prediction generation in the branch prediction device with respect to the value of the branch prediction information of the branch prediction information storage processing means or the index information for selecting the branch prediction group. In one period, the value of the index information in other periods executed after the one period is calculated in advance, and each index information required for each process in each period of the branch prediction generation pipeline. The index information control step that controls the supply of</u>Regarding the first branch instruction in the first period<u style="single">Based on the value of the index information corresponding to the first period calculated in the index information control step.</u>Regarding the first branch instruction in the first step of performing the first row selection process for selecting the branch prediction group and in the second period after the first period.<u style="single">, Based on the value of the index information corresponding to the second period calculated in the index information control step.</u>A first column selection process for selecting one or more branch prediction information, and a second row selection process for selecting the branch prediction group for a second branch instruction processed after the first branch instruction. And, in the second step of processing in parallel, and in the third period after the second period, the branch selected in the first column selection process with respect to the first branch instruction. A first branch prediction result generation process that generates a branch prediction result for the first branch instruction based on the prediction information, and a second branch prediction information that selects one or more branch prediction information for the second branch instruction. A third step of processing the column selection process and the third row selection process for selecting the branch prediction group for the third branch instruction processed after the second branch instruction in parallel. It is characterized in that processing including, is executed.</p><p> The actions and other gains of the present invention will be apparent from the "best embodiments for carrying out the invention" described below.</p>
<p> According to the present invention, since there is no hash logic circuit unit immediately before the branch prediction information storage processing means, a delay in branch prediction can be prevented, and the pipeline access control means has the first selection control process and the second selection control. By performing access processing to the branch prediction information storage processing means by pipeline processing in two stages of processing, the processing speed in branch prediction can be increased and the performance of the branch prediction device is improved.</p>
The embodiments described below do not unreasonably limit the content of the present invention described in the claims. Moreover, not all of the configurations described in the embodiments are essential constituent requirements of the present invention.
Hereinafter, an example of a preferred embodiment of the present invention will be specifically described with reference to the drawings. [First Embodiment] First, the configuration of the branch prediction device of the present invention will be described from the schematic configuration, and then the detailed configuration will be described.
(Outline configuration of branch prediction device) The schematic configuration of the branch prediction device of the present embodiment will be described with reference to FIGS. 1 and 6. FIG. 1 is a block diagram showing an example of a schematic configuration of the branch prediction device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram for explaining pipeline processing related to access to the branch prediction information storage processing means of the branch prediction device.
As shown in FIG. 1, the branch prediction device 1 determines branch prediction information (information indicating whether to predict branching or not branching) regarding a branch instruction and whether or not the immediately preceding branch is established (established / not established). The branch prediction information storage processing means 6 that stores the branch prediction group that groups the branch establishment / non-establishment information indicating) and stores the branch prediction information, and in each of the branch prediction groups based on the request. From the first selection control process for selectively controlling at least one branch prediction group (for example, the process of reference numeral 230CA shown in FIG. 6) and the branch prediction group selected in the first selection control process. Based on the second selection control process (for example, the process of reference numeral 230RA shown in FIG. 6) that selectively controls one or a plurality of the branch prediction information, and the branch prediction information selected in the second selection control process. A process including a prediction result generation process (for example, a process of reference numeral 230G shown in FIG. 6) for generating a branch prediction result is performed by pipeline processing, and access to the branch prediction information storage processing means 6 is controlled. It is configured to include the pipeline access control means 2. ---
Further, the pipeline access control means 2 is a first selection control means that accesses the branch prediction information storage processing means 6 and selectively controls at least one branch prediction group from the branch prediction groups. 4, the second selection control means 5 that selectively controls one or a plurality of the branch prediction information from the branch prediction group selected by the first selection control means 4, and the second selection control means 5. The prediction result generation means 7 that generates the branch prediction result based on the branch prediction information selected in the above, the first selection control process by the first selection control means 4, and the second by the second selection control means 5. It is configured to include an index information control means 3 that functions as a branch prediction generation pipeline control means that controls pipeline processing by the prediction result generation process by the selection control process / prediction result generation means 7.
Further, the pipeline access control means 2 can control the processing including the first selection control process and the second selection control process in a pipeline.
The index information control means 3 is a branch prediction generation pipe that performs the pipeline processing related to branch prediction generation with respect to the branch prediction information of the branch prediction information storage processing means 6 or the value of the index information for selecting the branch prediction group. The value of the index information in one period of the line (for example, the period of T2 = 0 shown in FIG. 6) and another period (for example, the period of T2 = 1 shown in FIG. 6) executed after the one period. Is calculated in advance, and control is performed to supply each index information required for each process in each period of the branch prediction generation pipeline.
Further, the index information control means 3 corresponds to another branch instruction preceding the branch instruction and is executed in the one period (for example, the period of T2 = 0 shown in FIG. 6). Based on the branch prediction result generated in the above, the value of the index information in the other period (for example, the period of T2 = 1 shown in FIG. 6) is calculated.
Further, the index information control means 3 has execution path history information (for example, shown in FIG. 3) relating to information on the paths of N branch instructions executed and passed from the branch instruction N before to the branch instruction to be the branch prediction target. Based on D2), the value of the index information corresponding to the branch instruction that is the branch prediction target is calculated.
Furthermore, as an example, the index information control means 3 selects the output of the shift register constituting the extension-Folded-Index-register unit (for example, reference numeral 10 shown in FIG. 2) by the first selection control means 4. It is preferable to use an input configuration.
The first selection control means 4 makes the first selection based on the value of the index information corresponding to the one period (for example, the period of T2 = 0 shown in FIG. 6) calculated by the index information control means 3. The control process (for example, the process of reference numeral 230CA shown in FIG. 6) is performed by row selection.
The second selection control means 5 makes the first selection for the branch prediction of the same branch instruction based on the value of the index information corresponding to the other period calculated by the index information control means 3. The second selection control process is performed by column selection in the other period different from the one period in which the control process is performed.
The branch prediction device 1 having the above-described configuration operates as follows. That is, the branch prediction device 1 uses the index information control means 3 to perform the first selection control process by the first selection control means 4, the second selection control process by the second selection control means 5, and the prediction result generation means 7. Controls the pipeline processing by the prediction result generation processing by.
At this time, the index information control means 3 performs the pipeline processing related to the branch prediction generation with respect to the branch prediction information of the branch prediction information storage processing means 6 or the value of the index information for selecting the branch prediction group. In one period of the prediction generation pipeline, the value of the index information in other periods executed after the one period is calculated in advance, and for each process in each period of the branch prediction generation pipeline. Provide each required index information. As a result, the index information can be advanced in the calculation process.
Further, the index information control means 3 corresponds to another branch instruction preceding the branch instruction and is based on the branch prediction result generated in the prediction result generation process executed in the one period. , Calculate the value of the index information in the other period.
Here, the first selection control means 4 performs the first selection control process by row selection based on the value of the index information corresponding to the one period calculated by the index information control means 3. Further, the second selection control means 5 is the first for branch prediction of the same branch instruction based on the value of the index information corresponding to the other period calculated by the index information control means 3. The second selection control process is performed by column selection in the other period different from the one period in which the selection control process is performed.
Further, the index information control means 3 branches the branch based on the execution path history information regarding the information of the paths of the N branch instructions executed and passed from the branch instruction N before to the branch instruction to be the branch prediction target. The value of the index information corresponding to the branch instruction that is the prediction target is calculated. As a result, by incorporating the execution path history information into the index calculation, the branch prediction accuracy can be improved without introducing a complicated hash logic configuration.
Further, the index information control means 3 includes a configuration in which the output of the shift register constituting the extended-Folded-Index-register unit is used as an input for row selection by the first selection control means. As a result, by directly inputting the row selection input to the register value, the change point of the register value can be fixed and the prediction accuracy can be prevented from deteriorating.
By performing the process of selecting the branch prediction information in the pipeline process in this way, the process of branch prediction can be performed at high speed. Further, since the delay in the branch prediction process does not enter the critical path of the processor, it is possible to provide a branch prediction device that can contribute to the improvement of the processing speed of the processor as a whole.
By performing the process of selecting the branch prediction information by the pipeline process as described above, the process of branch prediction can be performed at high speed. Further, since the delay in the branch prediction process does not enter the critical path of the processor, it is possible to provide a branch prediction device that can contribute to the improvement of the processing speed of the processor as a whole.
(Detailed configuration) FIG. 2 discloses an example of the detailed configuration of each of these means. The detailed configuration of the branch prediction device 1 will be described with reference to FIG. FIG. 2 is a block diagram showing an example of a detailed configuration of the branch prediction device of the present embodiment.
The branch prediction device 1 of the present embodiment uses branch history information D1 such as global branch history and execution path history information D2, and as shown in FIG. 2, is an extension of the index information control means 3. -A pipe that performs access processing by pipeline processing to the pattern history table 22, which is an example of the branch prediction information storage processing means 6, based on the information of the -Folded-Index-register unit 10 and the extension-Folded-Index-register unit 10. The lined pattern history table 20 and the prediction result generation logic 30A, which is an example of the prediction result generation means 7 for generating the prediction result based on the output from the pipelined pattern history table 20, are included.
As shown in FIG. 2, the extension-Folded-Index-register unit 10 includes a shift register 11 and a logic circuit 12.
The shift register 11 temporarily stores the branch history information for the past several instructions and the hash value of the branch instruction address.
The logic circuit 12 includes a function (information update function) for updating the temporarily stored information in the shift register 11. The input of the logic circuit 12 is the hash value of the rewind destination, the instruction address of the target branch instruction (for example, from the <branch destination address corresponding to each branch instruction> BTB, which is not shown), and the prediction result generation logic. The output of the branch prediction logic immediately before 30A and the output of the shift register 11 are used. Therefore, the logic circuit 12 has a function of inputting the hash value of the rewind destination, a function of inputting the target branch instruction address, a function of inputting the output of the immediately preceding branch prediction logic, and an output of the shift register. Includes input function.
The hash value of the rewind destination is selected when it is found that the branch prediction result is incorrect. Part of the branch instruction address, the output of the prediction result generation logic 30A, and the output of the shift register 11 are used for recalculation of the hash value.
The pipelined pattern history table 20 is based on the pattern history table 22 which is an example of the branch prediction information storage processing means for accumulating and processing the branch prediction information, and the output from the shift register 11 of the extension-Folded-Index-register unit 10. Then, from the row selection logic 21 that selects a specific group from the group group of branch prediction information stored in the pattern history table 22 by row selection, and from the pattern history table 22 that is selected by the row selection logic 21. Output from the first pipeline register 23, which is an example of the branch prediction group information temporary storage unit that temporarily holds a specific group of output branch prediction information, and the logic circuit 12 of the extension-Folded-Index-register unit 10. A copy register 27, which is an example of a column selection information temporary storage unit that is temporarily held by duplicating (column selection information among index information), and a first pipeline register based on the information from the copy register 27. The first column selection logic 24 as the first column selection logic circuit unit that selects some specific branch prediction information from a plurality of branch prediction information of a specific group stored in 23 by column selection. , Prediction result generation Based on the output from logic 30A, the second column selection selects specific branch prediction information from several branch prediction information selected by the first column selection logic 24 by column selection. It includes a second column selection logic 25 as a logic circuit unit and a second pipeline register 26 which is an example of a branch prediction information temporary storage unit that temporarily holds the output of the second column selection logic 25. It is composed.
Here, the copy register 27 (temporary storage unit for column selection information), the first pipeline register 23 (temporary storage unit for branch prediction group information), and the first column selection logic 24 (first column selection logic circuit unit) Therefore, it can also be called "first column selection means 5a". The "first column selection means 5a" can select at least two branch prediction information from one branch prediction group based on the value of the index information. It can also be called "second column selection means 5b" by the second column selection logic 25 and the second pipeline register 26. The "second column selection means 5b" is a branch prediction of one of the branch prediction information selected by the first column selection means based on the branch prediction result information generated by the prediction result generation process. Information can be selected.
The pattern history table 22 contains 1-bit branch prediction information (information indicating whether to predict branching or not branching) and 1-bit information indicating whether or not the immediately preceding branch is established (established / unestablished). Stores a total of 2 bits (branch establishment / non-establishment information). This information is composed of several groups (branch prediction groups) in order to realize a two-step read process. The row selection process selects an appropriate branch prediction group. The column selection process selects appropriate branch prediction information from within the branch prediction group.
The copy register 27 temporarily holds the information obtained by copying the hash value of the logic circuit 12 for inputting to the first column selection logic 24. That is, the copy register 27, which is an example of the column selection information temporary storage unit, is a column of the index information by duplicating a part of the values of the shift register 11 constituting the extension-Folded-Index-register unit 10. Selection information can be stored.
The row selection logic 21 directly decodes the output from the shift register 11 and reads an appropriate branch prediction group in the pattern history table 22. The read pattern history table 22 entry is stored in the first pipeline register 23.
The value of the first pipeline register 23 is selected by the first column selection logic 25 based on the value of the copy register 27. That is, the first pipeline register 23, which is an example of the branch prediction group information temporary storage unit, can temporarily store information about one branch prediction group selected by the first selection control means.
The first column selection logic 25 selects a value suitable for the value of the next branch instruction. That is, the first column selection logic 25 as the first column selection logic circuit unit has the value of the column selection information of the column selection information temporary storage unit and one branch prediction group of the branch prediction group information temporary storage unit. At least two branch prediction information can be selected from the one branch prediction group based on the information about.
The output of the second column selection logic 26 is selected by the output of the prediction result generation logic 30A and stored in the second pipeline register 26.
Here, the correspondence between the constituent elements described in the present embodiment and the constituent requirements described in the present invention will be described. As an example of the first selection control means 4, the row selection logic 21 can be mentioned. As an example of the second selection control means 5, a configuration including a first pipeline register 23, a first column selection logic 24, a second column selection logic 25, a second pipeline register 26, and a copy register 27 may be used. Can be mentioned. An example of the prediction result generation means 7 is the prediction result generation logic 30A. A pattern history table 22 and the like can be mentioned as an example of the branch prediction information storage processing means.
In the branch prediction device 1 in FIG. 2 having the above configuration, the extension-Folded-Index-register unit 10 efficiently transmits long branch history information (for example, global branch history information D1) and execution path history information D2. Hash. By inputting the execution path history information D2, the branch prediction accuracy can be improved.
Further, the output of the shift register 11 of the extension-Folded-Index-register unit 10 is the input of the row selection logic 21 of the pattern history table 22. As a result, the row selection logic 21 reads out a set of branch prediction information related to the target branch instruction, so that the branch prediction delay is reduced.
In addition, the column selection information also applies the output from the pipeline registers directly, reducing delays.
Further, since the reading process of the pattern history table 22 is processed by pipelined into two steps of row selection and column selection, the processing speed can be improved without impairing the branch prediction accuracy.
In this way, in the present embodiment, the extension-Folded-Index-register unit is utilized, the index using the execution path history information D2 is created, and the access to the pattern history table is pipelined. .. Therefore, it is possible to realize highly accurate branch prediction with low delay.
(Extended-Folded-Index-Detailed configuration of register unit) Next, the detailed configuration of the extended-Folded-Index-register unit 10 will be described with reference to FIG. FIG. 3 is a block diagram showing an example of the internal configuration of the expansion-Folded-Index-register unit of the branch prediction device of FIG.
With reference to FIG. 3, a detailed configuration example of the extended-Folded-Index-register unit shown in FIG. 2 is shown.
As shown in FIG. 3, the extension-Folded-Index-register unit 10 has a branch history register 13 as a branch history information temporary storage means for temporarily holding branch history information such as new branch history information D1, and an execution path history information. Execution path history information that temporarily holds the execution path history register 14 as a temporary storage means, and exclusive based on two input values of the logical value of the new branch history information D1 and the output logical value of the 7th register (C7) 11h. The first exclusive OR (XOR:) that performs a logical sum operation (outputs "1" when two input values are different and "0" when two input values are the same).new data is newly added to the exclusiveOR) arithmetic circuit unit 15a, the first register (C0) 11a that temporarily holds the output of the first exclusive logical sum arithmetic circuit unit 15a, and the first register (C0) 11a. When input, the old data of the 1st register (C0) 11a held until then is shifted and input, and the logical value and execution of the output of the 2nd register (C1) 11b and the 2nd register (C1) 11b The second exclusive logical sum operation circuit unit 15b that performs an exclusive logical sum operation based on the two input values with the output logical value of the path history register 14 and the second exclusive logical sum operation circuit unit 15b. When new data is newly input to the 3rd register (C2) 11c that temporarily holds the output and the 3rd register (C2) 11c, the old data of the 3rd register (C2) 11c that was held until then shifts. When new data is newly input to the 4th register (C3) 11d and the 4th register (C3) 11d, the old data of the 4th register (C3) 11d held until then is shifted. When new data is newly input to the input 5th register (C4) 11e and the 5th register (C4) 11e, the old data of the 5th register (C4) 11e held until then is shifted and input. When new data is newly input to the 6th register (C5) 11f and the 6th register (C5) 11f, the old data of the 6th register (C5) 11f held until then is shifted and input. The third exclusive logical sum operation is performed based on the two input values of the 7th register (C6) 11g, the output logical value of the branch history register 13, and the logical value of the new path history information D2. Exclusive logical sum operation is performed based on two input values of the arithmetic circuit unit 15c, the output logical value of the third exclusive logical sum operation circuit unit 15c, and the output logical value of the seventh register (C6) 11g. It is configured to include a fourth exclusive logical sum arithmetic circuit unit 15d to be performed, and an eighth register (C7) 11h for temporarily holding the output of the fourth exclusive logical sum arithmetic circuit unit 15d.The logical value of the output of the third exclusive OR arithmetic circuit unit 15c that performs the exclusive OR operation, the third exclusive OR arithmetic circuit unit 15c, and the logical value of the output of the seventh register (C6) 11g. 2 The 8th register (C7) that temporarily holds the outputs of the 4th exclusive OR operation circuit unit 15d that performs the exclusive OR operation based on the input value and the 4th exclusive OR operation circuit unit 15d. It is composed of 11h and.The logical value of the output of the third exclusive OR arithmetic circuit unit 15c that performs the exclusive OR operation, the third exclusive OR arithmetic circuit unit 15c, and the logical value of the output of the seventh register (C6) 11g. 2 The 8th register (C7) that temporarily holds the outputs of the 4th exclusive OR operation circuit unit 15d that performs the exclusive OR operation based on the input value and the 4th exclusive OR operation circuit unit 15d. It is composed of 11h and.
Here, the first register (C0) 11a, the second register (C1) 11b, the third register (C2) 11c, the fourth register (C3) 11d, the fifth register (C4) 11e, and the sixth register. The register (C5) 11f, the seventh register (C6) 11g, and the eighth register (C7) 11h constitute the cyst register 11 of the extension-Folded-Index-register unit 10 shown in FIG.
Further, the branch history register 13, the execution path history register 14, the first exclusive OR operation circuit unit 15a, the second exclusive OR operation circuit unit 15b, and the third exclusive OR operation circuit unit 15a. The logic circuit 12 of the extension-Folded-Index-register unit 10 shown in FIG. 1 is configured by the unit 15c and the fourth exclusive OR operation circuit unit 15d.
Further, the first register (C0) 11a, the third register (C2) 11c, and the eighth register (C7) 11h to which the output of each exclusive OR operation circuit unit is input are the branch history information D1 and the execution. It becomes variable based on the path history information D2. The second register (C1) 11b, the fourth register (C3) 11d, the fifth register (C4) 11e, the sixth register (C5) 11f, and the seventh register (C6) 11g are each bit. The value changes depending on the shift.
Furthermore, the values of the first register (C0) 11a, the second register (C1) 11b, and the eighth register (C7) 11h are copied to the copy register 27. Therefore, the shift register 11 includes a first register portion input to the row selection logic 21 and a second register portion copied to the copy register 27.
The execution path history register 14 stores the history related to the path information of the N branch instruction passed from the N previous branch instruction to the target branch instruction. High branch prediction accuracy is achieved by execution path history information.
In the configuration example of the logic circuit 12 shown in FIG. 3, a total of 25 bits of the 15-bit branch history information D1 and the 10-bit execution path history information D2 are compressed by using hash logic to generate 8-bit index information. The bit length and the like are variable, and it is possible to hash the bits.
The state one cycle ahead of the information stored in the first register (C0) 11a to the eighth register (C7) 11h is a simple bit shift except for the register that receives the XOR input. For example, of the registers 11a to 11h shown in FIG. 3, C0, C2, C3, C4, and C5 are the contents of C1, C3, C4, C5, and C6 in the next cycle. That is, C0, C2, C3, C4, and C5 become shifted C1, C3, C4, C5, and C6 in the next cycle.
Therefore, by using the register values of C0, C2, C3, C4, and C5 as index information for row access, the time of the pattern history table can be started one cycle before the branch prediction accuracy.
For this reason, the extended-Folded-Index-register 10 takes advantage of the fact that most of the values in the register after one cycle can be obtained, and is an index that includes the index information of the previous cycle and the index information of the subsequent cycle. Start accessing the pattern history table one cycle ahead of schedule without damaging the information. As a result, access to the pattern history table in the branch prediction result generation process can be pipelined in two stages (three stages including the prediction result generation process).
In addition, the extension-Folded-Index-register 10 is used to introduce the execution path history information D2 into the index calculation of the pattern history table without increasing the delay, and the branch prediction accuracy is about the same as when complicated hash logic is introduced. Can be realized. As a result, the hash logic can be removed without degrading the branch prediction accuracy. Therefore, while maintaining the branch prediction accuracy, the branch prediction delay can be prevented from entering the critical path of the processor, and the processing delay in the branch prediction can be reduced.
(About the pipeline structure of the processor) Here, prior to explaining the pipeline structure relating to the access to the pattern history table, which is a feature of the present embodiment, each stage of the pipeline structure of the processor will be described with reference to FIG. FIG. 4 is an explanatory diagram for explaining the pipeline structure of the processor including the branch predictor.
The branch prediction device 1 is assumed to be used on a processor having the pipeline structure shown in FIG. In FIG. 4, the pipeline structure has a total of 8 configurations of T = 0 to T = 9, but it can be applied to processors other than such 8 configurations.
In the pipeline processing of the processor, as shown in FIG. 4, four instructions, the first instruction 110, the second instruction 120, the third instruction 130, and the fourth instruction 140, are fetch stages (fetch processing), respectively. , Decode stage (decode processing), operand read stage (operand read processing), execution stage (execution processing), memory access stage (memory access processing), write-back stage (write-back processing), commit stage (commit processing,), It has a total of 8 stages of retirement stages (retirement processing).
Specifically, for the first instruction 110, T1 = 0 is the fetch stage 110F (first fetch process), T1 = 1 is the decode stage 110D (first decode process), and T1 = 2 is the operand read stage. 110OP (first operand read processing), execution stage 110EX (first execution processing) at T1 = 3, memory access stage 110MA (first memory access processing) at T1 = 4, write-back stage 110WR at T1 = 5 (1st write-back process), T1 = 6 is configured to process commit stage 110CO (1st commit process), and T1 = 7 is configured to process retirement stage 110RE (1st retirement process).
Regarding the second instruction 120, T1 = 1 for fetch stage 120F (second fetch processing), T1 = 2 for decoding stage 120D (second decoding processing), and T1 = 3 for operand read stage 120OP (second fetch processing). Operand read processing), execution stage 120EX (second execution processing) at T1 = 4, memory access stage 120MA (second memory access processing) at T1 = 5, write-back stage 120WR (second writing) at T1 = 6. (Return process), T1 = 7 is configured to process commit stage 120CO (second commit process), and T1 = 8 is configured to process retirement stage 120RE (second retirement process).
Regarding the third instruction 130, T1 = 2 is fetch stage 130F (third fetch process), T1 = 3 is decode stage 130D (third decode process), and T1 = 4 is operand read stage 130OP (third instruction 130). Operand read processing), execution stage 130EX (third execution processing) at T1 = 5, memory access stage 130MA (third memory access processing) at T1 = 6, write-back stage 130WR (third writing) at T1 = 7. (Return process), T1 = 8 is configured to process commit stage 130CO (third commit process), and T1 = 9 is configured to process retirement stage 130RE (third retirement process).
Regarding the fourth instruction 140, T1 = 3 is fetch stage 140F (fourth fetch process), T1 = 4 is decode stage 140D (fourth decode process), and T1 = 5 is operand read stage 140OP (fourth instruction). Operand read processing), execution stage 140EX (fourth execution processing) at T1 = 6, memory access stage 140MA (fourth memory access processing) at T1 = 7, write-back stage 140WR (fourth writing) at T1 = 8. (Return process), T1 = 9 is configured to process commit stage 140CO (fourth commit process), and T1 = 10 is configured to process retirement stage 140RE (fourth retirement process).
Therefore, when T1 = 0 (first processor period), the processor executes only the processing of the fetch stage 110F related to the first instruction 110.
At T1 = 1, the processor simultaneously executes the processing of the decoding stage 110D for the first instruction 110 and the processing of the fetch stage 120F for the second instruction 120.
At T1 = 2, the processor simultaneously executes the processing of the operand read stage 110OP for the first instruction 110, the processing of the decoding stage 120D for the second instruction 120, and the processing of the fetch stage 130F for the third instruction 130. To do.
At T1 = 3, the processor processes the execution stage 110EX for the first instruction 110, the operand read stage 120OP for the second instruction 120, the decode stage 130D for the third instruction 130, and the fourth. The processing of fetch stage 140F related to the instruction of is executed at the same time.
At T1 = 4, the processor processes the memory access stage 110MA for the first instruction 110, the execution stage 120EX for the second instruction 120, the operand read stage 130OP for the third instruction 130, and so on. The processing of the decoding stage 140D related to the instruction of 4 is executed at the same time.
At T1 = 5, the processor processes the write-back stage 110WR for the first instruction 110, the memory access stage 120MA for the second instruction 120, the execution stage 130EX for the third instruction 130, and so on. Operand read stage 140 OP processing related to instruction 4 is executed at the same time.
At T1 = 6, the processor processes the commit stage 110CO for the first instruction 110, the write-back stage 120WR for the second instruction 120, the memory access stage 130MA for the third instruction 130, and so on. Executes the processing of execution stage 140EX related to the instruction of 4 at the same time.
At T1 = 7, the processor processes the retirement stage 110RE for the first instruction 110, the commit stage 120CO for the second instruction 120, the write-back stage 130WR for the third instruction 130, and the fourth instruction. The processing of the memory access stage 140MA related to the instruction of is executed at the same time.
At T1 = 8, the processor simultaneously executes retirement stage 120RE processing for the second instruction 120, commit stage 130CO processing for the third instruction 130, and write-back stage 140WR processing for the fourth instruction 140. To do.
At T1 = 9, the processor simultaneously executes the processing of the retirement stage 130RE for the third instruction 130 and the processing of the commit stage 140CO for the fourth instruction 140.
At T1 = 10, the processor only performs retirement stage 140RE processing for the fourth instruction 140.
In the processor that performs the pipeline processing as described above, the branch prediction device generates branch prediction results at the fetch stages 110F, 210F, 310F, and 410F shown in FIG.
(About the pipeline structure for accessing the pattern history table) Next, an overview of the stages of the pipeline structure regarding access to the pattern history table will be described with reference to FIG. FIG. 5 is an explanatory diagram for explaining a pipeline structure relating to access to the pattern history table in the branch prediction device of FIG. In FIG. 5, for convenience of explanation, only three of the first branch instruction 210, the second branch instruction 220, and the third branch instruction 230 are listed, but the branch prediction corresponding to more branch instructions is given. The processing is sequentially pipelined.
As shown in FIG. 5, the pipeline structure for accessing the pattern history table is such that the first branch instruction 210, the second branch instruction 220, and the third branch instruction 230 are in the branch prediction group of the pattern history table, respectively. Pattern history table that performs access processing that selects by row selection logic Stage processing of row access (first selection control processing), branch prediction information from the branch prediction group selected by row selection logic is the first and second Pattern history table that performs access processing selected by column selection logics 24 and 25 Processes the stage of column access (second selection control processing), and performs processing that generates branch prediction results based on the selected branch prediction information. It has a total of three stages of branch prediction result generation stage processing (prediction result generation processing). Here, the stage of branch prediction result generation is processed in a shorter period than the period of other stages.
More specifically, for the first branch instruction 210, T2 = -2 indicates the pattern history table row access 210CA stage processing (first row selection processing), and T2 = -1 indicates the pattern history table column access 210RA. Stage processing (first row selection processing), branch prediction result generation at T2 = 0 210G stage processing (first branch prediction result generation processing) is configured to be processed.
Here, the value of T2 is a value that correlates with the value of T1 of the pipeline processing of the processor described above. That is, the branch prediction preprocessing is performed at the timing stage of T2 = -2 before T1 = 0 of the processor pipeline processing.
Regarding the second branch instruction 220, T2 = -1 processes the stage of the pattern history table row access 220CA (second row selection process), and T2 = 0 processes the stage of the pattern history table column access 220RA (second row selection process). Column selection process), T2 = 1 is configured to process the branch prediction result generation 220G stage process (second branch prediction result generation process).
Regarding the third branch instruction 230, T2 = 0 for pattern history table row access 230CA stage processing (third row selection processing), and T2 = 1 for pattern history table column access 230RA stage processing (third). Column selection process), T2 = 2 is configured to process the branch prediction result generation 230G stage (third branch prediction result generation process).
Therefore, in T2 = 2 (first period / first step), the branch prediction device processes the stage of the pattern history table row access 210CA related to the first branch instruction 210 (first row selection processing). Do only (first step).
In T2 = -1 (second period / second step), the branch predictor performs the stage processing (first column selection processing) of the pattern history table column access 210RA regarding the first branch instruction 210 and the first. Pattern history table related to 2 branch instruction 220 Row access 220 CA stage processing (second row selection processing) is executed at the same time (second step).
At T2 = 0 (third period, third step), the branch prediction device performs the branch prediction result generation 210G stage processing (first branch prediction result generation processing) and the first branch prediction result generation processing for the first branch instruction 210. Pattern history table column access 220RA stage processing (second column selection processing) for branch instruction 220 and pattern history table row access 230CA stage processing for third branch instruction 230 (third row selection processing) ) And at the same time (third step).
At T2 = 1 (fourth period / fourth step), the branch prediction device performs the branch prediction result generation 220G stage processing (second branch prediction result generation processing) and the second branch prediction result generation processing for the second branch instruction 220. Pattern history table related to branch instruction 220 of 3 Column access 230 RA stage processing (third column selection processing) is executed at the same time (fourth step).
At T2 = 2 (fifth period, fifth step), the branch prediction device executes only the branch prediction result generation 230G stage processing (second branch prediction result generation processing) related to the third branch instruction 230. (Fifth step).
The stage contents of the pipeline processing have been described above, but the operation of the branch prediction device for realizing such a pipeline processing and a more detailed processing procedure will be described below.
(Explanation of branch prediction device operation <processing procedure>) Various processing procedures in the branch prediction device will be described with reference to FIGS. 2, 3, 6, and 7. First, the "basic configuration of the branch prediction method" will be described, and then the "branch prediction procedure" and the "update procedure" after the branch prediction procedure will be described.
Here, the basic configuration of the branch prediction method according to the present embodiment will be described. In the branch prediction method according to the present embodiment, the branch prediction device that performs branch prediction related to the branch instruction receives branch prediction information (information indicating whether to predict branching or not branching) related to the branch instruction and immediately before. Refer to the branch prediction information storage processing means that stores each branch prediction group that groups the branch establishment / non-establishment information indicating whether or not the branch is established (establishment / non-establishment), and accumulates the branch prediction information. It generates a branch prediction result related to an instruction and performs branch prediction.
The basic configuration of the branch prediction method according to the present embodiment will be described using the above-mentioned pipeline processing stage. With respect to at least one branch instruction, each branch prediction information storage processing means has said branch prediction. The first selection control process (for example, reference numeral 230CA shown in FIG. 5) that selectively controls any one of the branch prediction groups from the groups, and the branch prediction group selected by the first selection control process. Based on the second selection control process (for example, reference numeral 230RA shown in FIG. 5) that selectively controls one or a plurality of the branch prediction information, and the branch prediction information selected in the second selection control process. A branch prediction result generation process (for example, reference numeral 230G shown in FIG. 5) that generates a branch prediction result related to the branch instruction is included, the first selection control process, the second selection control process, and the branch prediction. Pipeline processing for result generation processing can be performed for each branch instruction.
At this time, the first selection control process includes a row selection process in which the branch prediction group is selected and controlled by row selection. The first selection control process includes a column selection process for selectively controlling one or more branch prediction information by column selection.
In addition, the branch prediction method according to the present embodiment, as a specific configuration thereof, performs a first row selection process for selecting the branch prediction group with respect to the first branch instruction in the first period. One or more with respect to the first branch instruction in one step (eg, the step performed at T2 = -2 shown in FIGS. 5 and 6) and in the second period after the first period. A second step of performing the first column selection process for selecting the branch prediction information (for example, a step performed at T2 = -1 shown in FIGS. 5 and 6) and a third after the second period. First branch prediction that generates a branch prediction result for the first branch instruction based on the branch prediction information selected in the first column selection process for the first branch instruction during the period of It includes a third step of performing the result generation process (for example, the step performed at T2 = -1 shown in FIGS. 5 and 6).
At this time, in the second step (T2 = -1), the first column selection process (for example, reference numeral 210RA shown in FIGS. 5 and 6) and the second process after the first branch instruction are performed. With respect to the branch instruction of 2, the second row selection process for selecting the branch prediction group (for example, reference numeral 220CA shown in FIGS. 5 and 6) can be performed in parallel. Further, in the third step (T2 = -2), one or a plurality of the above regarding the first branch prediction result generation process (for example, reference numeral 210G shown in FIGS. 5 and 6) and the second branch instruction. The branch prediction group is selected for the second column selection process for selecting branch prediction information (for example, reference numeral 220RA shown in FIGS. 5 and 6) and the third branch instruction processed after the second branch instruction. The third row selection process (for example, reference numeral 230CA shown in FIGS. 5 and 6) can be processed in parallel.
Here, in the pipeline processing shown in FIGS. 5 and 6, the processing performed in the first period of T2 = -2 is performed in the first step, and the processing performed in the second period of T2 = -1 is performed in the second period. Step, the processing performed in the third period of T2 = 0 is performed in the third step, the processing performed in the fourth period of T2 = 1 is performed in the fourth step, and the processing performed in the fifth period of T2 = 2 is performed. The process can be referred to as the fifth step. In addition, each process (pattern history table row access, etc.) performed in each step can be referred to as each stage.
(About branch prediction procedure) First, the branch prediction procedure will be described with reference to FIGS. 2, 3, 6, and 7. In the processor equipped with the branch prediction device of the present embodiment, in this example, the branch prediction result generation 230G stage processing (branch prediction result generation 230G stage processing) is performed in the processing related to the branch prediction of the third branch instruction shown in FIGS. The procedure for generating the branch prediction result in "T2 = 2" (processing in the 5th step) is "T2 = 0" (3rd step), "T2 = 1" (4th step). , "T2 = 2" (fifth step) will be explained in this order.
First, as shown in FIG. 6, it is "T2 = 2" (fifth step) to fetch the branch instruction based on the branch prediction result generated by the branch prediction result generation process 230G in the T2 = 2 stage. Therefore, the processing related to branch prediction is started two cycles before fetching the branch instruction (T2 = 0, third step). At the start of this "T2 = 0" (third step), the first branch prediction result generation process and T2 = are the processes related to the branch prediction of the first branch instruction started at T2 = 2. -The second branch prediction result generation process has not been completed in the process related to the branch prediction of the second branch instruction started in 1.
<T2 = 0 (third step)> In the third period of T2 = 0 shown in FIG. 6, the branch predictor has the first register (C0) 11a, the third register (C2) 11c, and the fourth register (C3) constituting the shift register 11 shown in FIG. ) 11d, 5th register (C4) 11e, 6th register (C5) 11f The process of inputting the value that does not change in the next cycle (T2 = 1) to the row selection logic 21 and reading the branch information group from the pattern history table. (Step S101 shown in Fig. 7) <row selection process>.
Next, in the third period of T2 = 0 shown in FIG. 6, the branch predictor performs the next cycle (11a to 11h) in the shift register 11 (11a to 11h) of the extension-Folded-Index-register unit 10 shown in FIG. Calculate the value of T2 = 1) (step S102 shown in FIG. 7) <next cycle value calculation process>. The calculation of this value is performed using the branch prediction result generated by the branch prediction result generation process 210G of T2 = -2, which is the process related to the first branch instruction shown in FIG. "step 1". The branch prediction result corresponds to the output of the prediction result generation logic 30A shown in FIG.
Further, in the third period of T2 = 0 shown in FIG. 6, the branch predictor performs a process of using the calculated value (calculation result) as the input value of the shift register 11 in the next cycle (T2 = 1). Perform (step S103 shown in FIG. 7) <Next cycle value input process>.
In addition, in the third period of T2 = 0 shown in FIG. 6, the branch predictor inputs the calculated value (calculation result) as the input value of the shift register 11 in the next cycle (T2 = 1). Among the values, the values stored in the first register (C0) 11a, the second register (C1) 11b, and the eighth register (C7) 11h constituting the shift register 11 are input to the copy register 27. (Step S104 shown in Fig. 7) <Copy register value input processing>.
In this way, in the third period of T2 = 0 shown in FIG. 6, the branch predictor performs the stage processing (third row selection processing) of the row access 230CA of the pattern history table related to the third branch instruction. Do.
<T2 = 1 (4th step)> In the fourth period of T2 = 1 shown in FIG. 6, the branch predictor predicts two branches from the branch information group which is the output of the first pipeline register 23 based on the value of the copy register 27. The process of selecting information by the first column selection logic 24 is performed (step S105 shown in FIG. 7) <column selection first process (third column selection first process if limited to the third branch instruction)>.
Further, in the fourth period of T2 = 1 shown in FIG. 6, the branch prediction device receives the branch prediction result of the branch prediction result generation process 220G related to the second branch instruction (output of the prediction result generation logic 30A in FIG. 1). The branch prediction information of one value is selected by the second column selection logic 25 from each branch prediction information of the two values selected by the first column selection logic 24. (Step S106 shown in FIG. 7) <Column selection second process (third column selection second process if limited to the third branch instruction)> ... (Procedure 2). Here, since the delay of this part is not large, it is possible to process the operation of the next step ahead of schedule. The result obtained here is stored in the second pipeline register 26.
In this way, by the column selection first process and the column selection second process, in the fourth period of T2 = 1 shown in FIG. Stage processing (third column selection processing) is performed.
<T2 = 2 (5th step)> Next, in the fifth period of T2 = 2 shown in FIG. 6, the branch prediction device generates a branch prediction result for the third branch instruction based on the branch prediction result information stored in the second pipeline register 26. Generate a branch prediction result by 230G stage processing (third branch prediction result generation processing only for the third branch instruction) (step S108 shown in FIG. 7) <branch prediction result generation processing>.
Next, in the fifth period of T2 = 2 shown in FIG. 6, the branch prediction result information generated by the prediction result generation logic 30A is subjected to subsequent processing (further steps 1 and 2 in the next cycle). , The same processing <calculation of the value in the next cycle, processing such as selection of the second column in this cycle>), so the branch prediction device extends the branch prediction result information-Folded. Index Performs transmission processing to the register unit 10 and the second column selection logic 25 (step S109 shown in FIG. 7) <branch prediction result information transmission processing>.
The above paths (row selection process, column selection process, branch prediction result generation process) do not enter the critical path of the processor because each stage is reduced to a sufficiently simple task.
To summarize the above, in the third step, after the third row selection process, the third branch prediction result information generated by the first branch prediction result generation process is used as the basis for the third branch prediction result information. It is possible to perform a process of calculating in advance the value of the index information of the branch prediction information storage processing means to be processed in the fourth step in the fourth period after the period.
Further, in the third step, based on the calculated value of the index information, the value of the index information for the third column selection process to be processed in the fourth period is extracted, and a specific value of the index information is extracted. It is also possible to perform the process of holding in the column selection information temporary storage unit.
Further, in the third step, it is also possible to perform a process of holding the calculated value of the index information as the value of the index information for the fourth row selection process to be processed in the fourth period. it can.
On the other hand, in the fourth step, the second branch prediction result generation process for generating the second branch prediction result information generated for the second branch instruction and the third row selection process are performed respectively. A third column selection third that selects at least two branch prediction information based on any one of the branch prediction groups selected from the branch prediction groups and the value of the column selection information temporary storage unit. Based on the 1 process and the 2nd branch prediction result information generated in the 2nd branch prediction result generation process, each of the branch prediction information selected in the 3rd column selection 1st process Among them, a third column selection second process for selecting one branch can be included.
(About the update procedure) Next, the update procedure will be described with reference to FIG. FIG. 8 is an explanatory diagram for explaining the update procedure in the branch prediction device of the present embodiment.
First, when the branch instruction reaches the commit stage, the following processing exists. That is, it is determined whether or not the branch prediction is successful (step S111) <branch prediction success determination process>.
When the branch prediction is successful, the process of updating the 1-bit information (branch establishment / non-establishment information) indicating the establishment / non-establishment of the branch immediately before the entry indicated by the index value of the used pattern history table is performed (step S112). ) <Branch establishment availability information update processing>.
On the other hand, if the branch prediction fails, the next 2-bit value is recalculated by referring to the entry indicated by the index value of the used pattern history table (step S113) <recalculation process>.
With respect to the value after recalculation, it is determined whether or not the history bit and the establishment / non-establishment match (step S114) <history bit match determination process>. When the history bit and the establishment / non-establishment match, the value after recalculation is processed to use the matching value as the value of the new prediction bit. At this time, a process of writing a logic value opposite to the predicted bit to the history bit is performed (step S115) <predicted bit writing process>. If the history bit and the establishment / non-establishment do not match, the process of writing the execution result of the branch instruction to the history bit is performed (step S116) <execution result writing process>.
An effective pipeline making method can improve the branch prediction accuracy while making a pipeline.
As described above, according to the present embodiment, by performing each processing of row selection, column selection, and branch prediction result generation by pipeline processing, the processing speed related to access to the pattern history table is improved, and the branch prediction is performed. Processing can be performed at high speed.
Moreover, since the value of the extended-Folded-Index-register unit is directly input to the row selection logic of the pattern history table, the delay of the hash logic can be omitted. Further, the extended-Folded-Index-register unit, which is an example of the index information control means, has a configuration in which the output of the shift register is used as the input of the row selection logic, and the register value is directly input to the row selection logic. Since the change point of the register value is fixed, the pattern history table can be accessed in two stages without impairing the branch prediction accuracy.
Furthermore, the calculation of index information by the extension-Folded-Index-register unit as an index information control means is calculated in consideration of the execution path history information, so that the branch prediction accuracy is achieved without introducing complicated hash logic. Is improved.
Further, the branch prediction generation pipeline in which the index information control means performs the pipeline processing related to the branch prediction generation with respect to the branch prediction information of the branch prediction information storage processing means or the value of the index information for selecting the branch prediction group. In one period, the value of the index information in another period executed after the one period is calculated in advance, and each process required for each process in each period of the branch prediction generation pipeline is performed. Provides index information. Then, the first selection control means performs the first selection control process by row selection based on the value of the index information corresponding to the one period calculated by the index information control means 3. Further, the second selection control means is the first selection for the branch prediction of the same branch instruction based on the value of the index information corresponding to the other period calculated by the index information control means. The second selection control process is performed by column selection in the other period different from the one period in which the control process is performed. As a result, the index information can be advanced in the calculation process.
Further, since the delay in the branch prediction process does not enter the critical path of the processor, it is possible to provide a branch prediction device that can contribute to the improvement of the processing speed of the processor as a whole.
As described above, since there is no hash logic immediately before the branch prediction information storage processing means, the delay of branch prediction can be prevented, and the pipeline access control means has the first selection control process and the second selection control process. By dividing into stages and performing access processing to the branch prediction information storage processing means by pipeline processing, the processing speed in branch prediction can be increased, and the performance of the branch prediction device is improved.
Further, even if the number of bits of the index information is increased in order to improve the prediction accuracy, the processing speed is not delayed by performing the pipeline processing in two stages of row selection and column selection.
[Second Embodiment] Next, a second embodiment according to the present invention will be described with reference to FIG. In the following, the description of substantially the same configuration of the first embodiment will be omitted, and only the different parts will be described. FIG. 9 is a block diagram showing an example of a second embodiment in which the branch prediction device of the present invention is applied to the hybrid branch prediction device.
The second embodiment discloses an example in which the "branch prediction device" of the first embodiment described above is applied to a "hybrid branch prediction device". The branch prediction device shown in FIG. 2 is used as a part of the hybrid branch prediction device as shown in FIG.
The hybrid branch prediction device according to the present embodiment has, as its basic configuration, branch prediction information regarding a branch instruction (information indicating whether it is predicted to branch or not to branch) and whether or not the immediately preceding branch is established. The branch prediction information storage processing means includes a branch prediction information storage processing means that stores each branch prediction group that groups the branch establishment / non-establishment information indicating (establishment / non-establishment) and stores the branch prediction information. On the other hand, it is based on the pipelined branch history information storage processing unit (for example, reference numeral 20-1 shown in FIG. 10) that can be accessed by pipeline processing, and the branch prediction information or the index information for selecting the branch prediction group. A first index information control unit (for example, reference numeral 10B-1 shown in FIG. 10) for controlling access by the pipeline processing and performing processing at the fetch stage of the processor pipeline, and a processor that controls the index information. It includes a second index information control unit (for example, reference numeral 10A-1 shown in FIG. 10) for processing at the commit stage of the pipe line.
The pipelined branch prediction information storage processing unit (for example, reference numeral 20-1 shown in FIG. 10) is a first selection that controls selection processing of at least one branch prediction group from each branch prediction group. A second control means (for example, reference numeral 21 shown in FIG. 10) and a second control means for selecting and processing one or a plurality of the branch prediction information from the branch prediction group selected by the first selection control means. A branch prediction result is generated based on the selection control means (for example, a configuration consisting of reference numerals 23, 24, 25, 26, 27 shown in FIG. 10) and the branch prediction information selected by the second selection control means. Includes a prediction result generating means to be processed (eg, reference numeral 30B shown in FIG. 10).
The first index information control unit (for example, reference numeral 10B-1 shown in FIG. 10) has a first selection control process by the first selection control means and a second selection control by the second selection control means. It is preferable to control the pipeline processing of the processing and the processing including the prediction result generation processing by the prediction result generation means.
As shown in FIG. 9, the hybrid branch predictor 300 of the present embodiment has a commit stage update extension, which is an example of a second index information control unit used for rewind destination storage, as a specific configuration thereof. Folded-Index-Register Units 10A-1, 10A-2, 10A-3 and Fetch Stage Update Extension-Folded-Index-Register Unit 10B, which is an example of the first index information control unit used for speculative execution. 1, 10B-2, 10B-3, and pipelined pattern history table 20-1, 20-2, 20 which is an example of the pipelined branch prediction information storage processing unit having the same configuration as the configuration shown in Fig. 2. -3, the instruction counter 40, the pattern history table 50 which is an example of the branch prediction information storage processing unit, and the pipelined pattern history tables 20-1, 20-2, 20-3 and the pattern history table 50. It is configured to include a prediction result generation logic 30B, which is an example of a prediction result generation means for generating a prediction result based on each output.
Here, in the present embodiment, the pipelined pipeline pattern history tables 20-1, 20-2, and 20-3 shown in FIG. 9 are shown in FIG. 2 of the first embodiment, respectively. Corresponds to the pipelined pattern history table 20. Therefore, in more detail, the configuration is as shown in FIG.
In addition, the commit stage update extension-Folded-Index-register unit 10A-1, 10A-2, and 10A-3 for saving the rewind destination shown in FIG. 9 is replaced with the extension-Folded-Index-register unit 10 shown in FIG. Correspond. Furthermore, the fetch stage update extension-Folded-Index-register units 10B-1, 10B-2, and 10B-3 for speculative updates shown in FIG. 9 correspond to the extension-Folded-Index-register unit 10 shown in FIG. To do.
The prediction result generation logic 30B is a majority decision circuit as a majority decision processing unit that determines any one output by majority decision based on the outputs of the pipelined pattern history tables 20-2 and 20-3 and the pattern history table 50. A selector circuit 33 as a branch prediction result selection unit that selects one of 32, the output of this majority circuit 32, the output of the pattern history table 50, and each output of the pipelined pattern history table 20-1. And are configured to include.
Here, the delays of the 10B-1 20-1 33, 10B-2 20-2 32 33, and 10B-3 20-3 32 33 paths in FIG. 9 are also about the same. Further, the instruction counter 40 of one input serves as the input of the pattern history table 50 as it is. Here, the pattern history table 50 is smaller and has a shorter delay than other pattern history tables, and since this delay originally does not include a delay such as a hash function, the delay of this part enters the critical path of the processor. There is no such thing.
"Extension-Folded-Index-Register unit" is a commit stage update extension for rewind destination storage-Folded-Index-register unit 10A-1, 10A-2, 10A-3, and a fetch stage update extension for speculative execution. FoldedIndex Register units 10B-1, 10B-2, and 10B-3 are available in two types.
Fetch stage update extension for speculative execution-Folded-Index-Register units 10B-1, 10B-2, 10B-3 are updated using the instruction cache index used in the fetch stage and the output of the prediction result generation logic.
Commit stage update extension for saving rewind destination-Folded-Index-Register units 10A-1, 10A-2, 10A-3 use the instruction cache index used at the time of fetch and the result at the execution stage at the commit stage. Update. If the execution result in the execution stage is different from the predicted result, the pipeline is rewound in the commit stage.
At the time of "rewind", the commit stage update extension for saving the rewind destination-Folded-Index-register units 10A-1, 10A-2, 10A-3 are the commit stage update extension for saving the rewind destination-Folded- Index-Register unit 10A-1, 10A-2, 10A-3, fetch stage update extension for each speculative execution-Folded-Index-Register unit 10B-1, 10B-2, 10B-3 Copy each to. This guarantees the correctness of the branch prediction.
Commit stage update extension-Folded-Index-register unit 10A-1, 10A-2, 10A-3, fetch stage update extension-Folded-Index-register unit 10B-1, 10B-2, 10B-3 have different lengths. Hash the branch history of and generate the index information of the pipelined pattern history tables 20-1, 20-2, and 20-3.
For example, if the pipelined pipelined pattern history tables 20-1, 20-2, and 20-3 each have a capacity of 512 bytes, the commit stage update extension-Folded-Index-register unit 10A-1, Fetch stage update extension-Folded-Index-Register unit 10B-1 utilizes the branch history information for the previous 4 instructions and the lower 2 bits of the branch instruction cache index as hash input.
In the commit stage update extension-Folded-Index-register unit 10A-2 and the fetch stage update extension-Folded-Index-register unit 10B-2, the branch history information for the previous 12 instructions and the lower 2 bits of the branch instruction cache index are displayed. Use it as a hash input.
In the commit stage update extension-Folded-Index-register unit 10A-3 and the fetch stage update extension-Folded-Index-register unit 10B-3, the branch history information for the previous 24 instructions and the lower 2 bits of the branch instruction cache index are displayed. Use it as a hash input.
Each pipelined pattern history table unit 20-1, 20-2, 20-3, 50 has a total of 2 bits, which is 1-bit branch prediction information and 1-bit information indicating the establishment / non-establishment of the immediately preceding branch. To store.
The branch prediction information read from the pipelined pattern history table units 20-1, 20-2, 20-3 and the pattern history table 50 is used as an input for the majority decision circuit 32 and the selector circuit 33.
Here, the fetch stage update extension-Folded-Index-register unit 10B-1 can also be referred to as a "first index information control unit". The "first index information control unit" is based on the first selection control process by the first selection control means, the second selection control process by the second selection control means, and the prediction result generation means. It is possible to control the pipeline processing of the processing including the prediction result generation processing.
Further, the "first index information control unit" is used for speculative execution in the fetch stage and controls based on the instruction cache index used in the fetch stage and the output of the prediction result generation means. be able to. Further, each "first index information control unit" hashes branch histories of different lengths, and each index information of each branch prediction information of each of the pipelined branch prediction information storage units is used. Can be generated. In addition, each "first index information control unit" can be controlled based on branch history information for different numbers of instructions and branch instruction cache index information.
On the other hand, the commit stage update extension-Folded-Index-register unit 10A-1 can also be called a "second index information control unit". This "second index information control unit" controls at the commit stage based on the instruction cache index used for the fetch stage and the result at the execution stage, and the branch prediction based on the branch prediction information is performed. It can also be used for the rewind destination save process at the commit stage when it fails and the processor pipeline is rewound.
Further, in the "second index information control unit", the execution result and the prediction result in the execution stage are different, and when the rewind processing of the processor pipeline processing is performed in the commit stage, the index information is displayed. The process of copying to the first pipeline control unit can be performed. Further, each "second index information control unit" hashes branch histories of different lengths, and each index information of each branch prediction information of each of the pipelined branch prediction information storage units is used. Can be generated.
(About the update procedure) Here, regarding the update procedure, when the branch instruction reaches the commit stage, the following processing exists. That is, when the branch prediction is successful, the 1-bit information (branch establishment / non-establishment information) indicating the establishment / non-establishment of the branch immediately before the entry indicated by the index value of the used pattern history table is updated. Information update process>.
On the other hand, if the branch prediction fails, the next 2-bit value is recalculated by referring to the entry indicated by the index value in the pattern history table used <recalculation processing>.
For the value after recalculation, if the history bit and the establishment / non-establishment match, the matching value is used as the value of the new prediction bit. At this time, the logic value opposite to the predicted bit is written to the history bit <predicted bit writing process>. If the history bit and the establishment / non-establishment do not match, the execution result of the branch instruction is written to the history bit <execution result writing process>.
The values of the extension for speculative execution-Folded-Index-register unit 10B-1, 10B-2, 10B-3 are the extension for rewind destination storage-Folded-Index-register unit 10A-1, 10A-2, 10A. Overwrite processing is performed with a value of 3.
As described above, according to the present embodiment, it can be applied to a hybrid branch prediction device using a plurality of different pattern history tables while exhibiting the same effects as those of the first embodiment.
Here, in the above-described embodiment, the prediction result generation logic may be a simple majority decision circuit, a simple select circuit, or the like. Further, in the above embodiment, a single pattern history table may be used instead of the plurality of pattern history tables.
The other configurations, other steps, and their actions and effects are the same as in the case of the first embodiment described above.
[Third Embodiment] Next, a third embodiment according to the present invention will be described with reference to FIG. Hereinafter, the description of substantially the same configuration of the first embodiment will be omitted, and only the different parts will be described. FIG. 11 is a block diagram showing an example of a third embodiment in which the branch prediction device and the hybrid branch prediction device of the present invention are applied to a processor.
In the present embodiment, an example of a processor equipped with the branch prediction device of the first embodiment described above or the hybrid branch prediction device of the second embodiment described above is disclosed.
As a basic configuration, the processor according to the present embodiment has a plurality of processor pipeline processing devices (for example, reference numerals 411, 412, 413 shown in FIG. 11) that execute processor pipeline processing that sequentially shifts each stage based on an instruction. , 414, 415, 416, 417, 418, etc.) and the branch prediction device of the first embodiment described above or the second embodiment described above for predicting the branch of a branch instruction in the processor pipeline processing. It includes a hybrid branch prediction device of the above and a control device (for example, reference numeral 432 shown in FIG. 11) that controls each device.
The processor 400 of the present embodiment is a pipeline processor that performs pipeline processing, and as shown in FIG. 11, as a specific configuration thereof, an instruction fetch processing unit 411 that performs instruction fetch processing for fetching instructions from the instruction cache. , The decoding processing unit 412 that decodes the instruction fetched by the instruction fetch processing unit 411, and the operand read processing unit 413 that performs processing to read the register value of the register operand (accesses the required operand from the register). The execution processing unit (calculation) that executes the instruction (generates the result or memory address by combining the operands) based on the decoding result of the decoding processing unit 412 and the register value read by the operand read processing unit 413. Processing unit) 414 and execution processing to read the memory value corresponding to the address calculated by processing unit 414 from the data cache (access the memory to obtain the data operand as necessary) Memory access processing unit 415 A write-back processing unit 416 that performs write-back processing, a commit processing unit 417 that performs commit processing, a retirement processing unit 418 that performs retirement processing, and a branch prediction device or hybrid branch prediction device that is a characteristic configuration of the present invention. The branch prediction processing unit 421 and the above are included.
Further, as shown in FIG. 11, the processor 400 includes an address conversion processing unit 422 that performs address conversion processing, and a storage unit 431 that includes each data storage unit required for processing each part and each processing unit required for each processing. , A control unit 432 that controls each of these parts that perform pipeline processing in the processor, a clock generation processing unit 433 that generates each clock required for processing each part, and an external device that includes various interface functions with other devices. It is configured to include an interface unit 434 and.
The address translation processing unit 422 is performed prior to the instruction fetch processing or the memory access processing.
The execution processing unit 414 calculates the execution address in the case of a load / store instruction. In the case of a branch instruction, the branch destination address is calculated. The execution processing unit 414 includes one or more ALUs (Arithmetic and Logic Units), one or more FPUs (Floating Point Units), and the like.
As described above, according to the present embodiment, a processor capable of exhibiting the same effects as those of the first embodiment or the second embodiment can be configured, and the access processing to the pattern history table is branched. By performing pipeline processing while maintaining the prediction accuracy, branch prediction can be performed at high speed, and a processor capable of increasing the processing speed can be provided.
The superscalar processor may include an Out-of-order execution control processing unit (not shown) that controls out-of-order execution and the like. The out-of-order execution control processing unit has a function of executing a part of the processor pipeline stage, such as the "execution" stage, regardless of the order of instructions.
The other configurations, other steps, and their actions and effects are the same as in the above-described embodiment.
(Various variants) Further, the apparatus and method according to the present invention have been described according to some specific embodiments thereof, but with respect to the embodiments described in the main text of the present invention without departing from the gist and scope of the present invention. Various modifications are possible. For example, the number, position, shape, etc. of the constituent members are not limited to the above-described embodiment, and the number, position, shape, etc. suitable for carrying out the present invention can be used. That is, in the above embodiment, there are three pipelined pattern history tables, one pattern history table, three commit stage update extensions-Folded-Index-register units, and three fetch stage update extensions-Folded-Index-registers. Although the case where the number of units is three is shown, the present invention does not limit the number of these units.
Further, in the above-described embodiment, in the pipeline of access to the pattern history table, the pattern history table row access process (A stage), the pattern history table column access process (B stage), and the branch prediction result generation process (C stage). However, this is not limited to this, even if it is a pipeline access method that uses pattern history table column access processing (A stage), pattern history table row access processing (B stage), and branch prediction result generation processing (C stage). Good.
The pipeline structure in branch prediction is not limited to the three-stage pipeline structure shown in FIGS. 5 and 6, a two-stage pipeline structure as shown in FIG. 12 and a four-stage pipeline structure as shown in FIG. It may be a structure.
In the pipeline structure shown in FIG. 12, the first branch instruction 510 and the second branch instruction 520 are for processing the stage for row selection (for example, reference numeral 520CA) and for performing column selection and prediction result generation, respectively. It has a total of two stages of processing (eg, reference numeral 520RA).
Further, in the pipeline structure shown in FIG. 13, the first branch instruction 610, the second branch instruction 620, the third branch instruction 630, and the fourth branch instruction 640 each perform row selection stage processing ( For example, code 640CA), processing of the stage that performs the first column selection process (for example, code 640RAI), processing of the stage that performs the second column selection process (for example, code 640RAII), and processing of the stage that generates the prediction result (for example). It has a total of 2 stages with a code of 640G).
As described above, the method of pipeline access processing for the pattern history table is not limited to the pipeline access processing of three stages, and may be a pipeline structure of three or more stages.
Furthermore, not only when a pipeline access control means (first pipeline access control means) that pipelines access to the pattern history table and processes it is provided, but also as a pipeline access method, the first row access of the pattern history table is performed. Processing, pattern history table 2nd row access processing, pattern history table 1st column access processing, pattern history table 2nd column access processing, 1st branch prediction result generation processing, 2nd branch prediction result generation processing, etc. Super pipeline method (second pipeline access processing means) may be used.
Furthermore, the pipeline access method for the pattern history table is not limited to the single scalar method, but is a superscalar method (third pipeline access) including parallel processing of multiple, for example, two ways (processing in which multiple pipeline processing operates at the same time). Processing means) may be used. Specifically, the pattern history table 1st row access processing and the pattern history table 2nd row access processing are processed in the A stage, and the pattern history table 1st column access processing and the pattern history table 2nd column access processing are processed in the B stage. You may do so.
In addition, an independent clock may be prepared for each stage of the pipeline access processing and configured by the wave pipeline method (fourth pipeline access processing).
Further, the pattern history table, which is an example of the branch prediction information storage processing means, is not limited to the one stored as the pattern history information in which the branch prediction information and the branch establishment / non-establishment information indicating whether or not the immediately preceding branch is established are associated with each other. , It may be a table that stores various other information.
Although an example in which the "branch prediction device" of the present invention is applied to a hybrid branch prediction device similar to the "2bc-gskew format" has been described, it may be applied to various hybrid branch prediction devices of other types. For example, it can be applied to all those that make branch predictions of 3 or more (for example, 4, 5, etc.) and use their majority vote.
Further, the branch prediction method of the branch prediction information of the pipelined pattern history table unit having the characteristic configuration of the present invention may be various tables embodying various prediction methods.
Further, in the hybrid branch prediction device, in addition to the branch prediction device capable of pipeline processing, which is a characteristic configuration of the present invention, various branch prediction devices may be combined to make prediction by majority vote. Further, each branch prediction device that can be pipelined in the hybrid branch prediction device may be configured to perform a plurality of types of branch prediction, and the final prediction result may be determined by a majority vote.
Further, in the above-described embodiment, the "pipeline access control means" shows an example in which the "pipeline access control means" performs the pipeline process for the access of the read process for reading the branch prediction information from the pattern history table. , It may be configured to perform pipeline processing for access of writing processing.
In addition, the "extended-Folded-Index-register unit" is configured to update the index information based on the branch history information and the execution path history information, but in addition to this, various other history information is added. The register and the XOR circuit may be expanded so that the update process is performed in consideration of the update process.
In addition, in the second embodiment, there are two commit stage update extensions-Folded-Index-register units and fetch stage update extensions-Folded-Index-register units for one pipelined pattern history table unit. Although the configuration uses one "extension-Folded-Index-register unit", a configuration using three or more "extension-Folded-Index-register units" having various other functions or common functions may be used.
Furthermore, when selecting the pattern history table in two stages, one branch prediction group is selected by row selection and branch prediction information is selected by column selection, but the configuration is not limited to this, and column selection is not limited to this. One branch prediction group may be selected by, and branch prediction information may be selected by row selection.
Further, in the process of reading the information of the pattern history table, which is an example of the branch prediction information storage processing means, the row selection is not limited to the case where the branch prediction group is selected by selecting one row, and a plurality of rows are simultaneously selected. It may be the case that the branch prediction group is selected by selecting.
In addition, when a branch prediction group is selected by simultaneously selecting multiple rows, the configuration is such that a plurality of branch prediction information is read from the branch prediction group by selecting one column in the column selection. You may.
In the above-described embodiment, the branch prediction device is mounted in one processor, but the configuration is such that the branch prediction device is mounted on the multi-processor and the multi-processor configuration is composed of a plurality of processors equipped with the branch prediction device. There may be.
Further, the processor equipped with the "branch prediction device" and the "hybrid branch prediction device" of the above-described embodiment is not limited to a pipeline processor capable of normal pipeline processing, but a processor capable of superscala processing. It may be a processor capable of super pipeline processing.
Further, the processor may be either a RISC type or a CISC type or a CISC type in which a CISC instruction is divided into a plurality of RISC instructions and executed inside the processor. Further, "processor" is a general term that includes a multiprocessor, a dual processor in which a plurality of CPUs are integrated on one chip, and the like, in addition to a normal processor. Therefore, the "processor" including the "branch prediction device" and the "hybrid branch prediction device" of the present embodiment includes a multiprocessor including the processor, a multiprocessor including the processor and various other processors, and the processor. Includes dual processors including.
At this time, the multiprocessor may be either a centralized shared memory system or a distributed shared memory system.
The processor is a hard-wired system that realizes some of the functions of the control unit such as decoding processing (interpretation of instructions) by hardware, and a microcode system that realizes some of the functions of the control unit by software. It may be either.
Further, the processor may be a general-purpose processor or a dedicated processor for various processes.
Further, in the communication structure between the processor including the branch prediction device and the other device, the type of the interface formed on either one or both may be any interface developed in the future.
Further, the steps shown in each procedure include not only processes performed in chronological order according to the described procedure, but also processes performed in parallel or individually, although not necessarily processed in chronological order. You can also change the order in which the steps are performed. In addition, the specific steps described can be removed, added, or rearranged as combined steps, if desired.
Further, the functions of each means, each function, each stage, and each step of the device may be achieved by dedicated hardware (for example, a dedicated semiconductor circuit, etc.), or some of them are software-like. May be processed. That is, some of all the functions may be processed by hardware, and other functions may be processed by software. In the case of dedicated hardware, each part may be formed by an integrated circuit such as an LSI. These may be individually integrated into one chip, or may be integrated into one chip so as to include a part or all of them. Further, the LSI may include other functional blocks such as various image processing circuits. Furthermore, the method of integrated circuit formation is not limited to LSI, and if integrated circuit formation technology that replaces LSI appears due to advances in semiconductor technology or another technology derived from it, it is natural that functional blocks will be integrated using that technology. It may be converted.
Furthermore, it is easy to understand that the method of performing pipeline processing for accessing the pattern history table is not necessarily limited to a substantive device, and also functions as such a method. Therefore, the invention relating to the method is not necessarily limited to a substantive device, and there is no difference in that the method is also effective. In this case, a branch predictor, a processor, and the like can be included as an example for realizing the method.
By the way, such a branch prediction device may exist independently or may be used in a state of being incorporated in a certain device (for example, a processor), and the idea of the invention is not limited to this. It includes the aspect of. Therefore, it can be changed as appropriate, such as software or hardware. When the software of the branch prediction device is used as an example of embodying the idea of the invention, it must be said that the software naturally exists and is used on the storage medium that stores the software.
Further, in this case, a part may be software and a part may be realized by hardware, and a part corresponding to some software is stored in a storage medium as needed. It may be in a form that can be read as appropriate. Further, in the above description, the operation content of each step, each process, each stage, and the components of each part may be programmed and executed by a branch prediction device, a hybrid branch prediction device, or a computer.
In addition, examples of electronic devices equipped with the above-mentioned processors and the like include not only personal computers but also various servers, EWSs (engineering workstations), medium-sized computers, mainframes, and the like. In addition to the above examples, information terminals include portable information terminals, various mobile terminals, PDAs, mobile phones, wearable information terminals, various (portable, etc.) TVs, DVD recorders, various audio equipment and their remote controls, and various types. Examples include home appliances equipped with information and communication functions, game devices having network functions, and the like.
Further, each of the above embodiments includes various steps, and various inventions can be extracted by an appropriate combination of a plurality of disclosed constituent requirements. That is, it also includes an example of each of the above-described embodiments, or a combination of any of them and any of the modified examples. In this case, even if not particularly described in the present embodiment, the action and effect that are obvious from each configuration disclosed in each embodiment and their modified examples may be naturally included as the action and effect of the embodiment. it can. On the contrary, the configuration capable of exerting all the functions and effects described in the present embodiment is not always an essential constituent requirement of the essential feature portion of the present invention. Further, an embodiment having a configuration in which some constituent requirements are deleted from all the constituent requirements shown in the embodiment and a technical scope based on the configuration can also be an invention.
And, in order to facilitate understanding of the present invention, the description so far including each embodiment and examples thereof is a disclosure of an example of various embodiments of the present invention, that is, all of them are the present invention. It merely shows an example of embodiment in carrying out the invention, is an example, is not a limitation, and can be appropriately modified and / or changed. The present invention can be implemented in various forms based on the technical idea or its main features, and the technical scope of the present invention should not be construed in a limited manner by each embodiment and its variations. It is something that does not become. Therefore, each element disclosed above is intended to include all design changes and equivalents that fall within the technical scope of the present invention.
The present invention is applicable to computers, semiconductors, manufacturing industries that manufacture communication devices, and other similar industries, and more specifically, to applications such as pipelined processors.
<figref num="1">It is a block diagram which shows an example of the structure of the branch prediction apparatus by 1st Embodiment of this invention.</figref><figref num="2">It is a block diagram which shows an example of the structure of the branch prediction apparatus by 1st Embodiment of this invention.</figref><figref num="3">It is a block diagram which shows an example of the internal structure of the expansion-Folded-Index-register of the branch prediction apparatus of FIG.</figref><figref num="4">It is explanatory drawing for demonstrating the pipeline structure of the processor including the branch prediction apparatus of FIG.</figref><figref num="5">It is explanatory drawing for demonstrating the pipeline structure concerning the access to the pattern history table in the branch prediction apparatus of FIG.</figref><figref num="6">It is explanatory drawing for demonstrating the pipeline structure concerning the access to the pattern history table in the branch prediction apparatus of FIG.</figref><figref num="7">It is explanatory drawing for demonstrating the operation process (processing procedure) of the pipeline processing concerning access to the pattern history table in the branch prediction apparatus by 1st Embodiment of this invention.</figref><figref num="8">It is explanatory drawing for demonstrating the update procedure in the branch prediction apparatus according to 1st Embodiment of this invention.</figref><figref num="9">It is a block diagram which shows an example of the whole structure of the branch prediction apparatus (hybrid branch prediction unit) by the 2nd Embodiment of this invention.</figref><figref num="10">It is a block diagram which shows an example of the detailed structure of the branch prediction apparatus of FIG.</figref><figref num="11">It is a block diagram which shows an example of the whole structure of the processor by 3rd Embodiment of this invention.</figref><figref num="12">It is explanatory drawing for demonstrating the pipeline structure concerning the access to the pattern history table in the branch prediction apparatus by another embodiment of this invention.</figref><figref num="13">It is explanatory drawing for demonstrating the pipeline structure concerning the access to the pattern history table in the branch prediction apparatus by another embodiment of this invention.</figref><figref num="14">It is explanatory drawing for demonstrating the processing of the comparative example at the time of not performing the pipeline processing in a branch prediction apparatus.</figref><figref num="15">It is a block diagram which shows an example of the structure of the 1st related technology of a branch prediction apparatus.</figref>
Code description
1 Branch predictor 2 Pipeline access control means 3 Index information control means 4 First selection control means 5 Second selection control means 5a First column selection means 5b Second column selection method 6 Branch prediction information storage processing means 7 Prediction result generation means 10 Extended-Folded-Index-Register unit 11 Shift register section 12 Logic circuit unit 13 Branch history register 14 Execution path history register 15 Exclusive OR circuit section 20 Pipelined pattern history table unit (Pipeline branch history information storage processing unit) 21 Line selection logic part (line selection means) 22 Pattern history table 23 First pipeline register (branch prediction group information temporary storage unit) 24 First column selection logic (first column selection logic circuit section) 25 Second column selection logic 26 Second pipeline register 27 Copy register (temporary storage of column selection information) 30A Prediction result generation logic 300 Hybrid branch predictor 10A-1, 10A-2, 10A-3 Commit Stage Update Extension-Folded- Index Register unit (first index control unit) 10B-1, 10B-2, 10B-3 Fetch Stage Update Extension-Folded- Index Register unit (second index control unit) 30B Prediction result generation logic part 32 Majority circuit 33 Selector circuit 400 processors 421 Branch prediction processing unit
15 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15
Every citation, both waysCites: the store holds 8 of 9
| Document | Relation | Office |
|---|---|---|
| JP10040104A | Cites | Japan |
| JP2003005956A | Cites | Japan |
| WO2004068337A1 | Cites | World Intellectual Property Organization (WIPO) |
| JP2008217687A | Cites | Japan |
| JP2010509680A | Cites | Japan |
| JP2001521241A | Cites | Japan |
| JP2001527233A | Cites | Japan |
| WO2006028555A2 | Cites | World Intellectual Property Organization (WIPO) |
| Andre Seznec, Stephaen Felix, Venkata Krishnan, Yiannakis Sazeides,Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor,Proceedings of 29th Annual International Symposium on Computer Architecture,IEEE,2002年,Pages:295-306 | Non-patent | – |
| 石井康雄,平木敬,実行パス履歴情報を利用した分岐予測方法,情報処理学会論文誌,日本,社団法人情報処理学会,2006年 3月15日,Vol:47,No:SIG3(ACS13),Pages:58-72 | Non-patent | – |
| Quinn Jacobson, Eric Rotenberg, James E. Smith,Path-Based Next Trace Prediction,Proceedings of Thrtieth Annual IEE/ACM International Symposium on Microarchitecture,IEEE,1997年,Pages:14-23 | Non-patent | – |
4 members in 2 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 2007199074 | Japan | A | |
| JP20070199074 | – | – | – |
Members4
| Document | Office | Kind | |
|---|---|---|---|
| US2009037709A1 | United States of America | A1 | |
| JP2009037302A | Japan | A | |
| JP5145809B2This record | Japan | B2 | |
| US8892852B2 | United States of America | B2 |
13 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Cancellation because of no payment of annual feesLAPS | LAPS | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Decision of grant or rejection writtenTRDD | TRDD | |
| Request for written amendment filedJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Request for written amendment filedJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Report on retrievalJAPANESE INTERMEDIATE CODE: A971007A977 | A977 | |
| Written request for application examinationJAPANESE INTERMEDIATE CODE: A621A621 | A621 |
Numbers
- Publication
- 5145809
- Publication, DOCDB
- 5145809
- Publication, EPODOC
- JP5145809B
- Application
- 199074
- Application, DOCDB
- 2007199074
- Application, EPODOC
- JP20070199074
Titles2
- Japanese
- 分岐予測装置、ハイブリッド分岐予測装置、プロセッサ、分岐予測方法、及び分岐予測制御プログラム
- English
- Branch predictor, hybrid branch predictor, processor, branch prediction method, and branch prediction control program
Classification
- CPC, 2
- G06F9/3848
- G06F9/3844
- IPC, 1
- G06F9 38
