Clock domain check method, clock domain check program, and recording medium

The present invention relates to a CDC (clock-domain-crossing) technique that enables checking of a synchronization circuit in asynchronous transfer of a clock.

In Soc (system on chip), there are signals that span a huge number of clock domains on one chip. If the CDC (clock-domain-crossing) check is inadequate, there is a risk of malfunction due to glitch (spike voltage when switching input data) or an accident due to through current. Therefore, the CDC check is important. In the CDC check, the clock signal is propagated to the register based on the information showing the synchronous and asynchronous relationship of the clock signal, the register transfer point where the clock is asynchronous is found, and the circuit involved in the transfer is desired. It is checked whether or not it is a synchronization circuit. Then, error analysis is performed based on the check result.

In asynchronous transfer, the metastable state of the latch circuit generated by the asynchronous input signal is a danger zone surrounded by the setup time and hold time based on the rising or falling edge of the clock specified in the latch circuit. Will be done. If the setup time or hold time exceeds a certain period of time, the output signal becomes unstable. This condition is called "metas table" and causes system malfunction. As a measure against metastable, a circuit configuration that does not cause any trouble even if metastable occurs is adopted (see, for example, Patent Document 1).

Further, in a logic simulator that considers timing errors that occur in an asynchronous circuit, a technique that suppresses a large number of pseudo errors that occur in timing checks is known (for example, Patent Document 2). Here, the terminal of a specific cell and the predetermined time are specified in the timing error constraint specification information, and the logic simulator detects the terminal of the specific cell within the predetermined time specified in the timing error constraint specification information. The violation of the tolerance of the constraint is invalidated and the error message is not output.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 7-311735</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 2004-30186</text></patcit>

<p> According to the conventional CDC (clock-domain-crossing) check method, for example, when checking a Soc with a 10M gate scale, as many as 1M errors may be output. When the inventor of the present application examined this enormous error, it was found that even if the circuit itself violates the synchronous circuit, in most cases, the asynchronous transfer is not hindered due to the chip specifications. The circuit itself violates the synchronous circuit, but if it does not interfere with asynchronous transfer due to the chip specifications, it is regarded as a pseudo error. However, it is difficult to find the true error from the above 1M errors, and it takes a long time to analyze the error.</p><p> An object of the present invention is to provide a technique for reducing pseudo-errors.</p><p> The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.</p>

<p> A typical invention disclosed in the present application will be briefly described as follows.</p><p> That is, a stationary signal defined as a signal whose logical value does not change in asynchronous transfer is propagated to the check target circuit. Extract different combinations of asynchronous transfers between the transmitter register and the receiver register. From the extracted asynchronous transfer combination, the circuit to be checked is extracted by backtracing toward the transmitting side for each receiving side register and searching for the circuit to the transmitting side register and the transmitting side register and the stationary signal. However, the circuit for synchronizing a plurality of signals is excluded from the circuits to be checked. A stationary signal is propagated to the circuit to be checked for each combination of all combinations of the logical value "1" and the logical value "0" of the stationary signal. In the combination of the logical values of the propagated stationary signals, it is checked from the connection relationship whether or not there is one asynchronous transmitter register to which the signal change logically reaches. Based on this check result, it is determined whether or not the configuration of the circuit involved in asynchronous transfer is appropriate as a synchronization circuit for single signal transfer. As a result, it is possible to reduce pseudo errors by determining whether or not the configuration of the circuit involved in asynchronous transfer is appropriate.</p>

<p> A brief description of the effects obtained by representative of the inventions disclosed in the present application is as follows.</p><p> That is, it is possible to provide a technique for reducing pseudo errors.</p>

1. Typical embodiment First, a typical embodiment of the invention disclosed in the present application will be outlined. Reference numerals in the drawings referenced in parentheses in the schematic description of a typical embodiment merely exemplify those included in the concept of the component to which it is attached.

[1] In the clock domain check method according to the typical embodiment of the present invention, the following first to sixth steps are executed by the central processing unit (31).

That is, in the first step, a stationary signal defined as a signal whose logical value does not change in asynchronous transfer is propagated to the check target circuit (103). In the second step, different asynchronous transfer combinations are extracted between the transmitting side register and the receiving side register (104). In the third step, the circuit and the steady-state signal from the combination of asynchronous transfers extracted in the second step to the transmitting side register and the transmitting side register by back tracing toward the transmitting side for each receiving side register and the stationary signal. The circuit to be checked is extracted by searching for, and the circuit for synchronizing multiple signals is excluded from the circuit to be checked (106,107,112). In the fourth step, the stationary signal is propagated to the circuit to be checked for each combination of the logical value 1 and the logical value 0 of the stationary signal (1062). In the fifth step, in the combination of the logical values of the stationary signals propagated in the fourth step, it is checked from the connection relationship whether or not there is one asynchronous transmitter register to which the signal change logically reaches. (1064,1065). In the sixth step, based on the check result in the fifth step, it is determined whether or not the configuration of the circuit involved in asynchronous transfer is appropriate as a synchronization circuit for single signal transfer (110). According to the above configuration, it is determined whether or not the configuration of the circuit related to the asynchronous transfer is appropriate, and an error (pseudo) when the operation of the chip is not affected even if the synchronization circuit is violated. Error) is hard to detect, distinguishing it from the true error. This achieves a reduction in pseudo-errors.

[2] In addition, instead of the fourth step, the circuit to be checked extracted in the third step is used.<u style="single">Binary building diagram</u>Move to the above<u style="single">Binary building diagram</u>Is given a logical value "1" and a logical value "0", and the above<u style="single">Binary building diagram</u>And instead of the 5th step above,<u style="single">Binary building diagram</u>It is also possible to check whether or not there is one asynchronous sender register from the remaining variables of.

[3] In the above [1] and [2], the stationary signal is set to a fixed value of a logical value "0" or a logical value "1" when another signal that performs asynchronous migration changes in the asynchronous transfer. It is assumed that the logical value does not change.

[4] From another viewpoint, the clock domain check program checks the synchronization circuit in asynchronous transfer by causing the computer to execute the following first to sixth steps.

That is, in the first procedure, a stationary signal defined as a signal whose logical value does not change in asynchronous transfer is propagated to the circuit to be checked (103). In the second procedure, different asynchronous transfer combinations are extracted between the transmitting side register and the receiving side register (104). In the third procedure, the circuit and the steady-state signal from the combination of asynchronous transfers extracted in the second step to the transmitting side register and the transmitting side register by back tracing toward the transmitting side for each receiving side register and the stationary signal. The circuit to be checked is extracted by searching for, and the circuit for synchronizing multiple signals is excluded from the circuit to be checked (106,107,112). In the fourth procedure, the stationary signal is propagated to the circuit to be checked for each combination of the logical value 1 and the logical value 0 of the stationary signal (1061, 1062). In the fifth step, in the combination of the logical values of the stationary signals propagated in the fourth step, it is checked from the connection relationship whether or not there is one asynchronous transmitter register to which the signal change logically reaches. (1064,1065). In the sixth procedure, based on the check result in the fifth procedure, it is determined whether or not the configuration of the circuit involved in asynchronous transfer is appropriate as a synchronization circuit for single signal transfer (110).

[5] In addition, instead of the above-mentioned fourth procedure, the circuit to be checked extracted in the above-mentioned third procedure is used.<u style="single">Binary building diagram</u>Move to the above<u style="single">Binary building diagram</u>Is given a logical value "1" and a logical value "0", and the above<u style="single">Binary building diagram</u>And instead of the 5th step above,<u style="single">Binary building diagram</u>It is also possible to check whether or not there is one asynchronous sender register from the remaining variables of.

[6] In the above [4] and [5], the above-mentioned stationary signal is set to a fixed value of a logical value "0" or a logical value "1" when another signal that performs asynchronous migration changes in the asynchronous transfer. , It is assumed that the logical value does not change.

[7] The clock domain check program described in [4] to [6] above can be recorded on a computer-readable recording medium.

Here, the receiving side register and the transmitting side register include a D-type flip-flop circuit.

2. Description of the embodiment Next, the embodiment will be described in more detail.

FIG. 3 shows a configuration example of a computer system in which the clock domain check program according to the present invention is executed. The computer 30 shown in FIG. 1 includes, but is not particularly limited, a CPU (Central Processing Unit) 31, a hard disk device 32, an input device 33, a display device 34, and a memory 35, which are coupled to each other via a bus 36. Has been done. CPU31 executes a predetermined program. In this example, this CPU 31 executes a clock domain check program that enables checking of the synchronization circuit in asynchronous transfer. The hard disk device 32 stores various information such as various programs executed by the CPU 31 and a netlist of circuits to be checked. Although not particularly limited, the magnetic disk 321 which is the recording medium of the hard disk device 32 is detachable from the hard disk device 32. The magnetic disk 321 can be read and written by the computer 30 while being mounted on the hard disk device 32.

The CPU 31 performs a predetermined arithmetic process by reading the clock domain check program from the magnetic disk 321 of the hard disk device 32 and executing the program. The memory 35 is used as a work area for arithmetic processing in the CPU 31. The memory 35 is, for example, a RAM (random access memory) that can be randomly accessed. The input device 33 enables input of various information to the computer system, and the input device 33 includes various input devices such as a keyboard and a mouse. The display device 34 displays various information on the computer 30 as needed, and is, for example, a liquid crystal display device.

The stationary signal used in the clock domain check performed by the computer 30 having the above configuration will be described with reference to FIGS. 8 to 10.

As a circuit to be checked, consider an asynchronous transfer circuit including D-type flip-flop circuits 801 to 805 and a 3-input and gate 806 as shown in FIG. The flip-flop circuits 801 to 803 are synchronously operated with the first clock signal CLK1, and the flip-flop circuits 804 and 805 are synchronously operated with the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are in an asynchronous relationship with each other. Input signals In1, In2, When In3 changes randomly, the circuit shown in FIG. 8 may cause an error because the glitch at Andgate 806 is taken into the flip-flop circuit 804 as a correct state change. Here, when the input signal In1 is specified as a "stationary signal", this input signal In1 has a logic value of "0" even though the logic of other signals (that is, In2, In3) that perform asynchronous crossing changes. It is a fixed value of "or" or the logical value "1", and is regarded as a signal that does not change. Specifically, it refers to a signal for which the above is guaranteed, such as a mode signal or a software flow (for example, In1 does not change at the same time as In2 or In3). As a result, when two of the input signals In1, In2, and In3 are "stationary signals", the circuit is equivalent to a 1-bit signal crossover, so that there is no inconvenience as a synchronization circuit.

Further, the stationary signal is different from a normal logic-fixed signal, and there may be a plurality of patterns of logic combinations. As a circuit to be checked, for example, as shown in FIG. 9, consider a case where an asynchronous transfer circuit is formed including D-type flip-flop circuits 901 to 908 and a selection circuit 909. The D-type flip-flop circuits 903,904,907,908 are synchronized with the first clock signal CK1, the D-type flip-flop circuits 901,902 are synchronized with the second clock signal CK2, and the D-type flip-flop circuits 905,906 are synchronized with the third clock signal CK3. To. The selection circuit 909 selectively transmits the output signal of any one of the D-type flip-flop circuits 903 to 906 to the subsequent D-type flip-flop circuit 907 based on the output signals of the D-type flip-flop circuits 901 and 902. To do. In such a configuration, the logical output value of the output terminal (Q) of the D-type flip-flop circuit 901,902 is fixed to "0,0", and the output signal of the output terminal (Q) of the D-type flip-flop circuit 906 is set by the selection circuit 909. If selected, the asynchronous transfer check in that case is only the path from the D-type flip-flop circuit 906 to the D-type flip-flop circuit 907, and the path from the D-type flip-flop circuit 905 to the D-type flip-flop circuit 907. Asynchronous transfer check is not performed. Therefore, the output signals of the D-type flip-flop circuits 901 and 902 are set as "stationary signals", and four types of logic combination patterns are used., That is, set "0,0", "0,1", "1,0", "1,1". As a result, in the asynchronous transfer check of the circuit shown in FIG. 9, the output terminals (Q) of the D-type flip-flop circuits 903 to 906 are sequentially selected by the selection circuit 909 by switching the four types of logic combination patterns. As a result, asynchronous transfer check of the route from the D-type flip-flop circuit 903 to 906 to the D-type flip-flop circuit 907 can be performed.

In addition, the stationary signal is propagated across the flip-flop circuit. As a circuit to be checked, for example, as shown in FIG. 10, consider a case where a synchronous transfer circuit is formed including D-type flip-flop circuits 1001 to 1003 and 2-input and gate 1004 to 1007. Andgate 1004 obtains the AND logic of the output signal of the D-type flip-flop circuit 1001 and the output signal of the D-type flip-flop circuit 1002. The output signal of the and gate 1004 is transmitted to one input terminal of the and gate 1005 in the subsequent stage. The other input terminal of Andgate 1005 is fixed to the logical value "1". The output signal of the Andgate 1005 is transmitted to one input terminal of the Andgate 1006 in the subsequent stage. The output signal of the D-type flip-flop circuit 1003 is transmitted to the other input terminal of the and gate 1006. The output signal of the D-type flip-flop circuit 1006 is transmitted to one input terminal of the and gate 1007 in the subsequent stage. The other input terminal of the D-type flip-flop circuit 1007 is fixed to the logical value 0. In such a configuration, if the signal of the data input terminal (D) of the D-type flip-flop circuit 1001, 1002 is designated as a stationary signal, the logic of the output terminal of the and gate 1005 is determined. That is, when the signal of the data input terminal (D) of the D-type flip-flop circuit 1001,1002 is specified as a steady-state signal, this steady-state signal propagates forward from the D-type flip-flop circuit 1001,1002 to the and-gate 1005. As a result, the D-type flip-flop circuit 1001, The input signal of the data input terminal (D) of 1002, the output signal of Andgate 1004, and the output signal of Andgate 1005 have the "stationary signal" attribute. The stationary signal is a through condition in which the logical value of one input terminal is fixed, such as Andgate 1005, or when all input signals are stationary signals, such as Andgate 1004. Is propagated in the forward direction (signal transmission direction). Further, in FIG. 10, when the signal of the data input terminal (D) of the D-type flip-flop circuit 1003 is also designated as a stationary signal, the stationary signal is propagated to the output terminal of the and gate 1006. Since the other input terminal of the Andgate 1007 is fixed to the logical value 0, the stationary signal is not propagated to the output terminal of the Andgate 1007. Unlike the fixed signal, the stationary signal considers both the logical value 1 and the logical value 0.

FIG. 1 shows a processing procedure when the clock domain check program is executed on the computer 30 having the above configuration.

When the execution of the clock domain check program is started in the computer 30, the net list, the clock information, and various information related to the stationary signal, which are examples of the information about the circuit to be checked, are sent by the CPU 31 to the magnetic disk device 32. Read from disk 321. Here, the clock information includes information indicating the frequency of the clock signal, the synchronization / asynchronous relationship between the plurality of clock signals, and the like. Further, the stationary signal is a signal whose logical value does not change in asynchronous transfer, and any of the net name, signal name, and terminal name in the net list may be used to specify the stationary signal.

First, using a circuit netlist, if a circuit has a logically pre-fixed value (called a fixed value), that fixed value is given and propagated (101). Further, a clock signal is supplied to the circuit and propagated (102). There is a distinction between synchronous and asynchronous clock signals. The clock signal is propagated to the clock input terminal of the register (including the D-type flip-flop circuit), and the clock name is stacked on the clock input terminal. When a plurality of clock signals arrive, a plurality of clock names are stacked correspondingly.

A stationary signal is then supplied and propagated using a netlist (103). At this time, the stationary signal is transmitted across the register (including the D-type flip-flop circuit).

After the stationary signal is propagated in step 103, a combination of asynchronous transfers is extracted (104). That is, a route search is performed in the forward direction (signal transmission direction) from the register (including the D-type flip-flop circuit) and the input terminal, and a combination that becomes asynchronous transfer is extracted.

The circuit that is no longer asynchronous due to the propagation of the stationary signal is not extracted in step 104. For example, as shown in FIG. 11, when the selection operation of the selection circuits 1101 and 1102 is controlled by the stationary signal and the synchronous transfer is performed between the D-type flip-flop circuits 1102 and 1104, the asynchronous transfer is not performed. Therefore, it is not extracted in step 104 above.

Then, all the receiving side registers are extracted from the extraction result of the combination that becomes the asynchronous transfer obtained in the above step 104 (105). The following processing is performed for each of the receiving side registers.

In step 105, after the receiving register is extracted, it is determined whether or not a plurality of signal synchronization circuits exists for each receiving register (106). FIG. 5, FIG. 6, and FIG. 7 show an example of a synchronization circuit for a plurality of signals. For example, as shown in FIG. 5, the D-type flip-flop circuit 502 arranged after the combination circuit 501, the D-type flip-flop circuit 503 arranged after the combination circuit 501, and the D-type flip-flop circuit 503 are enabled. When an asynchronous transfer circuit is formed including D-type flip-flop circuits 54 and 505 for supplying signals, in addition to the data SIG [n: 0] output from the D-type flip-flop circuit 502, the enable signal enable Is synchronized by the clock signal CLK2 in the D-type flip-flop circuit 503. The enable signal enable is the original enable signal Enable_org D-type flip-flop circuit 504, Metastable measures are taken by synchronizing with the same clock signal in the two-stage configuration of 505. Further, as shown in FIG. 6, data transfer may be performed by interposing a FIFO (first in, first out) buffer 601 between the transmitting side and the receiving side. If the clock signal on the synchronization side (reception side) has a period of 3 times or less the clock signal on the transmission side, buffer it with the FIFO buffer 601 and use the flag corresponding to the buffer full condition (burst transfer request signal or burst transfer). By using (corresponding to the end signal), the frequency ratio of the synchronized signal can be tripled or more. In some cases, the synchronous transfer circuit is configured in this way, and it is determined whether or not there is an error in the connection of the synchronous circuit. Furthermore, a request (Requst) and an acknowledge (acknowledge) handshake may be performed between the transmitting side and the receiving side (synchronizing side). For example, as shown in FIG. 7, the transmitting side is synchronized with the first clock signal CLK1 and the receiving side is synchronized with the second clock signal CLK2. A request (Requst) is issued from the transmitting side to the receiving side, and an acknowledge is returned from the receiving side to the transmitting side. For the request (Requst) signal from the transmitting side to the receiving side, metastable measures are taken by the two-stage configuration of the D-type flip-flop circuits 701 and 702. For the acknowledge signal from the receiving side to the transmitting side, metastable measures are taken by the two-stage configuration of the D-type flip-flop circuits 703 and 704. Data transfer from the transmitting side to the receiving side is performed by the above acknowledge in response to the above request (Requst). As shown in FIG. 4, a single signal synchronization circuit is referred to as a single signal synchronization circuit with respect to the multiple signal synchronization circuit. That is, the D-type flip-flop circuit 402 arranged after the combinational circuit 401 and the D-type flip-flop circuit 403 arranged after the combination circuit 401,

If it is determined in the determination in step 106 that a plurality of signal synchronization circuits exist (Y), the plurality of signal synchronization circuits are excluded from the checked circuits (112). Then, in the determination in step 106, when it is determined that the synchronization circuit for a plurality of signals does not exist (N), and after the synchronization circuit for a plurality of signals is excluded from the check target circuit in the step 112, The circuit to be checked is extracted for each receiver register (107). That is, from the combination of asynchronous transfers extracted in step 104, the circuit and the stationary signal from the receiving side register to the transmitting side register and the transmitting side register by back tracing toward the transmitting side are searched for. The circuit to be checked is extracted with.

Next, an asynchronous path check is done (108). This asynchronous path check will be described in detail later with reference to FIG.

Based on the result of checking the asynchronous path in step 108 above, it is determined whether or not there is one asynchronous transfer (109). If it is determined that one asynchronous transfer exists in the determination in step 109, it is determined whether or not the circuit to be checked is appropriate as a synchronization circuit (110). For example, when the metastable measures are taken, it is judged to be appropriate as a synchronization circuit, and when the metastable measures are not taken, it is judged to be inappropriate. If it is determined that the synchronization circuit is appropriate (Y) in the determination in step 110, it is determined whether or not to end the process according to this flowchart (111). If the processing of steps 106 to 110 is not completed for all the receiving side registers extracted in step 105, the process returns to the determination of step 106, and for another receiving side register, steps 106 to 110 are described. Processing is executed. When the processing of steps 106 to 110 is completed for all the receiving side registers extracted in step 105, the processing according to this flowchart is completed in step 111. If it is determined that the synchronization circuit is inappropriate (N) in the determination in step 110, the processing according to this flowchart is terminated after the asynchronous transfer circuit error error message is output (113). To.

Next, the asynchronous path check in step 108 will be described in detail.

First, the flag (FLAG) is set to the logical value 0 (1060). Next, when the number of stationary signals in the circuit to be checked is "N" and the stationary signals are logical values "0" and logical value "1", all combinations, that is, 2 to the Nth power of logic Generate a combination (1061). For example, assuming that the number (N) of stationary signals in the circuit to be checked is 2, in step 1061 above, the combination pattern of "0,0", "0,1", "1,0", and "1,1" Is generated.

Next, a stationary signal is propagated for each combination of logics generated in step 1061 (1062). That is, when a plurality of stationary signals exist in the circuit to be checked, the circuit to be checked is propagated and simulated for each of the combination patterns of the stationary signals.

Then, based on the result of propagating the stationary signal in step 1062 in FIG. 2, it is determined whether or not there is a place where the signal transmission path is broken or a place where the clock signal is not propagated (1063). In this determination, if it is determined that there is no location where the signal transmission path is broken or where the clock signal does not propagate (N), there are two or more asynchronous transmitter registers in one circuit. Whether or not to do so is determined (1064). In this determination, if it is determined that there are no two or more asynchronous transmitter registers in one circuit (N), it is determined whether or not there is one asynchronous transmitter register (1065). ). In this determination, if it is determined that there is not one asynchronous transmitter register (N), the signal propagation information of the logical value "0" and the logical value "1" in the checked circuit is cleared ( 1068). Then, it is determined whether or not to end the asynchronous path check (1069). That is, for all combinations of the logical value "0" and the logical value "1" generated in the above step 1061, if the processing from the above steps 1062 to 1068 is not completed, the transition to the above step 1062 is performed. The processes of steps 1062 to 1068 are performed for another combination pattern of the logical value 0 and the logical value 1. Then, when the processing of the above steps 1062 to 1068 is completed for all the combinations of the logical value "0" and the logical value "1" generated in the above step 1061, the asynchronous path check in the above step 108 is completed. Then, the process proceeds to the determination in step 109 (FIG. 1). If it is determined in step 1064 that there are two or more asynchronous transmitter registers in one circuit (Y), an asynchronous transfer circuit miss error message is output and the flag (FLAG) is logical. The value is set to 0 (1066) and the asynchronous path check in step 108 ends. Also, in the determination in step 1065 above, there is one asynchronous transmitter register. If it is determined to be (Y), there is one asynchronous transfer, in other words, there is one circuit that logically looks like a one-to-one connection between the input and output, so the flag. After (FLAG) is set to the logical value 1, the process proceeds to the process of step 1068. In the determination in step 109 (FIG. 1), whether or not one asynchronous transfer exists is determined by the logical value of this flag (FLAG).

Here, the case where it is determined that there is one asynchronous transmitting side register (Y) in the determination in step 1065, that is, the case where the input and the output seem to be logically one-to-one connection will be described. ..

For example, as shown in FIG. 12, the circuit to be checked is an asynchronous transfer circuit composed of D-type flip-flop circuits 1201, 1202, 1204 and and gate 1203, and the output signal of the D-type flip-flop circuit 1202 is a steady signal. When this stationary signal has a logical value of "1", it is determined that the D-type flip-flop circuits 1201 and 1204 are connected one-to-one. Further, as shown in FIG. 13, the check target circuit includes a D-type flip-flop circuit 1301, 1302, 1304 and a selection circuit 1303 to form an asynchronous transfer circuit, and a signal for controlling the selection operation of the selection circuit 1303. When is a stationary signal, and when the stationary signal has a logical value of "0", it is determined that the D-type flip-flop circuits 1301 and 1304 are connected on a one-to-one basis, and the stationary signal has a logical value of "1". In the case of ", it is determined that the D-type flip-flop circuits 1302 and 1304 are connected one-to-one.

According to the above example, the following effects can be obtained.

(1) When the clock domain check program is read from the magnetic disk 321 of the hard disk device 32 by the CPU 31 and executed, the processing shown in the flowcharts shown in FIGS. 1 and 2 is performed. In this process, even if the synchronization circuit is violated, the error (pseudo error) that is actually a stationary signal with a logical value "0" or a logical value "1" and does not affect the operation of the chip is true. Since it is detected separately from the error of, it is difficult to detect it as an error. Therefore, the pseudo error information can be significantly reduced. According to the clock domain check actually performed by the present inventor, the pseudo error can be reduced to about 1/500 as compared with the conventional technique depending on the configuration of the circuit to be checked.

(2) Due to the action and effect of (1) above, the error analysis time can be significantly reduced, and the cost required for manufacturing the chip can be reduced.

Although the invention made by the present inventor has been specifically described above, it goes without saying that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

For example, in the above example, as shown in FIG. 2, the asynchronous path check was performed by simulation, but instead of this simulation, a binary decision graph can be used for each receiver register. That is, the circuit to be checked extracted in step 107<u style="single">Binary building diagram</u>Move to this<u style="single">Binary building diagram</u>Is given a logical value "1" and a logical value "0",<u style="single">Binary building diagram</u>And the steps to transform the above<u style="single">Binary building diagram</u>A step is provided to check whether or not there is one asynchronous sender register from the remaining variables of. The determination in step 110 is performed based on the check result of whether or not there is one asynchronous transmitter register. For example, the circuit to be checked shown in FIG. 14 (A) (basically equivalent to that shown in FIG. 13 and the clock signals CK1 and CK2 are asynchronous) is shown in FIG. 14 (B). It is moved to the binary decision graph so that it is transformed. Here, when the stationary signal C has a logical value of 1, as shown in FIG. 15 (A), the stationary signal C has a path of the logical value 1 and a path of the logical value 0. By excluding the path with the logical value "0", the 2-minute decision graph is transformed, and the asynchronous "a" remaining in the 2-minute decision graph is detected. When the stationary signal C has a logical value of 0, as shown in FIG. 15B, the stationary signal C has a path of the logical value 1 and a path of the logical value 0. By excluding the path with the logical value "1", the 2-minute decision graph is transformed, and the asynchronous "b" remaining in the 2-minute decision graph is detected. In this way, the binary decision graph is transformed and described above.<u style="single">Binary building diagram</u>From the remaining variables of, it is checked whether there is one asynchronous sender register. Even in this way, the same effect as in the case of the above simulation can be obtained.

Further, as in the case of the clock domain check, the pseudo error in the timing verification can be reduced by limiting the path in the timing verification by setting the stationary signal in the circuit to be the target of the timing verification. ..

The magnetic disk 321 is an example of a recording medium that can be read by the computer 30. As a recording medium that can be read by the computer 30, in addition to the magnetic disk 321 described above, an optical disk in an optical disk device or a semiconductor storage device such as a flash memory can be applied.

<figref num="1">It is a flowchart which shows an example of the processing procedure when the clock domain check program which concerns on this invention is executed.</figref><figref num="2">It is a flowchart which shows the detailed flow of the asynchronous path check in FIG.</figref><figref num="3">It is a block diagram of the whole configuration example of the computer system in which the clock domain check program is executed.</figref><figref num="4">This is a block of a configuration example of a synchronization circuit using a single signal.</figref><figref num="5">This is a block of a configuration example of a synchronization circuit using a plurality of signals.</figref><figref num="6">This is a block of a configuration example of a synchronization circuit using a plurality of signals.</figref><figref num="7">This is a block of a configuration example of a synchronization circuit using a plurality of signals.</figref><figref num="8">It is a block diagram for demonstrating the function of the stationary signal used in the said clock domain check.</figref><figref num="9">It is a block diagram for demonstrating the function of the stationary signal used in the said clock domain check.</figref><figref num="10">It is a block diagram for demonstrating the function of the stationary signal used in the said clock domain check.</figref><figref num="11">It is a block diagram for demonstrating the main operation when a clock domain check program is executed.</figref><figref num="12">It is a block diagram for demonstrating the main operation when a clock domain check program is executed.</figref><figref num="13">It is a block diagram for demonstrating the main operation when a clock domain check program is executed.</figref><figref num="14">It is explanatory drawing of the processing procedure when the clock domain check program which concerns on this invention is executed.</figref><figref num="15">It is explanatory drawing of the processing procedure when the clock domain check program which concerns on this invention is executed.</figref>

30 computers 31 CPU 32 Hard disk drive 321 magnetic disk 33 Input device 34 Display device 35 memory 36 bus