Alignment method for fabrication of integrated ultrasonic transducer array

The present invention generally relates to the manufacture of microfabricated ultrasonic transducers. In particular, the present invention relates to the manufacture of ultrasonic transducer arrays on CMOS wafers.

Recently, semiconductor processes have been used to manufacture ultrasonic transducers of the form known as microfabrication ultrasonic transducers (MUTs), which can be of the capacitive (cMUT) or piezoelectric (pMUT) type. The cMUT is a very small diaphragm-like device with electrodes that convert the voice vibration of the received ultrasonic signal into modulated capacitance. For transmission, the capacitive charge is modulated to vibrate the diaphragm of the device, which transmits sound waves.

One advantage of MUTs is that they can be made using semiconductor manufacturing processes such as microfabrication processes, which are classified as "microfabrication". In U.S. Pat. No. 6,359,367, "Microfabrication means (A) pattern forming tools (generally lithography such as projection aligners or wafer steppers), (B) PVD (physical vapor deposition), and CVD (chemical vapor deposition). , LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Chemical Vapor Deposition) and other vapor deposition tools and (C) Wet Chemical Vapor Deposition, Plasma Etching, Ion Milling, Sputter Etching, or Laser Etching and other etching tools Or microstructure formation using some of these. Microfabrication is usually performed on substrates or wafers made of silicon, glass, sapphire, or ceramic. Such substrates or wafers are generally very flat. It is smooth and has a size of a few inches in the lateral direction. These are usually processed as a group in a cassette moving from process tool to process. Each substrate advantageously makes multiple copies of the product ( It can be incorporated (although not always). There are two general types of microfabrication: 1) bulk microfabrication with a thick portion on which a wafer or substrate is formed, and 2) modeling. Is a surface microfabrication that is generally limited to surfaces, especially thin films deposited on the surface. The definitions of microfabrication used herein include silicon, sapphire, all types of glass materials, polymers (polygon, etc.). ), Polysilicon, Silicon Nitride, Silicon Oxide Nitride, Aluminum and Copper Alloys and Thin Metals such as Tungsten, Spin-On-Glass (SOG), Embeddable or Diffusion Additives, and Silicon Oxide and Nitride. Includes the use of conventional or known microfabrication materials, including growth films such as objects. "

A similar definition of microfabrication is incorporated herein. The resulting system from such a microfabrication process is commonly referred to as a "microfabrication electromechanical system" (MEMS).

cMUT is usually a hexagonal structure with a thin film that spreads throughout. This thin film is held near the substrate surface by the applied bias voltage. The thin film can be vibrated by applying a vibrating signal to the pre-biased cMUT, thus allowing the thin film to radiate sound energy. Similarly, when a sound wave is incident on a thin film, the resulting vibration can be detected as a voltage change in the cMUT. One "cMUT cell" is the term used herein to describe a single of these hexagonal "drum" structures. The cMUT cell can have a very small structure. A typical cell size is 25 to 50 microns from flat edge to edge on a hexagon. There are many ways in which cell size is determined by the designed acoustic response. It may not be possible to generate larger cells that work better in terms of desired frequency response and sensitivity.

The ultrasonic probe is designed on the basis of cMUT technology. In one known design, multiple cMUT cells are grouped together and the electrodes of a particular group of cells are wired together to form a larger transducer element. Some use a switching network to electrically connect elements (ie, so-called "partial elements" include a group of wired cMUT cells) to each other to connect larger elements, such as linear elements. Can be formed. Larger devices can be reconstructed by changing the state of the switching network. However, an element consisting of only one set of cMUT cells, all wired to each other, cannot be reconstructed.

According to one proposed architecture, each element contains a plurality of hexagonal MUT cells arranged in a honeycomb pattern with electrodes on thin films wired to each other. The outer ring of the MUT cell of each element forms another hexagon. These devices can be reconfigured to form larger devices using switching networks. An array of such small devices can be integrated with conventional metal oxide semiconductor (CMOS) switches and preamplifier / buffer circuits on silicon wafers to form reconfigurable beam forming devices. MEMS technology enables the realization of 2D cMUT arrays on CMOS electronics.

According to known manufacturing methods, pre-manufacturing CMOS wafers are flattened before starting the cMUT manufacturing process. A CMOS wafer contains an array of cells consisting of circuit elements in which each cell is used to provide locally required functionality to its associated cMUT element. The connection between the plane of the CMOS cell matrix and the plane of the cMUT element array can be realized in the vertical direction.

Lithography is commonly used in the manufacture of MEMS devices. This process typically involves pattern transfer to a photosensitive material by exposing the selected area to a radiation source such as light. Photosensitive materials undergo changes in their physical properties when exposed to radiation. Usually, a mask is used that allows light to pass through and shines only on a selected area of the photosensitive material. In micromachining lithography, a photosensitive material is usually a material (ie, a photoresist) whose chemical resistance to a developing solution changes when exposed to radiation of a particular wavelength. The developing solution is used to etch one of the two areas (exposed or unexposed areas). The photosensitive layer can be used as a temporary mask when etching the underlying layer and the pattern can be transferred to the underlying layer. The photosensitive layer may also be used as a template for patterning the deposited material.

In the manufacture of MEMS devices, layers of different structures to be manufactured need to be aligned with each other. Each mask should have a reference (ie, an alignment mark) that matches the corresponding reference mark on the pre-patterned layer so that the corresponding layer can be aligned with the other layers. To do. The alignment mark on the mask is transferred to the wafer, and the subsequent alignment mark on the mask can be matched with the alignment mark on the wafer.

Mask creation generally involves layout and pattern transfer to the mask. The term "layout" refers to the process of defining the pattern that appears on the mask, which also defines the geometry of the device being manufactured. Layout is typically done with graphical editing tools that work with files that contain layers of patterns. Each layer represents its own mask. Layout tools allow the user to view and edit all layers together or selected layers. Next, the pattern defined in the layout needs to be transferred to a light-transmissive mask coating on the light-transparent mask substrate.

In order to manufacture the cMUT layer on top of the CMOS layer, it is necessary to make a suitable mask using conventional layout tools. In the case of the honeycomb pattern of hexagonal cMUT elements, there are three symmetric intrinsic axes oriented 60 ° with respect to each other. The unique path that signals and controls the line in this coordinate system is along the axis of symmetry. In a linear array of CMOS devices, the unique axes of symmetry are orthogonal to each other. In this case, the unique path that sends the signal and controls the line is along one of the orthogonal axes. If non-orthogonal lines are drawn in a standard CMOS process, this can increase defect occurrence and complicate mask generation. When integrating hexagonal or honeycomb-like cMUT devices on top CMOS devices distributed in a linear grid, unit element mismatches occur.<patcit num="1"><text>U.S. Pat. No. 6,359,367</text></patcit>

<p> There is a need for a method of aligning the hexagonal grid of cMUT elements with the linear grid of CMOS cells during microfabrication. In particular, each hexagonal cMUT element needs to match its rectangular CMOS cell.</p>

<p> The present invention relates to an integrated circuit including a microfabricated hexagonal array of cMUT elements on a substrate containing a hexagonal array of CMOS cells, and one is a one-to-one correspondence between each cMUT element. It relates to a method of arranging each array so as to cover each CMOS cell. During the mask layout for micromachining the cMUT layer, either the hexagonal pattern or the alignment key is rotated until the axis of symmetry of the hexagonal pattern is aligned with the axis of the alignment key. Then, when the mask overlaps the CMOS substrate, the alignment key on the mask aligns with the alignment key on the substrate. This ensures that the cMUT element formed by optical lithography matches the CMOS cell.</p><p> One aspect of the invention is (a) laying out a pattern containing a first set of graphical data representing a hexagonal array of cMUT elements with axes of symmetry, and (b) two axes orthogonal to each other. Rotate the pattern by a predetermined angle selected so that the axis of symmetry of the hexagonal array of hexagonal cMUT elements aligns with the axis of the reference first fixed line frame with respect to the reference fixed line frame having A first alignment that includes a second set of graphical data that has a stage of processing a first set of graphical data to allow it to (c) and an axis aligned with the axis of the first fixed linear frame of the reference. The steps of laying out the keys, (d) transferring the rotated pattern and the first alignment key to the mask, and (e) the axis of symmetry aligned with the axis of the second fixed straight line frame of the reference. Place the mask across the substrate, including the hexagonal array of CMOS cells with, the second alignment key has an axis aligned with the axis of the reference second fixed straight frame, and the first alignment key is the first. It is an alignment method that includes a stage in which the mask is arranged so as to be aligned with the alignment key of 2.</p><p> Another aspect of the invention is (a) laying out a pattern containing a first set of graphical data representing a hexagonal array of cMUT elements with axes of symmetry, and (b) having axes and graphically. The stage of laying out the first alignment key containing the second set of data, and (c) the axis of symmetry with respect to the axis of symmetry of the hexagonal array of hexagonal cMUT elements. Mask the second set of graphical data to rotate the first alignment key by a given angle chosen to align, and (d) the pattern and the rotated first alignment key. Place the mask over the entire substrate, including the stage of transfer to, and (e) a hexagonal array of CMOS cells with symmetric orthogonal axes aligned with the axis of the second fixed linear frame of reference, respectively, and a second alignment. It is an alignment method that includes a step in which the key has an axis aligned with the axis of the reference second fixed straight frame and the first alignment key is aligned with the second alignment key.</p><p> A further aspect of the present invention is an integrated circuit including a substrate including a hexagonal array of CMOS cells and a hexagonal array of microfabrication elements, each of which has a one-to-one correspondence and covers each CMOS cell. ..</p><p> A further aspect of the present invention is an integrated circuit that includes a substrate containing a hexagonal array of CMOS cells and a hexagonal array of cMUT elements, with each micromachined element having a one-to-one correspondence covering each CMOS cell.</p>

Other aspects of the invention are disclosed below and claimed in the claims.

Next, reference is made to drawings in which the same element is assigned the same reference number in different drawings.

Referring to FIG. 1, a cross section of a typical cMUT transducer cell 2 is shown. Arrays of such cMUT transducer cells are typically made on substrate 4, such as highly doped silicon (and thus semi-conducting) wafers. In each cMUT transducer cell, a thin film or diaphragm 8 made of silicon nitride is suspended on the substrate 4. The thin film 8 is supported at the periphery by an insulating support 6 that can be made of silicon oxide or silicon nitride. The cavity 16 between the thin film 8 and the substrate 4 can be filled with air or gas, or can be evacuated in whole or in part. A film or layer of a conductive material, such as an aluminum alloy or other suitable conductive material, forms the electrode 12 on the thin film 8, and another film or layer made of the conductive material is the electrode 10 on the substrate 4. To form. Alternatively, the bottom electrode may be formed by appropriately doping the substrate.

Due to the micro-sized size of typical cMUTs, many cMUT cells are usually manufactured at very close distances to form a single transducer element. Each cell can have a round, rectangular, hexagonal, or other outer shape. A hexagonal cMUT cell is shown in Figure 2. The hexagonal shape results in a high density integration of the cMUT cells of the transducer element. cMUT cells can have different dimensions, thereby transducer elements, broadband especially the transducer will have a composite characteristics of the different cell sizes giving properties.

Each transducer element in a typical cMUT device is composed of a plurality of cMUT cells. For illustration, Figure 3 shows a "daisy" transducer element made from seven hexagonal cMUT cells 2, in which the center cell is surrounded by a ring of six cells, with each cell in the ring being the center cell. It touches each side of the ring and the adjacent cell of the ring. The upper electrodes 12 of each cell 2 are wired to each other. For a hexagonal array, six conductors 14 (shown in both Figures 2 and 3) radiate outward from the top electrode 12 and connect to the top electrodes of adjacent cMUT cells (with six). Except for peripheral cells that are not connected to three other cells). Similarly, the bottom electrodes 10 of each cell 2 are electrically connected to form a capacitive transducer element 40 that is seven times as large.

In an ultrasonic probe in which the hexagonal cMUT element 16 is distributed in a hexagonal pattern, there are three symmetric intrinsic axes X1, X2, and X3 as shown in FIG. These axes form a coordinate system that defines the array. The unique path that controls the line through the signal in this coordinate system is along the axis of symmetry because they are straight and continuous lines as shown in the figure. In CMOS devices containing rectangular CMOS cells arranged in an orthogonal grid, the symmetric eigenaxises are orthogonal and not aligned with the symmetric axes of the hexagonal grid. Similarly, CMOS cells in a linear grid do not match the cMUT elements in a hexagonal grid essentially due to differences in geometry.

According to one embodiment of the present invention, the above problems are overcome by constructing a hexagonal grid of hexagonal cMUT elements on a hexagonal grid of rectangular CMOS cells. An example of a hexagonal grid of rectangular CMOS cells 18 with orthogonal axes X and Y is shown in FIG. The hexagonal pattern is obtained by offsetting every other column by a distance equal to half the cell size in the column direction. The length and width of the rectangular CMOS cells are chosen so that the distance between the centers of the two rectangles along any diagonal is equal to the distance between the centers of the two hexagonal cMUT elements that overlap these CMOS cells.

The cMUT array is made using optical lithography. Each layer of the microfabricated structure requires its own mask. Each mask is a honeycomb or hexagon of hexagonal transducer elements, each of which consists of a geometric pattern forming the structure shown in FIG. 4, a "daisy" pattern in which each transducer element consists of seven hexagonal cMUT cells. It will have a coating with a pattern. During the mask layout, it is necessary to take steps to ensure that the CMOS substrate to be microfabricated and the geometric pattern on each mask are properly aligned. All of the masks are aligned on the same reference axis and all of them are rotated as much as needed to align with the CMOS device.

As disclosed herein, various methods are used to ensure that the hexagonally distributed hexagonal cMUT element matches the hexagonally distributed rectangular CMOS cells in the final manufactured structure. can do. Two methods are disclosed herein to ensure proper alignment of the cMUT and CMOS layers. However, the most appropriate method needs to be selected based on the available manufacturing processes.

According to the method disclosed herein, the CMOS cell is rectangular and offset by half the height of the cell as shown in FIG. This offset is easy to achieve. In this array, lines can be easily run along the rectangular grid axis.

According to the first method of the invention shown in FIG. 6, a hexagonal reference plane (X).₁, X₂, X₃) Is the linear reference plane (X) used within the cMUT layout tool._m, Y_m) Is rotated. This rotation is algorithmically realized by manipulating each vertex of the hexagonal cMUT element during layout. More precisely, this rotation is achieved by calculating the new coordinates of each vertex as the geometric pattern rotates a certain frequency away from the original axis. In addition, multiple alignment keys 20 (only one of which is shown in FIG. 6) are formed as part of the pattern on the mask. In the illustrated embodiment, each alignment key 20 has its own axis X in the reference plane._m, Y_mIncludes two orthogonally intersecting straight lines parallel to.

When the layout mask is generated in this way, it is easy to align the center of the hexagonal cMUT with the offset CMOS pattern shown in FIG. 5, which is illustrated in FIG. The plurality of alignment keys 20 on the mask for patterning the cMUT layer must be aligned with the plurality of alignment keys 22 formed on the CMOS substrate. Again, in FIG. 7, only one of each alignment key 20 and 22 is shown. The bottom of FIG. 7 represents a cMUT mask that covers the CMOS substrate, with the hexagonal pattern on the mask aligned exactly with the rectangular CMOS cells on the substrate. In this positional relationship, the alignment key 20 will be superimposed on the upper part of each alignment key 22. In the particular embodiment shown in FIG. 7, the overlapping alignment key 22 is under the alignment key 20 and therefore cannot be seen. However, those skilled in the art will appreciate that alignment keys are usually designed so that the key 20 on the mask is fitted inside the key 22 on the wafer and both keys are visible during the alignment. There will be.

According to the second method of the present invention shown in FIG. 8, a hexagonal reference plane (X).₁, X₂, X₃) Is designed to be the most convenient in the cMUT layout tool. Within this tool are multiple mask alignment keys 20 (only one of which is shown in Figure 8) that is rotated by a matching angle. This is because the Y axis of the alignment key 20 is the X in the cMUT plane.₃It means that it is parallel to the axis. During the manufacture of the cMUT, the mask is rotated and aligned with respect to a similar alignment key placed on the CMOS wafer. Thus, it is easy to align the center of the hexagonal cMUT with the offset CMOS pattern shown in FIG. The final result is the structure shown in FIG. 7 as well.

Therefore, according to the first disclosed method, the reference cMUT frame is rotated during the mask layout by designing a cMUT hexagonal axis that will be rotated with respect to the reference grid of straight lines in the cMUT plane. On the other hand, according to the second disclosed method, the reference cMUT frame is by rotating the exposed part of the mask with respect to the reference CMOS plane using the reference key placed on the CMOS device. Rotated during lithography. In both methods, the CMOS substrate incorporates alternating half-offsets of the CMOS cell rows to line up with the rotated cMUT cells.

The benefits provided by the aforementioned methods of alignment are wide-ranging. That is, 1) the need for non-straight lines in the CMOS layer is eliminated, which simplifies the mask layout of CMOS cells. 2) These methods allow rectangular CMOS cells to be evenly spaced, which simplifies the mask layout for CMOS cell lithography configurations. 3) These methods allow the use of linear layout rules in CMOS lithography, which is standard (non-linear layout rules are often not accepted by semiconductor manufacturers). 4) The possibility of yield loss due to the formation of non-linear mispatterned lines is eliminated. 5) These methods enable accurate matching of hexagonal cMUT cells and rectangular CMOS cells.

The disclosed alignment method is not limited to using cMUT, but may also be applied when manufacturing an array of hexagonal microfabrication devices on top of a corresponding array of rectangular electronic circuit cells. Can be done.

Although the present invention has been described with respect to preferred embodiments, it will be appreciated by those skilled in the art that various modifications can be made without departing from the scope of the invention and that equivalents can replace this element. Moreover, many modifications can be made to adapt a particular situation to the teachings of the invention without departing from the essential scope of the invention. Therefore, the present invention is not limited to the specific embodiment disclosed as the best mode in which the invention is intended to be practiced, but all embodiments included within the scope of the appended claims. Intended to include.

<figref num="1">Sectional view of a typical cMUT cell.</figref><figref num="2">Isometric view of the cMUT cell shown in Figure 1.</figref><figref num="3">An isometric view of a hexagonal cMUT element configured on top of a rectangular cell in an integrated electronic circuit according to one embodiment of the invention (adjacent elements and cells not shown).</figref><figref num="4">Top view of a hexagonal array of hexagonal cMUT elements with three superposed symmetric intrinsic axes.</figref><figref num="5">Top view of a hexagonal array of rectangular CMOS cells with two superposed symmetric orthogonal or linear axes.</figref><figref num="6">The figure which shows the layout of the hexagonal array of the hexagonal cMUT element algorithmically rotated with respect to the alignment key.</figref><figref num="7">FIG. 6 shows an alignment of masks with a hexagonal array pattern of hexagonal cMUT elements with a hexagonal array of linear CMOS cells.</figref><figref num="8">The figure which shows the layout of the hexagonal array of a hexagonal cMUT element and the alignment key which is algorithmically rotated with respect to the axis of symmetry of a hexagonal array.</figref>

Code description

2 Typical cMUT Transducer Cell 4 board 6 Insulation support material 8 thin film 10 Bottom electrode 12 Upper electrode 16 cavities