High output impedance charge pump for pll/dll

Related application This application claims the interests of US Provisional Application No. 60 / 528,958 filed on December 11, 2003. The entire teachings of the above application are incorporated herein by reference.

Background of the present invention A delay lock loop (DLL) with adjustable delay lines is used to synchronize the first clock signal with the second clock signal by delaying the first clock signal. The DLL includes a phase detector that detects the phase difference between the first clock signal and the second clock signal. Based on the detected phase difference, the DLL attaches the first clock signal to the second clock signal by adding an appropriate delay to the first clock signal until the second clock signal synchronizes with the first clock signal. Synchronize with the clock signal of.

FIG. 1 is a block diagram of the prior art DLL100. The externally supplied clock (CLK) is buffered in the clock buffer 101 and provides a reference clock (CLK_REF) connected to the voltage control delay line 102 and the phase detector 104. The voltage control delay line 102 produces an output clock (CLK_OUT), which is a delayed version of CLK_REF and is sent to the various circuits in the device and the replica delay circuit 103. Replica delay circuit 103 provides delay through buffer 101 and delay similar to wire routing delay. Replica delays are known as delay model circuits and are well known to those of skill in the art. See U.S. Pat. Nos. 5,796,673 to Foss et al. For a further explanation of replica delay. The feedback clock signal CLK_FB output from the replica delay circuit 103 is connected to the phase detector 104. Other prior art DLLs use digital tap delay lines. U.S. Pat. Nos. 5,796,673 and 6,087,868 by the same applicant describe such types of DLLs.

The phase detector 104 generates phase control signals (UP, DOWN) depending on the phase difference between CLK_REF and CLK_FB. The UP signal is set to logic "1" when the CLK_REF rising edge is first received, and the DOWN signal is set to logic "1" when the CLK_FB rising edge is first received. Both the UP and DOWN signals are reset to logic "0" when the subsequent rising edges of the two signals are received. Therefore, if the rising edge of CLK_REF is detected before the rising edge of CLK_FB, the UP signal shifts to logic "1" and is delayed in the voltage control delay line (VCDL) 102 until the next rising edge of CLK_FB is detected. To increase. Alternatively, if a CLK_FB rising edge is detected before the CLK_REF rising edge, the DOWN signal shifts to logic "1" and the delay is reduced until the next rising edge of CLK_REF is detected.

The phase control signal (UP / DOWN) of the phase detector 104 is coupled by the charge pump 105 and the loop filter 106, and the variable bias voltage V_CTRLGive 110. Bias voltage V_CTRLSelects the delay to add to CLK_REF by VCDL102 and synchronizes CLK_FB with CLK_REF.

FIG. 2 is a schematic view of the prior art charge pump 200 that can be used with the prior art DLL shown in FIG. With reference to the DLL system shown in Figure 1, the control voltage V that controls the voltage control delay 102 (Figure 1) in the DLL._CTRLThe ability to precisely control the DLL's response is partly determined. That is, the turning point is determined by how accurately the current can be applied to the OUT node of the charge pump 200 or drained from the OUT node.

The voltage at the OUT node of the charge pump 200 depends on the phase control signal (UP / DOWN) received from the phase detector 104 (FIG. 1). To reduce the delay, both the DOWN and ENABLE signals are asserted (logic "1"), which results in logic "1" at the gate of transistor 217 and "on" transistor 217. With the transistor 215 already "on", a current (pull-down current) flows from the node OUT to the transistor 215 and the transistor 217 and is grounded. This pull-down current drains the charge from the OUT node and lowers the voltage of the OUT node.

To increase the delay, both the UP and ENABLE signals are asserted (logic "1"), resulting in logic "0" at the gate of transistor 209 and transistor 209 "on". Both transistor 209 and transistor 210 are in the "on" state, and the current is V._ddFlows from the transistor 209 and through the transistor 210 to the OUT node. This current flows through the loop filter 106 (Fig. 1) and adds an charge to the node OUT. The added charge raises the voltage of the OUT node.

The charge pump 200 includes two current mirrors called M1 and M2 that control the magnitude of the current given to the OUT node of the charge pump 200. The current mirror M1 includes a master transistor 214 and slave transistors 210 and 212, V._ddControls the pull-up current flowing through the transistor 210. The current mirror M2 includes a master transistor 216 and a slave transistor 215. The transistor 216 takes in the current from the transistor 212 in the current mirror M1, mirrors it in the transistor 215, applies a pull-down current through the transistor 215, and grounds.

Although the DLL is locked, the phase detector 104 (Figure 1) typically asserts its UP and DOWN signals for the same period of time each clock cycle. Therefore, the charge pump 200 will receive both UP and DOWN signals asserted for the same period to maintain the same voltage at node OUT. In order to provide a zero static phase offset at the output of the DLL when both the UP and DOWN signals of the phase comparator are asserted for the same period, the current pulses cancel each other out and the change in net charge is loop filter 106 (Figure 1). The charge pump must generate the same current pulse at the output OUT (node OUT) so that it cannot be transmitted to.

Therefore, to minimize static phase error, the drain / source currents through transistors 210 and 215 should be matched as much as possible. Ideally, the magnitude of the current passing through the transistor 210 in the current mirror M1 and the transistor 215 in the current mirror M2 is the same. Current matching is performed by mirroring the current that enters the device 210 from the device 212 and flows down to the device 215 via the current mirror M2.

However, the voltage at node OUT may not be the same as the voltage at node "ctrl". Due to this voltage difference, the drain-source voltage of the bias transistor 216 in the current mirror M2 is different from the drain-source voltage of the transistor 215. The same applies to transistor 212 and transistor 210 with respect to the drain-source voltage of bias transistor 214 in the current mirror M1. Changes in source-drain voltage lead to changes in drain current, especially if the transistors 215 and 210 have low output impedance. This causes different drain / source currents to flow through the devices in each current mirror, eventually creating a current difference between the transistors 210 and 215. The current difference between transistor 215 and transistor 210 can be as much as about 20%, resulting in significant static phase error when the DLL is locked. In the embodiments shown, the output impedance of the transistor is reduced so that the static phase error increases as the technology miniaturizes.

The DLL static phase error is understood as the phase difference that always occurs between CLK_REF and CLK_FB when the DLL is in the locked state, and the charge supplied to the node OUT through the transistor 210 is the node OUT during each clock cycle. Equal to the charge drained from the transistor 215 through the transistor 215. Therefore, the phase detector detects that the clock signals are perfectly aligned and the voltage level at the node OUT does not change.

FIG. 3 is a graph showing the source and sink currents in the prior art DLL shown in FIG. 2 before the locked state. Trace 150 corresponds to the source current through transistor 210 in FIG. 2, and trace 152 corresponds to sink current through transistor 215 in FIG. Prior to the locked state, the source and sink currents are not equal and the source current is greater than the sink current. In the locked state, the areas below the traces 150 and 152 are the same. Therefore, if the currents are not equal, the DLL compensates with a phase error or "static phase error" to maintain the same charge at the node OUT. The regions are substantially equal because the phase error results from a low current signal that is wider in time than the high current signal. The falling edges of each trace 150, 152 occur at about the same time, but the rising edges occur at different times to compensate for the unequal source and sink currents. Therefore, there is a phase error due to the unique design of the prior art DLL.

<p><patcit num="1"><text>U.S. Pat. No. 5,796,673</text></patcit><patcit num="2"><text>U.S. Pat. No. 6,087,868</text></patcit></p>

<p> In submicron technology (ie, less than 0.13 microns), the output impedance of the transistor decreases as the channel length shrinks, so the transistor does not meet the output impedance requirements of the charge pump output transistor. One known method of increasing the output impedance of the charge pump to minimize static phase error is by using a cascade current source. However, cascade current sources are not well suited for the tendency of power supply voltage drops. For example, for a 1V supply voltage and a typical threshold voltage from 0.25V to 0.3V, the 1V supply voltage is too low to maintain two cascaded current sources in series, each with two threshold voltages. ..</p>

<p> Disclosure of invention Static phase error in charge pumps is minimized by the use of active current sources. Active current mirrors also mitigate the effects of low supply voltages. According to embodiments of the present invention, the charge pump includes a pull-up circuit, a pull-down circuit and an operational amplifier. The pull-up circuit supplies a pull-up current to increase the voltage at the charge pump output. The pull-down circuit supplies a pull-down current to reduce the voltage at the charge pump output. The operational amplifier has a first input and a second input. The first input is connected to the charge pump output and the second input is connected to the drain of the transistor that supplies current to the pull-down circuit. The operational amplifier output is connected to the transistor and the pull-down circuit. The op amp adjusts the voltage level of the op amp output so that the voltage difference between the op amp inputs is minimized and the difference between the pull-down and pull-up currents is reduced.</p><p> The charge pump may also include a starter circuit connected to the first input of the operational amplifier that sets the voltage of the first input to a voltage level below the supply voltage when the charge pump is powered up. In an embodiment of the invention, the power supply voltage supplied to the charge pump can be about 1 volt.</p><p> The pull-up circuit includes a first MOSFET device and a second MOSFET device. The drain of the first MOSFET is connected to the source of the second MOSFET, the source of the first MOSFET is connected to the power supply voltage node (or rail), and the drain of the second MOSFET is to the charge pump output. Be connected. The pull-up circuit supplies the pull-up current while the first MOSFET device is on.</p><p> The pull-down circuit includes a first NMOS device and a second MOSFET. The drain of the first MOSFET is connected to the source of the second MOSFET, the source of the first MOSFET is connected to the ground, and the drain of the second MOSFET is connected to the charge pump output. The pull-down circuit supplies a pull-down current while the first NMOS device is on.</p><p> The charge pump also includes a reference current source that supplies current to the pull-down and pull-up circuits. In one embodiment, the reference current source comprises a programmable array of transistors. The operational amplifier can be a low power rail-to-rail input, rail-to-rail output operational amplifier.</p><p> The aforementioned and other objects, features and advantages of the present invention will become apparent from the following more detailed description of preferred embodiments of the present invention, as shown in the accompanying drawings. In drawings, the same reference character refers to the same part through different figures. The drawings are not necessarily to a constant scale and instead the emphasis is on showing the principles of the invention.</p>

<figref num="1">It is a block diagram of the prior art delay lock loop.</figref><figref num="2">It is a schematic diagram of the prior art charge pump that can be used in the prior art DLL shown in FIG.</figref><figref num="3">It is a graph which shows the source and sink current in the prior art DLL shown in FIG. 2 before the locked state.</figref><figref num="4">It is the schematic of the charge pump by the principle of this invention.</figref><figref num="5">It is a graph which shows the source and sink current in the charge pump shown in FIG. 4 before the locked state.</figref><figref num="6">It is the schematic of the operational amplifier shown in FIG.</figref><figref num="7">FIG. 5 is a schematic array of programmable transistors that can be used in the charge pump of FIG.</figref><figref num="8">It is a block diagram of the prior art phase-locked loop in which a charge pump can be used.</figref><figref num="9">FIG. 5 is a schematic diagram showing another embodiment of a charge pump having a different configuration, including an operational amplifier that controls an operational amplifier that controls a P-MOS device instead of the NMOS transistor shown in the embodiment of FIG.</figref>

Detailed description of the present invention Descriptions of preferred embodiments of the present invention are as follows.

FIG. 4 is a schematic view of the charge pump 300 according to the principle of the present invention . The charge pump 300 includes a plurality of transistors. In the embodiments shown, the transistor is a metal oxide semiconductor (MOS) and is also referred to as a field effect transistor (FET). As is well known to those skilled in the art, there are two types of MOS transistors, n-channel MOS transistors (NMOS) and p-channel MOS transistors (PMOS). The charge pump 300 includes both NMOS and MOSFET transistors. MOSFET transistors are marked with a circle at the gate.

The charge pump 300 includes a current mirror M1 and an active current mirror M3. The current mirror M1 is similar to the current mirror M1 described in the prior art charge pump 200 shown in FIG. The active current mirror M3 includes an operational amplifier (op amp) 323, which actively equalizes the voltage on the node OUT to substantially equal the voltage on the node crtl to the transistor 315. The static phase error is minimized by minimizing the difference between the output (drain) current (charge pump pull-up current) of the transistor 310 and the output (drain) current (charge pump pull-up current) of the transistor 310.

The current mirror M1 includes biased MOSFET transistors 314 and MIMO transistors 310 and 312. Voltage V_bnSets the bias voltage for the current mirror M1 and sets the current through the MOSFET transistor 314. MOSFET transistors 314 and 313 provide a reference current source that supplies current to the pull-down and pull-up circuits. The current through the MOSFET transistor 314 is mirrored in the MOSFET transistors 312 and 310. The current flowing through each transistor in the current mirror can be modified by varying the size (width / length ratio) of these devices, as is well known to those skilled in the art.

The MOSFET device 314 in the current mirror M1 has a bias voltage V at the source-drain connection node of the MOSFET device 314._bnThe initial current is given to the charge pump depending on the voltage given by. When the charge pump is used in a DLL system, the bias voltage adjusts the maximum current of the charge pump according to the total delay of the delay chain so that the ratio between the reference frequency and the DLL bandwidth is constant.

The gate of the MOSFET transistor 314 is connected to the drain of the MOSFET transistor 314. The gates of the MOSFET devices 312 and 310 are connected to the gates of the MOSFET devices 314, allowing this initial current to be mirrored to the MOSFET transistors 312 and 310. The drain of the NMOS device 316 is connected to the drain of the MOSFET device 312. Therefore, the current mirrored in the MOSFET device 312 is the same current given to the NMOS device 316 in the current mirror M3. The gate of the NMOS device 316 is connected to the gate of the NMOS device 315, and the drain current of the NMOS device 316 can be mirrored by the NMOS device 315 in the current mirror M3 to provide a pull-down current.

Generally, when the charge pump is enabled (the signal ENABLE is asserted or driven to logic 1) and the signal UP is asserted, the transistor 309 drives the NAND gates 301, inverters 302 and 304 and passgate 303. It is turned "on" by the voltage applied to the gate of transistor 309 through. This causes current to flow through the MOSFETs 309 and 310 in the pull-up circuit. This current adds charge to the OUT node connected to the loop filter 206 (Figure 1). This increase in charge while transistor 309 is "on" causes an increase in the voltage at the node OUT, which is the voltage control delay line when the charge pump 300 is replaced by the charge pump 105 shown in the prior art DLL 100 shown in FIG. Causes an increase in the delay produced by 102. Similarly, when the charge pump is enabled (ENABLE high) and the signal DOWN is asserted, the transistor 317 is "on" by the voltage applied to the gate via the NAND gate 305 and the inverters 306, 307 and 308. This allows the current to flow through the transistors 315 and 317 of the pull-down circuit. This current flow, grounded from node OUT through transistors 315 and 317, removes charge from node OUT. This reduction in charge while the transistor 315 is "on" reduces the voltage at the node OUT and reduces the delay produced by the voltage control delay line 102 (FIG. 1).

The paths from the UP / DOWN signals at the inputs of NAND gates 302, 306 through inverters 303, 304 and through inverters 307, 308 to the gates of transistors 310 and 315 are matched to provide the same insertion delay. To. The passgate 308 is included in the path so as to replicate the delay added by the inverter 307 in the path from the DOWN signal to the gate of transistor 317. To compensate for the small voltage drop across the source and drain paths of the NMOS transistor 309 when the transistor 309 is "on", the MOSFETs 311 and 313 are added to give symmetry to the current path through the MOSFET 309. The NMOS transistor 318 provides symmetry to the current path through the MOSFET transistor 315.

The current mirror M3 has a pull-down current (grounded through the NMOS transistor 315) and a pull-up current (V)._ddControls the ratio between and through the MOSFET transistor 310). The pull-down current reduces the voltage on the note OUT, and the pull-up current increases the voltage on the node OUT. Therefore, the M1 current mirror sets the maximum current of the charge pump through the MOSFET device 310, and the M3 current mirror controls the ratio between pull-up and pull-down currents. The current mirrors M1 and M3 can be adjustable or programmable using well-known techniques. Transistors 315 and 316 in the current mirror M3 can be sized to send more or less current. This allows the circuit designer to compensate for other factors such as parasitic resistance and capacitance and parameter changes. However, such adjustments are static and cannot be readjusted once the chip is packaged and cannot compensate for voltage changes at the OUT node.

According to one embodiment of the invention, active adjustment of the current mirrors is provided by the use of operational amplifiers, as shown in FIG. The inverting input of the operational amplifier 323 in the active current mirror M3 is connected to the node OUT, and the non-inverting input of the operational amplifier 323 is connected to the node "n14". The output node of the operational amplifier 323 is connected to the node "ctrl" and the gate of the NMOS devices 315 and 316. The operational amplifier 323 adjusts the voltage on the control node "ctrl" when there is a voltage difference between the node OUT and "n14". The change in voltage on the control node "ctrl" causes a corresponding change in the voltage on node OUT and node "n14" via the NMOS devices 315, 316.

During operation of the charge pump, the operational amplifier 323 minimizes static phase error by keeping the voltage on node "n14" substantially equal to the output voltage on node OUT. It is important that the same pull-up and pull-down current pulses can be generated at the output (OUT) when the DLL is locked. In a DLL that has achieved a locked state, the node OUT is not actively charged or discharged most of the time because the UP and DOWN pulses are for equal periods. In addition, the UP and DOWN pulses can be shorter than the prior art charge pumps described in Figure 2, resulting in a reduction in the power required in the device. As a result, the voltage at the node OUT remains substantially constant. The change in voltage at the node "ctrl" causes a corresponding change in the current flowing through the NMOS transistors 315 and 316. However, since the capacitance of the node "n14" is smaller than the capacitance existing at the node OUT, the change in the voltage at the node "ctrl" affects the node "n14" more quickly than the node OUT.

The operational amplifier 323 actively controls the voltage of the node OUT as follows. That is, when the voltage on the node "n14" is higher than the voltage on the node OUT, the operational amplifier 323 increases the voltage on the node "ctrl". Increasing the voltage at node "ctrl" increases the current through the MOSFETs 316 and 315, which reduces the voltage on node "n14" until it is equal to the voltage at node OUT. If the voltage on node "n14" is lower than the voltage on node OUT, the op amp 323 drops the voltage on node "ctrl". This drop in voltage on the node "ctrl" reduces the current flowing through the MOSFETs 316 and 315. The voltage on the node "ctrl" changes the voltage on the node "n14" faster than the voltage on the node OUT, so that a new equilibrium point is reached where the voltage on the node "n14" is equal to the voltage on the node OUT. With the voltage on node "n14" and the output voltage OUT being substantially the same, the source / drain current (pull-down current) through the NMOS device 315 becomes the source / drain current (pull-up current) through the NMOS device 310. Substantially equal.

By providing the charge pump with an active current mirror containing an operational amplifier, the drain, source and gate voltage conditions of the NMOS transistor pairs 315, 316 and the MOSFET pairs 312 and 310 are substantially equal, leading as shown in FIG. It is much closer than a technical circuit, resulting in a matched current through the very accurate MIMO transistors 315 and MOSFET 310. Transistors 319 and 320 are simple buffer capacitances that are coupled within the bias nodes of the current mirrors M1 and M2 to prevent noise caused by the NMOS devices 315 and MOSFETs 310.

The operational amplifier 323 is preferably rail-to-rail (V)._ddFrom V_ss(Ground)) has an input range. In the embodiment in which the transistors 315 and 316 are MOSFET devices as shown in FIG. 4, the required output range is V._ddAbove ground, a predetermined voltage close to it, that is, one threshold voltage (V) of an NMOS transistor above ground._tn). This output voltage range ensures that the NMOS transistors 315 and 316 are not completely "off". This is because the circuit becomes inoperable when it is completely "off". In an alternative embodiment where the transistors 315, 316 are MOSFET devices as shown in FIG. 9, the required output range is V._ssFrom V_tp(Ie V_ddIt is one threshold voltage of the MOSFET transistor below. Therefore, an operational amplifier 323 having a rail-to-rail output range is suitable.

During the power-up phase, if the voltage of the node "n14" is lower than the voltage of the node OUT, the operational amplifier, i.e. the output of the node "ctrl", is driven low. Since the node "ctrl" is connected to the MOSFET device 315, the MOSFET device 315 can be "off". The circuit can stop in this state or take a long time to recover. In either case is undesirable.

The starter circuit, which includes the NMOS device 321 and the NMOS device 322, assists the charge pump in reaching the operating point during the power-up phase. The starter circuit first sets the voltage at node OUT to V_ddSet to a lower value. This allows the operational amplifier 323 to operate properly after the power-up phase. The activation signal asserted for a predetermined period after power-up during the power-up phase is coupled to the gate of the NMOS apparatus 322. The NMOS device 322 is a diode connected to both the gate and the source connected to the node OUT. The drain of the NMOS device 322 is connected to the drain of the NMOS device 321.

The NMOS device 322 is "on" while the start signal coupled to the drain of the NMOS device 321 is asserted. Node OUT is almost V_ddTherefore, with both the MOSFETs 321 and the MOSFETs 322 "on", the current flows through the MOSFETs 321 and 322 and the voltage at the node OUT drops.

Thus, the starter circuit ensures that the voltage at node OUT is lower than the voltage at node "n14" during the power-up phase, so that the different input voltages to the op amp 323 are initially positive and the NMOS device. Keeping 315 on During the start-up phase, the node "ctrl" at the output of the op amp 323 is driven to "high". This makes the node OUT approximately the threshold voltage of the NMOS transistor during this predetermined period. After the power-up phase, the start signal is asserted and stopped, and the start circuit no longer needs to be enabled.

The present invention reduces the current offset, that is, the difference in current flowing between the NMOS transistor 315 and the MOSFET transistor 310 to about 4%. This results in a highly reduced static phase error for the entire DLL system. By reducing the current offset of the charge pump from 20% to 4% in this embodiment, the total static phase error of the PLL / DLL is reduced from 300ps to 60ps.

FIG. 5 is a graph showing the source and sink current pulses in the charge pump shown in FIG. 4 before the locked state. In this embodiment, the trace 154 corresponds to the source current through the transistor 309 in FIG. 4, and the trace 156 corresponds to the sink current through the transistor 317 in FIG. In embodiments according to the invention, the source and sink currents are substantially equal in magnitude. Since Figure 5 shows the pulse before the locked state, the DLL begins to change the voltage at the node OUT in order to find the locked state and align the edges of the source and sink pulses. When the locked state is reached, the regions below the traces 154 and 156 become the same, resulting in a stable level of voltage at the node OUT. When the source and sink currents are substantially equal in magnitude, the pulse edges are more accurately matched, eliminating one of the largest components that causes static phase error.

FIG. 6 is a schematic view of an embodiment of the operational amplifier 323 shown in FIG. Operational amplifiers are based on complementary input pairs that operate at very low voltages. In the embodiment shown, the operational amplifier is V_ddFrom V_ssCan operate with a total power supply voltage of 1V, V_ssIs said to be about 0V (connected to ground).

The operational amplifier 323 includes two different amplifiers 442, 444, a bias circuit 446, and an output stage 440. The differential amplifiers 442, 444 have complementary input pairs including a first differential amplifier with NMOS transistor inputs pairs 411,412 and a second differential amplifier with MOSFET input pairs 404,405. The first differential amplifier 442 also includes MOSFET transistors 403 and NMOS transistors 406, 407. The second differential amplifier 444 also includes MOSFET transistors 409, 410 and NMOS transistors 413.

Output stage 440 includes transistors 401 and 402. The bias circuit includes transistors 414, 415, 416, 417, 418 and 419 and outputs the bias voltage transistor 401 of stage 440, transistor 403 of the first differential amplifier 442, and transistor 413 of the second differential amplifier 444. Give to.

The node OUT shown in FIG. 4 is connected to the differential input inm of each differential amplifier, and the node n14 shown in FIG. 4 is connected to the differential input inp of each differential amplifier. The output stage of the operational amplifier "diff_out" is connected to the node "ctrl" shown in FIG.

When charge pump 300 (Figure 4) is enabled (signal ENABLE is asserted or driven to logic 1), transistor 419 is turned on and current can flow through transistors 416, 417, 418 and 419. It becomes. The current of transistor 409 in the second differential amplifier 444 is mirrored in transistor 408. Transistor 408 provides the output of the second differential amplifier. The current from transistor 404 (representing the output of the first differential amplifier) and the current from transistor 408 (representing the output of the second differential amplifier) are summed in transistor 406 of the first differential amplifier 440. Mirrored by transistor 402 on the output stage. When the charge pump 300 is disabled (the signal ENABLE is stopped asserted or driven to logic 0), transistor 419 is off and the op amp is on the ctrl node because of logic 0 at the gate of transistor 419. Do not modify the voltage.

Another embodiment uses a programmable array master transistor for a reference current source in a current mirror to configure or test the operation of the circuit. FIG. 7 is a schematic representation of such a programmable array of transistors 500, suitable for replacing both transistors 313 and 314 of FIG. The four active row selection signals (SEL0b, SEL1b, SEL2b and SEL3b) are coupled to the four selection MOSFET transistors 501, 502, 503 and 504. Each select transistor is coupled to a different current mirror master MOSFET transistor 505, 506, 507, 508. One or more of the SEL signals are active low, which allows variable current to flow. The magnitude of the current varies depending on the number of SEL signals that are active low. For example, when only SEL0b is active low, current flows only through the MOSFETs 505 and 501, which is mirrored by transistors 312 and 310 in FIG. Since the current flows through the MOSFETs 505, 506, 507 and 508 and all the selection transistors, the magnitude of the current increases with all four selection signals in the active low state. This current is connected to the drains of transistors 310 and 312, V_bnMirrored by transistors 312 and 310 through the node.

The SEL signal can be controlled by register, fuse programming, mask programming or any other technique known to those of skill in the art. Four sets of programmable master transistors are shown, but any number can be used. Programmability can be added by replacing both transistors 416 and 418 in FIG. 4 with programmable arrays of transistors using a similar circuit that uses NMOS transistors.

The present invention is not limited to the charge pump used in the DLL. For example, the present invention can also be used for charge pumps in phase-locked loops. A phase-locked loop (PLL) is another well-known circuit for synchronizing a first clock signal with a second clock signal.

FIG. 8 is a block diagram of the prior art PLL600. The externally supplied clock (CLK) is buffered by the clock buffer 601 and gives a reference clock (CLK_REF) connected to the phase detector 604. The phase detector 604 generates phase control signals (UP, DOWN) depending on the phase difference between CLK_REF and CLK_FB.

The phase control signal (UP / DOWN) of the phase detector 604 is coupled by the charge pump 605 and the loop filter 606, and the variable bias voltage V_CTRLGive 110. Bias voltage V_CTRLControls a voltage controlled oscillator (VCO) 602 that outputs the clock signal CLK_OUT. The frequency of the output clock signal CLK_OUT is the bias voltage V_CTRLIt is proportional to 610. The VCO is well known to those of skill in the art.

The CLK_OUT signal is optionally linked to the distributor 603 to generate the feedback clock signal CLK_FB. If the phase detector detects the rising edge of CLK_REF before the rising edge of CLK_FB, then V_CTRLAsserts an UP signal that increases the frequency of the CLK_OUT signal. If the phase detector detects the rising edge of CLK_FB before the rising edge of CLK_REF, then V_CTRLAsserts a DOWN signal that lowers the frequency of the CLK_OUT signal.

FIG. 9 is a schematic representation of another embodiment of a charge pump having a different configuration, comprising an operational amplifier controlling an operational amplifier that controls a P-MOS device instead of the NMOS transistor shown in the embodiment of FIG. By applying the same principles of the present invention, the op amp 323 equalizes the drains of transistors 310', 312', 315' and 316' in the same manner as described in the embodiments shown in FIG.

The present invention has been described for use with charge pumps in PLL / DLL systems. However, the present invention is not limited to PLL / DLL systems. The present invention can be used in any system where a very precise current mirror is required and the output voltage of the current mirror will not reach ground, which will render the operational amplifier in the active current mirror inoperable. ..

The present invention has been shown and described in detail with reference to a preferred embodiment thereof, but various modifications have been made in form and details without departing from the scope of the invention covered by the appended claims. It will be understood by those skilled in the art.