Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof

The present invention relates to a semiconductor device in which a plurality of field effect transistors are provided on a semiconductor substrate, and a method for manufacturing the same.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or Metal Insulator Semiconductor Field Effect Transistor (MISFET), which uses silicon as a semiconductor substrate and applies polycrystalline silicon to the gate. Has been improved in its performance by means of device fine processing technology, various film forming technologies, and impurity control technology. For example, an integrated circuit element having various functions is configured by combining a plurality of MISFETs exhibiting different threshold voltage characteristics.

However, it is known that by using polycrystalline silicon as the gate electrode, the carriers in the gate electrode are depleted in the inverted state of the MOSFET channel, and the performance deteriorates. As a method for avoiding this, it has been proposed to apply metal, metal silicide, which is a compound of metal and silicon, and metal germanide, which is a compound of metal and germanium, to the gate electrode (Patent Document 1, Non-Patent Document 1, Non Patent Documents 1 and 2).

FIG. 5 is a diagram illustrating a MOSFET in which the metal silicide 506 described in Patent Document 1 is used as a gate electrode as a conventional example 1. In the figure, a source / drain region is formed on the semiconductor substrate 501 with a channel region separated. This source / drain area is LDD (Lightly Doped). It is a structure having a Drain) or a source / drain extension (Extension) 502, and has a low impurity concentration diffusion region in a portion close to the channel region. Moreover, in this source / drain portion, a metal silicide film 504 is formed on the surface of the impurity high concentration region 503 adjacent to the low impurity concentration diffusion region. The semiconductor substrate 501 is an N-type silicon substrate or a P-type silicon substrate, and is a P-type or N-type well region provided on the N-type silicon substrate or the P-type silicon substrate. A gate electrode is formed on the gate insulating film 505. This gate electrode is made of only metal silicide 506. The side wall spacer 507 of the gate electrode has a structure necessary for forming the above-mentioned source / drain region, and here, it is composed of a silicon oxide film and a silicon nitride film. In this conventional example 1, since the gate electrode is made of only metal silicide, the above-mentioned depletion of the gate electrode is solved. The material of the gate insulating film may be a silicon oxide film or a silicon nitride oxide film containing nitrogen. In this conventional example 1, cobalt silicide (CoSi) is added to the metal silicide.₂), NiSi is applied.

FIG. 6 shows the manufacturing method of the MISFET of the conventional example 1 in the order of processes. First, element separation is formed on a P-type or N-type silicon substrate 601 (Fig. 6 (a)). As a method for forming the element separation membrane, for example, there is an embedded element separation method (Shallow Trench Isolation). Well impurities are introduced into the active element portion by an ion implantation method. Then, a gate insulating film is deposited at 1 to 5 nm and polycrystalline silicon at about 50 nm. Next, polycrystalline silicon is processed using lithography and anisotropic etching techniques, and the portion that will later become the gate electrode is selectively left. Here, the polycrystalline silicon that serves as the gate electrode is called the sacrificial gate 602 (Fig. 6 (b)).

Then, the side wall silicon oxide film 603 is formed through an oxidation step. Next, a source / drain extension (low impurity concentration region) 604 is formed by ion implantation (Fig. 6 (c)). After activating RTA (Rapid Thermal annealing) at about 800 ° C., the silicon nitride film spacer 605 is processed and formed using the CVD method and anisotropic etching technology. The source / drain impurity concentration region 606 is then formed by ion implantation and activation RTA. This impurity high concentration region 606 is a deeper junction than the above-mentioned extension (Fig. 6 (d)).

After removing the silicon oxide and the insulating film on the upper surface of the polycrystalline silicon and the surface of the impurity high concentration region 606, a laminated film consisting of two layers in the order of Co / TiN is deposited by a sputtering method. Here, the film thickness of Co is the film thickness required for all of the above-mentioned polycrystalline silicon to be silicidized. In this conventional example 1, the film thickness is 16 nm. TiN functions as an antioxidant film (Fig. 6 (e)). CoSi for polycrystalline silicon using RTA₂Replace with. At the same time, the surface of the high impurity concentration region 606 in the source / drain region is CoSi.₂Will be. The unreacted Co and TiN are then removed by selective etching (Fig. 6 (f)).

After that, although not shown, as in the well-known MISFET, for example, after depositing an insulating film on the entire surface, flattening is performed by CMP treatment, and contacts of each part of the source, drain, and gate are opened, and W (tungsten) is formed there. ) Etc. are embedded to form a MISFET.

According to this manufacturing method, CoSi on the gate insulating film₂It has a gate electrode consisting only of a membrane, and also has a CoSi in the source / drain region.₂A self-aligned silicide electrode configuration with a film is realized. This has the advantage that the metal gate electrode can be formed in exactly the same number of steps as the usual method for producing silicide.

However, in the production method of Conventional Example 1, the bonding depth in the high impurity concentration region of the source / drain is CoSi.₂It is necessary to be deeper than the thickness of. On the other hand, as the device becomes finer, the bonding depth in this impurity high concentration region needs to be made shallower. Therefore, CoSi₂It becomes necessary to reduce the film thickness. In that case, the film thickness of the polycrystalline silicon must be reduced, which causes a problem that the process margin including the processing is reduced.

As a method for solving this problem, there is a method described in Non-Patent Document 3. This will be described with reference to FIG. 7 as Conventional Example 2.

Up to the polycrystalline silicon film formation, it is formed in the same manner as in Conventional Example 1 (Fig. 7 (a)). After forming the gate insulating film 702 and the polycrystalline film silicon 703 on the silicon substrate 701, a hard mask film of a silicon oxide film is formed, and the hard mask 704 is formed by lithography. Polycrystalline silicon is processed by this hard mask 704 and anisotropic etching to form a sacrificial gate 705 of polycrystalline silicon (Fig. 7 (b)).

The source / drain extension (impurity low concentration region) 706, the side wall silicon oxide film 707, and the silicon nitride film spacer 708 are formed in the same manner as in the conventional example 1. Here, it should be noted that the hard mask 704 remains on the polycrystalline silicon when the silicon nitride film spacer 708 is formed by anisotropic etching (Fig. 7 (c)).

Next, an impurity high concentration region 709 of the source / drain is formed by ion implantation, and a metal silicide film is selectively formed on the surface of the impurity high concentration region 709 of the source / drain using the prior art. Examples of the metal silicide that can be used here include NiSi. After forming a film in the order of Ni / TiN, RTA is performed at a temperature of about 450 ° C., and TiN and excess Ni are selectively removed to obtain a metal silicide film. At this point, metal silicide is formed on the surface of the source / drain region, but is absent on the surface of the sacrificial gate 705 due to the presence of the hard mask 704 (Fig. 7 (d)).

After depositing a silicon oxide film as an interlayer insulating film 710 with a film thickness larger than the surface step created by the laminated structure of polycrystalline silicon and hard mask 704, the surface is flattened by CMP and etched back to make the upper surface of polycrystalline silicon. Expose (Fig. 7 (e)). A Ni film is formed and polycrystalline silicon is completely replaced with NiSi by RTA (Fig. 7 (f)).

By the above method, the thickness of the source / drain region silicide and the thickness of the gate electrode silicide can be controlled independently.

As mentioned above, the gate electrode is CoSi.₂, A conventional example of substituting with NiSi has been described. However, as in Non-Patent Document 2, the gate electrode and the source / drain region are made into germanium by using a germanium substrate as the silicon substrate and forming a germanium film on the gate insulating film. You can also do it. Further, by combining the methods described in Non-Patent Document 2 and Non-Patent Document 3, it can be easily inferred that a germanide gate electrode is formed on a silicon substrate. Further, as the silicide, platinum silicide is also effective according to Patent Document 4.

According to Non-Patent Document 1, when a MISFET including a NiSi (nickel mono silicide) gate electrode having a plurality of widths or lengths is integrated on one semiconductor substrate, the production described in Patent Document 1 and Non-Patent Document 3 In the method, at the time of silicidation, the sacrificial gate 801 having a short gate length forms a Ni excess VDD803 having a high Ni content, and the sacrificial gate 802 having a long gate length does not silicide to the gate insulating film interface and is unreacted. It has been pointed out that sacrificial gate 804 will occur (Fig. 8). Non-Patent Document 1 states that the above problem can be solved by performing RTA in order to completely silicide polycrystalline silicon.

FIG. 9 describes the manufacturing method described in Non-Patent Document 1 as Conventional Example 3. First, using the manufacturing method described in Non-Patent Document 3, a step of selectively leaving polycrystalline silicon to be silicated, forming a short sacrificial gate 901 and a long sacrificial gate 902, and exposing the upper surface thereof is performed (up to the step of exposing the upper surface thereof). Figure 9 (a)).

Next, after depositing the Ni film, it is reacted with polycrystalline silicon by RTA to Si / Ni.₂Form a Si laminated structure. That is, Ni on the gate insulating film₂Polycrystalline silicon 903 should be left so that Si does not come into contact (Non-Patent Document 1, Fig. 5) (Fig. 9 (b)). Here, Ni₂The Si film thickness is determined by the amount of Ni deposited, the types of impurities in polycrystalline silicon, and the RTA temperature and time. In particular, the effects of RTA temperature are described in FIGS. 6 and 7 of Non-Patent Document 1. The temperature is preferably 300 ° C or lower, which is lower than the well-known temperature of forming NiSi, which is about 400 ° C. The unreacted metal is selectively etched and removed. After that, by RTA again, the above-mentioned Ni₂Ni diffuses from the Si layer to the lower Si layer, and the metal gate layer in contact with the gate insulating film becomes NiSi (Fig. 9 (c)).

This method solves the problem that the characteristics of MISFETs with multiple gate lengths fluctuate. In addition, Non-Patent Document 1 states that the Ni film thickness to react with polycrystalline silicon is 1.7 times that of polycrystalline silicon.₃Being able to form Si, and Ni₃It is stated that Si exhibits a work function that is 0.1-0.4 eV larger than NiSi. As a result, Ni₃By using Si as a gate electrode, it is possible to lower the threshold voltage of the p-type MISFET.

Non-Patent Document 4 describes a method for forming a silicide gate electrode having a composition in which NiSi and Ni are greater than 1 (Ni-rich) with respect to Si on one wafer. As a result, the NiSi electrode has a work function of about 4.5 eV, and the Ni-rich electrode has a larger work function. In Non-Patent Document 4, the thickness of the polycrystalline silicon to be reacted with Ni is changed between n MOSFET and p MOSFET as in the example of Non-Patent Document 1. By making the thickness of the polycrystalline silicon of the p MOSFET thinner than the thickness of the n MOSFET, NiSi is formed in the n MOSFET and Ni-rich silicide is formed in the p MOSFET. However, in this method, the reaction of Ni depends on the density of the transistor arrangement and the reaction time of Ni and silicon, and the composition ratio of Ni to Si changes. Therefore, normal operation can be expected by fluctuating the threshold voltage of the transistor. It disappears.

In addition, attempts to control the threshold have been made in other literature. Patent Document 2 has a two-layer gate electrode film, uses a silicon film doped with a lower layer conductor and a metal silicide film as an upper layer conductor, and attempts to control the threshold value by changing the film thickness of the lower layer conductor. It is a thing. However, in this method, the workability of the laminated gate electrodes is a problem. In this document, even if the film thickness of the upper conductor film is the same, the film thickness of the lower conductor film is different between the n and p channels. Therefore, at the time of etching for forming the gate electrode, the gate insulating film or the substrate having the smaller film thickness of the lower conductor layer may be exposed first, and the exposed surface may be excessively etched. Furthermore, since the film thickness of the lower layer conductive film is processed to be different between the n and p channel transistors, a silicon oxide film is formed in a part of the layer to be the gate electrode, thereby forming the gate electrode. There is a problem that the etching of the light film becomes difficult.

Patent Document 3 attempts to control the threshold value by separately producing gate electrodes by utilizing the material properties of a fully silicid gate and a partially silicidized gate with silicide. However, there is still the problem of gate depletion in partially silicated gates.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-252462</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2000-243853</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2005-228868</text></patcit><patcit num="4"><text>Japanese Patent Application Laid-Open No. 2005-217275</text></patcit><nplcit num="1"><text>"Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate length," 2005 Symposium on VLSI Technology Digest of Technical papers, pp. 72-73</text></nplcit><nplcit num="2"><text>"Material characterization of Metal-Germanide Gate Electrodes Formed by FUGE (Fully Germanided) Process," Extended Abstract of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, pp. 844-845</text></nplcit><nplcit num="3"><text>"Demonstration of Fully Ni-Silicided Metal Gates on HfO2 based high-k gate dielectrics as a candidate for low power applications," 2004 Symposium on VLSI Technology Digest of Technical papers, pp. 190-191</text></nplcit><nplcit num="4"><text>"CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and NMOS (Ni-rich Silicide) Gates on HfSiON," Technical Digest of 2005 International Electron Device Meeting, pp. 661-664</text></nplcit>

<p> In an LSI, since circuits having various functions are usually integrated, it is necessary to set a plurality of threshold voltages of MISFETs constituting the circuits. It is known that such a plurality of threshold voltages can be obtained by preparing a plurality of gate insulating film thicknesses or a plurality of MISFET channel impurity concentrations. By combining these methods with the method of Non-Patent Document 1, a plurality of threshold voltages can be obtained.</p><p> However, in order to obtain the film thickness of a plurality of gate insulating films, it is necessary to add many lithography steps and processing operations. Further, when the hafnium nitride silicate (HfSiON) described in Non-Patent Document 1 is applied to the gate insulating film, it is difficult to prepare a plurality of film thicknesses on one substrate.</p><p> The threshold voltage can also be controlled by the impurity concentration in the substrate channel region. However, if the concentration is increased in order to increase the threshold voltage, there arises a problem that the charge transport in the channel is deteriorated by scattering due to impurities. Further, if the impurity concentration in the channel region is lowered in order to lower the threshold voltage, the MISFET having a small gate length does not operate normally due to the short channel effect.</p><p> According to Non-Patent Document 4, it is possible to form a silicide having a composition of monosylicide and metal with respect to silicon greater than 1. However, as described in Non-Patent Document 1, the reaction of Ni depends on the density of transistor arrangement and the reaction time of Ni and silicon, and the composition ratio of Ni to Si changes. Therefore, the composition of Ni-rich silicide fluctuates, and the threshold voltage of the transistor fluctuates, so that normal operation cannot be expected.</p><p> The present invention has been made in view of the above circumstances, and in a semiconductor integrated circuit apparatus using a metal insulating film semiconductor field effect transistor having a metal semiconductor compound containing metal and silicon and / or germanium as essential components as a gate electrode. This is an attempt to set a plurality of threshold voltages without adjusting the impurity concentration in the gate insulating film or the channel region.</p>

<p> As a result of diligent studies to solve the above problems, the inventors of the present application are composed of a common component in a plurality of gate electrodes composed of a metal and a metal semiconductor compound containing silicon and / or germanium as essential components, and have only a composition ratio. By making the above different, it was found that a semiconductor device having a plurality of threshold voltages can be obtained while simplifying the process, and the present invention has been completed.</p><p> According to the present invention, MA_xA first transistor including a first gate electrode having a composition represented by, and MA._yA semiconductor device in which a MIS field effect transistor including at least a second transistor including a second gate electrode having a composition represented by is integrated (in the formula, M is W, Mo, Ni, Pt, Ta, Pd, Co, At least one metal element selected from the group consisting of and Ti, where A is silicon and / or germanium, 0 &lt;x 3 and 0 &lt;y 3, x and y are different). Provided.</p><p> Further, according to the present invention, MA_xThe first gate electrode having the composition represented by, MA_yA second gate electrode having a composition represented by, and MA._zFrom a group consisting of a semiconductor device in which a MIS field effect transistor including at least a third gate electrode having a composition represented by (in the formula, M is W, Mo, Ni, Pt, Ta, Pd, Co, and Ti). At least one metal element of choice, A is silicon and / or germanium, 0 &lt;x 3, 0 &lt;y 3, and 0 &lt;z 3, x, y and z are different. ) Is provided.</p><p> With the above-mentioned semiconductor device configuration, a plurality of threshold voltages can be obtained even in wells or channel regions having the same impurity concentration without changing the thickness of the gate insulating film or preparing a plurality of channel regions having different impurity concentrations. Can be set. In addition, good transistor performance is achieved by a simple process without requiring a large number of lithography processes and processing operations.</p><p> In addition, the MA_x,MA_y,Or MA_zMay be formed by reacting at least one of the metal elements with silicon and / or germanium at 500 ° C. or lower.</p><p> In the present invention, A is silicon and / or germanium, which can react with a metal to form a metal semiconductor compound. For example, examples of such a metal semiconductor compound include metal silicide, metal germanide, and metal silicon germanide, and metal silicide is preferable.</p><p> Further, according to the present invention, a step of forming an element separation film on a semiconductor substrate and A step of introducing impurities into the surfaces of a plurality of active element regions separately formed by the element separation membrane, and The step of forming a gate insulating film in the active element region and A step of forming a polycrystalline film on the gate insulating film and selectively etching it to form a plurality of gate electrodes. A step of forming a source / drain region by sandwiching the polycrystalline film and A step of selectively forming a conductive film made of a metal semiconductor compound containing an element of the same type as the element constituting the polycrystalline film as an essential element on the surface of the source / drain region. A step of forming an interlayer insulating film covering the polycrystalline film and the conductive film, and A step of selectively removing the interlayer insulating film to expose the upper surface of the polycrystalline film, and The step of forming a metal film on the upper surface of the exposed polycrystalline film and A step of heating to react the polycrystalline film with the metal film to form a plurality of gate electrodes made of a metal semiconductor compound containing the metal constituting the metal film and the element constituting the polycrystalline film as essential. A step of selectively arranging an element film of the same type as the element constituting the polycrystalline film on a part of the gate electrodes among the plurality of gate electrodes. A step of heating and reacting the gate electrode with the elemental film selectively arranged to form a gate electrode in which the composition ratio of the metal is smaller than the composition ratio before the reaction. A step of selectively removing the unreacted elemental film and Including Provided is a method for manufacturing a semiconductor device in which the elements constituting the polycrystalline film are silicon and / or germanium.</p><p> Further, according to the present invention At least one or more of the polycrystalline films after the step of selectively removing the interlayer insulating film to expose the upper surface of the polycrystalline film and before the step of forming a metal film on the exposed upper surface of the polycrystalline film. Provided is a method for manufacturing a semiconductor device, further comprising a step of selectively reducing the thickness of the above to form polycrystalline films having different thicknesses.</p><p> By further including such a step, the height of the upper surface of the final gate electrode can be brought closer. Therefore, no step is generated after the gate electrode is formed, and the depth of focus margin at the time of lithography can be maintained satisfactorily.</p>

<p> According to the present invention, a plurality of threshold voltages can be set even in the same substrate impurity concentration region without adjusting the impurity concentration in the gate insulating film or the channel region, so that the process can be simplified. .. Further, it is possible to provide a semiconductor device having a plurality of threshold voltages without deteriorating the deterioration of the channel region and without impairing the transistor performance.</p>

The semiconductor device in the present invention is MA._xA first transistor including a first gate electrode having a composition represented by, and MA._yA semiconductor device in which a MIS field effect transistor including at least a second transistor including a second gate electrode having a composition represented by is integrated (in the formula, M is W, Mo, Ni, Pt, Ta, Pd, Co, At least one metal element selected from the group consisting of and Ti, where A is silicon and / or germanium, 0 &lt;x 3 and 0 &lt;y 3, x and y are different). is there. A plurality of threshold voltages can be set by configuring the semiconductor device to include a plurality of transistors having the same composition component and different composition ratios.

Semiconductor devices are MA_zIt may include a third transistor including a third gate electrode having the composition represented by (in the equation, 0 &lt;z 3 and z is different from x and y above). Further, a transistor including a gate electrode having a different composition may be included.

Here, MA showing the composition of the gate electrode_x, MA_y, And MA_zThe description of is expressed based on M for convenience, and does not mean that M is limited to 1. For example, Ni₂A gate electrode having a Si-like composition is also included in the above composition, in which case NiSi according to the above description._0.5It is expressed as.

MA_x, MA_y, Or MA_zIs formed, for example, by reacting at least one of the above metal elements with silicon and / or germanium at 500 ° C. or lower.

Embodiments of the present invention will be described in more detail below with reference to the drawings. In all the drawings, the same components are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

(Embodiment 1) FIG. 1 is a cross-sectional view of the MISFET according to the present embodiment. In the figure, three MISFETs separated by an element-separating insulating film are arranged on a semiconductor substrate. The impurity concentration in the channel region is the same, and the gate insulating film is also the same. The gate electrode is a metal silicide, a metal germanide, or a metal silicon germanide having a different metal composition ratio, and is formed on the same substrate impurity concentration region 101. In the case of metal silicide, for example, NiSi and Ni, respectively.₂Si, Ni₃Si.

In the present embodiment, since the substrate impurity concentration in the channel region can be unified, deterioration of charge mobility due to scattering due to high-concentration impurities in the channel portion can be suppressed.

(Embodiment 2) A second embodiment of the present invention will be described with reference to FIG. For convenience, a cross-sectional view of one transistor will be described here as much as possible, and a cross-sectional view of a plurality of transistors will be used as necessary.

First, an element separation film is formed on the semiconductor substrate by, for example, an embedded element separation method or the like. Impurities are introduced into the surfaces of a plurality of active device regions separately formed by the device separation membrane, for example, by an ion implantation method or the like. Next, a gate insulating film is formed in the active element region.

A polycrystalline film made of silicon is formed on the same impurity concentration region 201 of the semiconductor substrate via a gate insulating film. The polycrystalline film is selectively etched to form a plurality of polycrystalline films 202 having a gate electrode shape. A side wall silicon oxide film is formed through an oxidation step, and a source / drain region is formed with the silicon polycrystalline film 202 sandwiched by an ion implantation method or the like. A conductive film made of metal silicide is selectively formed on the surface of the source / drain region. An interlayer insulating film covering the silicon polycrystalline film 202 and the conductive film is formed. Then, the interlayer insulating film is selectively removed to expose the upper surface of the silicon polycrystalline film 202. By such a procedure, a structure in which only the upper surface of the silicon polycrystalline film 202 is exposed from the interlayer insulating film of the silicon oxide film can be formed (FIG. 2 (a)). The film thickness of the polycrystalline silicon to be silicinated is preferably about 50 nm.

A metal film is formed on the upper surface of the exposed silicon polycrystalline film 202 with a thickness such that the composition ratio of the polycrystalline silicon and the metal becomes excessive. For example, nickel (Ni) having a film thickness of about 1.2 times or more the film thickness of the polycrystalline silicon is deposited on the silicon polycrystalline film 202. For example, the film thickness of Ni is about 80 nm. Next, it is heated to react the silicon polycrystalline film 202 with the metal film to form a gate electrode made of metal silicide having a composition of excess metal. For example, RTA treatment is performed at a temperature of about 300 ° C. for about 150 seconds. As a result, the silicon polycrystalline film 202 completely has a Ni excess composition Silicide (here, Ni).₂Replaced by Si). The unreacted metal is then removed by selective etching (Fig. 2 (b)).

Next, after depositing the silicon film 203 over the entire surface, using lithography and etching techniques, the silicon film 203 is selectively placed in the upper region of at least one or more MISFETs for which the work function of the silicide is desired to be reduced (Fig. 2 (Fig. 2). c)). The film thickness of the silicon film 203 is at least (Ni).₂It is a film thickness defined by (Ni film thickness required to form Si) / (Ni film thickness required to form NiSi)-(polycrystalline silicon film thickness). Here, it is at least about 50 nm.

By heating, the gate electrode made of metal silicide is reacted with the silicon film 203 selectively arranged to form a metal silicide having a reduced metal composition ratio. For example, RTA treatment is performed at a temperature of about 450 ° C. for about 60 seconds. As a result, Ni in the silicide diffuses into the silicon film 203 arranged on the silicide gate electrode, and the gate electrode becomes NiSi. In this case, the temperature is preferably 400 ° C or higher and 500 ° C or lower, and more preferably 400 ° C or higher and 450 ° C or lower. Since NiSi formed on the surface of the source and drain has poor heat resistance, if this temperature is too high, the resistance of the diffusion layer and the leakage current of the diffusion layer may increase. At this time, the gate electrode of the MISFET on which the silicon film is not arranged is Ni.₂It remains Si (Fig. 2 (d)).

The unreacted silicon film 204 is removed by selective etching (Fig. 2 (e)). The selective etching is preferably dry etching using a gas system containing HBr or wet etching using an aqueous KOH solution.

After that, as with the well-known MISFET, for example, after depositing an insulating film on the entire surface, flattening is performed by CMP treatment, contacts of each part of the source, drain, and gate are opened, and W (tungsten) and the like are contained therein. By embedding the plug, a MISFET is formed (not shown).

As mentioned above, NiSi and Ni₂Two types of VDD gate electrodes such as Si can be arranged on one substrate. In the present embodiment, the gate electrode made of two kinds of metal silicide is produced by performing the heat treatment of the gate electrode twice.

(Embodiment 3) As the third embodiment, using FIG. 3, NiSi, Ni₂Si, Ni₃A method for forming three Si silicide gate electrodes will be described.

A second embodiment has a structure in which a silicon polycrystalline film 302 substituted with silicide is arranged on the same substrate impurity concentration region 301 via a gate insulating film, and only the upper surface thereof is exposed from the interlayer insulating film of the silicon oxide film. Form in the same way as the morphology. After that, about 90 nm of Ni is formed on it (Fig. 3 (a)). Regarding the thickness of Ni, for example, according to Non-Patent Document 1, it is required that the film thickness of Ni is 1.7 times or more that of Si with respect to a silicon polycrystalline film of 50 nm.

By heat-treating at RTA condition of about 450 ° C for about 60 seconds, all the silicon polycrystalline film 302 of the gate electrode is Ni excess composition Silicide (here, Ni).₃Substitute with Si) and then remove the unreacted metal (Fig. 3 (b)).

Using lithography and etching techniques, the silicon film 303 is selectively placed in the upper region of the MISFET where the work function of the silicide is to be reduced (Ni).₂Formation of Si) (Fig. 3 (c)). For example, the silicon film thickness is formed at about 25 nm.

Ni under the silicon film 303 selectively placed after heat treatment at a temperature of about 240 ° C.₃Si to Ni₂Change to Si (Fig. 3 (d)). The heat treatment time is the Ni of the silicide gate electrode.₃Si is Ni, at least near the gate insulating film.₂It is the time until it becomes Si. For example, in this case, 1300 seconds or more is preferable. It is preferable to selectively remove the unreacted silicon film 304.

The silicon film 305 is selectively placed in the upper region of the MISFET where the work function of the silicide is desired to be smaller (formation of NiSi) (Fig. 3 (e)). The film thickness of the silicon film 305 is preferably about 100 nm, for example.

Ni under the silicon film 305 selectively arranged in Fig. 3 (e) by heat treatment at about 450 ° C.₃Change Si to NiSi (Fig. 3 (f)). The heat treatment time is the Ni of the VDD gate electrode.₃Let it be the time for Si to become NiSi, at least in the vicinity of the gate insulating film. Again, it is preferable to selectively remove the unreacted silicon film.

Using the above steps, NiSi, Ni on one semiconductor substrate₂Si, Ni₃Three Si silicide gate electrodes are formed. Here, Ni₃Instead of Si, Ni₃₁Si₁₂May be used.

According to this embodiment, three threshold voltages can be set with one channel region impurity concentration. Further, in the present invention, although not shown, the composition is changed after forming Ni-rich silicide or germanide even for gate electrodes having different gate lengths, so that the composition does not change due to the difference in the gate lengths. There are advantages. As a result, fluctuations and deterioration of electrical characteristics such as the threshold voltage are suppressed.

(Embodiment 4) In the embodiments described above, Ni₂The upper surface position of the gate electrode changed to Si and NiSi rises. Therefore, a step is formed on the surface after the formation of the second interlayer insulating film after the formation of the gate electrode by the amount of the change in the height. Next, the fourth embodiment of the present invention in which such a step does not occur will be described with reference to FIG.

"Proposal of new HfSiON CMOS fabrication process (HAMDAMA) for low standby power device," 2004IEDM technology Digest pp.95-98 has a two-layer gate of silicon and NiSi on one semiconductor substrate and all with NiSi. A method for integrating a certain MISFET is described. This document describes a method of producing in-plane a gate that completely replaces silicides and a gate that silicides only the upper surface by arranging sacrificial gate electrodes of different thicknesses in-plane. In this embodiment, the method of obtaining different sacrificial gate electrode thicknesses within the same wafer plane described therein is applied.

A silicon polycrystalline film is formed on the same substrate impurity concentration region 401 via a gate insulating film. The polycrystalline film is selectively etched to form a plurality of polycrystalline films 402 having a gate electrode shape. Only the upper surface forms a structure exposed from the interlayer insulating film of the silicon oxide film (Fig. 4 (a)).

The thickness of at least one or more silicon polycrystalline films is selectively reduced to form silicon polycrystalline films having different thicknesses. For example, the mask 404 is selectively arranged by lithography, and the sacrificial gate electrodes 403 having different thicknesses are formed by anisotropic etching having high selectivity for the silicon oxide film and the silicon nitride film (Fig. 4 (b)). ..

Ni is deposited on the whole, and all sacrificial gate electrodes 403 are Ni by RTA at 450 ° C.₃Completely replaced with Si and Ni excess composition Silicide (Ni₃Si). Selectively remove unreacted Ni and TiN (Fig. 4 (c)). Here, the thickness of Ni is such that at least the thickest sacrificial gate electrode is silicidal to Ni.₃The film thickness required to obtain Si. Further, it is preferable to form TiN on Ni here.

In the same manner as in the second embodiment, a silicon film is placed on the gate electrode for which the work function value is to be reduced, and heat treatment is performed to obtain Ni.₂It is possible to selectively arrange the Si gate electrode and the NiSi gate electrode (Fig. 4 (d) and Fig. 4 (e)).

In the present embodiment, it is possible to suppress an increase in the height of the gate electrode that occurs when a plurality of metal silicide MISFETs having different composition ratios are formed. That is, when the silicidization of the gate electrode is completed, there is almost no step in the height of the upper surface of the gate electrode. Therefore, the depth of focus margin at the time of lithography for contact formation is improved, the contact resistance is increased, and deterioration of transistor characteristics can be suppressed.

Although the embodiments of the present invention have been described above with reference to the drawings, these are examples of the present invention, and various configurations other than the above can be adopted.

For example, in the above embodiment, the description has been made using the example of a specific nickel silicide, but the present invention is not limited to this, and even if the above-mentioned silicide is composed of the same element but has a different composition ratio. Good. Also, MA_x, MA_y, And MA_zAs another example, NiSi and Ni are independent of each other.₂Si, Ni₃Si, Ni₃₁Si₁₂, W₅Si₃, W₃Si, WSi₂, Mo₃Si, Mo₅Si₃, Mo₃Si₂, MoSi₂, Pt₃Si, Pt₂Si, PtSi, Ta_4.5Si, Ta₂Si, Ta₅Si₃, TaSi₂, Pd₃Si, Pd₂Si, PdSi, Co₃Si, Co₂Si, CoSi, CoSi₂, TiSi₃, Ti₅Si₃, TiSi, TiSi₂One selected from the group consisting of. Here, MA_x, MA_y, And MA_zAre components of the same composition, but have different composition ratios. That is, MA_x, MA_y, And MA_zM and A are the same, but the composition ratios are different. Further, although silicon is used for the gate electrode in the above embodiment, germanium or silicon germanium may be used instead of silicon. For example, the gate electrode and the source / drain region can be made into a metal germanium by forming a germanium film on the gate insulating film using a germanium substrate.

<figref num="1">It is sectional drawing of the MISFET which concerns on Embodiment 1. FIG.</figref><figref num="2">It is sectional drawing which shows the manufacturing process of Embodiment 2.</figref><figref num="3">It is sectional drawing which shows the manufacturing process of Embodiment 3.</figref><figref num="4">It is sectional drawing which shows the manufacturing process of Embodiment 4.</figref><figref num="5">It is sectional drawing explaining the prior art example 1. FIG.</figref><figref num="6">It is sectional drawing which shows the manufacturing process of the prior art example 1. FIG.</figref><figref num="7">It is sectional drawing which shows the manufacturing process of the prior art example 2.</figref><figref num="8">It is sectional drawing explaining the problem of the prior art example 3.</figref><figref num="9">It is sectional drawing which shows the manufacturing process of the prior art example 3. FIG.</figref>

Code description

101 Same substrate impurity concentration region 201 Same substrate impurity concentration region 202 Silicon polycrystalline film 203 Silicon film 204 Unreacted silicon film 301 Same substrate impurity concentration area 302 Silicon polycrystalline film 303 Silicon film 304 Unreacted silicon film 305 Silicon film 401 Same substrate impurity concentration region 402 Silicon polycrystalline film 403 sacrificial gate electrode 404 mask 501 silicon substrate 502 Source / Drain Extension 503 Impurity high concentration region 504 Metal Silicide Film 505 Gate insulating film 506 Metal Silicide 507 Side wall spacer Silicon nitride film 601 Silicon substrate 602 Sacrifice Gate 603 Side wall silicon oxide film 604 Source / Drain Extension 605 Silicon Nitride Film Spacer 606 Impurity high concentration region 701 Silicon substrate 702 Gate insulating film 703 Silicon polycrystalline film 704 Hard mask 705 Sacrifice Gate 706 Source / Drain Extension 707 Side wall silicon oxide film 708 Silicon Nitride Film Spacer 709 Impurity high concentration region 710 Interlayer insulating film 801 Short sacrifice gate 802 long sacrifice gate 803 Ni Excess Silicide 804 Unreacted sacrifice gate 901 Short sacrifice gate 902 Long sacrifice gate 903 Silicon polycrystalline film