JP5116901B1

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Abstract

Problem to be solved.To provide a novel non-volatile latch circuit and a semiconductor device using the same. A latch portion having a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of a second element is electrically connected to an input of a first element. And a data holding part that holds the data of the latch part, and the latch part and the data holding part form a non-volatile latch circuit. The data holding unit uses a transistor using an oxide semiconductor as the semiconductor material constituting the channel forming region as the switching element. It also has an inverter electrically connected to the source electrode or drain electrode of this transistor. Using the above transistor, the data held in the latch portion can be written to the gate capacitance of the inverter or a separately prepared capacitance. [Selection diagram] Fig. 1

JP5116901B1, drawing sheet 1 — Sheet 1 of 32

Term

Projected expiry 27 August 2032.

1 claim: 1 independent, 0 dependent

1
ラッチ部と、前記ラッチ部のデータを保持するデータ保持部とを有し、前記データ保持部は、トランジスタと、インバータとを有し、前記トランジスタのチャネル形成領域は、酸化物半導体層を有し、前記トランジスタのソース電極及びドレイン電極の一方は、出力信号が与えられる配線に電気的に接続され、前記トランジスタのソース電極及びドレイン電極の他方は、前記インバータの入力に電気的に接続され、前記インバータの出力は、入力信号が与えられる配線に電気的に接続されていることを特徴とする不揮発性のラッチ回路。

239 paragraphs, as filed

The disclosed invention is a non-volatile logic circuit in which the stored logic state is not erased even when the power is turned off. And semiconductor devices using it. In particular, a non-volatile latch circuit and a semi-conduct using it. Regarding body equipment.

Non-volatile memory that incorporates the property of "nonvolatile" into the logic circuit, which does not erase the memory even when the power is turned off. An integrated circuit that integrates gic has been proposed. For example, non-volatile with a ferroelectric element A latch circuit has been proposed as non-volatile logic (Patent Document 1).

<patcit num="1"><text>International Publication No. 2003/044953</text></patcit>

However, the non-volatile latch circuit using a ferroelectric element has reliability of the number of rewrites and a low voltage. There is a problem in conversion. In addition, the ferroelectric element is polarized by the electric field applied to the element, and this amount Information is memorized by leaving poles. However, if this residual polarization is small, the effect of variation is large. It becomes difficult, and a high-precision readout circuit is required.In view of such problems, one embodiment of the present invention uses a novel non-volatile latch circuit and the like. One of the issues is to provide a semiconductor device.

In one embodiment of the invention, the output of the first element is electrically connected to the input of the second element and the second element. A latch part with a loop structure in which the output of the child is electrically connected to the input of the first element, and a latch It has a data holding part that holds the data of the chi part, and it is not possible due to this latch part and the data holding part. A volatile latch circuit is constructed. The data holding unit constitutes a channel formation region. A transistor using an oxide semiconductor as a semiconductor material is used as a switching element. ing. Also, an inn electrically connected to the source electrode or drain electrode of this transistor. I have a burter. Using the above transistor, the data held in the latch part can be obtained. It is possible to write to the gate capacity of the converter or the capacity prepared separately. In addition, the above Using the Langista, write to the gate capacity of the inverter or the capacity prepared separately. Can hold data.That is, one embodiment of the present invention includes a latch portion and a data holding portion that holds data in the latch portion. have. The data holding unit has a transistor and an inverter, and the transistor The channel formation region has an oxide semiconductor layer, and the source electrode and drain electric power of the transistor. One of the poles is electrically connected to the wiring to which the output signal is given and is the source electrode of the transistor. And the other of the drain electrodes are electrically connected to the input of the inverter and the output of the inverter A non-volatile latch circuit is constructed by being electrically connected to the wiring to which the input signal is given. It is made.In the above, the data holding unit can have a capacitance in addition to the transistor and the inverter. To. The above capacitance can be used for writing and holding the data held in the latch portion. Wear. One electrode of the above capacitance is connected to the other of the source electrode and the drain electrode of the transistor. It can be used by being connected to the air.In the above, the latch portion has a first element and a second element, and the output of the first element is the first. It is electrically connected to the input of the second element, and the output of the second element is electrically connected to the input of the first element. It has a loop structure that is continued. Further, the input of the first element is arranged so that an input signal is given. Electrically connected to the wire, the output of the first element is electrically connected to the wiring to which the output signal is given. Has a structure that has been created. For example, an inverter is used as the first element, and the second element is used. And an inverter can be used. Also, for example, NAND is used as the first element, and the first element is used. A clocked inverter can be used as the element of 2.In the above, the transistor transfers the data held in the latch part to the data holding part a. It has a function to write to the gate capacity of the converter or the capacity prepared separately. Also, Write the Langista in the gate capacity of the inverter of the data holding unit or the capacity prepared separately. It has a function to retain the crowded data.In the above, the oxide semiconductor layer formed of the oxide semiconductor material is used as the channel forming region. The transistor used has, for example, a channel width W of 1 × 10.4At μm, the channel length is 3 μm Even if it is an element, the off current at room temperature is 1 x 10-13Below A, Subthresholds A characteristic with an ing value (S value) of about 0.1 V / dec. (Gate insulating film thickness 100 nm) can be obtained. Is done. Therefore, the off-current when the voltage between the gate and the source electrode is almost 0, that is, The leakage current is significantly smaller than that of a transistor using silicon. Therefore, Chan-hae A transistor using an oxide semiconductor layer in the formation region is used as a switching element. Therefore, even after the supply of the power supply voltage to the latch circuit was stopped, it was accumulated in the capacity of the data holding unit. The charge can be retained as it is. That is, the data written in the data holding unit Can be kept as it is. In addition, the supply of power supply voltage to the latch circuit starts again. After that, the data held in the data holding unit can be read out. This will It can be restored to the logical state before the power supply voltage supply was stopped. Also, the temperature characteristics are high. It is possible to obtain a product in which the off-current is sufficiently low and the on-current is sufficiently high even at warm temperature. For example, this The Vg-Id characteristics of the transistor are off-current and on-current in the range of -25 ° C to 150 ° C. Data have been obtained that the temperature dependence of flow, mobility, and S value is small. In this way, the main departure The Ming dynasty has a wide temperature operating range, operates stably even at high temperatures, and remembers even when the power is turned off. It provides a non-volatile latch circuit in which the logical state does not disappear.In the above, various logic circuits can be provided by using a non-volatile latch circuit. Can be done. Further, various semiconductor devices using the above logic circuit can be provided. .. For example, among a plurality of block circuits of a logic circuit, one or a plurality of unused blocks The supply of power supply voltage to the circuit can be stopped. Use the above non-volatile latch circuit Therefore, even after the supply of the power supply voltage to the block circuit is stopped, the logical state of the block circuit is recorded. I can keep remembering. Also, after the supply of power supply voltage to the block circuit is restarted. In addition, the stored logical state can be read out. As a result, the supply of power supply voltage is stopped. It can be restored to the previous logical state.In the above, the oxide semiconductor layer is In-Ga-Zn-O type, In-Sn-O type, In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z nO system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn -O-based, In-O-based, Sn-O-based, and Zn-O-based materials can be used. Also, oxidation As the material semiconductor layer, one containing indium, gallium, and zinc can be used. Ma In addition, the hydrogen concentration of the oxide semiconductor layer is 5 × 10.19/cm3Below, preferably 5x1018/ cm3Below, more preferably 5x1017/cm3Below, more preferably 1x1016/ cm3Below, more preferably 1x1016/cm3Can be less than. Also, oxidation The carrier concentration of the semiconductor layer is 1 × 10.14/cm3Less than, preferably 1x1012/cm3Less than, more preferably 1x1011/cm3Can be less than. Also, transition The off current of the star at room temperature is 1 x 10-13It can be A or less.In the above, the transistor using the oxide semiconductor may be a bottom gate type. , Top gate type may be used. Also, it may be a bottom contact type or a top. It may be a contact type. Bottom gate transistors are at least on the insulating surface The gate electrode, the gate insulating film on the gate electrode, and the gate electrode on the gate insulating film. It has an oxide semiconductor layer serving as a channel forming region. Top gate type transistor At least on the oxide semiconductor layer, which is the channel formation region on the insulating surface, and on the oxide semiconductor layer. Has a gate insulating film and a gate electrode that overlaps the oxide semiconductor layer on the gate insulating film. To. Bottom contact transistors form channels on the source and drain electrodes It has an oxide semiconductor layer as a region. Top contact type transistor forms a channel It has a source electrode and a drain electrode on the oxide semiconductor layer as a region.In the present specification and the like, terms such as "upper" and "lower" have a positional relationship of components "directly above". Or, it does not limit that it is "directly under". For example, "Gate on the gate insulating layer The expression "electrode" excludes those containing other components between the gate insulating layer and the gate electrode. Do not remove. In addition, the terms "above" and "below" are merely expressions used for convenience of explanation, and are particularly words. Except for cases where the top and bottom are swapped, the top and bottom are also included.Further, in the present specification and the like, the terms "electrode" and "wiring" functionally limit these components. It is not fixed. For example, "electrodes" are sometimes used as part of "wiring" The reverse is also true. Furthermore, the terms "electrode" and "wiring" refer to multiple "electrodes" and "distribution". It also includes the case where "lines" are integrally formed.In addition, the "source" and "drain" functions can be used when using transistors with different polarities. , When the direction of the current changes in the circuit operation, it may be replaced. For this reason , In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.Further, in the present specification and the like, "electrically connected" means "having some kind of electrical action". Included when connected via. Here, "something that has some kind of electrical action" Is not particularly limited as long as it enables the exchange of electric signals between the connection targets.For example, "things that have some kind of electrical action" include not only electrodes and wiring, but also tigers. Switching elements such as engineers, resistance elements, inductors, capacitors, and various other machines Elements having a function and the like are included.

According to one embodiment of the present invention, an oxide semiconductor is used as a semiconductor material constituting a channel forming region. By using the used transistor as a switching element of the data holding unit, temperature operation It has a wide range and operates stably even at high temperatures, and the memorized logical state does not disappear even when the power is turned off. A latch with a built-in latch circuit or a data holding unit with a sufficiently long refresh period. The circuit can be realized. Data writing by transistor switching Since this is done, there is virtually no limit to the number of rewrites. Also, the write voltage is a transistor. It is about the threshold voltage of, and can operate at a low voltage. For example, the operating voltage is about 1V Or less. In addition, the electric charge accumulated in the capacity of the data holding unit is the Since it is retained as data as it is, it varies compared to the case where the residual polarization component is used as data. It is not easily affected by the data, and the data can be easily read.By using the above non-volatile latch circuit, it is possible to realize various logic circuits. is there. For example, in a logic circuit using a non-volatile latch circuit, the power supply of the unused block Power consumption can be reduced by turning off. Also, even if the power is turned off, the logical state Since it remembers the state, when the system starts when the power is turned on or when the power is turned off It is possible to terminate the system at high speed and with low power consumption.

<figref num="1">The figure which shows an example of the structure of the non-volatile latch circuit.</figref><figref num="2">The figure which shows an example of the structure of a part of a non-volatile latch circuit.</figref><figref num="3">The figure which shows an example of the cross section and the plane of the element which a non-volatile latch circuit has.</figref><figref num="4">The figure which shows an example of the manufacturing method of the element which a non-volatile latch circuit has.</figref><figref num="5">The figure which shows an example of the manufacturing method of the element which a non-volatile latch circuit has.</figref><figref num="6">The figure which shows an example of the manufacturing method of the element which a non-volatile latch circuit has.</figref><figref num="7">The figure which shows an example of the cross-sectional structure of the reverse stagger type transistor using an oxide semiconductor.</figref><figref num="8">The energy band diagram (schematic diagram) in the A-A'cross section of FIG.</figref><figref num="9">(A) Positive potential (+ V) at gate (GE1)G) Indicates a given state, and (B) a negative potential (-V) at the gate (GE1).G) Is given.</figref><figref num="10">Vacuum level and metal work function (φM), The figure which shows the relationship of electron affinity (χ) of an oxide semiconductor.</figref><figref num="11">The figure which shows the energy required for hot carrier injection in silicon (Si).</figref><figref num="12">The figure which shows the energy required for hot carrier injection in an oxide semiconductor (IGZO) of an In-Ga-Zn-O system.</figref><figref num="13">The figure which shows the energy required for hot carrier injection in silicon carbide (4H-SiC).</figref><figref num="14">The figure which shows the result of the device simulation about the short channel effect.</figref><figref num="15">The figure which shows the result of the device simulation about the short channel effect.</figref><figref num="16">The figure which shows the CV characteristic.</figref><figref num="17">Vg and (1 / C)2The figure which shows the relationship with.</figref><figref num="18">The figure which shows an example of the structure of the non-volatile latch circuit.</figref><figref num="19">The figure which shows an example of the structure and operation of the non-volatile latch circuit.</figref><figref num="20">The figure which shows an example of the structure and operation of the non-volatile latch circuit.</figref><figref num="21">The figure which shows an example of the structure and operation of the non-volatile latch circuit.</figref><figref num="22">The figure which shows an example of the structure of the non-volatile latch circuit.</figref><figref num="23">The figure which shows an example of the semiconductor device which used the non-volatile latch circuit.</figref><figref num="24">The figure which shows an example of the structure of the non-volatile latch circuit.</figref><figref num="25">The figure which shows an example of the evaluation result of the non-volatile latch circuit.</figref>

Embodiments and examples of the present invention will be described below with reference to the drawings. However, The present invention is not limited to the following description. Deviation from the gist of the present invention and its scope It is easily understood by those skilled in the art that the form and details can be changed in various ways without it. Because it is done. Therefore, the present invention describes the following embodiments and examples. It is not limited to interpretation. In addition, in explaining the structure of this invention using a drawing. Or, the symbols that refer to the same thing are commonly used between different drawings.

The size, layer thickness, or region of each configuration shown in the drawings and the like of each embodiment is , May be exaggerated for clarity. Therefore, not necessarily on that scale Not limited.

In addition, terms using ordinal numbers such as the first, second, and third used in the present specification refer to components. It is attached for convenience of identification, and does not limit the number.

(Embodiment 1) This embodiment is a configuration, operation, and non-conformity of a non-volatile latch circuit, which is one aspect of the disclosed invention. Fig. 1, Fig. 2, Fig. 3 to Fig. 6, Fig. 1, regarding the manufacturing method of the element of the volatile latch circuit, etc. This will be described with reference to FIGS. 7 to 17.

<Construction and operation of non-volatile latch circuit> FIG. 1 (A) shows the latch portion 411 and the data holding portion 401 for holding the data of the latch portion. The configuration of the non-volatile latch circuit 400 having the same is shown. Figure 1 (B) shows the data holding unit 4 The configuration of 01 is shown.

In the non-volatile latch circuit 400 shown in FIG. 1 (A), the output of the first element (D1) 412 is the first. Electrically connected to the input of the second element (D2) 413, the output of the second element (D2) 413 Latch section 41 having a loop structure electrically connected to the input of the first element (D1) 412 It has 1 and a data holding unit 401 for holding data of the latch unit.

The input of the first element (D1) 412 is connected to the wiring 414 to which the input signal of the latch circuit is given. It is connected airily. The output of the first element (D1) 412 is given by the output signal of the latch circuit. It is electrically connected to the obtained wiring 415.

When there are multiple inputs of the first element (D1) 412, one of them is the input signal of the latch circuit. It can be electrically connected to the wiring 414 given the number. Second element (D2) 413 If there are multiple inputs, one of them is electrically connected to the output of the first element (D1) 412. Can continue.

The first element (D1) 412 uses an element in which the input signal is inverted and the output is output. be able to. For example, the first element (D1) 412 has an inverter and NAND. ), NOR, clocked inverter, etc. can be used. Also, the second element (D2) 413 can use an element whose output is the inverted signal of the input signal. To. For example, the second element (D2) 413 has an inverter, NAND, and NOR. (Noah), clocked inverter, etc. can be used.

The data holding unit 401 uses an oxide semiconductor as a semiconductor material constituting the channel forming region. The transistor 402 that was used is used as a switching element. This transistor 402 One of the source electrode and the drain electrode of the above is electrically connected to the wiring 415 to which the output signal is given. It is being continued. Further, the data holding unit 401 includes the source electrode of the transistor 402 and the data holding unit 401. It has a capacitance 404 and an inverter 403 that are electrically connected to the other side of the drain electrode. .. That is, the capacitance 404 is on the other side of the source electrode and the drain electrode of the transistor 402. One of the electrodes of the inverter 403 and the input (input terminal) of the inverter 403 are electrically connected. this One of the electrodes with a capacity of 404, the input of the inverter 403, and the source electrode of the transistor 402. The node to which the other of the drain electrode is electrically connected is called a node S. The potential Vc is given to the other end of the electrode with a capacitance of 404.

The output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is given. To. The inverter 403 has a transistor 420 and a transistor 421. To The source electrode of the Langista 420 is electrically connected to a high level supply voltage VDD .. The source electrode of transistor 421 is electrically connected to the low-level power supply voltage VSS. There is.

The inverter 403 is not limited to the configuration shown in FIG. 1 (B), and is, for example, as shown in FIG. 2 (A). , N-channel transistor 420, N-channel transistor 421 may be used. However, a buffer may be provided in the output. Also, instead of the inverter 403, Sensua A pump circuit may also be used. For example, the differential amplification type sense amplifier times as shown in Fig. 2 (B). You may use the road. The differential amplification type sense amplifier circuit as shown in Fig. 2 (B) has N channels. Le-type transistors 421, N-channel transistors 501 and 502, and P-channel transistors It is composed of Langista 503 ~ 506. In either case, the input (input terminal) is float. It is important to be in a winging state (high impedance state).

The transistor 402 using this oxide semiconductor is held in the latch portion 411. A machine that writes data to the capacity 404 of the data holding unit 401 and the gate capacity of the inverter 403. Has the ability. Further, the transistor 402 has a capacity 404 of the data holding unit 401 and a. It has a function to hold the data written in the gate capacity of the converter 403.

Writing, holding, and reading the data held in the latch section 411 to the data holding section 401. The operation of squeezing out and rewriting will be described. First, the gate electrode of the transistor 402 Supply the potential to turn on the Langista 402 and turn on the transistor 402. .. As a result, the data held in the latch portion, that is, the wiring 4 to which the output signal is given. Fifteen potentials are applied to one electrode of capacitance 404 and the input terminal of inverter 403. So As a result, one electrode of the capacity 404 and the gate capacity of the inverter 403 have the wiring 415. Charges corresponding to the electric potential are accumulated (writing). After that, the gate electrode of the transistor 402 The potential of the transistor 402 is set as the potential at which the transistor 402 is turned off, and the transistor 402 is turned off. By setting the state, it accumulates in one electrode of the capacity 404 and the gate capacity of the inverter 403. The charged charge is retained (retained). One electrode of this capacity 404 and the inverter 403 Data can be read by reading the potential of the input terminal (reading). ). The data can be rewritten in the same manner as the above-mentioned data writing and holding.

The oxide semiconductor layer of the transistor 402 is an In-Ga-Zn-O system or In-Sn-. O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, A l-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system , Al-Zn-O type, In-O type, Sn-O type, Zn-O type materials are desired to be used. I.

The oxide semiconductor layer is highly purified by sufficiently removing impurities such as hydrogen. Is desirable. Specifically, the hydrogen concentration of the oxide semiconductor layer is 5 × 10.19/cm3Below, hope 5 × 1018/cm3Below, more preferably 5x1017/cm3Below, more hope Even better, 1x1016/cm3Below, more preferably 1x1016/cm3Less than. The carrier concentration of the oxide semiconductor layer is 1 × 10.14/cm3Less than, preferably 1x1012/cm3Less than, more preferably 1x1011/cm3Can be less than. Also The oxide semiconductor layer, which has a sufficiently reduced hydrogen concentration and is highly purified, is a general silicon wafer. Carry in c (silicon wafer to which a small amount of impurity elements such as phosphorus and boron are added) A Concentration (1 x 10)14/cm3Take a sufficiently small carrier concentration value compared to the degree) ..

In this way, the hydrogen concentration is sufficiently reduced and purified, and the carrier concentration is sufficiently low, i. Very good off-current characteristics by using typed or substantially i-shaped oxide semiconductors A sex transistor 402 can be obtained. For example, the channel width W is 1 × 10.4In μm Even if the channel length L is 3 μm, the drain voltage Vd applied to the drain electrode is +. In the case of 1V or + 10V, the gate voltage Vg applied to the gate electrode is from -5V. In the range of -20V, the off current at room temperature is 1 × 10.-13A or less. Also, the temperature In terms of characteristics, a transistor with sufficiently low off-current and sufficiently high on-current can be obtained even at high temperatures. Can be done. For example, the Vg-Id characteristic of transistor 402 is in the range of -25 ° C to 150 ° C. Data show that the temperature dependence of off-current, on-current, mobility, and S value is small. It has been. The hydrogen concentration in the oxide semiconductor layer is determined by secondary ion mass spectrometry (SIMS: S). It was measured by econdary Ion Mass Spectroscopy) To.

The oxide semiconductor constituting the oxide semiconductor layer is not particularly limited as long as it has a non-single crystal structure. I. For example, amorphous structure, microcrystal (microcrystal, nanocrystal, etc.) structure, poly Crystal structure, structure containing microcrystals and polycrystals in amorphous, microcrystals and polycrystals on the surface of amorphous structure Various structures such as a crystal-formed structure can be applied.

In this way, the hydrogen concentration is sufficiently reduced and purified, and the carrier concentration is sufficiently low, i. Switch transistor 402 using a typed or substantially i-shaped oxide semiconductor By using it as an element, even after the supply of power supply voltage to the latch circuit 400 is stopped, The charge accumulated in the capacity 404 of the data holding unit 401 and the gate capacity of the inverter 403 is poled. It can be held for a long time. That is, it is written in the data holding unit 401. The crowded data can be retained for an extremely long time. Also, the latch circuit 4 After the supply of the power supply voltage to 00 is restarted, the data held in the data holding unit 401 Can be read. This restores the logical state before the power supply voltage supply was stopped. be able to. In this way, the hydrogen concentration is sufficiently reduced and the purity is increased, and the carrier concentration is increased. Transistors with sufficiently low, i-shaped or substantially i-shaped oxide semiconductors 40 By using 2 as a switching element, the temperature operating range is wide and it operates stably even at high temperatures. Realize a new non-volatile latch circuit that does not erase the stored logical state even when the power is turned off. be able to.

Among the elements of the non-volatile latch circuit 400, the elements other than the transistor 402 are half. A material other than the oxide semiconductor can be used as the conductor material. Materials other than oxide semiconductors As, single crystal silicon, crystalline silicon and the like can be used. For example, Tran Elements other than the Gista 402 can be provided on a substrate containing a semiconductor material. Semiconductor materials Substrates including silicon wafers and SOI (Silicon on Insulato) r) A substrate, a silicon film on an insulating surface, etc. can be used. Materials other than oxide semiconductors By using, high-speed operation becomes possible.

Among the elements of the non-volatile latch circuit 400, the elements other than the transistor 402 are It is also possible to use an oxide semiconductor as the semiconductor material.

<Planar configuration and cross-sectional configuration of the element of the non-volatile latch circuit> FIG. 3 shows a transistor 402 included in the non-volatile latch circuit and a transistor 402. This is an example of the configuration of elements other than the above. Here, as an element other than the transistor 402, the data A transistor 421 included in the inverter 403 of the holding unit 401 will be described as an example. Transi Other elements other than the star 402 shall have the same or similar configuration as the transistor 421. Can be done. Elements such as capacitance 404 are other than transistor 402 or transistor 402. It can be formed by using the film constituting the element. Fig. 3 (A) shows the cross section, and Fig. 3 (B) shows the cross section. Indicates a plane. Here, FIG. 3 (A) shows lines A1-A2 and B of FIG. 3 (B). Corresponds to the cross section in 1-B2. Acid at the bottom, as shown in Figures 3 (A) and 3 (B) A transistor 421 using a material other than a compound semiconductor is provided, and an oxide semiconductor is used at the top. The transistor 402 that was used is provided.

The transistor 421 is a channel forming region 11 provided on the substrate 100 containing the semiconductor material. 6 and the impurity region 114 provided so as to sandwich the channel formation region 116 and the high concentration non-concentration Pure region 120 (collectively referred to as impurity region) and channel formation region 11 6 The gate insulating layer 108a provided on the gate insulating layer 108a and the gate provided on the gate insulating layer 108a. Source or drain electrode 1 that electrically connects electrode 110a to impurity region 114 It has 30a, a source electrode or a drain electrode 130b.

Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Further, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from a plane, A high-concentration impurity region 120 exists, and a metal compound region 124 is present on the high-concentration impurity region 120. Exists. Further, on the substrate 100, the element separation insulating layer 1 surrounds the transistor 421. 06 is provided, and the interlayer insulating layer 126 and the interlayer are provided so as to cover the transistor 421. An insulating layer 128 is provided. Source electrode or drain electrode 130a, source electrode Alternatively, the drain electrode 130b is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the mouth. That is, the source electrode The drain electrode 130a, the source electrode or the drain electrode 130b is the metal compound region 1 It is electrically connected to the high-concentration impurity region 120 and the impurity region 114 via 24. .. Further, the gate electrode 110a includes a source electrode or a drain electrode 130a or a source electrode. Alternatively, the electrode 130c provided in the same manner as the drain electrode 130b is electrically connected. ..

The transistor 402 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate. A gate insulating layer 138 provided on the electrode 136d and a gate insulating layer 138 provided on the gate insulating layer 138. The oxide semiconductor layer 140 and the oxide semiconductor layer 140 provided on the oxide semiconductor layer 140 Electrically connected source or drain electrode 142a, source or drain It has an in-electrode 142b and.

Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided to be crowded. Also, like the gate electrode 136d, the source electrode or drain The electrode 136a is in contact with the in electrode 130a and is in contact with the source electrode or the drain electrode 130b. The electrode 136b is in contact with the electrode 130c, and the electrode 136c is formed.

Further, the transistor 402 is protected so as to be in contact with a part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. There is. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or a dray. An opening is provided to reach the electrode 142a, the source electrode or the drain electrode 142b. The electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode through the opening. It is formed in contact with the pole 142a, the source electrode or the drain electrode 142b. Also, electricity At the same time as the formation of the pole 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, and the layer Electrodes 136a, 136b, 136c through the openings provided in the inter-insulation layer 146. An electrode 150a, an electrode 150b, and an electrode 150c in contact with the electrode 150c are formed.

Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. It is desirable that it is. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10.19/cm3Below, preferably 5x1018/cm3Below, more preferably 5x1017/cm3Below, more preferably 1x1016/cm3Below, more preferably 1x1016/cm3Less than. The carrier concentration of the oxide semiconductor layer 140 is 1 × 10.14/cm3Less than, preferably 1x1012/cm3Less than, more preferably 1x1011/cm3Not yet Can be full. In addition, oxide semiconductors with sufficiently reduced hydrogen concentration and high purity Layer 140 is a general silicon wafer (a small amount of impurity elements such as phosphorus and boron are added. Carrier concentration (1 x 10) in silicon wafer)14/cm3Degree) compared to ten Takes a small carrier concentration value per minute. In this way, the hydrogen concentration is sufficiently reduced to improve the purity. For i-type or substantially i-type oxide semiconductors with sufficiently low carrier concentration Therefore, a transistor 402 having extremely excellent off-current characteristics can be obtained. example For example, the channel width W is 1 × 10.4Drain even if the device is μm and the channel length L is 3 μm When the drain voltage Vd applied to the electrode is + 1V or + 10V, it is applied to the gate electrode. When the applied gate voltage Vg is in the range of -5V to -20V, the off current at room temperature is 1 ×. Ten-13A or less. The hydrogen concentration in the oxide semiconductor layer is determined by secondary ion mass spectrometry. Measured with (SIMS: Secondary Ion Mass Spectroscopy) It is a fixed one.

Further, an insulating layer 152 is provided on the interlayer insulating layer 146 and is buried in the insulating layer 152. Electrodes 154a, electrodes 154b, electrodes 154c, and electrodes 154d are provided so as to be inserted. ing. Here, the electrode 154a is in contact with the electrode 150a, and the electrode 154b is the electrode 150. In contact with b, electrode 154c is in contact with electrode 150c and electrode 150d, electrode 1 54d is in contact with electrode 150e.

That is, in the element of the non-volatile latch circuit shown in FIG. 3, the transistor 421 The gate electrode 110a and the source electrode or drain electrode 142a of the transistor 402 However, via the electrode 130c, the electrode 136c, the electrode 150c, the electrode 154c and the electrode 150d. And are electrically connected.

<Method of manufacturing the element of the non-volatile latch circuit> Next, an example of a method for manufacturing the element of the non-volatile latch circuit will be described. Less than First, the method of manufacturing the lower transistor 421 will be explained with reference to Fig. 4. After that, the method of manufacturing the upper transistor 402 will be described with reference to FIGS. 5 and 6. ..

<How to make the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4 (A)). Groups containing semiconductor materials The plate 100 includes a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. , Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. To. Here, when a single crystal silicon substrate is used as the substrate 100 containing the semiconductor material. An example will be shown. In general, "SOI substrate" is half silicon on the insulating surface. A substrate having a structure provided with a conductor layer, but in the present specification and the like, silicon is provided on an insulating surface. It is used as a concept including a substrate having a structure in which a semiconductor layer made of a material other than the above is provided. In other words , The semiconductor layer of the "SOI substrate" is not limited to the silicon semiconductor layer. Also, SOI The substrate also has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. Is also included.

A protective layer 102 serving as a mask for forming the element separation insulating layer is formed on the substrate 100. (See Figure 4 (A)). Examples of the protective layer 102 include silicon oxide and silicon nitride. An insulating layer used as a material such as silicon nitride oxide can be used. Before and after this process An impurity that imparts n-type conductivity in order to control the threshold voltage of the transistor. An element or an impurity element that imparts p-type conductivity may be added to the substrate 100. Semiconductors In the case of con, for example, phosphorus or arsenic is used as an impurity that imparts n-type conductivity. be able to. Impurities that impart p-type conductivity include, for example, boron and alumini. Umm, gallium and the like can be used.

Next, etching is performed using the above protective layer 102 as a mask, and the protective layer 102 is covered. Remove a part of the substrate 100 in the non-exposed area (exposed area). Half separated by this A conductor region 104 is formed (see Figure 4 (B)). For the etching, dry etching It is preferable to use wet etching, but wet etching may also be used. Etching gas and d The etching solution can be appropriately selected depending on the material to be etched.

Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region superimposing on the semiconductor region 104. The element-separated insulating layer 106 is formed by selectively removing the insulating layer of (see FIG. 4 (B)). ). The insulating layer is formed by using silicon oxide, silicon nitride, silicon nitride, etc. Is done. As a method of removing the insulating layer, there are polishing treatment such as CMP and etching treatment. , Any of them may be used. After forming the semiconductor region 104, or element separation insulation After the formation of the layer 106, the protective layer 102 is removed.

Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. To.

The insulating layer will be the gate insulating layer later, and can be obtained by using the CVD method, sputtering method, etc. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide A single-layer structure or a laminated structure of a film containing um, tantalum oxide, etc. is preferable. Besides, high density By oxidizing and nitriding the surface of the semiconductor region 104 by razuma treatment or thermal oxidation treatment. , The above insulating layer may be formed. High-density plasma processing is, for example, He, Ar, Kr, X. Perform using a rare gas such as e, or a mixed gas such as oxygen, nitric oxide, ammonia, nitrogen, and hydrogen. be able to. The thickness of the insulating layer is not particularly limited, but is, for example, 1 nm or more and 100 n. It can be less than or equal to m.

The layer containing the conductive material is a metal material such as aluminum, copper, titanium, tantalum, and tungsten. Can be formed using. In addition, semiconductor materials such as polycrystalline silicon containing conductive materials May be used to form a layer containing a conductive material. The forming method is also not particularly limited, and the vapor deposition method, C Various film forming methods such as the VD method, the sputtering method, and the spin coating method can be used. In addition, in this embodiment, it is an example of the case where the layer containing the conductive material is formed by using the metal material. It shall be shown.

Then, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. a, the gate electrode 110a is formed (see Fig. 4 (C)).

Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 4 (C)). And Impurities with shallow bonding depth by adding phosphorus (P) or arsenic (As) to the semiconductor region 104 It forms region 114 (see Figure 4 (C)). Here, an n-type transistor is formed. Phosphorus and arsenic are added for this purpose, but when forming a p-type transistor, boron (B) Impurity elements such as aluminum (Al) and aluminum (Al) may be added. In addition, in the impurity region 114 Due to the formation, the channel forming region 11 is below the gate insulating layer 108a of the semiconductor region 104. 6 is formed (see Figure 4 (C)). Here, the concentration of impurities to be added should be set appropriately. However, when the semiconductor element is highly miniaturized, it is desirable to increase its concentration. I'm sorry. Further, here, the step of forming the impurity region 114 after forming the insulating layer 112 is performed. Although it is adopted, it is also used as a step of forming the insulating layer 112 after forming the impurity region 114. good.

Next, the sidewall insulating layer 118 is formed (see FIG. 4 (D)). Sidewall insulation After forming an insulating layer so as to cover the insulating layer 112, the layer 118 has a high degree of anisotropy in the insulating layer. It can be formed in a self-aligned manner by applying an etching treatment. Also, at this time In addition, the insulating layer 112 is partially etched to form the upper surface of the gate electrode 110a and the impurity region. It is good to expose the upper surface of 114.

Next, cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. As such, an insulating layer is formed. Then, in the region in contact with the impurity region 114, phosphorus (P) and arsenic (As) and the like are added to form the high-concentration impurity region 120. After that, the above insulating layer is removed. Remove the gate electrode 110a, sidewall insulating layer 118, high-concentration impurity region 120, etc. A metal layer 122 is formed so as to cover it (see FIG. 4 (E)). The metal layer 122 is vacuum-deposited. It can be formed by using various film forming methods such as a method, a sputtering method, and a spin coating method. To. The metal layer 122 is metallized with low resistance by reacting with the semiconductor material constituting the semiconductor region 104. It is desirable to form it using a metal material that is a mixture. Examples of such metal materials include For example, there are titanium, tantalum, tungsten, nickel, cobalt, platinum and the like.

Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This makes it high A metal compound region 124 in contact with the concentration impurity region 120 is formed (see FIG. 4 (F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of 0a that comes into contact with the metal layer 122.

As the heat treatment, for example, a heat treatment by irradiation with a flash lamp can be used. To. Of course, other heat treatment methods may be used, but chemical reactions related to the formation of metal compounds In order to improve the controllability of, it is desirable to use a method that can realize heat treatment in a very short time. Good. The above metal compound region is formed by the reaction between the metal material and the semiconductor material. This is a region in which the conductivity is sufficiently enhanced. Forming the metal compound region As a result, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. In addition, metal compounds After forming the region 124, the metal layer 122 is removed.

Next, the interlayer insulating layer 126 and the interlayer insulating layer are covered so as to cover each structure formed by the above steps. Form 128 (see Figure 4 (G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 are made of oxide. Recon, Silicon Nitride, Silicon Nitride, Hafnium Oxide, Aluminum Oxide, Ta It can be formed by using a material containing an inorganic insulating material such as nutal. Also, polyimide, It can also be formed using an organic insulating material such as acrylic. In addition, here, the interlayer is interrupted. It has a two-layer structure consisting of an edge layer 126 and an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is limited to this. Not done. After the interlayer insulating layer 128 is formed, the surface thereof is subjected to CMP or etching treatment. Therefore, it is desirable to flatten it.

After that, an opening reaching the metal compound region 124 is formed in the interlayer insulating layer, and the opening is formed. Source electrode or drain electrode 130a, source electrode or drain electrode 130b Form (see Figure 4 (H)). Source electrode or drain electrode 130a or source electrode For the drain electrode 130b, for example, the PVD method or the CVD method is used in the region including the opening. After forming the conductive layer, a part of the conductive layer is used by etching or CMP. Can be formed by removing.

The source electrode or drain electrode 130a or the source electrode is provided by removing a part of the conductive layer. Alternatively, when forming the drain electrode 130b, process it so that its surface is flat. Is desirable. For example, after forming a thin titanium film or titanium nitride film in the area including the opening, If a tungsten film is formed so as to be embedded in the opening, it will not be possible due to the subsequent CMP. Removes required tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. Can be made to. In this way, the source electrode or drain electrode 130a, the source electrode Alternatively, by flattening the surface including the drain electrode 130b, it is good in a later process. It is possible to form favorable electrodes, wirings, insulating layers, semiconductor layers, and the like.

Here, the source electrode or the drain electrode 130 that comes into contact with the metal compound region 124 Only a and the source electrode or drain electrode 130b are shown, but in this step, An electrode that comes into contact with the electrode electrode 110a (for example, the electrode 130c in FIG. 3A) is provided. Can be formed together. Source or drain electrode 130a, source electrode or There is no particular limitation on the material that can be used as the drain electrode 130b, and various guides Electrical materials can be used. For example, molybdenum, titanium, chrome, tantalum, tongue By using conductive materials such as stainless steel, aluminum, copper, neodymium, scandium, etc. Wear.

As described above, the transistor 421 using the substrate 100 containing the semiconductor material is formed. Na After the above steps, electrodes, wiring, an insulating layer and the like may be further formed. Wiring structure and By adopting a multi-layer wiring structure consisting of a laminated structure of an interlayer insulating layer and a conductive layer, the height is increased. It is possible to provide a semiconductor device integrated every time.

<How to make the upper transistor> Next, using FIGS. 5 and 6, a transistor 402 is formed on the interlayer insulating layer 128. I will explain about it. Note that FIGS. 5 and 6 show various electrodes on the interlayer insulating layer 128 and tigers. Since it shows the manufacturing process of the engineer 402, etc., it exists at the bottom of the transistor 402. Transistors 421 and the like are omitted.

First, the interlayer insulating layer 128, the source electrode or the drain electrode 130a, the source electrode or the dowel. An insulating layer 132 is formed on the rain electrode 130b and the electrode 130c (see FIG. 5 (A)). Absolute The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. Also, Sirico Oxidation , Silicon Nitride, Silicon Nitride, Hafnium Oxide, Aluminum Oxide, Tanta Oxide It can be formed by using a material containing an inorganic insulating material such as le.

Next, with respect to the insulating layer 132, the source electrode or drain electrode 130a, the source electrode or An opening is formed to reach the drain electrode 130b and the electrode 130c. At this time, later An opening is also formed in the region where the gate electrode 136d is formed. And in the above opening The conductive layer 134 is formed so as to be embedded (see FIG. 5 (B)). Use a mask for the above opening It can be formed by a method such as etching. A photomask was used as the mask. It can be formed by a method such as exposure. Wet etching as etching Either etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching may be used. It is preferable to use ching. The conductive layer 134 is formed by a PVD method, a CVD method, or the like. It can be done using the membrane method. As a material that can be used for forming the conductive layer 134 , Molybdenum, titanium, chrome, tantalum, tungsten, aluminum, copper, neodymium , Conductive materials such as scandium, alloys and compounds (eg nitrides) of these, etc. Be done.

More specifically, for example, a titanium film is thinly formed in the region including the opening by the PVD method, and the CV is formed. After forming a thin titanium nitride film by the D method, a tungsten film is formed so as to be embedded in the opening. The method of making can be applied. Here, the titanium film formed by the PVD method is a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, saw) Function to reduce contact resistance with the electrode or drain electrode 130b, electrode 130c, etc.) Have. Further, the titanium nitride film formed thereafter is a burr that suppresses the diffusion of the conductive material. It has a function. In addition, after forming a barrier film made of titanium, titanium nitride, etc., plating is performed. A copper film may be formed by the method.

After forming the conductive layer 134, the conductive layer 1 is formed by using a method such as etching treatment or CMP. Part of 34 is removed to expose the insulating layer 132, electrode 136a, electrode 136b, electrode 1 36c, gate electrode 136d is formed (see Fig. 5 (C)). The conductive layer 134 Partially removed to form electrode 136a, electrode 136b, electrode 136c, gate electrode 136d When doing so, it is desirable to process it so that the surface is flat. Thus, the insulating layer 13 2. Flatten the surfaces of electrode 136a, electrode 136b, electrode 136c, and gate electrode 136d. As a result, good electrodes, wiring, insulating layers, semiconductor layers, etc. are formed in a later process. It becomes possible.

Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d. A gate insulating layer 138 is formed so as to cover the above (see FIG. 5 (D)). Gate insulating layer 138 Can be formed by using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon nitride oxide, aluminum oxide, oxidation. It is preferably formed so as to contain hafnium, tantalum oxide and the like. In addition, gate insulation The layer 138 may have a single-layer structure or a laminated structure. For example, as a raw material gas , Silane (SiH)4), By plasma CVD method using oxygen and nitrogen, it is not silicon oxide nitride. The gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. In the case of a laminated structure , For example , a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer. It is preferable to laminate a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the layer.

It should be noted that an oxide semiconductor (high) that has been i-shaped or substantially i-shaped by removing impurities. Purified oxide semiconductors) are extremely sensitive to interface states and interfacial charges. When an oxide semiconductor such as the above is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. Is. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is a high-quality product. Quality will be required.

For example, the high-density plasma CVD method using microwaves (2.45 GHz) is dense and has a dielectric strength. It is preferable in that a high-quality gate insulating layer 138 can be formed. Highly purified oxide half The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be a favorite.

Of course, a purified acid can be used as a gate insulating layer to form a high-quality insulating layer. Even when using a compound semiconductor layer, other people such as sputtering method and plasma CVD method The law can be applied. In addition, the heat treatment after formation modifies the film quality and interfacial properties. Insulation layer may be applied. In any case, the film quality as the gate insulating layer 138 is good. At the same time, those that can reduce the interface state density with the oxide semiconductor layer and form a good interface. It should be formed.

In addition, 85 ° C, 2 × 106V / cm, 12 hour gate bias / thermal stress test (B) In the T test), if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is cut by a strong electric field (B: bias) and high temperature (T: temperature), and is raw. The unbonded hand formed will induce a drift of the threshold voltage (Vth).

On the other hand, impurities of oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, and as described above, By improving the interface characteristics with the insulation layer, the transition is stable even for BT tests. It is possible to obtain data.

Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching using a mask is performed. The oxide semiconductor layer is processed by a method such as, to form an island-shaped oxide semiconductor layer 140. (See Fig. 5 (E)).

As the oxide semiconductor layer, In-Ga-Zn-O system, In-Sn-Zn-O system, In-A l-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn -O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer. In this embodiment, the oxide half Amorphous oxide using an In-Ga-Zn-O based metal oxide target as the conductor layer The semiconductor layer is formed by a sputtering method. In addition, in the amorphous oxide semiconductor layer, By adding recon, the crystallization can be suppressed, so for example, SiO2To The oxide semiconductor layer may be formed by using a target containing 2% by weight or more and 10% by weight or less.

As a target for producing the oxide semiconductor layer by the sputtering method, for example, oxidation A zinc-based metal oxide target can be used. Also, In, Ga, And a metal oxide target containing Zn (as a composition ratio, In2O3: Ga2O3: Zn It is also possible to use O = 1: 1: 1 [mol ratio] or the like. Also, In, Ga, and Zn As a metal oxide target, including In2O3: Ga2O3: ZnO = 1: 1: 2 [m ol ratio], or In2O3: Ga2O3: ZnO = 1: 1: 4 [mol ratio] composition ratio A target or the like may be used. Filling rate of metal oxide target is 90% or more 10 It is 0% or less, preferably 95% or more (for example, 99.9%). Metal oxide with high filling rate By using the target, a dense oxide semiconductor layer is formed.

The formation atmosphere of the oxide semiconductor layer is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides have a concentration of several ppm or less (desired). It is preferable to use a high-purity gas that has been removed to a concentration of several ppb or less).

When forming the oxide semiconductor layer, the substrate is held in a processing chamber kept in a reduced pressure state, and the substrate temperature is maintained. The degree is 100 ° C or more and 600 ° C or less, preferably 200 ° C or more and 400 ° C or less. Heat the substrate By forming the oxide semiconductor layer while increasing the concentration of impurities contained in the oxide semiconductor layer. Can be reduced. In addition, damage due to sputtering is reduced. And the processing room Introduce a sputter gas from which hydrogen and water have been removed while removing the residual water in the metal oxide. The oxide semiconductor layer is formed with the target. To remove residual water in the treatment chamber , It is preferable to use an adsorption type vacuum pump. For example, cryopump, ion pump , Titanium sublimation pumps can be used. In addition, as an exhaust means, tar It may be a bopump with a cold trap added. Exhaust using a cryopump In the film forming chamber, for example, hydrogen atom, water (H)2Compounds containing hydrogen atoms such as O) (Preferably, a compound containing a carbon atom) and the like are exhausted, so that the oxidation formed in the film forming chamber is performed. The concentration of impurities contained in the semiconductor layer can be reduced.

As the forming conditions, for example, the distance between the substrate and the target is 100 mm, and the pressure is 0.6. Pa, direct current (DC) power is 0.5kW, atmosphere is oxygen (oxygen flow rate ratio 100%) atmosphere, Such conditions can be applied. If you use a pulsed direct current (DC) power supply, it will be garbage. Is preferable because the film thickness distribution can be reduced and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer is 2 nm or more. Upper 200 nm or less, preferably 5 nm or more and 30 nm or less. In addition, the applied oxide half The appropriate thickness varies depending on the conductor material, so the thickness should be selected appropriately according to the material used. Good.

Before forming the oxide semiconductor layer by the sputtering method, argon gas is introduced into the plastic. Reverse sputtering that generates shavings is performed to remove dust adhering to the surface of the gate insulating layer 138. It is preferable to leave. Here, the reverse sputtering is, in normal sputtering, sputtering. Where the ions collide with the target, conversely, by colliding the ions with the treated surface Is a method of modifying the surface. As a method of colliding ions with the treated surface , Apply high frequency voltage to the treated surface side in an argon atmosphere to generate plasma near the substrate. There is a way to do it. Even if nitrogen, helium, oxygen, etc. are used instead of the argon atmosphere. good.

Etching of the oxide semiconductor layer can be either dry etching or wet etching. May be used. Of course, both can be used in combination. Egg to the desired shape Etching conditions (etching gas, etching solution, d) according to the material so that ching can be performed. Set the hatching time, temperature, etc. as appropriate.

Etching gas used for dry etching includes, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), Boron chloride (BCl)3), Silicon chloride (SiCl)4),Carbon tetrachloride( CCl4) Etc.) and so on. In addition, a gas containing fluorine (fluorine-based gas, for example, tetrafluorinated coal) Elementary (CF)4), Sulfur hexafluoride (SF6), Nitrogen trifluoride (NF3), Trifluoromethane (C HF3) Etc.), hydrogen bromide (HBr), oxygen (O2), Helium (He) in these gases Or a gas to which a rare gas such as argon (Ar) is added, or the like may be used.

As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma: induction A coupled plasma) etching method can be used. You can etch to the desired shape Etching conditions (the amount of power applied to the coil-type electrode, applied to the electrode on the substrate side) The amount of electric power, the electrode temperature on the substrate side, etc.) are set appropriately.

The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid. Ammonia superwater (mixture of ammonia, water, hydrogen peroxide solution) and the like can be used. Ma Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

Next, it is desirable to perform the first heat treatment on the oxide semiconductor layer. By this first heat treatment The oxide semiconductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is It is set to 300 ° C or more and 750 ° C or less, preferably 400 ° C or more and less than the strain point of the substrate. For example The substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 has a nitrogen atmosphere. Heat treatment is performed at 450 ° C for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. Prevent re-mixing of water and hydrogen without touching.

The heat treatment device is not limited to the electric furnace, but heat conduction from a medium such as heated gas, or It may be a device that heats an object to be processed by heat radiation. For example, GRTA (Gas) Rapid Thermal Anneal) device, LRTA (Lamp Rapid) RTA (Rapid Thermal Ann) for Thermal Anneal equipment, etc. eal) Equipment can be used. LRTA equipment is halogen lamp, metal halide Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats an object to be processed by the radiation of light (electromagnetic waves) emitted from a lamp such as a silver lamp. is there. The GRTA device is a device that performs heat treatment using high-temperature gas. As a gas, a A rare gas such as Lugon, or an inert substance such as nitrogen that does not react with the object to be treated by heat treatment. Gas is used.

For example, as the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 ° C to 700 ° C. Is charged and heated for several minutes, and then GRTA treatment is performed to remove the substrate from the inert gas. You may. The GRTA treatment enables high temperature heat treatment in a short time. Also for a short time Since it is a heat treatment, it can be applied even under temperature conditions exceeding the strain point of the substrate.

The first heat treatment is mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to perform the operation in an atmosphere that does not contain water, hydrogen, or the like. For example , Purity of nitrogen to be introduced into the heat treatment equipment, or rare gas such as helium, neon, argon, etc. 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (ie) , Impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

In addition, when an electric furnace is used for the first heat treatment, the atmosphere is switched when the temperature of the heat treatment is lowered. Can be done. For example, the atmosphere during heat treatment can be changed to an inert gas such as nitrogen, or helium or ne. The atmosphere is a rare gas such as on or argon, and the atmosphere is switched when the temperature drops to contain oxygen. You can be worried. The atmosphere containing oxygen includes oxygen gas or oxygen gas and nitrogen gas. Can be used as a mixed gas. Even when using this oxygen-containing atmosphere, in the atmosphere It is preferable that water, hydrogen, etc. are not contained in the water. Or, pure oxygen gas and nitrogen gas to be used The degree is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, ( That is, the impurity concentration is preferably 1 ppm or less, preferably 0.1 ppm or less).

The oxide semiconductor layer crystallizes depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. However, it may be microcrystal or polycrystal. For example, the crystallization rate is 90% or more, or 80. It may be an oxide semiconductor layer of% or more microcrystals. Also, the conditions of the first heat treatment, or Depending on the material of the oxide semiconductor layer, a field that becomes an amorphous oxide semiconductor layer that does not contain crystal components There is also a case.

In addition, fine crystals (particle size of 1 nm or more) are formed on an amorphous oxide semiconductor (for example, the surface of an oxide semiconductor layer). It is an oxide semiconductor layer in which upper 20 nm or less (typically 2 nm or more and 4 nm or less) is mixed. In some cases.

In addition, by arranging microcrystals in amorphous material, the electrical characteristics of the oxide semiconductor layer are changed. It is also possible. For example, acid using an In-Ga-Zn-O based metal oxide target When forming a compound semiconductor layer, In has electrical anisotropy.2Ga2ZnO7Crystal grain It is possible to change the electrical characteristics of the oxide semiconductor layer by forming microcrystal parts oriented with. it can.

More specifically, for example, In2Ga2ZnO7C-axis is perpendicular to the surface of the oxide semiconductor layer By orienting in a direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. Therefore, the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Also, this The microcrystal part such as is a function of suppressing the invasion of impurities such as water and hydrogen into the oxide semiconductor layer. Have.

The oxide semiconductor layer having the above-mentioned microcrystal portion is the oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. In addition, the Zn content is In or Ga content. By using a smaller sputter target, it is possible to form more preferably.

The first heat treatment on the oxide semiconductor layer 140 processes the island-shaped oxide semiconductor layer 140. It can also be applied to the previous oxide semiconductor layer. In that case, after the first heat treatment, is it a heating device? The substrate will be taken out and a photolithography process will be performed.

The above heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. , Dehydration treatment, dehydrogenation treatment and the like. Such dehydration treatment, dehydrogenation After the oxide semiconductor layer is formed, the treatment is performed on the oxide semiconductor layer 140 with a source electrode or a drain. After laminating the electrodes, after forming a protective insulating layer on the source electrode or drain electrode, etc. It is possible to do it at the timing of. In addition, such dehydration treatment and dehydrogenation treatment The reason is not limited to once, but may be performed multiple times.

Next, the source electrode or the drain electrode 142a, so as to be in contact with the oxide semiconductor layer 140, Form the source or drain electrode 142b (see Figure 5 (F)). Source electrode The drain electrode 142a, the source electrode or the drain electrode 142b is the oxide semiconductor layer 1 By forming a conductive layer so as to cover 40, and then selectively etching the conductive layer. Can be formed.

The conductive layer is PVD (Physical Vapor Depo) including the sputtering method. CVD (Chemical Vapor) such as sition) method and plasma CVD method It can be formed using the Deposition) method. Also, as a material for the conductive layer , Aluminum, chrome, copper, tantalum, titanium, molybdenum, tungsten It is possible to use an exposed element, an alloy containing the above-mentioned element as a component, or the like. Of the materials mentioned above Instead manganese, magnesium, zirconium, beryllium, thorium, yttrium A material selected from any one or more of the above may be used. Also, on aluminum Choose from tongue, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A material in which the above elements are singular or a combination of a plurality of the above elements may be used. The conductive layer has a single layer structure It may be a laminated structure of two or more layers. For example, aluminum containing silicon Single-layer structure of membrane, two-layer structure in which titanium film is laminated on aluminum film, titanium film and aluminum An example is a three-layer structure in which a um film and a titanium film are laminated. Also, In-Ga-Zn- O system, In-Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system , Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn-O series oxides A conductive film can be used. In this case, compared with the material used for the oxide semiconductor layer 140. , It is preferable to use a material having a high conductivity or a low resistivity for the oxide conductive film. Oxide The conductivity of the conductive film can be increased by increasing the carrier concentration. Oxide conductive film The carrier concentration can be increased by increasing the hydrogen concentration. In addition, the oxide conductive film key Charia concentration can be increased by increasing oxygen deficiency.

Here, the exposure at the time of forming the mask used for etching includes ultraviolet rays, KrF laser light, and ArF. It is preferable to use laser light.

The channel length (L) of the transistor is the lower end of the source electrode or drain electrode 142a. , Determined by the distance from the lower end of the source or drain electrode 142b. In addition, it should be noted. When exposure is performed so that the channel length (L) is less than 25 nm, it is several nm to several tens of nm. And mass using Extreme Ultraviolet with extremely short wavelength Exposure of the formation. Exposure with ultra-ultraviolet rays has a high resolution and a large depth of focus. Therefore, Design so that the channel length (L) of the transistor formed later is less than 25 nm. That is, the channel length (L) can be 10 nm or more and 1000 nm or less. It is possible, and the operating speed of the circuit can be increased. Furthermore, since the off-current value is extremely small, it is turned off. Power costs do not increase.

It should be noted that the oxide semiconductor layer 140 is not removed during the etching of the conductive layer. Adjust each material and etching conditions as appropriate. It depends on the material and etching conditions. Therefore, in the process, a part of the oxide semiconductor layer 140 is etched, and the groove portion (recess) is formed. ) May be an oxide semiconductor layer.

Also, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide half An oxide conductive layer is formed between the conductor layer 140 and the source electrode or drain electrode 142b. You may. Oxide conductive layer and source electrode or drain electrode 142a or source electrode The conductive layer for forming the drain electrode 142b must be continuously formed (continuous film formation). It is possible. The oxide conductive layer can function as a source region or a drain region. like this By providing an oxide conductive layer, it is possible to reduce the resistance of the source region or drain region. Therefore, high-speed operation of the transistor is realized.

Further, in order to reduce the number of masks used and the number of processes, exposure in which the transmitted light has a plurality of intensities. A resist mask is formed by a multi-tone mask, which is a mask, and etching is performed using this. You may do so. The resist mask formed by using the multi-gradation mask has a plurality of thicknesses. It is different because it has a staircase shape and can be further deformed by ashing. It can be used in a plurality of etching steps for processing a pattern. In other words, one multi-gradation Depending on the mask, a resist mask corresponding to at least two or more different patterns is formed. Can be done. Therefore, the number of exposure masks can be reduced and the corresponding photolithography can be performed. Since the graphic process can be reduced, the process can be simplified.

After the above step, N2O, N2, Or plasma treatment with gas such as Ar It is preferable to do. By the plasma treatment, on the surface of the exposed oxide semiconductor layer Adhering water etc. is removed. In addition, plasma treatment is performed using a mixed gas of oxygen and argon. You may go.

Next, the protective insulating layer 14 that comes into contact with a part of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 5 (G)).

The protective insulating layer 144 is prepared by mixing impurities such as water and hydrogen into the protective insulating layer 144 by a sputtering method or the like. It can be formed by appropriately using a method that does not allow it. Also, its thickness is at least 1 nm or more. It is on top. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and the like. There are silicon oxide and silicon nitride. Further, the structure may be a single layer structure, or may be a single layer structure. It may be a laminated structure. The substrate temperature when forming the protective insulating layer 144 is 300 ° C above room temperature. The atmosphere is preferably a rare gas (typically argon) atmosphere and an oxygen atmosphere. , Or a mixed atmosphere of a rare gas (typically argon) and oxygen is preferable.

When hydrogen is contained in the protective insulating layer 144, the hydrogen invades the oxide semiconductor layer and is caused by hydrogen. Oxygen is extracted from the oxide semiconductor layer, causing the back channel side of the oxide semiconductor layer to The resistance may be lowered and parasitic channels may be formed. Therefore, the protective insulating layer 14 It is important not to use hydrogen in the formation method so that 4 does not contain hydrogen as much as possible. is there.

Further, it is preferable to form the protective insulating layer 144 while removing the residual water in the treatment chamber. acid Make sure that the compound semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups, or water. To make it.

In order to remove the residual water in the treatment chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. preferable. In addition, as an exhaust means, a turbo pump with a cold trap added. You may. The film forming chamber exhausted by using the cryopump is, for example, hydrogen atoms or water (H).2Since compounds containing hydrogen atoms such as O) have been removed, they are formed in the film formation chamber. The concentration of impurities contained in the protective insulating layer 144 can be reduced.

The sputtering gas used to form the protective insulating layer 144 includes hydrogen, water, hydroxyl groups, or Impurities such as hydrides are removed to a concentration of several ppm or less (preferably, a concentration of several ppb or less). It is preferable to use the removed high-purity gas.

The second heat treatment (preferably 20) is then performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform 0 ° C or more and 400 ° C or less, for example, 250 ° C or more and 350 ° C or less). For example , Perform a second heat treatment at 250 ° C for 1 hour in a nitrogen atmosphere. When the second heat treatment is performed, the tiger It is possible to reduce the variation in the electrical characteristics of the engineer.

In addition, even if heat treatment is performed in the air at 100 ° C or more and 200 ° C or less, for 1 hour or more and 30 hours or less. Good. This heat treatment may be performed while maintaining a constant heating temperature, or from room temperature to 100 ° C. or higher. Raising the temperature to a heating temperature of 200 ° C and lowering the temperature from the heating temperature to room temperature are repeated multiple times. You may. Further, this heat treatment may be performed under reduced pressure before forming the protective insulating layer. Under reduced pressure The heating time can be shortened by performing the heat treatment with. The heat treatment is the second above. It may be performed instead of the heat treatment, or may be performed before or after the second heat treatment.

Next, the interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6 (A)). Intersection The edge layer 146 can be formed by using the PVD method, the CVD method, or the like. Also, Sirico Oxidation , Silicon Nitride, Silicon Nitride, Hafnium Oxide, Aluminum Oxide, Tanta Oxide It can be formed by using a material containing an inorganic insulating material such as le. Formation of interlayer insulation layer 146 After that, it is desirable to flatten the surface by a method such as CMP or etching. I'm sorry.

Next, the electrode 1 is applied to the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening reaching the electrode or drain electrode 142b is formed and embedded in the opening. The conductive layer 148 is formed (see FIG. 6 (B)). The above opening is etched with a mask, etc. It can be formed by the method of. The mask can be used for methods such as exposure using a photomask. Therefore, it can be formed. Wet etching and dry etching are used for etching. Either ching may be used, but from the viewpoint of microfabrication, dry etching should be used. Is suitable. The conductive layer 148 is formed by using a film forming method such as a PVD method or a CVD method. be able to. Materials that can be used to form the conductive layer 148 include molybdenum and chi. Tan, chrome, tantalum, tungsten, aluminum, copper, neodymium, scandium These include which conductive materials, their alloys, compounds (eg nitrides) and the like.

Specifically, for example, a titanium film is thinly formed in the region including the opening by the PVD method, and the CVD method is used. After forming a thin titanium nitride film, a tungsten film is formed so as to be embedded in the opening. Method can be applied. Here, the titanium film formed by the PVD method is at the interface. The oxide film is reduced, and the lower electrodes (here, electrodes 136a, 136b, 136c, and so on) are used. Contact with loose electrode or drain electrode 142a, source electrode or drain electrode 142b) It has a function to reduce tactile resistance. Further, the titanium nitride film formed thereafter is a conductive material. It has a barrier function that suppresses the diffusion of charges. In addition, a barrier film made of titanium, titanium nitride, etc. After forming the copper film, a copper film may be formed by a plating method.

After forming the conductive layer 148, the conductive layer 148 is formed by a method such as etching or CMP. The interlayer insulating layer 146 is exposed by removing a part of the electrode 150a, the electrode 150b, and the electrode 1. Form 50c, electrode 150d, and electrode 150e (see Fig. 6 (C)). In addition, the said conductive layer With a part of 148 removed, electrode 150a, electrode 150b, electrode 150c, electrode 150d, electricity When forming the pole 150e, it is desirable to process it so that the surface is flat. This As described above, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By flattening the surface of the electrode 150e, good electrodes, wiring, and isolation can be achieved in later processes. It is possible to form an edge layer, a semiconductor layer, and the like.

Further, an insulating layer 152 is formed, and an electrode 150a, an electrode 150b, and an electrode 1 are formed on the insulating layer 152. Form an opening that reaches 50c, electrode 150d, and electrode 150e, and embed it in the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. , The insulating layer 152 is exposed, and the electrode 154a, the electrode 154b, the electrode 154c, and the electrode 154. Form d (see Figure 6 (D)). The process is the same as when forming the electrode 150a or the like. Since there is, the details are omitted.

When the transistor 402 is manufactured by the method as described above, the hydrogen concentration of the oxide semiconductor layer 140 Degree is 5 × 1019atoms / cm3And at room temperature of transistor 402 Off current is 1 x 10-13It becomes A or less. Such hydrogen concentration is sufficiently reduced By applying the highly purified oxide semiconductor layer 140, the transistor 40 with excellent characteristics You can get 2. In addition, a transistor 42 that uses a material other than an oxide semiconductor at the bottom Semiconductor with excellent characteristics having 1 and having a transistor 402 using an oxide semiconductor on the top The device can be made.

As a semiconductor material that can be compared with an oxide semiconductor, silicon carbide (for example, 4H) -SiC) is available. Oxide semiconductors and 4H-SiC have some things in common. Ca Rear density is one example. According to the Fermi-Dirac distribution, a small number of oxide semiconductors Charia is 10-7/cm3Estimated to be a degree, but this is 6.7 in 4H-SiC × 10-11/cm3Similar to, it is an extremely low value. Intrinsic carrier density of silicon (1. 4x1010/cm3Compared to the degree), it is well understood that the degree is extraordinary. Wear.

The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, which is 4H-S. Since the energy bandgap of iC is 3.26eV, it is called a wide-gap semiconductor. In this respect as well, oxide semiconductors and silicon carbide are common.

On the other hand, there are extremely large differences between oxide semiconductors and silicon carbide. It's Rothes temperature. Semiconductor processes using silicon carbide are generally at 1500 ° C to 2000 ° C. Since heat treatment is required, it is difficult to form a laminated structure with a semiconductor element using another semiconductor material. .. This is because semiconductor substrates, semiconductor elements, etc. are destroyed at such high temperatures. .. On the other hand, oxide semiconductors are 300 to 500 ° C (below the glass dislocation temperature, at most 700 ° C). It can be manufactured by heat treatment (degree), and an integrated circuit was formed using other semiconductor materials. Above, it becomes possible to form a semiconductor element made of an oxide semiconductor.

Also, unlike the case of silicon carbide, it is possible to use a substrate with low heat resistance such as a glass substrate. Has the advantage of being. Furthermore, it is compared with silicon carbide in that it does not require heat treatment at high temperature. It has the advantage that the energy cost can be sufficiently lowered.

In addition, in oxide semiconductors, the Institute for Solid State Physics such as DOS (density of state) Although much research has been done, these studies have the idea of reducing DOS itself sufficiently. Not included. In one aspect of the disclosed invention, half an oxide of water or hydrogen can cause an increase in DOS. A highly purified oxide semiconductor is produced by removing it from the conductor. This is DOS that It is based on the idea of reducing things sufficiently. And this is extremely good It enables the manufacture of industrial products.

In addition, oxygen is supplied to the unbonded hands of the metal generated by oxygen deficiency, due to oxygen deficiency. By reducing DOS, it becomes a more purified (i-type) oxide semiconductor. It is also possible. For example, forming an oxygen-rich oxide film in close contact with the channel formation region, It is possible to supply oxygen from the oxide film to reduce DOS due to oxygen defects.

Defects in oxide semiconductors include levels of 0.1 to 0.2 eV below the conduction band due to excess hydrogen and oxygen. It is attributed to deep levels due to shortages. To eliminate these defects We think that the technical idea of thoroughly removing hydrogen and supplying sufficient oxygen is correct. available.

Oxide semiconductors are generally n-type, but in one aspect of the disclosed invention, impurities, In particular, i-type is realized by removing water and hydrogen. In this respect, like silicon etc. It can be said that it does not include i-type by adding impurities, but includes a technical idea that has never existed before.

<Transistor conduction mechanism using oxide semiconductors> Here, regarding the conduction mechanism of the transistor using the oxide semiconductor, FIGS. 7 to 10 are used. explain. In the following explanation, an ideal situation is assumed for easy understanding. Not all reflect reality. In addition, the following explanation is just a consideration It should be added that it does not affect the effectiveness of the invention.

Figure 7 shows a cross section of an inverted staggered transistor (thin film transistor) using an oxide semiconductor. It is a figure. An oxide semiconductor layer (O) is placed on the gate electrode (GE1) via a gate insulating layer (GI). S) is provided, and a source electrode (S) and a drain electrode (D) are provided on the source electrode (S), and a saw is provided. An insulating layer is provided so as to cover the electrode (S) and the drain electrode (D).

FIG. 8 shows an energy band diagram (schematic diagram) in the AA'cross section of FIG. Also, the figure The black circles () in 8 indicate electrons, and the white circles () indicate holes, which are charged (-q, + q), respectively. )have. Positive voltage on the drain electrode (V)DAfter applying> 0), the broken line is the gate electricity. When no voltage is applied to the pole (VG= 0), the solid line is the positive voltage (V) on the gate electrodeG> 0) mark The case of adding is shown. Due to high potential barrier when no voltage is applied to the gate electrode Indicates an off state in which carriers (electrons) are not injected from the electrodes to the oxide semiconductor side and no current flows. Su. On the other hand, when a positive voltage is applied to the gate, the potential barrier is lowered and a current flows on. Show the state.

FIG. 9 shows an energy band diagram (schematic diagram) in the cross section of B-B'in FIG. 7. Figure 9 (A) shows the positive voltage (V) at the gate electrode (GE1).G> 0) is given, It shows an on state in which carriers (electrons) flow between the source electrode and the drain electrode. Ma In addition, Fig. 9 (B) shows the negative voltage (V) at the gate electrode (GE1).GWith <0) applied The case where it is off (a state in which a small number of carriers do not flow) is shown.

Figure 10 shows the vacuum level and the work function of the metal (φ).M), Relationship between electron affinity (χ) of oxide semiconductor Is shown.

At room temperature, the electrons in the metal are degenerate, and the Fermi level is located in the conduction band.

On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E).F) Is the bandgap Intrinsic Fermi level located in the center (Ei), And is located closer to the conduction band. It should be noted that , It is known that a part of hydrogen in oxide semiconductors becomes a donor and is one of the factors for n-type formation. Has been done.

On the other hand, the oxide semiconductor according to one aspect of the invention disclosed is an acid of hydrogen, which is a factor of n-type formation. Removed from compound semiconductors and contains as few elements (impurity elements) as possible other than the main components of oxide semiconductors. By purifying it in this way, it is made genuine (type i) or genuine. ..

That is, instead of adding impurity elements to form i-type, impurities such as hydrogen and water are removed as much as possible. By doing so, it is characterized by being highly purified i-type (intrinsic semiconductor) or close to it. ing. This results in the Fermi level (E)F) Is the true Fermi level (E)i) be able to.

Oxide semiconductor bandgap (Eg) Is 3.15eV and electron affinity (χ) is 4.3V. Is said to be. The work function of titanium (Ti) that constitutes the source electrode and drain electrode is It is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface Therefore, a Schottky type barrier is not formed for electrons.

At this time, as shown in FIG. 9 (A), the electrons are the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface with (the lowest energy-stable part of the oxide semiconductor).

Also, as shown in FIG. 9 (B), when a negative potential is applied to the gate electrode (GE1), a small number Since the number of holes that are carriers is practically zero, the current is as close to zero as possible. To.

In this way, high purity is achieved so that elements other than the main components of oxide semiconductors (impurity elements) are not included as much as possible. By increasing the degree, it becomes true (i type) or substantially true, so the boundary with the gate insulating layer Surface characteristics are important. Therefore, the gate insulating layer can form a good interface with the oxide semiconductor. What can be done is required. Specifically, for example, it is produced at a power supply frequency in the VHF band to the microwave band. Insulation layer produced by CVD method using high-density plasma formed, or produced by sputtering method It is preferable to use an insulating layer or the like.

While purifying the oxide semiconductor, the interface between the oxide semiconductor and the gate insulating layer is improved. As a result, for example, the channel width W of the transistor is 1 × 10.4μm, channel length L 10 for 3 μm-13Off current below A, sub-threshold of 0.1V / dec. The rud swing value (S value) (thickness of the gate insulating layer: 100 nm) can be realized.

In this way, it is high so that elements other than the main component of the oxide semiconductor (impurity elements) are not included as much as possible. By purifying, the operation of the transistor can be improved.

<Resistance to hot carrier deterioration of transistors using oxide semiconductors> Next, regarding the resistance to hot carrier deterioration of transistors using oxide semiconductors, FIGS. 11 to 11 This will be described with reference to FIG. In the following explanation, an ideal situation is assumed for easy understanding. And not all of them reflect the reality. Also, the following explanation is It should be added that this is just one consideration.

Channel hot electron injection (CHE injection) is the main cause of hot carrier deterioration. And drain avalanche hot carrier injection (DAHC injection). In addition, the following is simple Since it is simple, only electrons are considered.

CHE injection means that the semiconductor layer has more energy than the barrier of the gate insulating layer. This is a phenomenon in which the electrons that have become are injected into the gate insulating layer or the like. Conferring energy on electrons Is done by accelerating the electrons in a low electric field.

DAHC injection is a game of new electrons generated by the collision of electrons accelerated by a high electric field. G. A phenomenon in which the material is injected into an insulating layer. The difference between DAHC injection and CHE injection is the collision ion Whether or not it is accompanied by avalanche surrender due to conversion. In addition, in DAHC injection, the semiconductor battery is used. An electron with kinetic energy equal to or greater than the end gap is required.

11 and 12 show silicon (Si) and In-Ga-Zn-O based oxide semiconductors (I). Indicates the energy required for various hot carrier injections estimated from the band structure of GZO). .. In FIGS. 11 and 12, the left represents CHE injection and the right represents DAHC injection.

In silicon, the deterioration due to DAHC injection is more serious than that due to CHE injection. This is Siriko There are very few carriers (eg electrons) that are accelerated without collision in the environment. , Silicon has a small bandgap and is prone to avalanche breakdown To. Avalanche breakdown increases the number of electrons that can cross the barrier of the gate insulating layer, CHE It easily exceeds the probability of injection.

In In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon. It is not much different from the case of, and the probability is still low. Also required for DAHC injection Energy is about the same as the energy required for CHE injection due to the wide bandgap. To.

In other words, the probability of CHE injection and DAHC injection is low, and it is hot compared to silicon. High resistance to deterioration of charia.

By the way, the bandgap of In-Ga-Zn-O oxide semiconductors is used as a high pressure resistant material. It is about the same as silicon carbide (SiC), which is attracting attention. Figure 13 shows the 4H-SiC. Indicates the energy required for various hot carrier injections. For CHE injection, In-Ga -Zn-O-based oxide semiconductors have a slightly higher threshold and can be said to be advantageous.

As mentioned above, In-Ga-Zn-O-based oxide semiconductors deteriorate hot carriers compared to silicon. It can be seen that the resistance to source-drain destruction is very high. Also carbonized It can be said that a withstand voltage comparable to that of silicon can be obtained.

<Short-channel effect in transistors using oxide semiconductors> Next, regarding the short-channel effect in transistors using oxide semiconductors, FIGS. 14 and 14 and FIGS. It will be described using 15. In the following explanation, an ideal situation is assumed for easy understanding. Not all of them reflect the reality. In addition, the following explanation is open It should be added that this is just one consideration.

The short-channel effect becomes apparent with the miniaturization of transistors (reduction of channel length (L)). Deterioration of electrical characteristics. The short-channel effect is that the drain effect extends to the source. It is due to. Specific examples of the short-channel effect are a decrease in threshold voltage and an S value. There is an increase in leakage current and an increase in leakage current.

Here, a device simulation is used to suppress the short-channel effect. I verified the structure. Specifically, the carrier concentration and the thickness of the oxide semiconductor layer are made different. Prepare 4 types of models and check the relationship between channel length (L) and threshold voltage (Vth). did. As a model, a transistor with a bottom gate structure is used, and an oxide semiconductor capacitor is used. Rear concentration 1.7 x 10-8/cm3, Or 1.0 × 1015/cm3As one of , The thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. Oxide semiconducting In-Ga-Zn-O-based oxide semiconductor as the body, 100 nm thick as the gate insulating layer A silicon oxide film was used. Band gap of oxide semiconductor is 3.15 eV, electron parent Sum force is 4.3 eV, relative permittivity is 15, electron mobility is 10 cm2Assumed / Vs. Oxidative nitrogen The relative permittivity of the siliconized silicon film was assumed to be 4.0. Silvaco device simulation for calculation I used the software "Atlas".

There is no big difference in the calculation results between the top gate structure and the bottom gate structure.

The calculation results are shown in FIGS. 14 and 15. Figure 14 shows the carrier concentration of 1.7 × 10.-8/ c m3In the case of, in Fig. 15, the carrier concentration is 1.0 × 10.15/cm3This is the case. Figure 14 And in Fig. 15, the channel length is based on a transistor with a channel length (L) of 10 μm. Amount of change in threshold voltage (Vth) when (L) is changed from 10 μm to 1 μm (Δ Vth) is shown. As shown in Fig. 14, the carrier concentration of the oxide semiconductor is 1.7 × 1. 0-8/cm3When the thickness of the oxide semiconductor layer is 1 μm, the amount of change in the threshold voltage is (ΔVth) was -3.6V. Further, as shown in FIG. 14, the carry of the oxide semiconductor A Concentration is 1.7 x 10-8/cm3When the thickness of the oxide semiconductor layer is 30 nm, The amount of change in the threshold voltage (ΔVth) was -0.2V. Also, as shown in FIG. Carrier concentration of oxide semiconductor is 1.0 × 1015/cm3And the thickness of the oxide semiconductor layer When was 1 μm, the amount of change in threshold voltage (ΔVth) was -3.6 V. Also, the figure As shown in 15, the carrier concentration of the oxide semiconductor is 1.0 × 10.15/cm3And acid When the thickness of the compound semiconductor layer is 30 nm, the amount of change in threshold voltage (ΔVth) is -0.2. It was V. The result is that in a transistor using an oxide semiconductor, the oxide semiconductor layer It can be said that it is possible to suppress the short-channel effect by reducing the thickness of. For example , When the channel length (L) is about 1 μm, it is an oxide semiconductor layer with a sufficiently high carrier concentration. However, if the thickness is about 30 nm, the short-channel effect can be sufficiently suppressed. To be understood.

<Carrier concentration> The technical idea of the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer. It tries to be as close to the true (i type) as possible. Below, how to find the carrier concentration, The actually measured carrier concentration will be described with reference to FIGS. 16 and 17.

First, how to obtain the carrier concentration will be briefly described. Carrier concentration is MOS capacity Obtained by producing data and evaluating the CV measurement result (CV characteristics) of the MOS capacitor. It is possible.

More specifically, C is a plot of the relationship between the gate voltage Vg of the MOS capacitor and the capacitance C. -Obtain the V characteristic, and from the CV characteristic, the gate voltage Vg and (1 / C)2Representing the relationship with Get the rough and (1 / C) in the weakly inverted region in the graph2Find the derivative value of Carrier concentration N by substituting the minute value into Eq. (1)dThe size of is required. The formula In (1), e is an elementary charge, ε0Is the permittivity of the vacuum and ε is the relative permittivity of the oxide semiconductor. To.

Next, the carrier concentration actually measured using the above method will be described. For measurement, A titanium film with a thickness of 300 nm is formed on the lath substrate, and 100 titanium nitride films are formed on the titanium film. It is formed with a thickness of nm and uses an In-Ga-Zn-O-based oxide semiconductor on a titanium nitride film. An oxide semiconductor layer is formed with a thickness of 2 μm, and a silicon oxynitride film is 300n on the oxide semiconductor layer. A sample (MOS key) formed with a thickness of m and a silver film formed with a thickness of 300 nm on a silicon oxynitride film. Capashita) was used. The oxide semiconductor layer is metal-oxidized containing In, Ga, and Zn. Spatter using an object target (In: Ga: Zn = 1: 1: 0.5 [atom%]) It was formed by the ang method. The atmosphere of forming the oxide semiconductor layer is a mixed atmosphere of argon and oxygen. Surrounding air (flow rate is Ar: O2= 30 (sccm): 15 (sccm)).

Fig. 16 shows the CV characteristics, and Fig. 17 shows Vg and (1 / C).2The relationship with each is shown. Figure (1 / C) in 17 weakly inverted regions2Carrier obtained from the differential value of Eq. (1) The concentration is 6.0 x 1010/cm3Met.

Thus, i-shaped or substantially i-shaped oxide semiconductors (eg, carrier concentrations are 1x1012/cm3Less than, preferably 1x1011/cm3By using (below) It is possible to obtain a transistor with extremely excellent off-current characteristics.

A semiconductor material that constitutes a channel formation region using the non-volatile latch circuit according to this embodiment. A transistor using an oxide semiconductor as a material is used as a switching element for the data holding unit. By using it, the temperature operation range is wide and it operates stably even at high temperatures, and it is memorized even when the power is turned off. Non-volatile latch circuit whose logical state does not disappear or data with a sufficiently long refresh period A latch circuit with a built-in holding unit can be realized. Transistor writing data Since it is performed by switching the above, there is virtually no limit to the number of rewrites. Also write The built-in voltage is about the threshold voltage of the transistor, and it is possible to operate at a low voltage. Example For example, the operating voltage can be reduced to 1V or less. In addition, the electric charge accumulated in the capacity of the data holding unit Is retained as data as it is, so it is not easily affected by variations and the data is read. It can be easily squeezed out.

By using the above non-volatile latch circuit, it is possible to realize various logic circuits. is there. For example, power consumption can be reduced by turning off the power of unused blocks. it can. Also, since the logical state is memorized even when the power is turned off, the power is turned on. To start the system at the time and shut down the system when the power is turned off at high speed and with low power consumption. And is possible.

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 2) The present embodiment relates to the configuration of a non-volatile latch circuit, which is one aspect of the disclosed invention. An example different from FIG. 1 will be described with reference to FIG. FIG. 18 (A) shows the latch portion 411 and the latch. A non-volatile latch circuit 400 having a data holding unit 401 and a data holding unit 401 for holding the data of the switch portion. The configuration is shown. FIG. 18B shows the configuration of the data holding unit 401.

FIG. 18 shows an example in which the configuration of the data holding unit 401 is different from that of FIG. Specifically, the data This is an example in which the capacity of the holding unit 401 (capacity 404 in FIG. 1) is not provided. Other configurations are the same as in Fig. 1. Since it seems like this, the explanation is omitted. The configuration of the transistor 402 is the same as that of the first embodiment. ..

The data holding unit 401 uses an oxide semiconductor as a semiconductor material constituting the channel forming region. The transistor 402 that was used is used as a switching element. Also this transistor 4 It has an inverter 403 that is electrically connected to the other of the source electrode and drain electrode of 02. ing.

An output signal is given to one of the source electrode and the drain electrode of the transistor 402. It is electrically connected to the wiring 415. The output of the inverter 403 is given by an input signal. It is electrically connected to the wiring 414 to be connected. Inverter 403 is transistor 420 And the transistor 421. The source electrode of transistor 420 is high level It is electrically connected to the power supply voltage VDD. The source electrode of transistor 421 is low level It is electrically connected to the power supply voltage VSS of VSS.

In this embodiment, there is no capacity to be connected to the node S. In this case, Invar Charges are accumulated in the gate capacitance of the transistors that make up the 403. Here, preferably , The gate capacity of the transistor 421 of the inverter 403 is that of the inverter 403. It can be larger than the gate capacitance of the transistor 420. Of the gate capacity The size is the channel length L of the transistor, the channel width W, the film thickness of the gate insulating film, and the dielectric constant. It can be controlled by the method. By doing this, the transistor 420 and the transistor The ratio of the capacity configured between VSS and node S out of the gate capacity of 421 has increased, and the tiger The potentials of the gate electrodes of the engineer 420 and transistor 421 are affected by the fluctuation of VDD. It is preferable because it becomes difficult.

The inverter 403 is not limited to the configuration shown in FIG. 18 (B), and is shown in FIG. 2 (A), for example. It may be composed of N-channel transistors, or it may be configured with a buffer at the output. I. Further, a sense amplifier circuit may be used instead of the inverter 403. For example, Figure 2 A differential amplification type sense amplifier circuit as shown in (B) may be used. In either case, enter It is important that the force terminals are in a floating state (high impedance state). Also In the circuit shown in Fig. 2 (A), the input charge is stored in the gate capacitance of transistor 421. Is done. Further, in the circuit shown in FIG. 2 (B), the input charge is the gate capacity of the transistor 421. Accumulate in quantity. The circuits shown in FIGS. 2 (A) and 2 (B) are mainly composed of these gate capacitances. Because it is configured between VSS and node S, the potential of the input terminal is affected by the fluctuation of VDD. It is preferable because it is hard to get rid of.

The transistor 402 using this oxide semiconductor is held in the latch portion 411. It has a function to write data to the gate capacity of the inverter 403 of the data holding unit 401. .. Further, the transistor 402 is used for the gate capacitance of the inverter 403 of the data holding unit 401. It has a function to retain the written data.

Writing, holding, and reading the data held in the latch section 411 to the data holding section 401. The operation of squeezing out and rewriting will be described. First, the gate electrode of the transistor 402 Supply the potential to turn on the Langista 402 and turn on the transistor 402. .. As a result, the data held in the latch portion, that is, the wiring 4 to which the output signal is given. Fifteen potentials are applied to the input terminals of the inverter 403. As a result, the inverter 403 Charges corresponding to the potential of the wiring 415 are accumulated in the gate capacitance (writing). After that, The potential of the gate electrode of the Langista 402 is used as the potential at which the transistor 402 is turned off. , By turning off the transistor 402, it is stored in the gate capacitance of the inverter 403. The accumulated charge is retained (retained). Reading the potential of the input terminal of the inverter 403 Allows the data to be read (read). Data rewriting is above It can be done in the same way as writing and holding data.

This embodiment can be freely combined with other embodiments.

(Embodiment 3) The present embodiment relates to the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. This will be described with reference to FIGS. 19 and 1.

FIG. 19A shows the latch portion 411 and the data holding portion 401 for holding the data of the latch portion. The configuration of the non-volatile latch circuit 400 having the above is shown. Figure 19 (B) shows the non-volatile An example of the timing chart of the latch circuit 400 is shown.

FIG. 19A is an example in which the configuration of the latch portion 411 of FIG. 1A is specifically shown. Figure 19 In (A), in the configuration of the latch portion 411 of FIG. 1 (A), an inverter is used as the first element. This is an example of using an inverter as the second element. The configuration of transistor 402 is actually It is the same as the form 1 of the application.

The latch portion 411 has an inverter 412 and an inverter 413. Inverter 4 The output of 12 is electrically connected to the input of inverter 413, and the output of inverter 413 is It has a loop structure that is electrically connected to the input of the converter 412. In addition, the latch part 41 1 has a switch 431 and a switch 432, and is introduced via the switch 432. The output of the data 413 is electrically connected to the input of the inverter 412.

The input of the inverter 412 is given the input signal of the latch circuit via the switch 431. It is electrically connected to the wiring 414. The output of the inverter 412 is the output signal of the latch circuit. It is electrically connected to the wiring 415 to which the number is given.

The data holding unit 401 uses an oxide semiconductor as a semiconductor material constituting the channel forming region. The transistor 402 that was used is used as a switching element. Also this transistor 4 Capacitance 404 and inverter electrically connected to the other of the source and drain electrodes of 02 It has 403 and.

The potential of the input signal IN is given to the wiring 414 from the circuit in the previous stage. The potential of wiring 415 is output It is given to the subsequent circuit as a force signal OUT. Switch 431 has a clock signal φ1 The rank is given. When a high level potential is applied to the clock signal φ1, switch 431 Is turned on. The potential of the clock signal φ2 is given to the switch 432. Clock signal When a high level potential is applied to φ2, the switch 432 is turned on. Transistor 4 The potential of the control signal ST is given to the gate of 02. The control signal ST is a high level potential Is given, the transistor 402 has a potential to turn on. Switch 405 is controlled The potential of the signal LD is given. The control signal LD is displayed when a high level potential is applied. It has a potential to turn on. During the normal operating period, the clock signal φ2 It has a signal in which the clock signal φ1 is inverted. Here, the control signal and clock signal are high. An example in which the transistor and the switch are turned on at the level is shown.

Inverter 403 of data holding unit 401 and inverter of latch unit 411 412 and inverter 413 have high level power supply voltage VDD and low level, respectively. The power supply voltage VSS is given.

Next, as shown in FIG. 19 (B), the non-volatile latch circuit 400 is in the operating state (operating period) and stopped. Input signal IN, output signal OUT, control signal ST, during the stopped state (non-operating period) Example of potential timing chart of control signal LD, clock signal φ1 and clock signal φ2 Shown. The potentials of the node S of the data holding unit 401 and the power supply voltage VDD are also shown. node S indicates the potential of one electrode of the capacitance 404 and the input terminal of the inverter 403. Na A fixed potential is applied to the other electrode of capacity 404. For example, given a ground potential There is.

In FIG. 19 (B), period a, period b, period d, and period e are operating periods, and period c is not. The operating period. The period a and the period e are normal operating periods, and the clock signal φ1 and the clock High-level or low-level potentials are alternately applied to the signal φ2. Period b is inactive The preparation period before the period. Period b is also called the start-up period. Period d is the power supply voltage VDD This is the preparation period from when is turned on until the normal operation period begins. Period d is also the start-up period Say.

In the normal operation period (period a), the clock signal φ1 has a high level and the clock signal φ2. When a low level potential is applied to, switch 432 is turned off and the inverter loop is turned off. When it is cut off, the switch 431 is turned on and the potential of the input signal enters the inverter 412. Be empowered. The potential of the input signal is inverted by the inverter 412, and it is set as the output signal OUT in the subsequent stage. Given to the circuit. Input signal when a high level potential is applied to the clock signal φ1 If the potential of is high, an output signal with a low potential is obtained. clock If the potential of the input signal is low level when a high level potential is given to the signal φ1 , An output signal with a high level of potential is obtained. Low level clock signal φ1 When a high level potential is applied to the signal φ2, the switch 431 is turned off and the switch 431 is turned off. Switch 432 is turned on, an inverter loop is formed, and the potential of the output signal OUT is maintained. (Data is latched). During normal operation, the control signal ST has a transition. No potential is given to turn on the star 402. Node S holds the potential that it had previously held Have. Here, it is an indefinite value.

Next, in the preparation period (period b) before the non-operation period, the transistor 40 is sent to the control signal ST. When the potential to turn 2 is given, the transistor 402 is turned on and the potential of the output signal is turned on. Is given to node S (write). If the potential of the output signal is high level, node S The potential of is high. After that, the transistor 402 is turned off at the control signal ST. The position is given, the transistor 402 is turned off, and the potential of node S is floating. Become a voice. As a result, the potential written to the node S is retained (retained) as it is. It should be noted that , The clock signal φ2 and the clock signal φ1 may maintain the potential at the end of the period a. Or, The clock signal φ2 is fixed at the high level, the clock signal φ1 is fixed at the low level, and at the end of period a. You may latch the data of. The control signal ST is the transistor 40 after the start of period b. You may give a potential to turn 2 on, or transistor 402 turns on at the same time as the start of period b You may give the potential which becomes.

Next, during the non-operating period (period c), the power supply is stopped and the power supply voltage VDD drops. .. Clock signal φ1, clock signal φ2, input signal IN, output signal OUT are VDD-VS Any value between S can be taken. During this time, the potentials of the control signal ST and control signal LD It is kept at a low level. For example, it is held at the ground potential. Smell during non-operation period (period c) Since the potential of node S is in a floating state, the charge accumulated in node S is the same. It is held as it is (hold). When the power supply voltage VDD drops, the potential of node S becomes It may fluctuate slightly due to the influence of capacitive coupling with the power supply potential. Of course, it accumulates in node S Since the charged charge is retained, the power supply voltage VDD is supplied again and the original potential is restored. ..

Next, in the preparation period (period d) from when the power supply voltage VDD is turned on until the normal operation period is entered. In the state where the clock signal φ2 and the clock signal φ1 are fixed at the low level, the control signal When the potential to turn on the switch 405 is given to the No. LD, the switch 405 is turned on. , The potential held in the node S is inverted by the inverter 403 and given to the latch part 411. Be done. Then, after the control signal LD is given the potential to turn on the switch 405, The potential at the end of period a is given to the lock signal φ2 and the clock signal φ1. This will The logical state of period d can be returned to the logical state before entering the non-operation period. Control signal LD , The low level may be set before the end of period d, or the switch 405 will be turned on until the end. You may keep the rank.

Next, in the normal operation period (period e), the clock signal φ1 and the clock signal φ2 are changed to c. A level and low level potentials are given, and the normal operating state is reached. Normal operating period (period) At the start of e), the clock signal φ1 and the clock signal φ2 are the normal operating periods before that (e). It may start from the same potential as at the end of period a), or is it the next state of potential at the end of period a? You can start from.

As for the potential of node S, the potential at which transistor 402 is turned on is given to the control signal ST next. It is rewritten at the timing. Therefore, the transistor 402 is then turned on for the control signal ST. The potential of the node S is maintained as it is until the timing when the potential becomes.

In the period d, the potential Vc of the other electrode having the capacitance 404 is the value between VDD and VSS. You may. As a result, the node S is given a potential that takes into account the increment of the potential Vc, and the reading is performed. It is possible to perform the feeding operation more stably.

This embodiment can be freely combined with other embodiments.

(Embodiment 4) The present embodiment relates to the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. An example different from that of FIG. 19 will be described with reference to FIGS. 20 and 18. Figure 20 (A) shows A non-volatile machine having a chi portion 411 and a data holding portion 401 for holding the data of the latch portion. The configuration of the switch circuit 400 is shown. FIG. 20 (B) shows the data of the non-volatile latch circuit 400. An example of an iming chart is shown.

FIG. 20 shows an example in which the configuration of the data holding unit 401 is different from that of FIG. Specifically, day This is an example in which the capacity of the holding portion (capacity 404 in FIG. 19) is not particularly provided. Other configurations are shown in Figure 19 Since it is the same as the above, the description thereof will be omitted.

Further, FIG. 20 (A) is an example in which the configuration of the latch portion 411 of FIG. 18 (A) is specifically shown. FIG. 20 (A) is shown as the first element in the configuration of the latch portion 411 of FIG. 18 (A). This is an example in which a burter is used and an inverter is used as the second element. Structure of data holding unit 401 The formation will be described with reference to FIG. The configuration of the transistor 402 is the same as that of the first embodiment. The same is true.

The data holding unit 401 uses an oxide semiconductor as a semiconductor material constituting the channel forming region. The transistor 402 that was used is used as a switching element. Also this transistor 4 It has an inverter 403 that is electrically connected to the other of the source electrode and drain electrode of 02. ing.

An output signal is given to one of the source electrode and the drain electrode of the transistor 402. It is electrically connected to the wiring 415. The output of the inverter 403 is the switch 405. It is electrically connected to the wiring 414 to which the input signal is given via. Inverter 403 The configuration of is as shown in Fig. 18 (B), and the inverter 403 is the transistor 420. It has a transistor 421. The source electrode of transistor 420 is a high level electric It is electrically connected to the source voltage VDD. The source electrode of transistor 421 is low level It is electrically connected to the power supply voltage VSS of.

In this embodiment, there is no capacity to be connected to the node S. In this case, Invar Charges are accumulated in the gate capacitance of the transistor connected to the input of the 403. Here, good Furthermore, the gate capacity of the transistor 421 of the inverter 403 is the inverter 4 It shall be larger than the gate capacitance of the transistor 420 possessed by 03. Large gate capacity For the transistor channel length L, channel width W, gate insulating film thickness, permittivity, etc. It can be more controlled. By doing this, the input capacity of the inverter 403 is mainly It is composed of the capacitance between the mode S and VSS, and the potential of the input terminal is not easily affected by the fluctuation of VDD. Therefore, it is preferable.

The transistor 402 using this oxide semiconductor is held in the latch portion 411. It has a function to write data to the gate capacity of the inverter 403. Also, a transistor The 402 has a function of holding the data written in the gate capacitance of the inverter 403. There is.

FIG. 20B shows an example of a timing chart of the non-volatile latch circuit 400. Figure 20 The timing chart of (B) is almost the same as the timing chart of FIG. 19 (B). Therefore, the description is omitted.

This embodiment can be freely combined with other embodiments.

(Embodiment 5) The present embodiment relates to the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. An example different from that of FIG. 19 will be described with reference to FIG. Figure 21 (A) shows the non-volatile memory. The configuration of the switch circuit 400 is shown. The configuration of the non-volatile latch circuit 400 is shown in FIG. 19 (A). ). FIG. 21 (B) shows the timing chart of the non-volatile latch circuit 400. An example is shown.

In the timing chart shown in FIG. 21 (B), after the power supply voltage VDD is supplied again. In period d, the control signal ST is given a potential to turn on the transistor 402. System Is the control signal LD high level at the rising timing when the signal ST becomes high level? It suffices if it is after the timing of falling down. In addition, the control signal ST drops to a low level. The timing is such that the clock signal φ1 and the clock signal φ2 have the same potential as at the end of the period a. It suffices if it is within the period. In period d, the transistor 402 is sent to the control signal ST. Given the potential to turn on, the potential of node S can be refreshed. To.

In the timing chart of FIG. 21 (B), the timings other than the control signal ST are shown in FIG. 19 (B). Since it is the same as B), the description is omitted.

This embodiment can be freely combined with other embodiments.

(Embodiment 6) The present embodiment is a logic having a plurality of non-volatile latch circuits, which is one aspect of the disclosed invention. The circuit configuration will be described with reference to FIG.

FIG. 22 has a latch portion 411 and a data holding portion 401 for holding the data of the latch portion. The configuration of a logic circuit having two non-volatile latch circuits 400 is shown.

The configuration of the data holding unit 401 is the same as that in FIG. 1 (A) or FIG. 18 (A). Latch part 41 The configuration of 1 is the first element in the configuration of the latch portion 411 of FIG. 1 (A) or FIG. 18 (A). This is an example in which NAND is used as the second element and a clocked inverter is used as the second element.

The latch portion 411 has a NAND 412 and a clocked inverter 413. NA The output of the ND412 is electrically connected to the input of the clocked inverter 413 and is clocked. It has a loop structure in which the output of inverter 413 is electrically connected to the input of NAND412. ing. Further, the latch portion 411 has an analog switch 431.

One of the inputs of NAND412 is the latch circuit 400 via analog switch 431. It is electrically connected to the wiring 414 to which the input signal is given. The output of NAND412 is It is electrically connected to the wiring 415 to which the output signal of the latch circuit 400 is given. NAN The other one of the inputs of the D412 is electrically connected to the wiring to which the signal RSTB is given. To.

The logic circuit shown in FIG. 22 is a non-volatile latch circuit 400 as described above. It has a circuit 400a and a non-volatile latch circuit 400b. Non-volatile latch circuit 4 00a is electrically connected to the wiring 414 to which the potential of the input signal is given from the circuit in the previous stage. To. The wiring 415 to which the potential of the output signal of the non-volatile latch circuit 400a is given is non-volatile. It is electrically connected to the wiring 414 to which the potential of the input signal of the sex latch circuit 400b is given. To. The non-volatile latch circuit 400b is a wiring 4 in which the potential of the output signal is given to the circuit in the subsequent stage. It is electrically connected to 15. Analog switch in non-volatile latch circuit 400a The clock signal φ1 and the inverted signal of the clock signal φ1 are given to the chi 431, and the clock doi An inverted signal of a clock signal φ2 and a clock signal φ2 is given to the converter 413. Also , In the non-volatile latch circuit 400b, the clock signal φ to the analog switch 431 An inverted signal of 2 and the clock signal φ2 is given, and the clocked inverter 413 is clocked. An inverted signal of the signal φ1 and the clock signal φ1 is given.

This embodiment can be freely combined with other embodiments.

(Embodiment 7) In the present embodiment, the semiconductor device using the non-volatile latch circuit obtained in the previous embodiment An example of an electronic device equipped with the above will be described with reference to FIG. Disadvantages obtained in the previous embodiment Electronic devices equipped with semiconductor devices that use volatile latch circuits have unprecedented superior characteristics. Have. Therefore, a new semiconductor device using the non-volatile latch circuit is used. It is possible to provide electronic devices with various configurations. It should be noted that the non-volatility according to the previous embodiment. Semiconductor devices using the latch circuit of the above are integrated and mounted on a circuit board, etc., and each electronic device It will be installed inside.

FIG. 23 (A) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. It is a notebook type personal computer, and has a main body 301, a housing 302, a display unit 303, and a key. -It is composed of board 304 and so on. The semiconductor device according to the disclosed invention is a notebook type. By applying it to a personal computer, a notebook-type personal compilation with excellent performance A tutor can be provided.

FIG. 23 (B) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. It is a personal digital assistant (PDA), and the main unit 311 has a display unit 313 and an external interface. 315 and operation buttons 314 and the like are provided. Also, a stylus as an accessory for operation There are 312. Applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA) Therefore, it is possible to provide a personal digital assistant (PDA) with excellent performance.

FIG. 23 (C) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. An electronic book 320 is shown as an example of the electronic paper. The e-book 320 has a housing 321 It is composed of two housings, the housing 323 and the housing 323. The housing 321 and the housing 323 have a shaft portion 3. It is integrated by 37, and can be opened and closed with the shaft portion 337 as an axis. This With such a configuration, the electronic book 320 can be used like a paper book.

The display unit 325 is incorporated in the housing 321 and the display unit 327 is incorporated in the housing 323. There is. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be different. The screen may be displayed. By configuring to display different screens, for example The text is displayed on the right display (display 325 in Fig. 23 (C)), and the text is displayed on the left display (Fig. 23). In (C), the image can be displayed on the display unit 327).

Further, FIG. 23 (C) shows an example in which the housing 321 is provided with an operation unit and the like. For example, the case The body 321 is equipped with a power supply 331, operation keys 333, a speaker 335, and the like. Operation key -333 allows you to send pages. In addition, the keyboard and the port are on the same surface as the display part of the housing. It may be configured to include an inting device or the like. Also, on the back and sides of the housing, the outside Connection terminal (earphone terminal, USB terminal, AC adapter and USB cable, etc. (Terminals that can be connected to various cables, etc.), a recording medium insertion part, etc. may be provided. .. Further, the electronic book 320 may be configured to have a function as an electronic dictionary.

Further, the electronic book 320 may be configured to be able to transmit and receive information wirelessly. By radio, electricity It is also possible to purchase and download the desired book data from the child book server. It is possible.

Electronic paper can be applied to any field as long as it displays information. Is. For example, in addition to e-books, posters, in-car advertisements for vehicles such as trains, and credit It can be applied to display on various cards such as cards. The invention to be disclosed To provide electronic paper with excellent performance by applying semiconductor devices to electronic paper. Can be done.

FIG. 23 (D) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. It is a mobile phone. The mobile phone is composed of two housings, a housing 340 and a housing 341. Has been done. The housing 341 includes a display panel 342, a speaker 343, and a microphone 34. 4, pointing device 346, camera lens 347, external connection terminal 348, etc. I have. Further, the housing 340 is a solar cell 349 that charges the mobile phone, and is outside. It is equipped with a memory slot 350 and the like. In addition, the antenna is built in the housing 341. ing.

The display panel 342 has a touch panel function, and the image is displayed in Fig. 23 (D). Multiple operation keys 345 are indicated by dotted lines. The mobile phone is a solar cell 34. A booster circuit is mounted to boost the voltage output in 9 to the voltage required for each circuit. Ma In addition to the above configuration, a non-contact IC chip, a small recording device, etc. shall be built-in. You can also.

The display direction of the display panel 342 changes as appropriate according to the usage pattern. Also, display panel 3 Since it has a camera lens 347 on the same surface as the 42, it is possible to make a video call. Su The peaker 343 and microphone 344 are not limited to voice calls, but videophones, recordings, and replays. Raw etc. are possible. Furthermore, the housing 340 and the housing 341 slide, as shown in Fig. 23 (D). It can be changed from the unfolded state to the overlapping state, and it can be miniaturized to be suitable for carrying. Noh.

External connection terminal 348 can be connected to various cables such as AC adapter and USB cable Therefore, charging and data communication are possible. Also, a recording medium is stored in the external memory slot 350. Can be inserted to accommodate the storage and movement of larger amounts of data. Also, in addition to the above functions It may be provided with an infrared communication function, a television reception function, and the like. The invention to be disclosed By applying semiconductor devices to mobile phones, it is possible to provide mobile phones with excellent performance. Wear.

FIG. 23 (E) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. It is a digital camera. The digital camera has a main body 361, a display unit (A) 367, and an eyepiece. Part 363, operation switch 364, display (B) 365, battery 366, etc. It is made. By applying the semiconductor device according to the disclosed invention to a digital camera, it is excellent. It is possible to provide a digital camera with excellent performance.

FIG. 23 (F) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment. It is a television device. In the television device 370, the display unit 373 is assembled in the housing 371. It is expected. The display unit 373 can display an image. In addition, here Shows a configuration in which the housing 371 is supported by the stand 375.

The operation of the television device 370 can be performed by using the operation switch provided in the housing 371 or a separate remote controller. It can be performed by the operating device 380. To the operation key 379 provided in the remote control device 380 You can control the channel and volume, and operate the image displayed on the display unit 373. can do. Further, the remote controller 380 is output from the remote controller 380. A display unit 377 for displaying the information to be displayed may be provided.

The television device 370 is preferably configured to include a receiver, a modem, and the like. To. The receiver can receive general television broadcasts. Also via a modem One-way (received from sender) by connecting to a wired or wireless communication network Person) or two-way (between sender and receiver, or between recipients, etc.) And is possible. By applying the semiconductor device according to the disclosed invention to a television device, It is possible to provide a television device having excellent performance.

The configurations, methods, etc. shown in this embodiment are appropriately combined with the configurations, methods, etc. shown in other embodiments. Can be used together

In this embodiment, the result of evaluating the operation of the non-volatile latch circuit, which is one aspect of the disclosed invention. Is shown.FIG. 24 shows the configuration of the non-volatile latch circuit used for the evaluation. Non-volatile rack shown in Fig. 24 The circuit 400 includes a latch portion 411 and a data holding portion 401 that holds data in the latch portion. Have.The latch portion 411 is composed of an inverter 412, an inverter 413, and a transistor. It has a switch 431 and a switch 432 composed of transistors.The data holding unit 401 uses an oxide semiconductor as a semiconductor material constituting the channel forming region. It consists of the transistor 402, the capacity 404, the inverter 403, and the transistor. It has a switch 405 and a switch 405. In addition, node S is one electrode of capacity 404 and a. It shows the potential of the input terminal of the converter 403.The transistor 402 was manufactured according to FIGS. 5 (A) to (G) and 6 (A) to (D), and FIG. 6 A transistor having the same structure as the transistor shown in (D) was used. Transistor 402 A highly purified oxide semiconductor with a channel length L = 3 μm and a channel width W = 5 μm is used. Langista.Inverter 412, Inverter 413, Inverter 403, Transistor It consists of a switch 431, a switch 432 consisting of transistors, and a transistor. The switch 405 is made of a transistor made of silicon.The potential of the input signal IN is given to the wiring 414 from the circuit in the previous stage. The potential of wiring 415 is output It is given to the subsequent circuit as a force signal OUT. The potential of signal φ1 is given to switch 431. Be done. The potential of the signal φ2 is given to the switch 432. Transistor 402 gate Is given the potential of the control signal ST. The potential of the control signal LD is given to the switch 405. Is done.Figures 25 (A) and 25 (B) show the evaluation results of the non-volatile latch circuit 400. Figure 25 (A) shows , Power supply voltage VDD, input signal IN, control signal ST, output signal O during write operation The result of measuring the potential of UT with an oscilloscope is shown. Figure 25 (B) shows the read operation. In, the potentials of the power supply voltage VDD, the input signal IN, the control signal LD, and the output signal OUT are set. The result measured by the loscope is shown. In the evaluation of the non-volatile latch circuit 400, The power supply voltage at the time of power supply was VDD = 5V and VSS = 0V.First, the operation of writing the potential of the output signal OUT to the node S and holding it was performed (Fig. 25 (A). )reference). The potential of the output signal OUT at the time of writing was set to 5V, and the potential of the input signal IN was set to 0V. .. The control signal ST is given a potential at which the transistor 402 is turned on (here, a potential of 5 V). Turn on the transistor 402 and set the potential of the output signal OUT (here, the potential of 5V) to the node. Given to S (write). The period for turning on the transistor 402 is 200 microseconds. And said.After that, the potential at which the transistor 402 is turned off (here, the potential of 0V) is applied to the control signal ST. Given, the transistor 402 was turned off and the potential of node S was floated ( Retention).During writing and holding, the control signal LD has a potential at which switch 405 is turned off (here 0). V potential) was given.During writing and holding, the signal φ2 and the signal φ1 are the potentials before the writing operation (here, the signal). No. φ2 was held at low level (0V), and signal φ1 was held at high level (5V) potential).Next, the power supply is stopped (also called turning off the power), and it is non-volatile for 10 minutes at room temperature. Latch circuit 400 was left unattended. When the power supply is stopped (also called the non-operating period), the power supply is powered. The potential of pressure VDD decreased. During this time, the potential of the control signal ST and control signal LD is changed to the potential of 0V. Retained.After that, the power supply is restarted (also called turning on the power), and the potential of the power supply voltage VDD is set to 5V. I made it.Next, the operation of reading the potential of the node S was performed (see FIG. 25 (B)). At the time of reading Set the potential of signal φ2 and signal φ1 to low level (0V), switch 432, switch 431 Was turned off. In this state, the potential at which the switch 405 is turned on in the control signal LD (here, A potential of 5V) was applied and switch 405 was turned on. When switch 405 is turned on, it comes out A potential of 5V was output (read) as the potential of the force signal OUT.As for the potential of the output signal OUT, the potential of the node S is the inverter 403 and the inverter 412. It was output via. Therefore, from Fig. 25 (B), the node before the power supply is stopped. The potential written in S is retained as it is even after the power supply is stopped, and is used as the potential of the output signal OUT. It was confirmed that it was output. That is, by using the non-volatile latch circuit 400, electricity is generated. It was confirmed that the logical state before the power supply was stopped could be restored immediately after the power supply was restarted.

100 boards 102 Protective layer 104 Semiconductor area 106 element separation insulation layer 108a Gate insulating layer 110a gate electrode 112 Insulation layer 114 Impurity region 116 Channel formation area 118 sidewall insulation layer 120 High concentration impurity region 122 metal layer 124 Metal compound area 126 Interlayer insulation layer 128 interlayer insulation layer 130a drain electrode 130b drain electrode 130c electrode 132 Insulation layer 134 Conductive layer 136a electrode 136b electrode 136c electrode 136d gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a drain electrode 142b drain electrode 144 Protective insulation layer 146 Interlayer insulation layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulation layer 154a electrode 154b electrode 154c electrode 154d electrode 301 body 302 housing 303 Display 304 keyboard 311 body 312 stylus 313 Display 314 operation buttons 315 external interface 320 e-book 321 chassis 323 housing 325 Display 327 Display 331 power supply 333 Operation keys 335 speaker 337 Shaft 340 chassis 341 housing 342 Display panel 343 speaker 344 microphone 345 Operation keys 346 Pointing device 347 Camera lens 348 External connection terminal 349 solar cells 350 external memory slot 361 main body 363 Eyepiece 364 Operation switch 365 Display (B) 366 battery 367 Display (A) 370 Television device 371 chassis 373 Display 375 stand 377 Display 379 Operation keys 380 remote control device 400 latch circuit 400a latch circuit 400b latch circuit 401 Data retention unit 402 transistor 403 inverter 404 capacity 405 switch 411 Latch part 412 1st element 413 Second element 414 Wiring 415 Wiring 420 transistor 421 transistor 431 switch 432 switch 501 N-channel transistor 502 N-channel transistor 503 P-channel transistor 504 P-channel transistor 505 P-channel transistor 506 P-channel transistor

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Document	Relation	Office	Cited during
CN112054783A	Cited by	China	Search report
JP2000077982A	Cites	Japan	–
JP2009206942A	Cites	Japan	–
WO2003044953A1	Cites	World Intellectual Property Organization (WIPO)	–
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JP2005323295A	Cites	Japan	–
WO2004059838A1	Cites	World Intellectual Property Organization (WIPO)	–
JP60025269A	Cites	Japan	–
JP2000269457A	Cites	Japan	–
JP2005269616A	Cites	Japan	–
JP2009212443A	Cites	Japan	–
JP2006165532A	Cites	Japan	–

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Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

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