Semiconductor device and fabrication method thereof
6 claims: 6 independent, 0 dependent
- 1トランジスタ上に第1の絶縁膜を有し、 前記第1の絶縁膜上に第1及び第2の配線を有し、 前記第1及び第2の配線上に第2の絶縁膜を有し、 前記第2の絶縁膜上に第1の電極を有し、 前記第1の電極上に第3の絶縁膜を有し、 前記第3の絶縁膜上に画素電極及び第2の電極を有し、 前記画素電極は、前記第1の電極と重なる第1の領域と、前記第1の電極と重ならない第2の領域と、を有し、 前記画素電極は、前記第1の配線 と 電気的に接続されており、 前記第1の配線は、前記トランジスタのソース又はドレインの一方と電気的に接続されており、 前記第2の電極は、前記第1の電極と接触せず、 前記第2の電極は、画素部の外側において前記第2の配線と電気的に接続されており、 前記第2の電極は、前記第1の電極と重なる領域を有 し、 前記第1の電極と前記第2の電極との間に容量を形成することができる ことを特徴とする液晶表示装置。
- 22つのチャネル形成領域を有するトランジスタ上に第1の絶縁膜を有し、 前記第1の絶縁膜上に第1乃至第3の配線を有し、 前記第1乃至第3の配線上に第2の絶縁膜を有し、 前記第2の絶縁膜上に第1の電極を有し、 前記第1の電極上に第3の絶縁膜を有し、 前記第3の絶縁膜上に画素電極及び第2の電極を有し、 前記画素電極は、前記第1の電極と重なる第1の領域と、前記第1の電極と重ならない第2の領域と、を有し、 前記画素電極は、前記第1の配線 と 電気的に接続されており、 前記第1の配線は、前記トランジスタのソース又はドレインの一方と電気的に接続されており、 前記第3の配線は、前記トランジスタのソース又はドレインの他方と電気的に接続されており、 前記第1の配線は、前記2つのチャネル形成領域の一方と重なる領域を有し、 前記第3の配線は、前記2つのチャネル形成領域の他方と重なる領域を有し、 前記第2の電極は、前記第1の電極と接触せず、 前記第2の電極は、画素部の外側において前記第2の配線と電気的に接続されており、 前記第2の電極は、前記第1の電極と重なる領域を有 し、 前記第1の電極と前記第2の電極との間に容量を形成することができる ことを特徴とする液晶表示装置。
- 3トランジスタ上に第1の絶縁膜を有し、 前記第1の絶縁膜上に第1及び第2の配線を有し、 前記第1及び第2の配線上に第2の絶縁膜を有し、 前記第2の絶縁膜上に第1の電極を有し、 前記第1の電極上に第3の絶縁膜を有し、 前記第3の絶縁膜上に画素電極及び第2の電極を有し、 前記画素電極は、前記第1の電極と重なる第1の領域と、前記第1の電極と重ならない第2の領域と、を有し、 前記画素電極は、前記第1の配線 と 電気的に接続されており、 前記第1の配線は、前記トランジスタのソース又はドレインの一方と電気的に接続されており、 前記第2の電極は、前記第1の電極と接触せず、 前記第2の電極は、画素部の外側において前記第2の配線と電気的に接続されており、 前記第2の電極は、前記第1の電極と重なる領域を有し、 前記第2の配線は、コモン電位を供給する機能を有 し、 前記第1の電極と前記第2の電極との間に容量を形成することができる ことを特徴とする液晶表示装置。
- 42つのチャネル形成領域を有するトランジスタ上に第1の絶縁膜を有し、 前記第1の絶縁膜上に第1乃至第3の配線を有し、 前記第1乃至第3の配線上に第2の絶縁膜を有し、 前記第2の絶縁膜上に第1の電極を有し、 前記第1の電極上に第3の絶縁膜を有し、 前記第3の絶縁膜上に画素電極及び第2の電極を有し、 前記画素電極は、前記第1の電極と重なる第1の領域と、前記第1の電極と重ならない第2の領域と、を有し、 前記画素電極は、前記第1の配線 と 電気的に接続されており、 前記第1の配線は、前記トランジスタのソース又はドレインの一方と電気的に接続されており、 前記第3の配線は、前記トランジスタのソース又はドレインの他方と電気的に接続されており、 前記第1の配線は、前記2つのチャネル形成領域の一方と重なる領域を有し、 前記第3の配線は、前記2つのチャネル形成領域の他方と重なる領域を有し、 前記第2の電極は、前記第1の電極と接触せず、 前記第2の電極は、画素部の外側において前記第2の配線と電気的に接続されており、 前記第2の電極は、前記第1の電極と重なる領域を有し、 前記第2の配線は、コモン電位を供給する機能を有 し、 前記第1の電極と前記第2の電極との間に容量を形成することができる ことを特徴とする液晶表示装置。
- 5請求項1乃至請求項4のいずれか一項において、 前記第3の絶縁膜上に有機樹脂膜を有し、 前記有機樹脂膜は、前記第1の電極の端部と重なる領域を有し、 前記有機樹脂膜は、前記第3の絶縁膜上に接する領域を有し、 前記画素電極は、前記第3の絶縁膜上に接する領域と前記有機樹脂膜 上 に接する領域とを有することを特徴とする液晶表示装置。
- 6請求項1乃至請求項4のいずれか一項において、 前記第1の電極上に有機樹脂膜を有し、 前記有機樹脂膜は、前記第1の電極の端部と重なる領域を有し、 前記有機樹脂膜は、前記第1の電極上に接する領域を有し、 前記画素電極は、前記第3の絶縁膜上に接する領域と前記有機樹脂膜 上 に接する領域とを有することを特徴とする液晶表示装置。
Independent claims6
47 paragraphs, as filed
The present invention is a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface. The present invention relates to a semiconductor device having a circuit composed of the above and a method for manufacturing the same. In particular, the present invention is a pixel The same group (pixel matrix circuit) and the drive circuit (driver circuit) provided around it Electricity represented by a liquid crystal display device or EL (electroluminescence) display device installed on a board An electro-optical device (also called an electronic device) and an electric appliance (with an electronic device) equipped with an electro-optical device. Also referred to).
In the specification of the present application, a semiconductor device is a device that functions by utilizing semiconductor characteristics. In general, the above electro-optic device and electric appliances using the electro-optic device are also included in the semiconductor device. Mu.
Development of a semiconductor device having a large-area integrated circuit formed by TFT on a substrate having an insulating surface Is progressing. Active matrix type liquid crystal display device, EL display device, and close contact type image The age sensor is known as a typical example. In particular, crystalline silicon membranes (typically poly) A TFT (hereinafter referred to as a polysilicon TFT) using a silicon film as an active layer moves by electric field effect. Since the degree is high, it is possible to form various functional circuits.
For example, an active matrix type liquid crystal display device displays an image for each functional block. Pixel part, shift register circuit based on CMOS circuit, level shifter circuit, buff Integrated circuits such as circuits and sampling circuits are formed on a single substrate. In addition, close contact type For image sensors, sample hold circuits, shift register circuits, multiplexer circuits, etc. Which integrated circuit is formed using TFT.
The operating conditions of each of these drive circuits (also called peripheral drive circuits) are not necessarily the same. Since it is not one, naturally the characteristics required for TFT are not a little different. In the pixel part Is a configuration provided with a pixel TFT that functions as a switch element and an auxiliary holding capacity, and is a liquid crystal. It is driven by applying a voltage to. Here, the liquid crystal needs to be driven by alternating current, A method called frame inversion drive is often adopted. Therefore, the required TFT characteristics The off-current value (drain current value that flows when the TFT is off) must be sufficiently low. There was a point. Moreover, since a high drive voltage is applied to the buffer circuit, even if a high voltage is applied. It was necessary to increase the pressure resistance to the extent that it would not break. Also turned on to increase current drive capability It was necessary to secure a sufficient current value (drain current value that flows when the TFT is on).
However, there is a problem that the off-current value of the polysilicon TFT tends to be high. Ma Also, like the MOS transistors used in ICs, etc., the polysilicon TFT has an on-current value. Deterioration phenomenon such as deterioration of is observed. The main cause is hot carrier injection and dray It is considered that hot carriers generated by a high electric field near the engine cause deterioration phenomenon. ing.
Low-concentration drain (LDD: Lightly) as a TFT structure to reduce the off-current value Doped Drain) structure is known. This structure has channel formation regions and high concentrations of impurities A low-concentration impurity region is provided between the source region or drain region to which Yes, this low-concentration impurity region is called the LDD region.
In addition, as a structure to prevent deterioration of the on-current value due to hot carrier injection, so-called The GOLD (Gate-drain Overlapped LDD) structure is known. This structure is in the LDD territory Since the area is arranged so as to overlap the gate wiring via the gate insulating film, it is near the drain. It is effective in preventing hot carrier injection and improving reliability. For example, "Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997 discloses the GOLD structure with sidewalls made of silicon, It has been confirmed that extremely excellent reliability can be obtained compared to TFTs of other structures.
In addition, there are tens to millions of pixels in the pixel section of the active matrix liquid crystal display device. TFTs are arranged in the TFT, and each of the TFTs is provided with a pixel electrode. The liquid crystal is sandwiched However, a counter electrode is provided on the opposite substrate side, forming a kind of capacitor with a liquid crystal as a dielectric. It is made up. Then, the voltage applied to each pixel is controlled by the switching function of the TFT. By controlling the charge on this capacitor, the liquid crystal is driven, and the amount of transmitted light is controlled to display the image. It is a mechanism to show.
However, this capacitor gradually accumulates due to leakage current caused by off-current and the like. Since the amount is reduced, the amount of transmitted light changes, which causes the contrast of the image display to decrease. Was there. Therefore, in the past, a capacitance wiring was provided to separate the capacitor from the capacitor that uses liquid crystal as a dielectric. Capacitors (called holding capacities) are provided in parallel, and the loss of capacitors that use liquid crystal as a dielectric is I was supplementing the amount.
<p> However, the pixel TFT of the pixel part and the logic of the shift register circuit, buffer circuit, etc. The TFT of the clock circuit (also referred to as the drive circuit) (hereinafter referred to as the drive TFT) is required. The characteristics are not always the same. For example, in a pixel TFT, the gate wiring is large. Reverse bias (minus for n-channel TFT) Although a voltage is applied, the TFT of the drive circuit is basically operated by applying a reverse bias voltage. There is nothing. The operating speed of the former may be 1/100 or less of the latter.</p><p> In addition, the GOLD structure is certainly highly effective in preventing deterioration of the on-current value, but on the other hand, it is a normal LD. There was a problem that the off-current value became larger than that of the D structure. Therefore, especially the pixel TFT It was not a preferable structure for. On the contrary, the normal LDD structure suppresses the off-current value. Although highly effective, it was known to be weak against hot carrier injection.</p><p> In this way, a semi with a plurality of integrated circuits such as an active matrix type liquid crystal display device. In a conductor device, it was not always preferable to form all TFTs with the same structure. ..</p><p> Further, as shown in the conventional example, a holding capacity using a capacitance wiring is formed in the pixel portion to provide a sufficient capacity. When trying to secure the amount, the aperture ratio (the ratio of the area where an image can be displayed to the area of one pixel) Had to sacrifice. In particular, as used in projector-type display devices In a small high-definition panel, the pixel area per pixel is also small, so the aperture ratio due to capacitive wiring The decline was a problem.</p><p> The present invention is a technique for solving such a problem, and is arranged in each circuit of a semiconductor device. By making the structure of the TFT suitable according to the function of the circuit, the operability of the semiconductor device The purpose is to improve performance and reliability.</p><p> Further, in a semiconductor device having a pixel portion for another purpose, a holding capacity provided in the pixel is provided. It is an object of the present invention to provide a structure for reducing the area of the space and improving the aperture ratio.</p>
<p> In order to solve the above problems, the configuration of the present invention includes a pixel unit and a drive circuit on the same substrate. In a semiconductor device, the LDD region of the n-channel TFT that forms the drive circuit is partly Alternatively, all of them are formed so as to overlap the gate wiring of the n-channel TFT with a gate insulating film in between. The LDD region of the pixel TFT formed and forming the pixel portion is formed in the gate wiring of the pixel TFT. It is characterized in that it is formed so as not to overlap with the gate insulating film sandwiched between them.</p><p> Further, in addition to the above configuration, a light-shielding film provided on the resin film with a holding capacity of the pixel portion, the said It may be formed of an oxide of a light-shielding film and a pixel electrode. This keeps a very small area Since the holding capacity can be formed, the aperture ratio of the pixels can be improved.</p><p> Further, a more detailed configuration of the present invention is a semiconductor device including a pixel unit and a drive circuit on the same substrate. In the drive circuit, the entire LDD region is connected to the gate wiring with the gate insulating film in between. The first n-channel TFT formed so as to overlap, and a part of the LDD region is a gate insulating film. Includes a second n-channel TFT formed to overlap the gate wiring across the The LDD region is formed in the pixel area so that it does not overlap the gate wiring with the gate insulating film in between. It is characterized in that the pixel TFT is included. Of course, the holding capacity of the pixel part is on the organic resin film. It may be formed of a light-shielding film provided in the light-shielding film, an oxide of the light-shielding film, and a pixel electrode.</p><p> In the above configuration, in the LDD region of the n-channel TFT forming the drive circuit. Is an element belonging to Group 15 of the periodic table at a concentration 2 to 10 times that of the LDD region of the pixel TFT. You just have to include the element. In addition, the LDD region of the first n-channel TFT is channeled. The LDD region of the second n-channel TFT is formed between the formation region and the drain region. It may be formed so as to sandwich the channel formation region.</p><p> Further, the configuration of the present invention relating to the manufacturing process is a semi-conduction including a pixel portion and a drive circuit on the same substrate. In the method of manufacturing the body device, the active layer of the first n-channel TFT forming the drive circuit. In addition, a channel formation region, a source region, a drain region, and the drain region and the channel The process of forming the LDD region between the region and the drive circuit, and the second n-cha that forms the drive circuit. In the active layer of the flannel-type TFT, the channel formation region, the source region, the drain region, and the saw LDD region between the space region and the channel formation region and the drain region and the channel The process of forming the LDD region between the formation region and the p-channel type TF that forms the drive circuit. Steps to form channel formation regions, source regions and drain regions in the active layer of T, and before In the active layer of the pixel TFT that forms the pixel area, the channel formation region, source region, and drain region With the step of forming the region and the LDD region between the drain region and the channel formation region. , And the LDD region of the first n-channel type TFT is entirely the first n-channel type. The second n-channel type is formed by overlapping the gate wiring of the TFT with the gate insulating film sandwiched between them. The LDD region of the TFT is partially connected to the gate wiring of the first n-channel TFT and has a gate insulating film. The LDD region of the pixel TFT is formed by overlapping with each other, and the gate wiring of the pixel TFT is formed. It is characterized in that it is arranged so as not to overlap with the gate insulating film sandwiched between the two.</p><p> Further, the configuration of another invention relating to the manufacturing process is a half including a pixel portion and a drive circuit on the same substrate. In the method for manufacturing a conductor device, the first step of forming an active layer on a substrate and the contact with the active layer. The second step of forming the gate insulating film and the activity of the n-channel TFT that forms the drive circuit. Add elements belonging to Group 15 of the periodic table to the sex layer and n<sup>-</sup>The third step of forming the region and the game The fourth step of forming a conductive film on the insulating film and the p-channel type by patterning the conductive film. In the fifth step of forming the gate wiring of the TFT and the active layer of the p-channel type TFT, the p-chi Using the gate wiring of the channel type TFT as a mask, the elements belonging to Group 13 of the periodic table are self-aligned. Add and p<sup>++</sup>Conduction not patterned in the 6th step of forming the region and the 5th step The seventh step of patterning the film to form the gate wiring of the n-channel TFT and the n-channel Elements belonging to Group 15 of the periodic table are added to the active layer of the channel-type TFT, and n<sup>+</sup>Form a region Mask the 8th step and the gate wiring of the n-channel TFT and the p-channel TFT Add elements belonging to Group 15 of the periodic table in a self-aligned manner as n<sup>--</sup>9th step to form the area And, characterized by having.</p><p> Further, a more detailed configuration of the present invention is a semiconductor device including a pixel unit and a drive circuit on the same substrate. In the method of producing the table, the first step of forming the active layer on the substrate and the game in contact with the active layer. In the second step of forming the insulating film and in the active layer of the n-channel TFT that forms the drive circuit. Add elements belonging to Group 15 of the periodic table to n<sup>-</sup>The third step of forming the region and the gate insulation The fourth step of forming a conductive film on the film and the p-channel type TFT by patterning the conductive film. In the fifth step of forming the gate wiring of the above, and in the active layer of the p-channel type TFT, the p-channel Using the gate wiring of the type TFT as a mask, elements belonging to Group 13 of the periodic table are added in a self-aligned manner. , P<sup>++</sup>The sixth step of forming the region and the conductive film not patterned in the fifth step are combined. The seventh step of turning to form the gate wiring of the n-channel TFT and the n-channel Elements belonging to Group 15 of the periodic table are added to the active layer of the type TFT, and n<sup>+</sup>8th work to form the area Using the gate wiring of the n-channel TFT and the p-channel TFT as a mask Add elements belonging to Group 15 of the periodic table in a self-aligned manner, n<sup>--</sup>The 9th step of forming the area and It is characterized by having.</p><p> In this configuration, p<sup>++</sup>Area, n<sup>+</sup>Area or n<sup>--</sup>The order of the steps to form the region is You may change it as appropriate. The basics of the finally formed TFT in any order The function does not change, and the effect of the present invention is not impaired.</p>
<p> By using the present invention, a circuit having appropriate performance according to the specifications required by the circuit on the same substrate. It becomes possible to arrange the operating performance of the semiconductor device (specifically, the electro-optical device in this case). And reliability was greatly improved.</p><p> In addition, in the pixel part of an electro-optical device represented by AM-LCD, a small area and a large size are used. A holding capacity having a capacity can be formed. Therefore, diagonally 1 inch or less Even in AM-LCD, it is possible to secure sufficient holding capacity without lowering the aperture ratio. It has become possible.</p><p> Further, a semiconductor device having such an electro-optical device as a display medium (specifically, here). The operating performance and reliability of electrical appliances) could also be improved.</p>
<figref num="1">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="2">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="3">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="4">The figure which shows the structure of the holding capacity.</figref><figref num="5">The figure which shows the manufacturing process of the holding capacity.</figref><figref num="6">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="7">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="8">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="9">Cross-sectional structure diagram of an active matrix type liquid crystal display device.</figref><figref num="10">A perspective view of an active matrix type liquid crystal display device.</figref><figref num="11">Top view of the pixel section.</figref><figref num="12">The cross-sectional view which shows the structure of the holding capacity.</figref><figref num="13">The circuit block diagram of the active matrix type liquid crystal display device.</figref><figref num="14">The cross-sectional view which shows the manufacturing process of a crystalline semiconductor film.</figref><figref num="15">The cross-sectional view which shows the manufacturing process of a crystalline semiconductor film.</figref><figref num="16">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="17">Top view and cross-sectional view of the pixel portion.</figref><figref num="18">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="19">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="20">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="21">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="22">The figure which shows the manufacturing process of a pixel part and a drive circuit.</figref><figref num="23">The figure which shows the structure of a pixel part and a drive circuit.</figref><figref num="24">The figure which shows the structure of the active matrix type EL display device.</figref><figref num="25">The figure which shows the top surface structure and the cross-sectional structure of an EL display device.</figref><figref num="26">The figure which shows the cross-sectional structure of an EL display device.</figref><figref num="27">The figure which shows the top surface structure of the pixel part of an EL display device.</figref><figref num="28">The figure which shows the cross-sectional structure of an EL display device.</figref><figref num="29">The figure which shows the circuit structure of the pixel part of an EL display device.</figref><figref num="30">The figure which shows an example of an electric appliance.</figref><figref num="31">The figure which shows an example of an electric appliance.</figref><figref num="32">The figure which shows the structure of an optical engine.</figref><figref num="33">The figure which shows the ID-VG curve of the n channel type TFT.</figref><figref num="34">The figure which shows the relationship between the deterioration rate of the electric field effect mobility and the length of a Lov region.</figref><figref num="35">The figure which shows the time-dependent change of the current consumption and the minimum operating voltage.</figref><figref num="36">The figure which shows the ID-VG curve of the n channel type TFT.</figref><figref num="37">The figure which shows the relationship between the deterioration rate of the electric field effect mobility and the length of a Lov region.</figref><figref num="38">The figure which shows the time-dependent change of the current consumption and the minimum operating voltage.</figref>
Embodiments of the present invention will be described in detail with reference to the following examples. ..
<p> Embodiments of the present invention will be described with reference to FIGS. 1 to 3. Here, it is installed in and around the pixel section. A method of simultaneously producing a TFT of a drive circuit that can be driven will be described.</p><p> [Step of forming active layer and gate insulating film: FIG. 1 (A)] In FIG. 1 (A), the substrate 101 Use a glass substrate, quartz substrate or plastic substrate (including film). Is desirable. In addition, a substrate with an insulating film formed on the surface of a silicon substrate or metal substrate May be.</p><p> Then, on the surface of the substrate 101 on which the TFT is formed, an insulating film containing silicon (silicon) ( In the present specification, a generic term for a silicon oxide film, a silicon nitride film, or a silicon nitride film is used. The base film 102 made of (s) is 100 to 400 nm thick by plasma CVD method or sputtering method. Formed in. In the present specification, the silicon nitride film is SiOxNy (however, 0 < An insulating film represented by x, y <1), which refers to an insulating film containing silicon, oxygen, and nitrogen in a predetermined ratio. Su.</p><p> In this embodiment, as the undercoat film 102, the silicon nitride film 102 is set to 25 to 100 nm, here. Then, to a thickness of 50 nm, apply the silicon oxide film 103 to 50 to 300 nm, here 150 nm. It was formed with a two-layer structure with the thickness of. The base film 102 is installed to prevent impurity contamination from the substrate. It is not necessary to provide it when a quartz substrate is used.</p><p> Next, a known film forming method is to form an amorphous silicon film with a thickness of 20 to 100 nm on the base film 102. Formed in. The amorphous silicon film is preferably at 400 to 550 ° C, although it depends on the hydrogen content. Dehydrogenate by heating for several hours, set the hydrogen content to 5 atom% or less, and perform the crystallization process. It is desirable to do so. In addition, the amorphous silicon film can be formed by other manufacturing methods such as sputtering and vapor deposition. It may be formed, but the impurity elements such as oxygen and nitrogen contained in the film should be sufficiently reduced. Is desirable. Here, the base film and the amorphous silicon film can be formed by the same film forming method. Since it is possible, both may be continuously formed. After forming the base film, it is once exposed to the atmosphere By eliminating it, it is possible to prevent surface contamination, and the characteristics of the manufactured TFTs vary. It is possible to reduce the luck.</p><p> The step of forming a crystalline silicon film from an amorphous silicon film is a known laser crystallization technique. Alternatively, a thermal crystallization technique may be used. In addition, a catalytic element that promotes the crystallization of silicon is used. Alternatively, a crystalline silicon film may be produced by a method of thermal crystallization. In addition, microcrystalline silicon film Or a crystalline silicon film may be directly deposited and formed. In addition, single crystal silico It is connected using the known technology of SOI (Silicon On Insulators) that sticks the insulator on the substrate. A crystalline silicon film may be formed.</p><p> The unnecessary part of the crystalline silicon film formed in this way is removed by etching to form an island-shaped semiconduct. Body membranes (hereinafter referred to as active layers) 104 to 106 were formed. N channels of crystalline silicon membrane In the area where the type TFT is manufactured, 1 × 10 in advance to control the threshold voltage<sup>15</sup>~ 5×10<sup>17</sup>cm<sup>-3</sup>Boron (B) may be added at a certain concentration.</p><p> Next, the active layers 104 to 106 are covered with silicon oxide or silicon nitride as the main component. The gate insulating film 107 was formed. The gate insulating film 107 is preferably 10 to 200 nm. May be formed to a thickness of 50 to 150 nm. For example, N in the plasma CVD method<sub>2</sub>O and Si H<sub>4</sub>A silicon nitride film of 75 nm is formed from the raw material, and then in an oxygen atmosphere or acid. In a mixed atmosphere of element and hydrochloric acid, it is thermally oxidized at 800 to 1000 ° C to form a 115 nm gate insulating film. You may. (Fig. 1 (A))</p><p> [N<sup>-</sup>Region formation: Figure 1 (B)] Active layers 104, 106 and all regions forming the wiring A resist mask 10 on the surface and a part of the active layer 105 (including the region that becomes the channel formation region) 8 to 111 are formed, and an impurity element that imparts n-type is added to form a low-concentration impurity region 112. It was done. This low-concentration impurity region 112 was later gate-insulated into the n-channel TFT of the CMOS circuit. The LDD region that overlaps the gate wiring via the membrane (in the present specification, this LDD region is referred to as the Lov region. Call. In addition, ov means overlap. ) Is an impurity region for forming. It should be noted that , The concentration of the impurity element that imparts n-type contained in the low-concentration impurity region formed here (n)<sup>-</sup>). Therefore, in the present specification, the low-concentration impurity region 112 is defined as n.<sup>-</sup>Called an area It can be changed.</p><p> Here Phosphine (PH<sub>3</sub>) Is plasma-excited without mass separation Phosphorus was added in. Of course, an ion implantation method for mass separation may be used. .. In this step, phosphorus was added to the semiconductor layer underneath through the gate insulating film 107. Addition Phosphorus concentration is 2 × 10<sup>16</sup>~5×10<sup>19</sup>atoms / cm<sup>3</sup>It is preferable to set it in the range of, here Is 1x10<sup>18</sup>atoms / cm<sup>3</sup>And said.</p><p> After that, the resist masks 108 to 111 are removed, and the temperature is 400 to 900 ° C in a nitrogen atmosphere. The heat treatment is preferably performed at 550 to 800 ° C. for 1 to 12 hours, and the mixture added in this step is added. The step of activating the mixture was carried out. Further, this activation may be performed by a laser. It should be noted that Although this step can be omitted, a higher activation rate can be expected if it is performed.</p><p> [Formation of gate wiring: Fig. 1 (C)] The first conductive film 113 is made of tantalum (Ta) and chita. Element (Ti), molybdenum (Mo), tungsten (W) or any It is a conductive material whose main component is the above element, and is formed to a thickness of 10 to 100 nm. First conductive film For 113, for example, tantalum nitride (TaN) or tungsten nitride (WN) may be used. Is desirable.</p><p> Further, a second conductive film 114 is selected from Ta, Ti, Mo, and W on the first conductive film 113. A conductive material whose main component is one of the above elements or any of the above elements, with a thickness of 100 to 400 nm. Formed in. For example, Ta may be formed to a thickness of 200 nm. Also, although not shown, Conductive films 113, 114 (especially) below the first conductive film 113 or above the second conductive film 114. In order to prevent oxidation of the conductive film 114), a silicon film is formed with a thickness of about 2 to 20 nm. It is effective to do.</p><p> [Formation of p-ch gate wiring and p<sup>++</sup>Region formation: Fig. 2 (A)] Resist mask 115 ~ 118 is formed, and the first conductive film and the second conductive film (hereinafter referred to as laminated films) are formed. Ching, p-channel TFT gate wiring (also called gate electrode) 119, gate arrangement Lines 120 and 121 were formed. In addition, here, all the areas above the n-channel TFT Conductive films 122 and 123 were left so as to cover the surface.</p><p> Then, the resist masks 115 to 118 are left as they are to be used as a mask, and the p-channel type T is used. A step of adding an impurity element that imparts p-type to a part of the semiconductor layer 104 on which the FT is formed. went. Here, boron is used as the impurity element, and diborane (B)<sub>2</sub>H<sub>6</sub>) Using IOND It was added by the pup method (of course, the ion implantation method may be used). Here 5x10<sup>20</sup>~3×10<sup>21</sup>atoms / cm<sup>3</sup>Boron was added to the concentration of. The impurity area formed here The concentration of the impurity element that imparts the p-type contained in the region (p<sup>++</sup>). Therefore, the book In the specification, impurity regions 124 and 125 are p.<sup>++</sup>It can be rephrased as an area.</p><p> In this step, the resist masks 115 to 118 are used to form the gate insulating film 10. 7 is removed by etching to expose a part of the active layer 104, and then an impurity source that imparts p-type. The step of adding the element may be performed. In that case, since the acceleration voltage can be low, it is given to the active layer. There is less damage and throughput is improved.</p><p> [Formation of nch gate wiring: Fig. 2 (B)] Next, the resist masks 115 to 118 are After removal, resist masks 126 to 129 are formed, and the gate wiring of the n-channel TFT Formed 130 and 131. At this time, the gate wiring 130 is n<sup>-</sup>Overlapping with region 112 via the gate insulating film 107 Formed.</p><p> [N<sup>+</sup>Region formation: Fig. 2 (C)] Next, the resist masks 126 to 129 were removed, and the resist masks were removed. Gist masks 132-134 were formed. And in the n-channel TFT, the source A step was performed to form an impurity region that functions as a region or drain region. Resist The mask 134 was formed so as to cover the gate wiring 131 of the n-channel TFT. This is after LDD area so that it does not overlap with the gate wiring on the n-channel TFT of the pixel part in the process of This is to form a region.</p><p> Then, an impurity element that imparts n-type was added to form impurity regions 135 to 139. Again, Phosphine (PH<sub>3</sub>) Ion doping method (of course, Ion Implante) The phosphorus concentration in this area is 1 × 10<sup>20</sup>~1×10<sup>21</sup>atoms / cm<sup>3</sup>And said. It should be noted that the n-type contained in the impurity regions 137 to 139 formed here is imparted. The concentration of impurity elements (n)<sup>+</sup>). Therefore, in the present specification, the impurity region 13 7 ~ 139 n<sup>+</sup>It can be rephrased as an area. Also, the impurity region 135 is already n<sup>-</sup>region Strictly speaking, phosphorus was added at a concentration slightly higher than the impurity regions 136 to 139. Including.</p><p> In this step, the resist masks 132 to 134 and the gate wiring 130 are used. The gate insulating film 107 is etched as a screw to expose a part of the active layers 105 and 106. After that, a step of adding an impurity element that imparts n-type may be performed. In that case, the acceleration voltage Since it can be low, it causes less damage to the active layer and improves throughput.</p><p> [N<sup>--</sup>Region formation: Fig. 3 (A)] Next, the resist masks 132 to 134 are removed and the image is drawn. A process of adding an impurity element that imparts n-type to the active layer 106, which is an n-channel TFT of the elementary part. I went about. In the impurity regions 140 to 143 formed in this way, the n<sup>-</sup>1/2 of the area ~ 1/10 concentration (specifically 1 x 10)<sup>16</sup>~5×10<sup>18</sup>atoms / cm<sup>3</sup>) Will add phosphorus Sea urchin. It should be noted that the n-type contained in the impurity regions 140 to 143 formed here is imparted. The concentration of impurity elements (n)<sup>--</sup>). Therefore, in the present specification, the impurity region 14 0 ~ 143 n<sup>--</sup>It can be rephrased as an area. Also, in this process, it is hidden by the gate wiring. N in all impurity regions except the impurity region 167<sup>--</sup>Phosphorus is added at the concentration of , It is very low concentration and can be ignored.</p><p> [Thermal activation process: Fig. 3 (B)] Next, the protective insulation that will later become part of the first interlayer insulating film. A film 144 was formed. The protective insulating film 144 includes a silicon nitride film, a silicon oxide film, and a silicon nitride oxide. It may be formed of a recon film or a laminated film in which they are combined. Also, the film thickness is 100 to 4 It should be 00 nm.</p><p> Then activate the impurity elements that impart the n-type or p-type added at the respective concentrations. Therefore, a heat treatment step was performed. This process is performed by Furnace Annealing Method, Laser Annealing Method, Alternatively, it can be performed by the rapid thermal annealing method (RTA method). Here Fane The activation step was carried out by the sanneal method. Heat treatment is 300 ~ 650 in a nitrogen atmosphere Heat treatment was performed at ° C, preferably 400 to 550 ° C, here 450 ° C, for 2 hours.</p><p> In addition, heat for 1-12 hours at 300-450 ° C in an atmosphere containing 3-100% hydrogen. The treatment was performed and a step of hydrogenating the active layer was performed. This process is half done by heat-excited hydrogen This is the process of terminating the dangling bond of the conductor layer. Plasma as another means of hydrogenation Hydrogenation (using hydrogen excited by plasma) may be performed.</p><p> [Formation of interlayer insulating film, source / drain wiring, light-shielding film, pixel electrode, and holding capacity: Fig. 3 (C) )] After the activation process is completed, an interlayer insulation with a thickness of 0.5 to 1.5 μm is provided on the protective insulating film 144. Membrane 145 was formed. The first is a laminated film composed of the protective insulating film 144 and the interlayer insulating film 145. An interlayer insulating film was used.</p><p> Then a contact hole that reaches the source or drain area of each TFT Was formed, and source wirings 146 to 148 and drain wirings 149 and 150 were formed. Figure Although not shown, in this embodiment, these wirings are made of aluminum with a Ti film of 100 nm and Ti. Lamination of a three-layer structure in which a nium film of 300 nm and a Ti film of 150 nm are continuously formed by a sputtering method. It was made into a film. A laminated film of a copper film and a titanium nitride film is used as the source wiring and drain wiring. You may stay.</p><p> Next, as the passivation film 151, a silicon nitride film, a silicon oxide film, or nitrogen is used. Formed with a silicon oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm) Ta. After that, if hydrogenation treatment is performed in this state, favorable results are obtained for improving the characteristics of the TFT. Was done. For example, from 1 to 12 o'clock at 300 to 450 ° C in an atmosphere containing 3 to 100% hydrogen. The same effect was obtained by performing the heat treatment during the period, or by using the plasma hydrogenation method. Here, a contact hole for connecting the pixel electrode and the drain wiring will be formed later. At the position, an opening may be formed in the passivation film 151.</p><p> Then, a second interlayer insulating film 152 made of an organic resin was formed to a thickness of about 1 μm. Organic Resins include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzo). Cyclobutene) and the like can be used. The advantage of using an organic resin film is the film formation method. It is easy to use, it has a low relative permittivity, so it can reduce parasitic capacitance, and it has excellent flatness. I can raise my throat. It is also possible to use an organic resin film or an organic SiO compound other than those described above. it can. Here, a type of polyimide that is thermally polymerized after being applied to a substrate is used and baked at 300 ° C. Formed.</p><p> Next, in the region to be the pixel portion, a light-shielding film 153 is formed on the second interlayer insulating film 152. Ta. Light-shielding film 153 is selected from aluminum (Al), titanium (Ti), and tantalum (Ta). It was formed to a thickness of 100 to 300 nm with a film containing one of the above elements as a main component. Soshi The surface of the light-shielding film 153 is anodized or plasma-oxidized to 30 to 150 nm (preferably). Furthermore, an oxide (oxide film) 154 having a thickness of 50 to 75 nm) was formed. Here is a light-shielding film An aluminum film or a film containing aluminum as a main component is used as 153, and the oxide 154 As an aluminum oxide film (alumina film) was used.</p><p> In this case, the insulating film is provided only on the surface of the light-shielding film, but the insulating film is a plasma CV. It may be formed by a vapor phase method such as D method, thermal CVD method or sputtering method. Even in that case, the membrane The thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Also, oxidation Silicon film, silicon nitride film, silicon oxide film, DLC (Diamond like carbon) A membrane or an organic resin membrane may be used. Further, a laminated film combining these may be used. I.</p><p> Next, a contact hole reaching the drain wiring 150 is formed in the second interlayer insulating film 152. Then, the pixel electrode 155 was formed. Note that the pixel electrodes 156 and 157 are adjacent to each other. It is a pixel electrode of a pixel. When the pixel electrodes 155 to 157 are used as a transmissive liquid crystal display device, When a transparent conductive film is used and a reflective liquid crystal display device is used, a metal film may be used. here Is a compound of indium oxide and tin oxide (with ITO) to make it a transmissive liquid crystal display device. A film (called) was formed to a thickness of 100 nm by sputtering.</p><p> Further, at this time, a region where the pixel electrode 155 and the light-shielding film 153 overlap each other via the oxide 154. 158 formed a holding capacity.</p><p> Acty having a CMOS circuit forming a drive circuit and a pixel portion on the same substrate in this way. The Bmatrix substrate is completed. The CMOS circuit that forms the drive circuit is an n-channel type. TFT181 and p-channel type TFT182 are formed, and n-channel type TFT is used for the pixel part. Pixel TFT183 was formed.</p><p> In the p-channel type TFT181 of the CMOS circuit, the channel formation region 161 and p<sup>++</sup>Ryo The source region 162 and the drain region 163 formed by the region were formed. Also, n Chane The type TFT182 has a channel formation region 164, a source region 165, and a drain region 16 6. The LDD area (Lov area) 167 that completely overlaps the gate wiring is formed via the gate insulating film. Made. At this time, the source area 165 and the drain area 166 are n, respectively.<sup>+</sup>Area (strictly Is (n<sup>-</sup>+ n<sup>+</sup>) Region), Lov region 167 is n<sup>-</sup>Formed in the area.</p><p> Also, in Fig. 3 (C), a piece of the channel formation region 164 is used to reduce the resistance component as much as possible. The Lov region is placed only on the side (only on the drain region side), but the channel formation region 164 is It may be placed on both sides by sandwiching it.</p><p> In addition, the pixel TFT 183 has channel formation areas 168 and 169, source areas 170, and so on. Drain area 171, LDD area that does not overlap with the gate wiring via the gate insulating film (hereinafter, This LDD area is called the Loff area. Note that off means offset. ) 172 ~ 175 , Loff regions 173, 174 touching n<sup>+</sup>Region (effective in reducing off-current value) 176 Been formed. At this time, the source area 170 and the drain area 171 are n, respectively.<sup>+</sup>Formed in the area And the Loff area 172 ~ 175 is n<sup>--</sup>Formed in the area.</p><p> The present invention is a TFT that forms each circuit according to the circuit specifications required by the pixel unit and the drive circuit. We were able to optimize the structure of the semiconductor device and improve the operating performance and reliability of the semiconductor device. Specifically Specifically, the n-channel TFT has a different arrangement of the LDD area according to the circuit specifications, and the Lov area. Or by using the Loff area properly, high-speed operation or hot carry on the same board A. A TFT structure that emphasizes countermeasures and a TFT structure that emphasizes low off-current operation have been realized.</p><p> For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT182 is high. Shift register circuit, frequency division circuit, signal division circuit, level shifter circuit, which emphasizes high-speed operation, Suitable for logic circuits such as buffer circuits. In addition, the n-channel type TFT183 has a low cost. Suitable for pixel parts and sampling circuits (also called transfer gates) that emphasize current operation doing.</p><p> In addition, the length (width) of the Lov region is 0.5 to 3.0 μm for a channel length of 3 to 7 μm. Tablewise, it may be 1.0 to 1.5 μm. In addition, Loff provided in pixel TFT183 Regions 172 to 175 have a length (width) of 0.5 to 3.5 μm, typically 2.0 to 2.5 μm. It should be done.</p>
<p> In this embodiment, it is connected to the n-channel type TFT401 of the pixel part of the active matrix board. Other configurations of the retained capacity will be described with reference to FIG. The cross-sectional structure shown in Fig. 4 is implemented. It is exactly the same up to the point where oxide 154 is formed according to the fabrication process described in Example 1. So, the structure up to that point has already been explained in Figures 1 to 3. Therefore, in this embodiment, it is referred to as Example 1. The explanation will focus on only the differences.</p><p> Oxide 154 obtained by oxidizing the light-shielding film 153 and the light-shielding film 153 according to the step of Example 1. After forming, spacers 402 to 404 made of an organic resin film are formed. As an organic resin film For polyimide, polyamide, polyimide amide, acrylic, BCB (benzocyclobu) A membrane selected from ten) can be used. Then spacer 402, second interlaminar The edge film 152 and the passivation film 151 are etched to form a contact hole, and the fruit is formed. The pixel electrode 405 is formed of the same material as in Example 1. The pixel electrodes 406 and 407 are adjacent to each other. It is a pixel electrode of another pixel.</p><p> In this way, the light-shielding film 153 and the pixel electrode 405 are placed in the overlapping region via the oxide 154. A holding capacity of 408 is formed. By providing spacers 402 to 404 in this way This prevents short circuits that occur between the light-shielding film 153 and the pixel electrodes 405 to 407. Can be</p><p> The configuration of this embodiment can be combined with the configuration of Example 1.</p>
<p> In this embodiment, it is connected to the n-channel TFT of the pixel portion of the active matrix substrate. Other configurations of the holding capacity will be described with reference to FIG. The cross-sectional structure of FIG. 5 is shown in Example 1. It is exactly the same up to the point where the light-shielding film 153 is formed according to the manufacturing process described. The structure up to this point has already been described in FIGS. Therefore, this embodiment is different from the first embodiment. The explanation will be given focusing only on the points.</p><p> First, after forming the light-shielding film 153 according to the step of Example 1, cover the end of the light-shielding film 153. In this way, spacers 501 to 503 made of an organic resin film are formed. As an organic resin film, Polyimide, polyamide, polyimide amide, acrylic, BCB (benzocyclobutene) A film selected from the above can be used. (Fig. 5 (A) )</p><p> Next, oxide 5 is applied to the exposed surface of the light-shielding film 153 by anodizing or plasma oxidation. Form 04. Oxide 504 is formed in the portion in contact with the spacers 501 to 503. Not done. (Fig. 5 (B))</p><p> Next, the spacer 501, the second interlayer insulating film 152, and the passivation film 151 are attached. The contact hole is formed by ching, and the pixel electrode 505 is formed of the same material as in Example 1. To. The pixel electrodes 506 and 507 are pixel electrodes of other adjacent pixels.</p><p> In this way, the light-shielding film 153 and the pixel electrode 505 are placed in the overlapping region via the oxide 504. A holding capacity of 508 is formed. By providing spacers 501 to 503 in this way This prevents short circuits that occur between the light-shielding film 153 and the pixel electrodes 505 to 507. Can be</p><p> The configuration of this embodiment can be combined with the configuration of Example 1.</p>
<p> In this embodiment, FIGS. 6 to 8 are used for the configuration of the present invention, and the pixels are provided in and around the pixel portion. Creating an active matrix board that simultaneously forms a CMOS circuit, which is the basic form of a drive circuit. The manufacturing method will be described.</p><p> First, a silicon nitride film 602a is placed on the substrate 601 as a base film at 50 to 500 nm. , Typically formed to a thickness of 100 nm. The silicon nitride film 602a is SiH.<sub>4</sub>When N<sub>2</sub>O and NH<sub>3</sub>Is produced as a raw material gas, and the nitrogen concentration contained is 25 atomic%. It was set to be less than 50 atomic%. After that, heat of 450 ~ 650 ° C in a nitrogen atmosphere The treatment was performed to densify the silicon nitride film 602a.</p><p> Furthermore, the thickness of the silicon nitride film 602b is 100 to 500 nm, typically 200 nm. Amorphous semiconductor films (not shown) were continuously formed to a thickness of 20 to 80 nm. In this example, an amorphous silicon film was used as the amorphous semiconductor film, but a microcrystalline silicon film or Amorphous silicon germanium film may be used.</p><p> And Japanese Patent Application Laid-Open No. 7-130652 (US Pat. Nos. 5,643,826 and 5,9) Crystallize the amorphous silicon film by the crystallization means described in No. 23,962) and condense it. A crystalline silicon film (not shown) was formed. The technique described in the publication is a crystal of an amorphous silicon film. Catalytic elements that promote crystallization (nickel, cobalt, germanium, tin, lead, Using one or more elements selected from palladium, iron, and copper, typically nickel) It is a crystallization means. Specifically, in a state where the catalytic element is retained on the surface of the amorphous silicon film. It is heat-treated to change an amorphous silicon film into a crystalline silicon film.</p><p> After the crystalline silicon film is formed in this way, it remains by irradiating it with excimer laser light. Crystallizes the existing amorphous component to improve the overall crystallinity. Excimer laser The light may be a pulse oscillation type or a continuous oscillation type, but by processing the beam shape into a linear shape and irradiating it. It can also be used for large substrates.</p><p> Next, the crystalline silicon film is patterned to form active layers 603 to 606, and further. A gate insulating film 607 was formed by covering them. The gate insulating film 607 is SiH.<sub>4</sub>And N<sub>2</sub>O It is a silicon nitride film produced from and here, in which it is 10 to 200 nm, preferably 5. It was formed with a thickness of 0 to 150 nm. (Fig. 6 (A))</p><p> Next, the entire surface of the active layers 603 and 606 and a part of the active layers 604 and 605 (channel formation region). Resist masks 608 to 611 were formed to cover the area). And phosphin (P H<sub>3</sub>) Is added as an impurity element (phosphorus in this example) that imparts n-type by the ion doping method. And later becomes the Lov area or Loff area n<sup>-</sup>Regions 612 to 614 were formed. In this process Acceleration voltage is 6 to add phosphorus to the active layer beneath it through the gate insulating film 607. Set to 5keV. The concentration of phosphorus added to the active layer is 2 x 10<sup>16</sup>~5×10<sup>19</sup>atoms / cm<sup>3</sup>It is preferable to set it in the range of 1 × 10 here.<sup>18</sup>atoms / cm<sup>3</sup>And said. (Fig. 6 (B)) </p><p> Next, the first conductive film 615 was formed of tantalum nitride (TaN) by a sputtering method. Subsequently, a second conductive film 616 containing aluminum (Al) as a main component is applied to 100 to 300 n. Formed to a thickness of m. (Fig. 6 (C))</p><p> Then, the second conductive film was etched to form the wiring 617. In the case of this embodiment, the second Since the conductive film of is Al, the selectivity of the phosphoric acid solution with the underlying TaN film is good. It was. In addition, tantalum a third conductive film 618 over the first conductive layer 615 and wiring 617. It was formed to a thickness of 100 to 400 nm (200 nm in this example) at Ta). In addition, this A tantalum nitride film may be further formed on the tantalum film. (Fig. 6 (D))</p><p> Next, resist masks 619 to 624 are formed, and a part of the first conductive film and the third conductive film is formed. Etching removed, low resistance connection wiring 625, p-channel TFT gate wiring 626 , The gate wiring 627 of the pixel portion was formed. The conductive films 628 to 630 are n-channel type T. Leave it on the area that will be the FT. In addition, this connection wiring 625 minimizes the wiring resistance. (For example, the wiring part from the input / output terminal of the external signal to the input / output terminal of the drive circuit) To be done. However, due to the structure, the wiring width becomes thick to some extent, so fine wiring is required. It is not suitable for the part.</p><p> The etching of the first conductive film (TaN film) and the second conductive film (Ta film) is CF.<sub>4</sub>And O<sub>2</sub>of It could be done with a mixed gas. Then, leave the resist masks 619 to 624 as they are. Then, an impurity source that imparts p-type to a part of the active layer 603 on which the p-channel type TFT is formed. The step of adding the element was carried out. Here, boron is used as the impurity element, and diborane (B)<sub>2</sub>H<sub>6</sub>) Was added by the ion doping method (of course, the ion implantation method may be used). .. Boron addition concentration is 5 × 10<sup>20</sup>~3×10<sup>21</sup>atoms / cm<sup>3</sup>(2 × 10 in this example<sup>21</sup>atoms /cm<sup>3</sup>). And p with high concentration of boron added<sup>++</sup>Formed regions 631 and 632 Ta. (Fig. 7 (A) )</p><p> In this step, the gate insulating film is used as a mask from resist masks 619 to 624. After etching 107 to expose a part of the active layer 603, a step of adding boron is performed. You may. In that case, since the acceleration voltage can be low, there is little damage to the active layer. , Throughput is also improved.</p><p> Next, after removing the resist masks 619 to 624, a new resist mask 633 to 6 is used. Formed 38. This is for forming the gate wiring of the n-channel TFT. Gate wiring 639 to 641 of n-channel TFT was formed by dry etching method. .. At this time, gate wiring 639 and 640 are n<sup>-</sup>Shaped to overlap part of areas 612-614 It was done. (Fig. 7 (B))</p><p> Next, after removing the resist masks 633 to 638, new resist masks 642 to 6 Formed 47. Resist masks 644 and 646 are n-channel TFT gate wiring 64 0, 641 and n<sup>-</sup>It was formed so as to cover a part of the area.</p><p> Then, 1 × 10 impurity elements (phosphorus in this example) that impart n-type are added.<sup>20</sup>~1×10<sup>21</sup>at oms / cm<sup>3</sup>(5 × 10 in this example<sup>20</sup>atoms / cm<sup>3</sup>) To the active layer 604 ~ 606 n<sup>+</sup>Regions 647 to 653 were formed. (Fig. 7 (C))</p><p> In this step, the gate insulating film 107 is used with the resist masks 642 to 647. Is removed by etching to expose a part of the active layers 604 to 606, and then phosphorus is added. May be done. In that case, since the acceleration voltage can be low, there is little damage to the active layer. It also improves throughput.</p><p> Next, the resist masks 642 to 646 are removed to form an n-channel TFT in the pixel area. A step of adding an impurity element (phosphorus in this example) that imparts n-type to the sex layer 606 was performed. Thus n<sup>-</sup>Concentration of 1/2 to 1/10 of the region (specifically 1 x 10)<sup>16</sup>~5×10<sup>18</sup>ato ms / cm<sup>3</sup>) With phosphorus added n<sup>--</sup>Regions 654 to 657 were formed.</p><p> Also, in this process, all defects except the impurity areas 658 to 660 hidden by the gate wiring N in the pure area<sup>--</sup>Phosphorus was added at the concentration of. In fact, its concentration is so low that it is absent You can see it. However, strictly speaking, the area indicated by 659 and 660 is n.<sup>-</sup>Is an area On the other hand, the regions indicated by 661 and 662 are (n).<sup>-</sup>+ n<sup>--</sup>) Region, and the above n<sup>-</sup>Area 659 , Contains phosphorus at slightly higher concentrations than 660. (Fig. 8 (A)) </p><p> Next, the protective insulating film 663 with a thickness of 100 to 400 nm is SiHed by the plasma CVD method.<sub>4</sub>, N<sub>2</sub>O , NH<sub>3</sub>It was formed of a silicon nitride film made from. Content in this silicon nitride film It was desirable to form the hydrogen concentration so that it would be 1 to 30 atomic%. Protective insulating film 66 3 is also a silicon oxide film, a silicon nitride film, or a laminated film that combines them. Can be used.</p><p> Then activate the impurity elements that impart the n-type or p-type added at the respective concentrations. Therefore, a heat treatment step was performed. This process is performed by Furnace Annealing Method, Laser Annealing Method, Alternatively, it can be performed by the rapid thermal annealing method (RTA method). Here Fane The activation step was carried out by the sanneal method. Heat treatment is 300 ~ 650 in a nitrogen atmosphere Heat treatment was performed at ° C, preferably 400 to 550 ° C, here 450 ° C, for 2 hours.</p><p> In addition, heat for 1-12 hours at 300-450 ° C in an atmosphere containing 3-100% hydrogen. The treatment was performed and a step of hydrogenating the active layer was performed. This process is carried out by thermally excited hydrogen This is the process of terminating the dangling bond of the semiconductor layer. As another means of hydrogenation, Plas Hydrogenation (using plasma-excited hydrogen) May be done. (Fig. 8 (B))</p><p> After completing the activation process, an interlayer insulating film 6 with a thickness of 0.5 to 1.5 μm is placed on the protective insulating film 663. Formed 64. The first interlayer film is a laminated film composed of the protective insulating film 663 and the interlayer insulating film 664. It was used as an insulating film.</p><p> Then a contact hole that reaches the source or drain area of each TFT Was formed, and source wirings 665 to 668 and drain wirings 669 to 672 were formed. Na Although not shown, the drain wires 669 and 670 are the same to form a CMOS circuit. It is connected as one wire. In addition, the connection wiring 673, 67 that connects the input / output terminals and the circuits. 4 was also formed at the same time. Although not shown, in this embodiment, this wiring is used with a Ti film of 100. Aluminum film 300 nm including nm and Ti, Ti film 150 nm are continuously sputtered. The formed three-layer structure laminated film was used.</p><p> Next, as the passivation film 675, a silicon nitride film, a silicon oxide film, or nitrogen is used. Formed with a silicon oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm) Ta. Passivation membrane 675 is SiH by plasma CVD method<sub>4</sub>, N<sub>2</sub>O, NH<sub>3</sub>Formed from Silicon nitride film, or SiH<sub>4</sub>, N<sub>2</sub>, NH<sub>3</sub>With a silicon nitride film made from It should be formed.</p><p> First, N prior to the formation of the membrane<sub>2</sub>O, N<sub>2</sub>, NH<sub>3</sub>Etc. by plasma hydrogenation treatment A hydrogenation process was performed. The hydrogen excited by the plasma treatment is provided in the first interlayer insulating film. If it is supplied and the substrate is heated to 200 to 400 ° C, the hydrogen will be diffused to the lower layer side as well. The sex layer could be hydrogenated. Although the conditions for producing this passivation film are particularly limited. However, it is desirable to use a dense film.</p><p> Further, after forming the passivation film, a hydrogenation step may be further performed. For example Heat treatment at 300-450 ° C for 1-12 hours in an atmosphere containing 3-100% hydrogen. The same effect was obtained by using the plasma hydrogenation method. In addition, here later At the position where a contact hole for connecting the pixel electrode and the drain wiring is formed in An opening may be formed in the passivation film 151.</p><p> Then, a second interlayer insulating film 676 made of an organic resin was formed to a thickness of about 1 μm. Organic Resins include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzo). Cyclobutene) and the like can be used. The advantage of using an organic resin film is the film formation method. It is easy to use, it has a low relative permittivity, so it can reduce parasitic capacitance, and it has excellent flatness. I can raise my throat. In addition, organic resin films other than those mentioned above and those with also be used as the machine-based SiO compound it can. Here, a type of polyimide that is thermally polymerized after being applied to a substrate is used and baked at 300 ° C. Formed.</p><p> Next, in the region to be the pixel portion, a light-shielding film 677 is formed on the second interlayer insulating film 676. Ta. Light-shielding film 153 is selected from aluminum (Al), titanium (Ti), and tantalum (Ta). It was formed to a thickness of 100 to 300 nm with a film containing one of the above elements as a main component. It should be noted that If an insulating film such as a silicon oxide film is formed on the second interlayer insulating film 676 at 5 to 50 nm. , The adhesion of the light-shielding film formed on this could be improved. Also, the first made of organic resin CF on the surface of the interlayer insulating film 676 of 2<sub>4</sub>When plasma treatment using gas is applied, surface modification is performed. It was possible to improve the adhesion of the light-shielding film formed on the film.</p><p> Further, it is possible to form not only a light-shielding film but also other connection wiring. For example, drive times It is possible to form a connection wiring that connects circuits in the road. However, in that case, use a light-shielding film or connection wiring. Before forming the film to be formed, a contact hole is formed in the second interlayer insulating film in advance. There is a need.</p><p> Next, the surface of the light-shielding film 677 is anodized or plasma-oxidized (anodized in this example). According to the method), anodized oxide 678 with a thickness of 30 to 150 nm (preferably 50 to 75 nm) Formed. In this embodiment, the light-shielding film 677 is mainly composed of an aluminum film or aluminum. Aluminum oxide film (alumina film) is formed as anodic oxide 678 because the film is used. Made.</p><p> At the time of anodic oxidation treatment, ethylene glycol tartrate having a sufficiently low alkali ion concentration is first used. A solution was prepared. This is a 15% aqueous solution of ammonium tartrate and ethylene glycol Is a 2: 8 mixed solution, and ammonia water is added to this solution to make the pH 7 ± 0.5. Adjusted to sea urchin. Then, a platinum electrode serving as a cathode is provided in this solution, and a light-shielding film 677 is formed. Immerse the substrate in the solution, and use the light-shielding film 677 as the anode, and keep it constant (several mA to several tens of mA). A current was applied. The voltage between the cathode and anode in solution changes over time as the oxide grows. However, adjust the voltage so that the current becomes constant, and when it reaches 150V, make the voltage constant. And held for 15 minutes. In this way, the surface of the light-shielding film 677 has a thickness of 50 to 75 nm. Anodized oxide 678 could be formed. Numerical values related to the anodizing method shown here. Is only an example, and the optimum value can naturally change depending on the size of the element to be manufactured and the like.</p><p> In addition, although the insulating film is provided only on the surface of the light-shielding film here, the insulating film is a plasma CV. It may be formed by a vapor phase method such as D method, thermal CVD method or sputtering method. Even in that case, the membrane The thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Also, oxidation Silicon film, silicon nitride film, silicon oxide film, DLC (Diamond like carbon) A membrane or an organic resin membrane may be used. Further, a laminated film combining these may be used. I.</p><p> Next, the drain wiring 672 is reached on the second interlayer insulating film 676 and the passivation film 675. A contact hole was formed to form a pixel electrode 679. The pixel electrodes 680 and 6 Reference numeral 81 denotes pixel electrodes of different pixels adjacent to each other. Pixel electrodes 679 to 681 are transmissive type A transparent conductive film is used for a liquid crystal display device, and gold is used for a reflective liquid crystal display device. A genus membrane may be used. Here, indium oxide and acid are used to make a transmissive liquid crystal display device. A compound (ITO) film with tin oxide was formed to a thickness of 100 nm by a sputtering method.</p><p> At this time, the pixel electrode 679 and the light-shielding film 677 overlapped with each other via the anodized oxide 678. Region 682 formed the retention capacity.</p><p> In this way, an active machine having a CMOS circuit as a drive circuit and a pixel unit on the same board The trick board is completed. The drive circuit is a p-channel type TFT801, n-channel type. TFT802 and 803 are formed, and the pixel part is a pixel TFT80 consisting of an n-channel type TFT. 4 was formed. (Fig. 8 (C))</p><p> In the p-channel type TFT801 of the CMOS circuit, the channel formation region 701 and p<sup>++</sup>The source region 702 and the drain region 703 formed by the regions were formed.</p><p> In addition, the n-channel type TFT802 includes a channel formation area 704, a source area 705, and the like. A drain region 706 and a Lov region 707 were formed on one side of the channel formation region. This At, the source area 705 and the drain area 706 are (n), respectively.<sup>-</sup>+ n<sup>+</sup>) Formed in the area Lov region 707 is n<sup>-</sup>Formed in the area. In addition, the Lov area 707 completely overlaps with the gate wiring. Was formed.</p><p> In addition, the n-channel type TFT803 includes a channel formation area 708, a source area 709, and the like. Drain region 710, and Lov regions 711a, 712a and on both sides of the channel formation region Loff regions 711b and 712b were formed. At this time, the source area 709 and the drain area 7 10 is each (n<sup>-</sup>+ n<sup>+</sup>) Region, Lov region 711a, 712a is n<sup>-</sup>Area, Loff area 71 1b and 712b are (n<sup>--</sup>+ n<sup>-</sup>) Formed in the region. In this structure, a part of the LDD area Is arranged so as to overlap the gate wiring, so that the Lov area and the Loff area are realized. ..</p><p> Further, in the pixel TFT 804, the channel formation regions 713 and 714, the source region 715, N in contact with drain area 716, Loff area 717 to 720, Loff area 718, 719<sup>+</sup>Region 721 was formed. At this time, the source area 715 and the drain area 716 are n, respectively.<sup>+</sup>Formed by regions, Loff regions 717 to 720 are n<sup>--</sup>Formed in the area.</p><p> In this embodiment, each circuit is formed according to the circuit specifications required by the pixel unit and the drive circuit. By optimizing the structure of the FT, we were able to improve the operating performance and reliability of the semiconductor device. Specifically, the n-channel TFT has different LDD region arrangements according to the circuit specifications, and Lov. High-speed operation or hot key on the same board by using different areas or Loff areas. We have realized a TFT structure that emphasizes measures against carriers and a TFT structure that emphasizes low off-current operation.</p><p> For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT802 is high. Shift register circuit, frequency division circuit, signal division circuit, level shifter circuit, which emphasizes high-speed operation, Suitable for logic circuits such as buffer circuits. That is, one side of the channel formation region (dray) By arranging the Lov region only on the side of the region), it is hot while reducing the resistance component as much as possible. The structure emphasizes career measures. In the case of the above circuit group, the functions of the source region and drain region do not change, and carriers (electrons) This is because the direction of movement of) is constant. However, if necessary, L on both sides of the channel formation region You can also place an ov area.</p><p> In addition, the n-channel TFT803 emphasizes both hot carrier countermeasures and low off-current operation. Suitable for sampling circuits (sample hold circuits). That is, the Lov area is placed. By doing so, it becomes a hot carrier countermeasure, and by arranging the Loff area, low off current operation is achieved. It was realized. In addition, the function of the source area and the drain area of the sampling circuit is reversed and the carry Since the moving direction of a changes by 180 °, the structure should be line-symmetrical around the gate wiring. Must be. In some cases, only the Lov region may be used.</p><p> In addition, the n-channel type TFT804 has a pixel section that emphasizes low off-current operation and sampling times. Suitable for roads (sample hold circuit). That is, it may be a factor that increases the off-current value. Low off-current operation is realized by arranging only the Loff area without arranging the Lov area. .. In addition, the LDD region with a concentration lower than the LDD region of the drive circuit should be used as the Loff region. Therefore, even if the on-current value drops a little, measures are taken to thoroughly reduce the off-current value. Sa In addition, n<sup>+</sup>Region 721 has been found to be very effective in reducing off-current values. To.</p><p> In addition, the length of the Lov region 707 of the n-channel TFT802 is longer than the channel length of 3 to 7 μm. The width (width) may be 0.5 to 3.0 μm, typically 1.0 to 1.5 μm. Also n The length (width) of the Lov regions 711a and 712a of the channel type TFT803 is 0.5 to 3.0 μm. , Typically 1.0 ~ 1.5μm, Loff area 711b, 712b length (width) is 1.0 ~ It may be 3.5 μm, typically 1.5 to 2.0 μm. Also installed in pixel TFT804 The length (width) of the Loff region 717 to 720 is 0.5 to 3.5 μm, typically 2. It may be 0 to 2.5 μm.</p><p> Furthermore, the p-channel type TFT801 is formed in a self-aligned manner. Chanel type TFT802 ~ 804 are formed in a non-self-aligned manner. The point is also one of the features of the present invention.</p><p> In this embodiment, the active matrix substrate configuration described in the first embodiment is an n-channel type. Since the configuration of TFT803 is only added, the thin film material in the manufacturing process and the impurity addition process The conditions described in Example 1 can be used as they are for the numerical range, the film thickness range of the thin film, and the like. Noh. Further, it is possible to combine the configuration of this embodiment with the configuration of Example 2 or Example 3. Noh.</p>
<p> In this example, an active matrix type liquid crystal display device is used from an active matrix substrate. The manufacturing process will be described. As shown in FIG. 9, the alignment film 9 is applied to the substrate in the state shown in FIG. 8 (C). Form 01. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 903 and an alignment film 904 were formed on the substrate 902 on the opposite side. Shape the alignment film After it is formed, it is subjected to rubbing treatment to orient the liquid crystal molecules with a certain pretilt angle. Sea urchin. Then, the pixel part and the active matrix board on which the CMOS circuit is formed are paired. A sealing material, a spacer (both not shown), etc. are used to connect the facing substrate by a known cell assembly process. And stick them together. After that, liquid crystal material 905 is injected between both substrates, and a sealant (not shown). Completely sealed by. A known liquid crystal material may be used as the liquid crystal material. In this way The active matrix type liquid crystal display device shown in FIG. 9 has been completed.</p><p> Next, the configuration of this active matrix type liquid crystal display device is shown in the perspective view of FIG. 10 and FIG. 11 This will be described with reference to the top view of. 10 and 11 are associated with the cross-sectional structural views of FIGS. 6 to 8. Therefore, a common code is used. In addition, the cross-sectional structure along A-A'shown in FIG. 11 (B) Corresponds to the cross-sectional view of the pixel portion shown in FIG. 8 (C).</p><p> The active matrix substrate includes the pixel portion 1001 formed on the glass substrate 601 and the pixel portion 1001. It is composed of a scanning (gate) line driving circuit 1002 and a signal (source) line driving circuit 1003. The pixel TFT 804 in the pixel section is an n-channel TFT, and the drive circuit provided around it is C. It is configured on the basis of a MOS circuit. Scanning (gate) line drive circuit 1002 and signal ( The source) line drive circuit 1003 has a gate wiring 641 and a source wiring 668, respectively, and the pixel part 1 It is connected to 001. Also, is it the external input / output terminal 1005 to which the FPC1004 is connected? Connection wirings 625 and 673 to the input / output terminals of the drive circuit are provided.</p><p> FIG. 11 is a top view showing a part (one pixel) of the pixel portion 1001. Here in Figure 11 (A) Is a top view showing the superposition of the active layer, gate wiring, and source wiring, and the figure (B) is the top view. It is a top view which shows the state which superposed the light-shielding film and the pixel electrode on top. In FIG. 11 (A), The gate wiring 641 intersects with the active layer 606 below it via a gate insulating film (not shown). I'm pointing. Although not shown, the active layer 606 includes a source region and a drain region. , N<sup>--</sup>A Loff region consisting of regions is formed. Also, 1101 is active with source wiring 668. The contact part with the sex layer 606, 1102 is the contour between the drain wiring 672 and the active layer 606. It is a part of the kuto.</p><p> Further, in FIG. 11 (B), an anodized oxide (shown here) is formed on the surface of the pixel TFT. There is no light-shielding film 677 on which (pointing to the anodized oxide 678 in Fig. 8 (C)) is formed, and each pixel Pixel electrodes 679 to 681 provided in and are formed. And the light-shielding film 677 and pixels A holding capacity 682 is formed in the region where the electrode 679 and the electrode 679 overlap with each other via the anodized oxide. In addition, 1 Reference numeral 103 denotes a contact portion between the drain wiring 672 and the pixel electrode 679.</p><p> In this example, an alumina film having a high relative permittivity of 7 to 9 was used as the dielectric material for the holding capacity. Therefore, it is possible to reduce the area for forming the required capacity. Further, the light-shielding film formed on the pixel TFT as in this embodiment is used as one electrode of the holding capacity. By doing so, the aperture ratio of the image display unit of the active matrix type liquid crystal display device can be improved. Was done.</p><p> The active matrix type liquid crystal display device of this embodiment has the structure described in Example 4. Although explained in light of reference, the act can be freely combined with any of the configurations of Examples 1 to 3. A live matrix type liquid crystal display device can be manufactured.</p>
<p> The holding capacity provided for each pixel of the pixel portion is the electrode that is not connected to the pixel electrode (the present invention). In the case of, the holding capacity can be formed by setting the light-shielding film) to a fixed potential. On the spot In that case, the light-shielding film is in a floating state (electrically isolated state) or a common potential (as data). It is desirable to set it to the intermediate potential of the transmitted image signal).</p><p> Therefore, in this embodiment, FIG. 12 is used for the connection method when the light-shielding film is fixed at the common potential. I will explain. In FIG. 12 (A), 1201 is a pixel produced in the same manner as in Example 1. It is a TFT, and 1202 is a light-shielding film that functions as one electrode of the holding capacity. Light-shielding film 1 202 extends to the outside of the pixel portion, and has a second interlayer insulating film 1204 and a passivation film 1. Power line 120 that gives a common potential through the contact hole 1206 provided in 205 It is connected to 3.</p><p> In this way, outside the pixel section, it is electrically connected to the power line that gives a common potential. Can be set to the common potential. Therefore, in this case, before forming the light-shielding film 1202 A process to etch the second interlayer insulating film 1204 and passivation film 1205 is required. Become.</p><p> Next, in FIG. 12B, 1207 is a pixel TFT produced in the same manner as in Example 1. 1208 is a light-shielding film that functions as one electrode of the holding capacity. Light-shielding film 1208 Extends to the outside of the pixel area, and in the region indicated by 1209, the conductive film 1210 and the oxide Overlapping via 1211. This conductive film 1210 is a conductor formed at the same time as the pixel electrode 1212. It is an electric film.</p><p> The conductive film 1210 has a second interlayer insulating film 1213 and a passivation film 121. With the power line 1216 that gives a common potential through the contact hole 1215 provided in 4. You are connected. At this time, in the region 1209, the light-shielding film 1208, the oxide 1211, and the conductive film 12 A capacitor consisting of 10 is formed. This capacitor is actually driven by AC Short circuit. That is, in region 1209, the light-shielding film 1208 and the conductive film 12 are electrostatically coupled. Since the 10 is electrically connected, the light-shielding film 1208 and the power line 1216 are practically connected. Is done.</p><p> By adopting the structure shown in Fig. 12 (B) in this way, the light-shielding film can be used without increasing the number of steps. It is possible to set the mon potential.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 5. Noh.</p>
<p> FIG. 13 shows an example of the circuit configuration of the active matrix substrate shown in the fourth embodiment. Real The active matrix board of the example is the source signal line side drive circuit 1301 and the gate signal line side. Drive circuit (A) 1307, gate signal line side drive circuit (B) 1311, precharge circuit 1 It has 312 and a pixel unit 1306. The source signal line side drive circuit 1301 is a shift register. Star circuit 1302, level shifter circuit 1303, buffer circuit 1304, sampling times It has road 1305. In addition, the gate signal line side drive circuit (A) 1307 is a shift register. It is equipped with a star circuit 1308, a level shifter circuit 1309, and a buffer circuit 1310. Ge The drive circuit (B) 1311 on the signal line side has the same configuration.</p><p> Here, the shift register circuits 1302 and 1308 have a drive voltage of 5 to 16 V (typically 1). 0V), and the n-channel TFT used in the CMOS circuit that forms the circuit is shown in Fig. 8 (C). The structure indicated by 802 in is suitable.</p><p> In addition, the level shifter circuits 1303 and 1309 and the buffer circuits 1304 and 1310 are driven. The dynamic voltage is as high as 14 to 16V, but like the shift register circuit, the n-cha in Fig. 8 (C) CMOS circuits including flannel type TFT802 are suitable. In addition, the gate wiring is double gate The structure is effective in improving the reliability of the circuit.</p><p> In addition, the sampling circuit 1305 has a drive voltage of 14 to 16V, but it has a source region and a voltage. Since the rain region is inverted and the off-current value needs to be reduced, the n-channel in Fig. 8 (C) CMOS circuits including the Le-type TFT803 are suitable. In addition, actually form the sampling circuit When it is formed, it should be formed by combining an n-channel TFT and a p-channel TFT. To.</p><p> In addition, the pixel section 1306 has a drive voltage of 14 to 16V, which is different from the sampling circuit 1305. Since it requires a lower off-current value, it has a complete LDD structure (Lov region is placed). It is desirable to have a structure that does not exist), and the n-channel TFT 804 shown in Fig. 8 (C) is a pixel TFT. It is desirable to use as.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 2 to 6. It is possible.</p>
<p> In this example, FIG. 14 shows a step of forming an active layer to be an active layer (active layer) of the TFT. It will be described using. First, 200 nm-thick nitrogen on a substrate (glass substrate in this example) 1401. Base film 1402 made of silicon oxide film and amorphous semiconductor film with a thickness of 50 nm (not in this example) Crystalline silicon film) 1403 is continuously formed without being released to the atmosphere.</p><p> Next, an aqueous solution (acetic acid) containing a catalytic element (nickel in this example) of 10 ppm in terms of weight. Nickel aqueous solution) is applied by the spin coating method, and the catalyst element-containing layer 1404 is coated with an amorphous semiconductor. It is formed on the entire surface of the film 1403. Catalytic elements that can be used here are other than nickel (Ni). , Germanium (Ge), Iron (Fe), Palladium (Pd), Tin (Sn), Lead (Pb) , Cobalt (Co), Platinum (Pt), Copper (Cu), Gold (Au). ( Figure 14 (A))</p><p> Further, in this embodiment, the method of adding nickel by the spin coating method was used, but the vapor deposition method or the method of adding nickel was used. Amorphous semiconductor with a thin film (nickel film in the case of this example) made of catalytic elements by the putter method or the like. The means for forming on the film may be taken.</p><p> Next, prior to the crystallization process, a heat treatment process is performed at 400 to 500 ° C for about 1 hour, and water is used. After desorbing the element from the membrane, 4-1 at 500 to 650 ° C (preferably 550 to 570 ° C). Heat treatment is performed for 2 hours (preferably 4 to 6 hours). In this example, heat at 550 ° C for 4 hours The treatment is performed to form a crystalline semiconductor film (crystalline silicon film in this example) 1405. ( Figure 14 (B)) </p><p> Next, a gettering process that removes the nickel used in the crystallization process from the crystalline silicon film. Do the same. First, a mask insulating film 1406 is applied to the surface of the crystalline semiconductor film 1405 at 150 nm. It is formed to a thickness and the opening 1407 is formed by patterning. And the exposed crystalline material A step of adding an element belonging to Group 15 of the periodic table (phosphorus in this example) to the semiconductor film is performed. U. 1x10 by this process<sup>19</sup>~1×10<sup>20</sup>atoms / cm<sup>3</sup>Gettering with phosphorus at the concentration of Region 1408 is formed. (Fig. 14 (C))</p><p> Next, in a nitrogen atmosphere, 450 to 650 ° C (preferably 500 to 550 ° C), 4 to 24:00 A heat treatment step is performed for an interval (preferably 6 to 12 hours). Crystalline semiconductor by this heat treatment process Nickel in the film moves in the direction of the arrow, and the gettering area is due to the gettering action of phosphorus. Captured in area 1408. That is, since nickel is removed from the crystalline semiconductor film, the crystal The nickel concentration contained in the quality semiconductor film 1409 is 1 × 10.<sup>17</sup>atms / cm<sup>3</sup>Below, preferably 1 × 10<sup>16</sup>atms / cm<sup>3</sup>It can be reduced to the following. (Fig. 14 (D))</p><p> Then, after removing the mask insulating film 1406, the gettering region 1408 is completely removed. Patterning is performed so as to remove the active layer 1410. In addition, in Fig. 14 (E), it is active. Although only one sex layer 1410 is shown, the simultaneous formation of multiple active layers on the substrate. Needless to say.</p><p> The active layer 1410 formed as described above is a catalytic element that promotes crystallization (here, here. By using nickel), it is formed of a crystalline semiconductor film with very good crystallinity. .. In addition, after crystallization, the catalytic element is removed by the gettering action of phosphorus, and the active layer The concentration of catalytic elements remaining in 1410 is 1 × 10.<sup>17</sup>atms / cm<sup>3</sup>Below, preferably 1 × 10<sup>16</sup>atms / cm<sup>3</sup>It is as follows.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 7. It is possible.</p>
<p> In this example, Fig. 15 shows the process of forming the active layer that becomes the active layer (active layer) of the TFT. It will be described using. Specifically, Japanese Patent Application Laid-Open No. 10-247735 (US Application No. 09/03) Use the technology described in (4,041).</p><p> First, 200 nm-thick silicon nitride oxide is placed on a substrate (glass substrate in this embodiment) 1501. Undercoat film 1502 made of film and amorphous semiconductor film with a thickness of 50 nm (in this example, amorphous silicon film) ) Form 1503 continuously without releasing it to the atmosphere. Next, the mask made of silicon oxide film is removed. The marginal membrane 1504 is formed to a thickness of 200 nm to form the opening 1505.</p><p> Next, an aqueous solution (vinegar) containing a catalytic element (nickel in this example) of 100 ppm in terms of weight. Nickel acid aqueous solution) is applied by a spin coating method to form a catalyst element-containing layer 1506. At this time, the catalyst element-containing layer 1506 is selectively selected in the region where the opening 1505 is formed. Contact the amorphous semiconductor film 1503. The catalytic element that can be used here is nickel (Ni). Besides, germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead Elements such as (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au) is there. (Fig. 15 (A))</p><p> Further, in this embodiment, the method of adding nickel by the spin coating method was used, but the vapor deposition method or the method of adding nickel was used. Amorphous semiconductor with a thin film (nickel film in the case of this example) made of catalytic elements by the putter method or the like. The means for forming on the film may be taken.</p><p> Next, prior to the crystallization process, a heat treatment process is performed at 400 to 500 ° C for about 1 hour, and water is used. After desorbing the element from the membrane, 6 to 1 at 500 to 650 ° C (preferably 550 to 600 ° C). Heat treatment is performed for 6 hours (preferably 8 to 14 hours). In this example, 14 hours at 570 ° C Heat treatment is performed. As a result, the direction parallel to the approximate substrate (arrows) starting from the opening 1505. Crystallization progresses in the direction shown), and a crystalline semiconductor film with macroscopic crystal growth directions aligned (this implementation) In the example, a crystalline silicon film) 1507 is formed. (Fig. 15 (B)) </p><p> Next, a gettering process that removes the nickel used in the crystallization process from the crystalline silicon film. Do the same. In this embodiment, the mask insulating film 1504 formed earlier is used as a mask as it is. A step of adding an element belonging to Group 15 of the periodic table (phosphorus in this example) was performed, and the opening 150 1 × 10 on the crystalline semiconductor film exposed in 5.<sup>19</sup>~1×10<sup>20</sup>atoms / cm<sup>3</sup>Phosphorus-containing ge at the concentration of Form the tattering region 1508. (Fig. 15 (C))</p><p> Next, in a nitrogen atmosphere, 450 to 650 ° C (preferably 500 to 550 ° C), 4 to 24:00 A heat treatment step is performed for an interval (preferably 6 to 12 hours). Crystalline semiconductor by this heat treatment process Nickel in the film moves in the direction of the arrow, and the gettering area is due to the gettering action of phosphorus. Captured in territory 1508. That is, since nickel is removed from the crystalline semiconductor film, the crystal The nickel concentration contained in the quality semiconductor film 1509 is 1 × 10.<sup>17</sup>atms / cm<sup>3</sup>Below, preferably 1 × 10<sup>16</sup>atms / cm<sup>3</sup>It can be reduced to the following. (Fig. 15 (D))</p><p> Then, after removing the mask insulating film 1504, the gettering region 1508 is completely removed. Patterning is performed so as to remove the active layer 1510. In addition, in Fig. 15 (E), it is active. Although only one sex layer 1510 is shown, the simultaneous formation of multiple active layers on the substrate. Needless to say.</p><p> The active layer 1510 formed as described above is a catalytic element that promotes crystallization (here, here. By selectively adding nickel) to crystallize, a crystalline semiconduct with very good crystallinity It is formed by the body membrane. Specifically, rod-shaped or columnar crystals are arranged in a specific direction. It has a crystal structure. In addition, after crystallization, the catalytic element is used as a gettering action for phosphorus. The concentration of catalytic elements remaining in the active layer 1510 is 1 × 10<sup>17</sup>atms / cm<sup>3</sup>Below, preferably 1 × 10<sup>16</sup>atms / cm<sup>3</sup>It is as follows.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 7. It is possible.</p>
<p> In Examples 8 and 9, in order to getter the catalytic element used for crystallizing the semiconductor film. However, in this example, when the above catalytic element is gettered using another element. Will be described.</p><p> First, a crystalline semiconductor film is obtained according to the steps of Example 8 or Example 9. However, this embodiment The substrate that can be used in is a heat-resistant substrate that can withstand 700 ° C or higher, typically a quartz substrate. , Metal substrate, silicon substrate. Further, in this embodiment, the catalyst element (Nicke) used for crystallization Let the concentration of (take an example) be as low as possible. Specifically, weight conversion on an amorphous semiconductor film A nickel-containing layer of 0.5 to 3 ppm is formed in the above, and heat treatment is performed for crystallization. This will The nickel concentration contained in the formed crystalline semiconductor film is 1 × 10.<sup>17</sup>~1×10<sup>19</sup>atoms / cm<sup>3</sup>(Typically 5 × 10<sup>17</sup>~1×10<sup>18</sup>atoms / cm<sup>3</sup>).</p><p> Then, after forming the crystalline semiconductor film, heat treatment is performed in an oxidizing atmosphere containing a halogen element. Do. The temperature is 800 to 1150 ° C (preferably 900 to 1000 ° C) and the processing time is 1. 0 minutes to 4 hours (preferably 30 minutes to 1 hour).</p><p> In this embodiment, in an atmosphere containing 3 to 10% by volume of hydrogen chloride with respect to the oxygen atmosphere. Then, heat-treat at 950 ° C for 30 minutes. By this process, nickel in the crystalline semiconductor film is removed. It becomes a volatile chloride compound (nickel chloride) and escapes into the treatment atmosphere. That is, halogen Nickel can be removed by the gettering action of the elements. However, half crystalline If the concentration of nickel present in the conductor film is too high, oxidation will proceed abnormally at the nickel segregation part. Causes the problem of Therefore, the concentration of nickel used in the crystallization stage should be as low as possible. There is a need.</p><p> The concentration of nickel remaining in the crystalline semiconductor film thus formed is 1 × 10.<sup>17</sup>atms /cm<sup>3</sup>Below, preferably 1 × 10<sup>16</sup>atms / cm<sup>3</sup>It becomes as follows. After this, the crystalline semiconductor film is pattered. It can be used as an active layer of TFT by forming an active layer by thinning. ..</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 9. Noh. That is, it can be used in combination with the gettering step using phosphorus shown in Examples 8 and 9. Noh.</p>
<p> In this embodiment, the crystalline semiconductor film used in the present invention (take a crystalline silicon film as an example). The process for improving the crystallinity of the above will be described. First, any of the operations of Examples 8 to 10. The active layer is formed according to the procedure. However, in this embodiment, 800 to 800 as the substrate forming the TFT. It is necessary to use a material that uses a substrate that can withstand a temperature of 1150 ° C. As such a substrate Quartz substrate, metal substrate, silicon substrate, ceramic substrate (ceramic glass substrate) (Including).</p><p> Then, on it, a silicon nitride film, a silicon oxide film, or a silicon nitride film and oxidation A gate insulating film made of a laminated film in which a silicon film is laminated is formed. The thickness of the gate insulating film is 2 It is set to 0 to 120 nm (typically 60 to 80 nm). In this example, SiH<sub>4</sub>Gas and N<sub>2</sub>O gas A silicon oxide film is formed at a film formation temperature of 800 ° C using a mixed gas with.</p><p> After forming the gate insulating film, heat treatment is performed in an oxidizing atmosphere. The temperature is 800 ~ 1150 The temperature is C (preferably 900 to 1000 ° C) and the processing time is 10 minutes to 4 hours (preferably 30). Minutes to 1 hour). In this case, the dry oxidation method is the most preferable, but the wet oxidation method is used. It may be. Moreover, the oxidizing atmosphere may be a 100% oxygen atmosphere, and it is the case of Example 10. Sea urchin may contain a halogen element.</p><p> By this heat treatment, the active layer is oxidized near the interface between the active layer and the gate insulating film, and the thermal oxide film is formed. It is formed. As a result, the level of the interface is reduced and very good interface characteristics are exhibited. Become. Furthermore, the active layer is oxidized to reduce the film thickness, and excess sill generated during the oxidation Defects in the film are greatly reduced by the cone, and it has good crystallinity with very low defect density. It becomes a semiconductor film.</p><p> When this example is carried out, the final active layer has a film thickness of 20 to 60 nm, and the gate insulating film is formed. Adjust the thickness so that it is 50 to 150 nm (typically 80 to 120 nm). Also missing The active layer is oxidized at least 50 nm in order to fully bring out the effect of reducing the sink density. It is preferable to do so.</p><p> Next, an n-type impurity element is added in the same manner as in Example 1, and n that later becomes the Lov region.<sup>-</sup>Form a region To do. In addition, 700-950 ° C (700-950 ° C) in an inert atmosphere to activate n-type impurity elements. The heat treatment is preferably performed at 750 to 800 ° C.). In this example, 800 ° C in a nitrogen atmosphere Heat treat for 1 hour. After this, FIG. 1 (C) of Example 1 or later or FIG. 6 of Example 4 ( C) The following steps may be followed.</p><p> The crystal structure of the active layer that has undergone the steps as in this example has a unique crystal structure with continuity in the crystal lattice. It becomes a structure. Its features will be described below.</p><p> The active layer formed according to the above-mentioned production step is microscopically composed of a plurality of needle-shaped or rod-shaped crystals ( Hereinafter, it has a crystal structure in which rod-shaped crystals (hereinafter abbreviated as rod-shaped crystals) are gathered and lined up. This is TEM (Toru It could be easily confirmed by observation by hyperelectron microscopy).</p><p> In addition, when electron beam diffraction and X-ray (X-ray) diffraction are used, the surface (channel) of the active layer can be used. The part to be formed) is {11 as the main orientation plane, although the crystal axis contains some deviation. It was confirmed that it had a 0} surface. Applicant details electron diffraction photographs with a spot diameter of about 1.5 μm As a result of close observation, the diffraction spots corresponding to the {110} plane appear clearly, but each spot is It was confirmed that it had a distribution on concentric circles.</p><p> In addition, the applicant applies HR-TEM (high resolution) to the grain boundaries formed by contacting individual rod-shaped crystals. Observed by transmission electron microscopy) and confirmed that the crystal lattice is continuous at the grain boundaries. I acknowledged. This is easy because the observed plaids are continuously connected at the grain boundaries. I was able to confirm.</p><p> The continuity of the crystal lattice at the grain boundaries is called the "planar grain boundaries". It is caused by the grain boundary. The definition of planar grain boundaries herein is "Characterizati". on of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Sh imokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp It is the "Planar boundary" described in ".751-758,1988".</p><p> According to the above paper, the planar grain boundaries include diploid grain boundaries, special stacking defects, and special twist grain boundaries. Is included. This planar grain boundary is characterized by being electrically inactive. That is, the grain boundaries However, it does not function as a trap that hinders the movement of carriers, so it actually exists. Can be considered not.</p><p> Especially when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin boundary is Σ. Also called the corresponding grain boundary of 3. The Σ value is a parameter that indicates the degree of consistency of the corresponding grain boundaries. It is known that the smaller the Σ value, the better the consistency of the grain boundaries.</p><p> Results of detailed observation of the crystalline silicon film obtained by the applicant in this example using TEM. , Most of the grain boundaries (90% or more, typically 95% or more) correspond to Σ3 grain boundaries, that is, {21 1} It turned out to be a twin grain boundary.</p><p> At the grain boundaries formed between two crystal grains, the plane orientation of both crystals is {110}. In some cases, if the angle formed by the lattice fringes corresponding to the {111} plane is θ, then Σ3 when θ = 70.5 °. It is known to be the corresponding grain boundary of.</p><p> In the crystalline silicon film of this example, each plaid of adjacent crystal grains at the grain boundary is exactly about 70. It is continuous at an angle of .5 °, which means that this grain boundary is a {211} twin boundary. I came to a conclusion.</p><p> When θ = 38.9 °, it becomes the corresponding grain boundary of Σ9, but there are other grain boundaries like this. Ta.</p><p> Such a crystal structure (to be exact, the structure of the grain boundary) is two different crystals at the grain boundary. It shows that the grains are joined very consistently. That is, the crystal lattice at the grain boundaries Are continuously connected, making it extremely difficult to create trap levels due to crystal defects, etc. There is. Therefore, it seems that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundaries. Can be done.</p><p> Furthermore, the heat treatment process at a high temperature of 700 to 1150 ° C (heat in this example). Defects existing in the crystal grains are almost eliminated by the oxidation process or gettering process) It is confirmed by TEM observation. This is a defect before and after this heat treatment process It is clear from the fact that the numbers have been significantly reduced.</p><p> This difference in the number of defects is the electron spin resonance analysis (ESR). Appears as a difference in spin density. At present, it is manufactured according to the manufacturing process of this example. The spin density of the crystalline silicon film is at least 5 × 10.<sup>17</sup>spins / cm<sup>3</sup>Below (preferably 3x10<sup>17</sup>s pins / cm<sup>3</sup>The following) is known to be. However, this measured value is an inspection of existing measuring equipment. The actual spin density is expected to be even lower as it is close to the output limit.</p><p> From the above, the crystalline silicon film obtained by carrying out this example is in the crystal grains and formed. Considered as a single crystal silicon film or a substantial single crystal silicon film because there are virtually no grain boundaries. It s good.</p><p> (Knowledge about electrical characteristics of TFT) The TFT using the active layer of this example showed electrical characteristics comparable to that of MOSFET. Book out TFT prototyped by the applicant (however, the film thickness of the active layer is 30 nm, and the film thickness of the gate insulating film is 100 nm). The following data is obtained from.</p><p> (1) Sub-thread that is an index of switching performance (agility of on / off operation switching) The shoulder coefficient is 60 to 100 mV / decade for both N-channel and P-channel TFTs. It is as small as (typically 60 to 85 mV / decade). (2) Field effect mobility (μ), which is an index of TFT operating speed<sub>FE</sub>), But N-channel TFT 200 ~ 650cm<sup>2</sup>/ Vs (typically 300 ~ 500cm<sup>2</sup>/ Vs), P channel type TFT 100 ~ 300cm<sup>2</sup>/ Vs (typically 150 ~ 200cm<sup>2</sup>/ Vs) and large. (3) Threshold voltage (V), which is an index of TFT drive voltage<sub>th</sub>) Is an N-channel TFT It is as small as -0.5 to 1.5 V and -1.5 to 0.5 V for P-channel TFTs.</p><p> As described above, extremely excellent switching characteristics and high-speed operation characteristics can be realized. Has been confirmed. The configuration of this embodiment can be freely set to any of the configurations of Examples 1 to 10. It is possible to combine. However, for the crystallization of the amorphous semiconductor film, Examples 8 to 10 show. It is important to use a catalytic element that promotes crystallization as described above.</p>
<p> In this example, a crystalline semiconductor film crystallized by any of the means shown in Examples 8 and 9. (Take a crystalline silicon film as an example), the catalytic element used for crystallization (nickel in this example) Let's take) as an example to explain the means of gettering. Note that FIG. 16 is used for the explanation. ..</p><p> First, the state shown in FIG. 2B is obtained according to the same steps as in Example 1. Next, in Fig. 2 (C) Add phosphorus as in the process. At that time, in this embodiment, the resist mask 132 shown in FIG. 2 (C) Instead of, a resist mask 1601 as shown in FIG. 16 (A) is used. That is, Fig. 2 (C In), a resist mask was provided to hide the entire area of the p-channel TFT. In Fig. 16 (A), p<sup>++</sup>A resist mask is formed so as not to hide the edges of the region.</p><p> In this state, phosphorus is added under the same conditions as in the step of FIG. 2 (C). As a result, p-channel type TFT p<sup>++</sup>Phosphorus was also added to the ends of regions 124 and 125, (p.<sup>++</sup>+ n<sup>+</sup>) Area 160 2, 1603 are formed. At this time, p<sup>++</sup>Impurity element that imparts p-type contained in the region Concentration is n<sup>+</sup>If it is added at a concentration sufficiently higher than the phosphorus contained in the region, that portion is p.<sup>++</sup>Can be maintained as an area.</p><p> Next, after removing the resist masks 1601, 133 and 134, FIG. 3 (A) of Example 1 The phosphorus addition step is carried out at the same concentration as above. By this process n<sup>--</sup>Regions 140-143 are formed Is done. (Fig. 16 (B))</p><p> Next, as in FIG. 3 (B) of Example 1, the added impurity element (phosphorus or boron) Perform the activation step. In this example, this activation step is performed by furnace anneal or lamp ani. It is preferable to carry out by When using Furnace anneal, 450 ~ 650 ° C The heat treatment is preferably performed at 500 to 550 ° C, here at 500 ° C for 4 hours. (Fig. 16 (C))</p><p> In the case of this embodiment, up to the source area of both the n-channel type TFT and the p-channel type TFT. Or be sure to n in the drain area<sup>+</sup>It has a region containing phosphorus at a concentration corresponding to the region. That Therefore, in the heat treatment process for thermal activation, the gettering effect of nickel by phosphorus is exhibited. Obtainable. That is, nickel moves from the channel formation region in the direction indicated by the arrow, and the nickel moves. Gettered by the action of phosphorus contained in the loose or drain region.</p><p> When this example is carried out in this way, the step of activating the impurity element added to the active layer and the result It can also be used as a gettering process for the catalytic element used for crystallization, which is effective in simplifying the process. is there.</p><p> Also n for gettering<sup>+</sup>The region is formed by the source region of the p-channel TFT. And part of the drain area. Therefore, the source region and drain of the p-channel TFT It is not necessary to add an impurity element that imparts P-type to a high concentration in the entire region. That is, P type is given The step of adding the impurity element to be added can be shortened, and the throughput can be improved. Further, the resistance of the source region and the drain region can be reduced.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 11. Is possible. However, when crystallization of an amorphous semiconductor film, a catalytic element that promotes crystallization is used. It is an effective technology when it is used.</p>
<p> In this embodiment, when the configuration of the pixel portion is different from that of the fifth embodiment (see FIG. 11). This will be described with reference to FIG. The basic structure is the same as the structure described in Examples 4 and 5. Therefore, the same reference numerals are used for the same parts.</p><p> FIG. 17A is a cross-sectional view of the pixel portion of this embodiment, and is a gate wiring (however, a portion overlapping the active layer). 1700, 1st conductive film 1701, 2nd conductive film 1702 and 3rd conductive film It is characterized in that it is formed by laminating the film 1703. This gate wiring 1700 is explained in Example 4. It is formed at the same time as the formation of the clarified connection wiring 625. Therefore, the first conductive film is tantalum nitride. The second conductive film is a film containing aluminum as a main component, and the third conductive film is a tantalum film.</p><p> The top view at this time is as shown in FIG. 17 (B). That is, of the gate wiring Of these, the part that overlaps with the active layer (this part may be called the gate electrode) 1704a, 1704b Consists of a laminated structure of the first and third conductive films. On the other hand, the gate wiring 1700 is the gate wiring 1 The wiring width is wider than 704a and 1704b, and it has a three-layer structure as shown in Fig. 17 (A). Made. That is, in the gate wiring, the part that is simply used as wiring should have as much wiring resistance as possible. In order to make it smaller, it is preferable to have a structure as in this example.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 12. It is possible.</p>
<p> In this example, FIG. 18 shows a case where the TFT is manufactured in a process order different from that of the fourth embodiment. It will be described using. Since the process up to the middle process is the same as in Example 4, the same process Will use the same code. Further, the impurity elements to be added are the same impurities as in Example 4. Take an element as an example.</p><p> First, the state shown in FIG. 7B is obtained according to the step of Example 4. In this embodiment, the state is shown in Fig. 1. Shown in 8 (A). Next, remove the resist masks 633 to 638 and n<sup>--</sup>Form a region Perform the phosphorus addition step. The conditions may be the same as the step of FIG. 8 (A) of Example 4. Figure 18 In (B), the region represented by 1801 to 1803 is n.<sup>-</sup>N in the area<sup>--</sup>Corresponds to the area Phosphorus-added region, 1804 ~ 1806 is the Loff region of the pixel TFT n<sup>--</sup>It is an area. (Fig. 18 (B))</p><p> Next, resist masks 1807 to 1811 are formed, and phosphorus is added under the same conditions as in FIG. 7 (C). Added. By this step, regions 1812 to 1818 in which phosphorus was added at a high concentration were formed. To. (Fig. 18 (C))</p><p> After that, if the steps after FIG. 8 (B) are performed according to the step of Example 4, it will be described in FIG. 8 (C). It is possible to obtain a pixel portion having a structure of the above. When this embodiment is used, a CMOS circuit is formed. n in the source area and drain area of the p-channel TFT<sup>+</sup>Phosphorus at a concentration corresponding to the region The composition is not added. Therefore, p<sup>++</sup>The boron concentration required for the addition process is low, Luput improves. In addition, Fig. 18 (C) In the process of n-channel TFT p<sup>++</sup>If phosphorus is also added to the edge of the region, it will be carried out. It is possible to perform the gettering process of Example 12.</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> When this example was carried out, it was finally formed in the active layer due to the change in the process order. The concentration of the impurity element contained in the impurity region may be different from that of Example 4. But However, since the actual function of each impurity region does not change, the final result of this embodiment is implemented. For the explanation of the structure, the explanation of the structure in FIG. 8 (C) can be referred to as it is. Also, the real thing It is possible to apply the configuration of the example to Example 1 or Example 4, and other Examples 2 and 3 , 5 to 13 configurations can be freely combined.</p>
<p> In this example, FIG. 19 shows a case where the TFT is manufactured in a process order different from that of the fourth embodiment. It will be described using. Since the process up to the middle process is the same as in Example 4, the same process Will use the same code. Further, the impurity elements to be added are the same impurities as in Example 4. Take an element as an example.</p><p> First, the state shown in FIG. 6 (D) is obtained according to the process of Example 4. And then n-channel type T Form FT gate wiring and other connection wiring. In Figure 19 (A), 1901 , 1902 is connection wiring, 1903 ~ 1905 is n-channel TFT gate wiring, 190 Reference numeral 6 is a conductive film for later forming the gate wiring of the p-channel type TFT.</p><p> Next, resist masks 1907 to 1911 are formed, which is the same as the step of FIG. 7 (C) of Example 4. Phosphorus is added under the same conditions. Thus, the impurity region 1912 to 191 containing a high concentration of phosphorus 8 is formed. (Fig. 19 (A))</p><p> Next, after removing the resist masks 1907 to 1911, the resist masks 1919 to 1 The 924 is formed, and the gate wiring 1925 of the p-channel TFT is formed. And Figure 7 ( Add boron under the same conditions as in A), and p<sup>++</sup>It forms regions 1926 and 1927. (Fig. 19) (B))</p><p> Next, after removing the resist masks 1919 to 1924, the resist masks were removed under the same conditions as in FIG. 8 (A). Is added. By this addition process (n<sup>-</sup>+ n<sup>--</sup>) Regions 1930, 1931 and n<sup>--</sup>Ryo Regions 1932 to 1935 are formed. (Fig. 19 (C))</p><p> After that, if the steps after FIG. 8 (B) are performed according to the step of Example 4, it will be described in FIG. 8 (C). It is possible to obtain a pixel portion having a structure of the above. When this embodiment is used, a CMOS circuit is formed. n in the source area and drain area of the p-channel TFT<sup>+</sup>Phosphorus at a concentration corresponding to the region The composition is not added. Therefore, p<sup>++</sup>The boron concentration required for the addition process is low, Luput improves.</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> When this example was carried out, it was finally formed in the active layer due to the change in the process order. The concentration of the impurity element contained in the impurity region may be different from that of Example 4. But However, since the actual function of each impurity region does not change, the final result of this embodiment is implemented. For the explanation of the structure, the explanation of the structure in FIG. 8 (C) can be referred to as it is. Also, the real thing It is possible to apply the configuration of the example to Example 1 or Example 4, and other Examples 2 and 3 , 5 to 11 and 13 can be freely combined.</p>
<p> In this example, FIG. 20 shows a case where the TFT is manufactured in a process order different from that of the fourth embodiment. It will be described using. Since the process up to the middle process is the same as in Example 4, the same process Will use the same code. Further, the impurity elements to be added are the same impurities as in Example 4. Take an element as an example.</p><p> First, the state of FIG. 6 (D) is obtained according to the process of Example 4, and the state of FIG. 6 (D) is obtained according to the process of Example 15. Obtain the state shown in 19 (A). In this embodiment, this state is shown in FIG. 20 (A). In addition, Fig. 2 The code used for 0 (A) is the same as that in FIG. 19 (A).</p><p> Next, after removing the resist masks 1907 to 1911, the resist masks were removed under the same conditions as in FIG. 8 (A). Is added. By this addition process (n<sup>-</sup>+ n<sup>--</sup>) Regions 2001, 2002 and n<sup>--</sup>Ryo Regions 2003-2006 are formed. (Fig. 20 (B))</p><p> Next, resist masks 2007 to 2012 are formed, and the gate wiring of the p-channel type TFT is performed. Form 2013. Then, boron was added under the same conditions as in Fig. 7 (A), and p.<sup>++</sup>Area 20 Form 14, 2015. (Fig. 20 (C))</p><p> After that, if the steps after FIG. 8 (B) are performed according to the step of Example 4, it will be described in FIG. 8 (C). It is possible to obtain a pixel portion having a structure of the above. When this embodiment is used, a CMOS circuit is formed. No phosphorus is added to the source and drain regions of the p-channel TFT. To. Therefore, p<sup>++</sup>Lower boron concentration required for addition process, improving throughput ..</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> When this example was carried out, it was finally formed in the active layer due to the change in the process order. The concentration of the impurity element contained in the impurity region may be different from that of Example 4. But However, since the actual function of each impurity region does not change, the final result of this embodiment is implemented. For the explanation of the structure, the explanation of the structure in FIG. 8 (C) can be referred to as it is. Also, the real thing It is possible to apply the configuration of the example to Example 1 or Example 4, and other Examples 2 and 3 , 5 to 11 and 13 can be freely combined.</p>
<p> In this example, FIG. 21 shows a case where the TFT is manufactured in a process order different from that of the fourth embodiment. It will be described using. Since the process up to the middle process is the same as in Example 4, the same process Will use the same code. Further, the impurity elements to be added are the same impurities as in Example 4. Take an element as an example.</p><p> First, the state shown in FIG. 6 (D) is obtained according to the process of Example 4. And Fig. 7 (A) Process (p-channel TFT gate wiring and p<sup>++</sup>Fig. 7 (B) without performing the region formation step) ), The gate wiring of the n-channel TFT and other connection wiring are formed. In addition, it should be noted. In FIG. 21 (A), the same reference numerals as those in FIG. 7 (B) are used. However, it is a p-channel TFT. For the region, a resist mask 2101 was formed, and later a p-channel TFT game was formed. The conductive film 2102 that becomes the wiring is left.</p><p> Next, phosphorus is added under the same conditions as in FIG. 8 (A) while leaving the resist mask. this Depending on the addition process (n<sup>-</sup>+ n<sup>--</sup>) Regions 2103-2105 and n<sup>--</sup>Area 2106 ~ 210 8 is formed. (Fig. 21 (B))</p><p> Next, resist masks 2109 to 2113 are formed, which is the same as the step of FIG. 7 (C) of Example 4. Phosphorus is added under the same conditions. Thus, impurity regions 2114 to 212 containing high concentrations of phosphorus 0 is formed. (Fig. 21 (C))</p><p> Next, after removing the resist masks 2109 to 2113, a new resist mask 212 1 to 2126 are formed, and the gate wiring 2127 of the p-channel TFT is formed. And Boron was added under the same conditions as in Fig. 7 (A), and p.<sup>++</sup>It forms regions 2128 and 2129. ( Figure 21 (D))</p><p> After that, if the steps after FIG. 8 (B) are performed according to the step of Example 4, it will be described in FIG. 8 (C). It is possible to obtain a pixel portion having a structure of the above. When this embodiment is used, a CMOS circuit is formed. No phosphorus is added to the source and drain regions of the p-channel TFT. To. Therefore, p<sup>++</sup>Lower boron concentration required for addition process, improving throughput ..</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> When this example was carried out, it was finally formed in the active layer due to the change in the process order. The concentration of the impurity element contained in the impurity region may be different from that of Example 4. But However, since the actual function of each impurity region does not change, the final result of this embodiment is implemented. For the explanation of the structure, the explanation of the structure in FIG. 8 (C) can be referred to as it is. Also, the real thing It is possible to apply the configuration of the example to Example 1 or Example 4, and other Examples 2 and 3 , 5 to 11 and 13 can be freely combined.</p>
<p> In this example, FIG. 22 shows a case where the TFT is manufactured in a process order different from that of the fourth embodiment. It will be described using. Since the process up to the middle process is the same as in Example 4, the same process Will use the same code. Further, the impurity elements to be added are the same impurities as in Example 4. Take an element as an example.</p><p> First, the state of FIG. 6 (D) is obtained according to the process of Example 4, and the figure is shown according to the process of Example 17. Obtain the state shown in 21 (B). In this embodiment, this state is shown in FIG. 22 (A). In addition, Fig. 2 The reference numerals used in 2 (A) are the same as those in FIG. 21 (B).</p><p> Next, after removing the resist mask, new resist masks 2201 to 2206 are formed. Then, the gate wiring 2207 of the p-channel type TFT is formed. And the same as in Fig. 7 (A) Add boron under the conditions, p<sup>++</sup>It forms regions 2208 and 2209. (Fig. 22 (B))</p><p> Next, resist masks 2210 to 2214 are formed, and under the same conditions as in the step of FIG. 7 (C). Add phosphorus. In this way, impurity regions 2215 to 2221 containing a high concentration of phosphorus are formed. Is done. (Fig. 22 (C))</p><p> After that, if the steps after FIG. 8 (B) are performed according to the step of Example 4, it will be described in FIG. 8 (C). It is possible to obtain a pixel portion having a structure of the above. When this embodiment is used, a CMOS circuit is formed. No phosphorus is added to the source and drain regions of the p-channel TFT. To. Therefore, p<sup>++</sup>Lower boron concentration required for addition process, improving throughput .. Also, in the process shown in Fig. 22 (C), p<sup>++</sup>Phosphorus is also added to the ends of regions 2208 and 2209 By doing so, it is possible to carry out the gettering step of Example 12.</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> When this example was carried out, it was finally formed in the active layer due to the change in the process order. The concentration of the impurity element contained in the impurity region may be different from that of Example 4. But However, since the actual function of each impurity region does not change, the final result of this embodiment is implemented. For the explanation of the structure, the explanation of the structure in FIG. 8 (C) can be referred to as it is. Also, the real thing It is possible to apply the configuration of the example to Example 1 or Example 4, and other Examples 2 and 3 , 5 to 13 configurations can be freely combined.</p>
<p> In the manufacturing process examples shown in Examples 4 and 14 to 18, the gate wiring of the n-channel TFT is formed. Acts as a Lov region before and after<sup>-</sup>It is premised on forming an area ing. And p<sup>++</sup>Area, n<sup>--</sup>The feature is that both regions are formed in a self-aligned manner. ing.</p><p> However, in order to obtain the effect of the present invention, the final structure is shown in FIGS. 3 (C) and 8 (C). It suffices if it has such a structure, and it is not limited to the process leading to it. Therefore , In some cases p<sup>++</sup>Area or n<sup>--</sup>It is also possible to form the region using a resist mask. is there. In that case, the production process example of the present invention is not limited to Examples 4 and 14 to 18, and any combination is used. It is possible to make it.</p><p> In the present invention, an impurity element committee that imparts one conductivity to the active layer, which is the active layer of the TFT, is added. When doing n<sup>-</sup>Region formation, n<sup>+</sup>Region formation, n<sup>--</sup>Region formation, p<sup>++</sup>Four areas A process is required. Therefore, there are 24 ways of manufacturing steps in which this order is changed, and there are 24 examples. Six of them are shown in 4, 14-18. However, since the effects of the present invention can be obtained in all the remaining 18 ways, the impurities are in any order. It may form a region.</p><p> It also forms a source or drain region n<sup>+</sup>Area or p<sup>++</sup>When forming an area Before adding the impurity element, the gate insulating film is etched to expose a part of the active layer. Impurity elements may be added to the exposed portion. In that case, the acceleration voltage can be low, so There is less damage to the active layer and throughput is improved.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 2 to 11 and 13. It is possible. In addition, depending on the process order, it can be combined with Example 12. is there.</p>
<p> In this embodiment, a case where the present invention is used for a bottom gate type TFT will be described. concrete The case where it is used for the inverted stagger type TFT is shown in FIG. In the case of the inverted staggered TFT of the present invention , Especially, except that the positional relationship between the gate wiring and the active layer is different from the top gate type TFT of the present invention. It doesn't differ much. Therefore, in this embodiment, the structure is significantly different from that shown in FIG. 8 (C). The explanation will be given focusing on the above points, and the explanation will be omitted because the other parts are the same as in Fig. 8 (C). ..</p><p> In FIG. 23, 11 and 12 are CMOS circuits that form shift register circuits and the like, respectively. The p-channel type TFT, n-channel type TFT, and 13 form a sampling circuit, etc. The channel type TFT, 14 is an n-channel type TFT that forms a pixel portion. These are the base film It is formed on the provided substrate.</p><p> In addition, 15 is the gate wiring of the p-channel type TFT11, and 16 is the gate wiring of the n-channel type TFT12. Gate wiring, 17 is n-channel type TFT13 gate wiring, 18 is n-channel type TFT1 It is the gate wiring of No. 4, and is formed by using the same material as the gate wiring described in the fourth embodiment. Can be done. Further, 19 is a gate insulating film, which can also use the same material as in Example 4. it can.</p><p> An active layer (active layer) of each TFT 11 to 14 is formed on the active layer. p-channel type TFT A source region 20, a drain region 21, and a channel formation region 22 are formed in the active layer of 11. Is done.</p><p> In addition, the source region 23, drain region 24, and L are included in the active layer of the n-channel TFT12. A DD region (Lov region 25 in this case) and a channel formation region 26 are formed.</p><p> In addition, the active layer of the n-channel type TFT13 includes a source region 27, a drain region 28, and L. DD region (in this case, Lov region 29a, 30a and Loff region 29b, 30b), channel type A growing region 31 is formed.</p><p> In addition, the active layer of the n-channel type TFT14 includes a source region 32, a drain region 33, and L. DD region (in this case, Loff region 34 to 37), channel formation region 38, 39, n<sup>+</sup>Area 4 0 is formed.</p><p> The insulating film represented by 41 to 45 is intended to protect the channel formation region and the LDD region. Is formed for the purpose of forming.</p><p> As described above, the present invention is applied to a bottom gate type TFT represented by an inverted stagger type TFT. That is easy. In addition, in preparing the inverted staggered TFT of this embodiment, the present specification The production process shown in the other examples described in the document is a process for producing a known inverted staggered TFT. It should be applied to. Further, the active matrix type liquid crystal display as shown in Examples 5 and 7. It is also possible to apply the configuration of this embodiment to the device.</p>
<p> In this embodiment, when the present invention is applied to a reflective liquid crystal display device manufactured on a silicon substrate. Will be described. In this example, in Example 1 or Example 4, the crystalline silicon film is used. Instead of the active layer, n-type or p-type is directly attached to the silicon substrate (silicon wafer). The TFT structure of the present invention may be realized by adding the provided impurity element. It is also reflective Therefore, a metal film having high reflectance may be used as the pixel electrode.</p><p> That is, nchas that include at least a pixel unit and a drive circuit on the same substrate to form a drive circuit. The LDD area of the flannel TFT is arranged so that at least part or all of it overlaps the gate wiring. The LDD area of the pixel TFT that is placed and forms the pixel part is arranged so that it does not overlap with the gate wiring. In the LDD region of the n-channel TFT that forms the drive circuit, the LDD area of the pixel TFT It is a structure that contains an impurity element that imparts n-type at a higher concentration than the region. Just do it.</p><p> The configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 7 and 13 to 19. It is possible to make it.</p>
<p> In Examples 1 to 21, the Lov region and the Loff region are arranged only in the n-channel TFT, and the Lov region and the Loff region are arranged only in the n-channel TFT. The explanation has been made on the premise that the position is used properly according to the circuit specifications, but the TFT size is small. The same can be said for p-channel TFTs when it becomes shorter (channel length becomes shorter). Become so.</p><p> That is, when the channel length is 2 μm or less, the short-channel effect becomes apparent. In some cases, it may be necessary to place the Lov region in the p-channel TFT. like this In the present invention, the p-channel TFT is limited to the structures shown in Examples 1 to 21. Instead, it may have the same structure as the n-channel TFT.</p><p> The configuration of this embodiment is for any of the configurations of Examples 1 to 21 and their combinations. Needless to say, this also applies.</p>
<p> FIG. 33 shows the drain current (ID) of the n-channel TFT 802 prepared according to Example 4. ) And the gate voltage (VG) graph (hereinafter referred to as ID-VG curve) and electric field Effect mobility (μ<sub>FE</sub>) Is a graph. At this time, the source voltage (VS) is 0V and the drain voltage The pressure (VD) was 1V or 14V. The measured value is that the channel length (L) is 8 μm and the channel length (L) is 8 μm. The flannel width (W) was 7.5 μm, and the film thickness (Tox) of the gate insulating film was 115 nm.</p><p> In FIG. 33, the thick line shows the ID-VG curve before the stress test, and the dotted line shows the ID-VG curve after the stress test. However, there is almost no change in the curve before and after the stress test, and hot carrier deterioration is suppressed. It turned out that. The stress test conducted here was performed at room temperature with a source voltage of 0 V. It is a test that holds for 60 seconds with a rain voltage of 20V and a gate voltage of 2V. This is a test that accelerates the deterioration of the carrier.</p><p> In addition, a similar stress test was performed, and the field effect mobility (μ) was determined by the length of the Lov region.<sub>FE</sub>) Figure 34 shows the results of investigating how the deterioration rate of the product changes. In addition, here μ<sub>FE</sub>Deterioration rate Is 1- (μ before stress test<sub>FE</sub>/ Μ after stress test<sub>FE</sub>) × 100. As a result, hot carry when the length of the Lov region is 0.5 μm or more, preferably 1 μm or more. A Due to the effect μ<sub>FE</sub>It was found that the deterioration of was suppressed.</p><p> In addition, a liquid crystal display device was manufactured according to Examples 4 and 5, and its long-term reliability test was performed. The results are shown in FIGS. 35 (A) and 35 (B). In this test, the shift of the source line drive circuit Gista power supply is positive power supply (9.6V), negative power supply 1 (-2.4V) , Negative power supply 2 (-9.6V), and the power supply of the shift register of the gate line drive circuit is the positive power supply (9). .6V), negative power supply 1 (-2.4V), negative power supply 2 (-11.0V) at 85 ° C atmospheric ring It is operating at the border.</p><p> Here, Fig. 35 (A) shows the change over time of the current consumption in the shift register of the source line drive circuit. It was confirmed that there was almost no change up to 3000 hours. Also, the figure 35 (B) is the minimum operating voltage (shift register) in the shift register of the source line drive circuit. Shows the change over time (the lowest voltage at which) operates, and there is almost no change up to 3000 hours. I was able to confirm that. Also, although not shown here, the shift register of the gate line drive circuit Similar results were obtained for Star.</p>
<p> FIG. 36 shows an n-channel TFT prepared according to Example 11 (provided that the n-channel TF is formed. ID-VG curve and field effect mobility of (same structure as T802). At this time, the source power The pressure (VS) was 0V and the drain voltage (VD) was 1V or 14V. In addition, the measured value is Channel length (L) is 8.1 μm, channel width (W) is 7.6 μm, and gate insulating film thickness (Tox) ) Was 120 nm.</p><p> In FIG. 36, the thick line shows the characteristics before the stress test, and the dotted line shows the characteristics after the stress test. Almost no hot carrier deterioration was observed before and after the stress test. In addition, I went here The tress test has almost the same conditions as the stress test described in Example 23, but the game during stress The voltage was set as high as 4V.</p><p> In addition, a similar stress test was performed, and the field effect mobility (μ) was determined by the length of the Lov region.<sub>FE</sub>) Figure 37 shows the results of investigating how the deterioration rate of (definition is the same as in Example 23) changes. .. As is clear from FIG. 37, the hot carrier effect when the length of the Lov region is 1 μm or more. By μ<sub>FE</sub>It was found that the deterioration of was suppressed.</p><p> Further, a liquid crystal display device was produced according to Examples 4, 5 and 11 and its long time was obtained. The results of the reliability test are shown in FIGS. 38 (A) and 38 (B). In this test, the source line drive times The power supply of the shift register of the road and the power supply of the shift register of the gate line drive circuit are positive power supply 1 (8). Operates in an atmospheric environment at 80 ° C as .5V), positive power supply 2 (4.2V), negative power supply (-8.0V) I'm making it.</p><p> Here, FIG. 38 (A) shows the time course of the current consumption in the shift register of the source line drive circuit. It was confirmed that there was almost no change until 2000 hours. Also, the figure 38 (B) shows the time course of the minimum operating voltage in the shift register of the source line drive circuit. It was confirmed that there was almost no change until 2000 hours. Also, this Although not shown here, the same result was obtained for the shift register of the gate line drive circuit.</p>
<p> According to the present invention, when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed on the interlayer insulating film. It can also be used. That is, it is also possible to realize a semiconductor device having a three-dimensional structure. Also, as a board, SIMOX, Smart-Cut (registered trademark of SOITEC), ELTRA It is also possible to use an SOI substrate such as N (registered trademark of Canon Inc.).</p><p> The configuration of this embodiment is any of the configurations of Examples 1 to 7, 13 to 19, and 21 to 24. It can be freely combined.</p>
<p> The liquid crystal display device produced by the present invention can use various liquid crystal materials. Such materials include TN liquid crystal, PDLC (polymer-dispersed liquid crystal), FLC (ferroelectricity). Liquid crystals), AFLCs (anti-strongly attracting liquid crystals), or mixtures of FLC and AFLC.</p><p> For example, "H. Furue et al .; Charakteristics and Drivng Scheme of Polymer-Stabiliz ed Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gr ay-Scale Capability, SID, 1998 , T. Yoshida et al .; A Full-Color Thresholdless An tiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time, 841, SI Materials disclosed in D97 DIGEST, 1997 "or US Pat. No. 5,594,569 can be used. To.</p><p> In particular, a thresholdless antiferroelectric liquid crystal (no threshold value) When using ric LCD (abbreviated as TL-AFLC), the operating voltage of the liquid crystal is lowered to about ± 2.5V. Since it can be reduced, the power supply voltage may be about 5 to 8V. That is, the drive circuit and the pixel unit can be operated with the same power supply voltage, and the entire liquid crystal display device can be operated. It is possible to reduce the power consumption of the body.</p><p> In addition, ferroelectric liquid crystals and antiferroelectric liquid crystals have the advantage of faster response speed than TN liquid crystals. Have. A crystalline TFT as used in the present invention can realize a TFT having a very high operating speed. Therefore, the speed of the image response speed that fully utilizes the speed of the response speed of the ferroelectric liquid crystal and the antiferroelectric liquid crystal. It is possible to realize a liquid crystal display device.</p><p> The liquid crystal display device of this embodiment is used as a display unit of an electric appliance such as a personal computer. It goes without saying that it is effective to use it.</p><p> In addition, the configuration of this embodiment can be freely combined with any of the configurations of Examples 1 to 25. Is possible.</p>
<p> The present invention is an active matrix type EL (electroluminescence) display ( It can also be applied to an EL display device). An example is shown in FIG.</p><p> FIG. 24 is a circuit diagram of the active matrix type EL display of this embodiment. 81 is It represents the display area, and the X direction (source side) drive circuit 82 and Y direction (gate) around it. Side) Drive circuit 83 is provided. Further, each pixel of the display area 81 is a switching T. It has FT84, capacitor 85, current control TFT86, EL element 87, and switching. For TFT84, X direction signal line (source signal line) 88a (or 88b), Y direction signal line (ge) Signal line) 89a (or 89b, 89c) is connected. Also, TFT86 for current control Power lines 90a and 90b are connected to.</p><p> In addition, with respect to the active matrix type EL display of this Example, Examples 1 to 4, Any combination of 6 and 8 to 25 may be combined.</p>
<p> In this example, an EL (electroluminescence) display device was manufactured using the present invention. An example will be described. Note that FIG. 25 (A) is a top view of the EL display device of the present invention. 25 (B) is the cross-sectional view.</p><p> In FIG. 25 (A), 4002 is an image formed on the substrate 4001 (see FIG. 13 (B)). Element part, 4003 is the source side drive circuit, 4004 is the gate side drive circuit, each drive The dynamic circuit reaches FPC (Flexible Print Circuit) 4006 via wiring 4005. , Connected to an external device.</p><p> At this time, the pixel unit 4002, the source side drive circuit 4003, and the gate side drive circuit 4004 1st sealing material 4101, covering material 4102, filler 4103 and 2nd sheet so as to surround The material 4104 is provided.</p><p> Further, FIG. 25 (B) corresponds to a cross-sectional view obtained by cutting FIG. 25 (A) with A-A', and the substrate 400 Drive TFT included in source side drive circuit 4003 on top of 1 (however, here n channel type TFTs and p-channel TFTs are illustrated. ) Included in 4201 and pixel section 4002 A current control TFT (TFT that controls the current to the EL element) 4202 is formed.</p><p> In this embodiment, the drive TFT4201 has the p-channel type TFT181 and n-channel shown in FIG. A TFT with the same structure as the type TFT182 is used, and the current control TFT4202 has p in Fig. 3. A TFT having the same structure as the channel type TFT181 is used. In addition, the pixel section 4002 has electricity. A holding capacity (not shown) connected to the gate of the flow control TFT 4202 is provided.</p><p> An interlayer insulating film made of a resin material (flat) is placed on the drive TFT4201 and the pixel TFT4202. Chemical film) 4301 is formed and electrically connected to the drain of pixel TFT4202 on it. A pixel electrode (anode) 4302 is formed. Transparent with a large work function for the pixel electrode 4302 A bright conductive film is used. As a transparent conductive film, a compound of indium oxide and tin oxide or Can use a compound of indium oxide and zinc oxide.</p><p> Then, an insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is a pixel. An opening is formed on the electrode 4302. In this opening, the pixel electrode 4302 An EL (electroluminescence) layer 4304 is formed on the top. EL layer 4304 is public Known organic EL materials or inorganic EL materials can be used. Also low for organic EL materials There are molecular (monomer) materials and polymer (polymer) materials, but either one may be used. ..</p><p> As a method for forming the EL layer 4304, a known vapor deposition technique or coating method technique may be used. Also , EL layer structure is free of hole injection layer, hole transport layer, light emitting layer, electron transport layer or electron injection layer It may be combined with the above to form a laminated structure or a single layer structure.</p><p> On the EL layer 4304, a conductive film having a light-shielding property (typically aluminum, copper or Cathode 4305 made of a conductive film containing silver as a main component or a laminated film of them and another conductive film) It is formed. In addition, water and oxygen existing at the interface between the cathode 4305 and the EL layer 4304 are discharged as much as possible. It is desirable to remove it. Therefore, both are continuously formed in vacuum, or the EL layer 4304 is formed. Formed in a nitrogen or rare gas atmosphere, forming cathode 4305 without contact with oxygen or moisture It is necessary to devise such as. In this embodiment, the multi-chamber method (cluster tool method) By using the film forming apparatus of the formula), the above-mentioned film forming is possible.</p><p> And cathode 4305 is electrically connected to wire 4005 in the region indicated by 4306. Is done. The wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and is anisotropically conductive. It is electrically connected to the FPC4006 via film 4307.</p><p> As described above, from the pixel electrode (anode) 4302, EL layer 4304, and cathode 4305. EL element is formed. This EL element is the first sealing material 4101 and the first sealing material 4. Surrounded by cover material 4102 attached to substrate 4001 by 101, filler 410 Enclosed by 3.</p><p> The cover material 4102 includes a glass plate, a metal plate (typically a stainless steel plate), and a ceramic. Kusu board, FRP (Fiberglass-Reinforced Plastics) board , PVF (Polyvinyl Fluoride) film, Mylar film, Polyester fill Acrylic film or acrylic film can be used. Also, use aluminum foil for PVC. A sheet having a structure sandwiched between a film or a Mylar film can also be used.</p><p> However, if the direction of light emission from the EL element is toward the cover material side, the cover material is not transparent. Must be. In that case, glass plate, plastic plate, polyester film or Uses a transparent material such as acrylic film.</p><p> Further, as the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone tree Use fat, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) be able to. A hygroscopic substance (preferably barium oxide) is provided inside the filler 4103. If it is set aside, deterioration of the EL element can be suppressed.</p><p> Further, a spacer may be contained in the filler 4103. At this time, the spacer is oxidized. If it is formed of barium, the spacer itself can be made hygroscopic. Also, space If a spacer is provided, a resin is placed on the cathode 4305 as a buffer layer to relieve the pressure from the spacer. It is also effective to provide a film.</p><p> Also, wiring 4005 is electrically connected to FPC4006 via an anisotropic conductive film 4307. Be connected. Wiring 4005 is pixel part 4002, source side drive circuit 4003 and gate side drive The signal sent to the dynamic circuit 4004 is transmitted to the FPC4006, and the FPC4006 is used as an external device. Is electrically connected to.</p><p> Further, in this embodiment, the exposed portion of the first sealing material 4101 and a part of FPC4006 are covered. The second sealing material 4104 is provided so that the EL element is thoroughly shielded from the outside air. To. In this way, the EL display device having the cross-sectional structure shown in FIG. 25 (B) is obtained. In addition, E of this embodiment The L display device may be manufactured by combining any of the configurations of Examples 1 to 4, 6 to 20, and 22. I don't know.</p><p> Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 26, a top surface structure is shown in FIG. 27 (A), and a circuit diagram. Is shown in FIG. 27 (B). Common symbols are used in FIGS. 26, 27 (A) and 27 (B). So you can refer to each other.</p><p> In FIG. 26, the switching TFT 4402 provided on the substrate 4401 is shown in FIG. It is formed using the n-channel TFT183 of C). Therefore, the description of the structure is n channels See the description of type TFT183. Also, the wiring indicated by 4403 is Switchon. With gate wiring that electrically connects the gate electrodes 4404a and 4404b of TFT4402 for is there.</p><p> Although this embodiment has a double gate structure in which two channel formation regions are formed. , Single gate structure with one channel formation region or tripe with three It may have a lugate structure.</p><p> The drain wiring 4405 of the switching TFT 4402 is the current control TFT 44. It is electrically connected to the gate electrode 4407 of 06. In addition, TFT4406 for current control Is formed using the p-channel type TFT181 shown in Fig. 3 (C). Therefore, the description of the structure is p Refer to the description of the channel type TFT181. In this embodiment, a single gate structure is used. Although it is constructed, it may have a double gate structure or a triple gate structure.</p><p> First passive on top of TFT 4402 for switching and TFT 4406 for current control An ion film 4408 is provided, and a flattening film 4409 made of resin is formed on the film. flat It is very important to flatten the step by TFT using the tanning film 4409. Later shape Since the EL layer formed is very thin, the presence of steps may cause light emission failure. is there. Therefore, before forming the pixel electrodes so that the EL layer can be formed as flat as possible, it is flat. It is desirable to make it portable.</p><p> In addition, 4410 is a pixel electrode (anode of an EL element) made of a transparent conductive film for current control. It is electrically connected to the drain wiring 4411 of TFT4406. As pixel electrode 4410 Is a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide? A conductive film made of the above can be used.</p><p> An EL layer 4412 is formed on the pixel electrode 4410. In addition, in FIG. 26, there is only one pixel. Although not shown, in this embodiment, the EL layer corresponding to each color of R (red), G (green), and B (blue). Are made separately. Further, in this embodiment, a low molecular weight organic EL material is formed by a thin film deposition method. To. Specifically, a 20 nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer. , 70 nm thick Tris-8-quinolinolatoaluminum complex (Al) as a light emitting layer on it q<sub>3</sub>) It has a laminated structure with a film. Alq<sub>3</sub>Control the emission color by adding a fluorescent dye to can do.</p><p> However, the above example is an example of an organic EL material that can be used as an EL layer. There is no need to limit it to. Free combination of light emitting layer, charge transport layer or charge injection layer It suffices to form an EL layer (a layer for emitting light and moving carriers for that purpose). .. For example, in this example, a low-molecular-weight organic EL material is used as the EL layer, but the content is high. A child-based organic EL material may be used. In addition, there is no silicon carbide or the like as a charge transport layer or a charge injection layer. It is also possible to use machine materials. Known materials can be used as these organic EL materials and inorganic materials.</p><p> Next, a cathode 4413 made of a light-shielding conductive film is provided on the EL layer 4412. Book In the case of the embodiment, an alloy film of aluminum and lithium is used as the light-shielding conductive film. Of course , A known MgAg film (alloy film of magnesium and silver) may be used. As a cathode material , Add a conductive film consisting of elements belonging to Group 1 or Group 2 of the periodic table or those elements A conductive film may be used.</p><p> The EL element 4414 is completed when the cathode 4413 is formed. In addition, here The EL element 4414 is a pixel electrode (anode) 4410, an EL layer 4412, and a cathode 4413. Refers to the formed capacitor.</p><p> Next, the upper surface structure of the pixels in this embodiment will be described with reference to FIG. 27 (A). Switchon The source of the TFT 4402 for operation is connected to the source wiring 4415, and the drain is the drain wiring. Connected to 4405. The drain wiring 4405 is a current control TFT 4406 game. It is electrically connected to the electrode 4407. The source of the current control TFT4406 is current. Electrically connected to supply line 4416 and drain is electrically connected to drain wiring 4417 Is done. In addition, the drain wiring 4417 is electrically connected to the pixel electrode (anode) 4418 shown by the dotted line. Connected to.</p><p> At this time, a holding capacity is formed in the region indicated by 4419. Retention capacity 4419 Semiconductor film 4420 electrically connected to the current supply line 4416, the same layer as the gate insulating film It is formed between the marginal membrane (not shown) and the gate electrode 4407. Also, the gate electrode 440 7. The capacitance formed by the same layer as the first interlayer insulating film (not shown) and the current supply line 4416 It can be used as a holding capacity.</p><p> The configuration of this embodiment can be freely combined with the configurations of Examples 1 to 4, 6 and 8 to 25. It is possible to give.</p>
<p> In this embodiment, an EL display device having a pixel structure different from that of the 28th embodiment will be described. .. FIG. 28 is used for the explanation. In addition, the part with the same code as in Fig. 26 is carried out. See the description in Example 26.</p><p> In Fig. 28, as the current control TFT4501, the n-channel type TFT182 in Fig. 3 (C) is used. Use a TFT with the same structure. Of course, the gate electrode 4502 of the current control TFT 4501 is It is connected to the drain wiring 4405 of the TFT 4402 for itching. Also, current control The drain wiring 4503 of the TFT 4501 for is electrically connected to the pixel electrode 4504. ..</p><p> In this embodiment, the pixel electrode 4504 functions as a cathode of the EL element and uses a light-shielding conductive film. And form. Specifically, an alloy film of aluminum and lithium is used, but 1 in the periodic table Uses a conductive film composed of elements belonging to Group or Group 2 or a conductive film to which those elements are added. I just need to be there.</p><p> An EL layer 4505 is formed on the pixel electrode 4504. In addition, in FIG. 28, there is only one pixel. Although not shown, in this embodiment, the EL layer corresponding to G (green) is vapor-deposited and coated (preferably). Or spin coating method). Specifically, 20n as an electron injection layer An m-thick lithium fluoride (LiF) film is provided, and a 70 nm-thick PPV (PPV) is used as a light emitting layer on the film. It has a laminated structure with a polyparaphenylene vinylene) film.</p><p> Next, an anode 4506 made of a transparent conductive film is provided on the EL layer 4505. This implementation In the case of the example, as a transparent conductive film, a compound of indium oxide and tin oxide or indium oxide A conductive film composed of a compound of zinc oxide is used.</p><p> The EL element 4507 is completed when the anode 4506 is formed. In addition, here The EL element 4507 includes a pixel electrode (cathode) 4504, an EL layer 4505, and a cathode 4506. Refers to the formed capacitor.</p><p> At this time, it is very important that the current control TFT 4501 has the structure of the present invention. have. The current control TFT4501 is for controlling the amount of current flowing through the EL element 4507. Since it is an element, a large amount of current flows, and there is a risk of deterioration due to heat and deterioration due to hot carriers. Is also a high element. Therefore, gate insulation is provided on the drain side of the current control TFT4501. The present application in which the LDD region 4509 is provided so as to overlap the gate electrode 4502 via the membrane 4508. The structure of the invention is extremely effective.</p><p> Further, the current control TFT 4501 of this embodiment has a gate electrode 4502 and an LDD region 450. A parasitic capacitance called a gate capacitance is formed between 9 and 9. By adjusting this gate capacity It is also possible to have the same function as the holding capacity 4419 shown in FIGS. 27 (A) and 27 (B). To. In particular, when operating the EL display device in a digital drive system, the holding capacity key The gate capacity is smaller than when operating with an analog drive system. Can be used as a substitute for the holding capacity.</p><p> The configuration of this embodiment can be freely combined with the configurations of Examples 1 to 4, 6 and 8 to 25. It is possible to give.</p>
<p> In this embodiment, it is used for the pixel portion of the EL display device shown in Example 28 or 29. Examples of possible pixel structures are shown in FIGS. 29 (A) to 29 (C). In this embodiment, 4 601 is the source wiring of the switching TFT 4602, and 4603 is the switching TFT. 4602 gate wiring, 4604 is current control TFT, 4605 is capacitor, 4606 , 4608 is a current supply line, and 4607 is an EL element.</p><p> FIG. 29 (A) shows an example in which the current supply line 4606 is shared between the two pixels. Immediately The special feature is that the two pixels are formed so as to be line-symmetrical with respect to the current supply line 4606. There is a sign. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined. Can be refined.</p><p> In addition, FIG. 29 (B) shows the case where the current supply line 4608 is provided in parallel with the gate wiring 4603. Is an example of. In Fig. 29 (B), the current supply line 4608 and the gate wiring 4603 overlap. The structure is provided so that it does not occur, but if the wiring is formed in different layers, it will not work. It can also be provided so as to overlap via the limbus. In this case, power supply line 4608 and gate Since the occupied area can be shared with the wiring 4603, the pixel part is further improved in definition. be able to.</p><p> Further, in FIG. 29 (C), the current supply line 4608 is gated in the same manner as in the structure of FIG. 29 (B). It is provided parallel to the 4603, and the two pixels are line-symmetrical with respect to the current supply line 4608. It is characterized in that it is formed in this way. Also, connect the current supply line 4608 to the gate wiring 4603. It is also effective to provide it so that it overlaps one of them. In this case, reduce the number of power supply lines Therefore, the pixel portion can be further improved in definition.</p>
<p> The electro-optical device and semiconductor circuit of the present invention are used as a display unit and a signal processing circuit of an electric appliance. be able to. Such appliances include video cameras, digital cameras, and projects. Kutar, projection TV, goggle type display (head mounted display) ), Navigation system, sound reproduction device, notebook personal computer, game Devices, personal digital assistants (mobile computers, mobile phones, handheld game consoles or e-books) Etc.), an image reproduction device equipped with a recording medium, and the like. Figure 3 shows specific examples of these appliances Shown in 0 to 32.</p><p> FIG. 30 (A) shows a mobile phone, which is a main body 2001, a voice output unit 2002, and a voice input unit 20. It consists of 03, display unit 2004, operation switch 2005, and antenna 2006. From this application Ming's electro-optic device is on the display unit 2004, and the semiconductor circuit of the present invention is on the audio output unit 2002, sound. It can be used for voice input unit 2003, CPU, memory, etc.</p><p> FIG. 30B shows a video camera, which is a main body 2101, display unit 2102, and audio input unit 21. It consists of 03, operation switch 2104, battery 2105, and image receiving unit 2106. Application The electro-optical device of the present invention is on the display unit 2102, and the semiconductor circuit of the present invention is on the audio input unit 2103. Or it can be used for CPU, memory, etc.</p><p> Figure 30 (C) shows a mobile computer (mobile computer), which is the main body 2201. , Camera unit 2202, image receiving unit 2203, operation switch 2204, display unit 2205 Is done. The electro-optical device of the present invention is on the display unit 2205, and the semiconductor circuit of the present invention is a CPU or a display unit. It can be used for moly and the like.</p><p> Fig. 30 (D) shows a goggle type display, which is the main body 2301, the display unit 2302, and the aer. It is composed of 2303 parts. The electro-optical device of the present invention is displayed on the display unit 2302, which is a half of the present invention. The conductor circuit can be used for a CPU, a memory, or the like.</p><p> Figure 30 (E) shows the rear projector (projection TV), which is the main body 2401. Light source 2402, liquid crystal display 2403, polarization beam splitter 2404, reflector 2 It consists of 405, 2406 and screen 2407. The present invention applies to the liquid crystal display device 2403. It can be used, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.</p><p> Figure 30 (F) shows the front projector, which includes the main unit 2501, the light source 2502, and the liquid crystal table. It consists of a display device 2503, an optical system 2504, and a screen 2505. The present invention can be used in the liquid crystal display device 2502, and the semiconductor circuit of the present invention is a CPU or a display device. It can be used for moly and the like.</p><p> Fig. 31 (A) shows a personal computer, which is the main body 2601, the video input unit 2602, Includes display 2603, keyboard 2604, etc. The electro-optical device of the present invention is a display unit 260. Third, the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.</p><p> Figure 31 (B) shows an electronic game device (game device), which is the main body 2701 and the recording medium 2702. , Display 2703 and controller 2704. Output from this electronic gaming device Audio and video are reproduced on a display display including the housing 2705 and the display unit 2706. Communication means or electronic gaming device and display display between controller 2704 and main unit 2701 Wired communication, wireless communication or optical communication can be used as the means of communication with the spray. In this example Is configured to detect infrared rays with the sensor units 2707 and 2708. Electric light of the present invention The academic device is used for the display units 2703 and 2706, and the semiconductor circuit of the present invention is used for the CPU, memory, etc. Can be</p><p> FIG. 31 (C) shows a pre-recording medium (hereinafter referred to as a recording medium) on which the program is recorded. -Yar (image playback device), main unit 2801, display unit 2802, speaker unit 2803, Includes recording medium 2804 and operation switch 2805. This image playback device is a recording medium. Music using DVD (Digital Versatile Disc), CD, etc. You can watch movies, watch movies, play games, and play the Internet. Electro-optic device of the present invention Can be used for the display unit 2802, CPU, memory, etc.</p><p> Fig. 31 (D) shows a digital camera, which is the main body 2901, the display unit 2902, and the eyepiece unit 290. 3. Includes operation switch 2904 and image receiving unit (not shown). The electro-optical device of the present invention is a display It can be used for part 2902, CPU, memory, etc.</p><p> For the rear projector shown in Fig. 30 (E) and the front projector shown in Fig. 30 (F). A detailed description of the optical engine that can be used is shown in FIG. In addition, Fig. 32 ( A) is the optical engine, and Fig. 32 (B) is the light source optical system built into the optical engine. ..</p><p> The optical engine shown in Fig. 32 (A) is the light source optical system 3001, mirrors 3002, and 3005. ~ 3007, Dichroic mirror 3003, 3004, Optical lens 3008a ~ 300 Includes 8c, prism 3011, liquid crystal display device 3010, and projection optical system 3012. Projection optics System 3012 is an optical system including a projection lens. In this embodiment, the liquid crystal display device 3010 is used. Although an example of a three-plate type to be used is shown, a single-plate type may be used. Also, in Fig. 32 (A) In the optical path indicated by the arrow, an optical lens, a film with a polarizing function, and a phase difference are adjusted. A film for this purpose, an IR film, or the like may be provided.</p><p> Further, as shown in FIG. 32 (B), the light source optical system 3001 has light sources 3013, 3014, and so on. Synthetic prism 3015, collimator lens 3016, 3020, lens array 3017, Includes 3018 and polarization conversion element 3019. Note that Fig. 32 (B) The light source optical system shown in (1) uses two light sources, but may be one or three or more. Ma Also, somewhere in the optical path of the light source optical system, an optical lens, a film with a polarizing function, and a phase difference are adjusted. A knotting film, an IR film, or the like may be provided.</p><p> As described above, the scope of application of the present invention is extremely wide, and it can be applied to electric appliances in all fields. And is possible. What kind of combination of the electric appliances of this example is in Examples 1 to 30? It can also be realized by using the above configuration.</p>
601 board 602a, 602b Undercoat 603 ~ 606 active layer 607 Gate insulating film 612 ~ 614 n<sup>-</sup>region 615 First conductive film 616 Second conductive film 618 Third conductive film 626, 639, 640, 641 Gate wiring 625, 627 connection wiring 631, 632 p<sup>++</sup>region 647 ~ 653 n<sup>+</sup>Area or (n<sup>+</sup>+ n<sup>-</sup>)region 654 ~ 657 n<sup>--</sup>region 663 Protective insulating film 664 Interlayer insulating film 665 ~ 668 Source wiring 669 ~ 672 Drain wiring 673, 674 Connection wiring 675 Passivation membrane 676 Second interlayer insulating film 677 Light-shielding film 678 Oxide 679 ~ 681 Pixel electrode 682 Retention capacity 701, 704, 708, 713, 714 channel formation region 702, 705, 709, 715 Source area 703, 706, 710, 716 Drain area 707, 711a, 712a Lov region 711b, 712b, 717 ~ 720 Loff area 721 n<sup>+</sup>region
48 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38 Sheet 39 Sheet 40 Sheet 41 Sheet 42 Sheet 43 Sheet 44 Sheet 45 Sheet 46 Sheet 47 Sheet 48
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| Document | Relation | Office |
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| JP07234421A | Cites | Japan |
| JP10010581A | Cites | Japan |
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55 members in 3 offices
Priority claims7
| Document | Office | Kind | Date |
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| 1999045558 | Japan | – | |
| 4555899 | Japan | A | |
| 4555899 | Japan | A | |
| 2012084519 | Japan | A | |
| 199945558 | – | – | – |
| JP19990045558 | – | – | – |
| JP20120084519 | – | – | – |
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| Document | Office | Kind | |
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| EP1031873A2 | European Patent Office (EPO) | A2 | |
| JP2000312007A | Japan | A | |
| US6576926B1 | United States of America | B1 | |
| US2003197179A1 | United States of America | A1 | |
| EP1031873A3 | European Patent Office (EPO) | A3 | |
| US2005040401A1 | United States of America | A1 | |
| US6967129B2 | United States of America | B2 | |
| US2007200113A1 | United States of America | A1 | |
| US7365393B2 | United States of America | B2 | |
| US7442991B2 | United States of America | B2 | |
| US2009014724A1 | United States of America | A1 | |
| JP2009237573A | Japan | A | |
| JP4372943B2 | Japan | B2 | |
| US7745829B2 | United States of America | B2 | |
| US2010264421A1 | United States of America | A1 | |
| EP2284605A2 | European Patent Office (EPO) | A2 | |
| US8030659B2 | United States of America | B2 | |
| US2012007095A1 | United States of America | A1 | |
| JP2012145952A | Japan | A | |
| JP2012150484A | Japan | A | |
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| JP2012190022A | Japan | A | |
| JP2012191216A | Japan | A | |
| US2013001568A1 | United States of America | A1 | |
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| JP5116886B2 | Japan | B2 | |
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| JP2013041286A | Japan | A | |
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| US8558241B2 | United States of America | B2 | |
| US8575619B2 | United States of America | B2 | |
| JP5358707B2 | Japan | B2 | |
| JP5409831B2 | Japan | B2 | |
| JP2014032409A | Japan | A | |
| JP2014052634A | Japan | A | |
| US2014160385A1 | United States of America | A1 | |
| JP5608798B2 | Japan | B2 | |
| JP2014240962A | Japan | A | |
| JP5648105B2 | Japan | B2 | |
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| JP2015038612A | Japan | A | |
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| US9431431B2 | United States of America | B2 | |
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| US2017052398A1 | United States of America | A1 | |
| JP2017182084A | Japan | A | |
| EP2284605A3 | European Patent Office (EPO) | A3 | |
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Numbers
- Publication
- 5116887
- Publication, DOCDB
- 5116887
- Publication, EPODOC
- JP5116887B
- Application
- 84519
- Application, DOCDB
- 2012084519
- Application, EPODOC
- JP20120084519
Titles2
- Japanese
- 液晶表示装置
- English
- Liquid crystal display device
Classification
- CPC, 26
- G02F1/13454
- G02F1/1368
- H10D86/451
- H10D86/60
- H10D86/441
- H10D30/6737
- H10D30/6743
- H10D30/6715
- H10D30/6719
- H10D30/6721
- H10D30/6731
- H10D30/6745
- H10K59/123
- H10K59/124
- H10K59/126
- H10K59/131
- H10K59/1213
- H10K59/1201
- H10D86/00
- H10D86/021
- H10D86/421
- G02F1/136286
- G02F1/133345
- G02F1/136227
- G02F2201/123
- G02F2202/104
- IPC, 12
- G02F1 1368
- H01L21 336
- H01L29 786
- G09F9 30
- G02F1 136
- G02F1 1362
- H01L21 77
- H01L21 84
- H01L27 12
- H01L27 32
- H01L51 50
- H05B44 00
