Method for manufacturing soi substrate and semiconductor device

The present invention is an SOI (Silicon on Insulator) substrate and manufactured by the substrate. The present invention relates to semiconductor devices to be manufactured and a method for manufacturing them. Especially related to bonded SOI technology Single crystal or polycrystalline on a substrate that is flexible and has an insulating surface. SOI substrates with semiconductor layers bonded, semiconductor devices manufactured by them, and their Regarding the manufacturing method.

Instead of a silicon wafer made by thinly slicing a single crystal semiconductor ingot, A single crystal called a silicon-on-insulator with a thin single crystal semiconductor layer on the edge surface. Integrated circuits using semiconductor substrates (SOI substrates) have been developed. Integrated using an SOI substrate By providing a transistor that forms a circuit, between the drain of the transistor and the substrate Since it is possible to reduce the parasitic capacitance in the semiconductor and improve the performance of the semiconductor integrated circuit, SOI The board is attracting attention.

As a method for manufacturing an SOI substrate, a hydrogen ion implantation peeling method is known (for example, a special method). See License 1). The hydrogen ion implantation peeling method involves implanting hydrogen ions into a silicon wafer. A microbubble layer is formed from the surface to a predetermined depth, and the hydrogen ion implantation surface is made of another silicon. Separated by stacking with a wafer and performing heat treatment to peel off the microbubble layer as a cleavage surface. A thin silicon layer (SOI layer) is bonded to the silicon wafer of. To peel off the SOI layer In addition to the heat treatment of, an oxide layer is formed on the SOI layer by heat treatment in an oxidizing atmosphere, and then The oxide layer is removed, and then heat treatment is performed in a reducing atmosphere at 1000 to 1300 ° C to join. It is said that it is necessary to increase the strength and improve the damage layer on the surface of the SOI layer.

An example of a semiconductor device using an SOI substrate is known by the applicant (patent). See Reference 2). Again, stress-induced trap levels and defects are removed in the SOI layer. It is disclosed that a heat treatment of 1050 to 1150 ° C is required to remove.

<p><patcit num="1"><text>U.S. Pat. No. 6372609</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2000-12864</text></patcit></p>

<p>In the conventional method for manufacturing an SOI substrate, the bonding strength with the SOI layer is strengthened, and the SOI layer is formed. It was necessary to heat-treat at a high temperature of 1000 ° C or higher to improve the surface damage layer. .. Therefore, a glass substrate used for manufacturing liquid crystal panels and a substrate with a heat resistant temperature of about 700 ° C. In addition, the SOI layer could not be formed on plastic with a lower heat resistant temperature. what if Even if the SOI layer is provided on the glass substrate by the hydrogen ion implantation peeling method, the bonding strength is increased. Because the high temperature heat treatment cannot be applied, the bonding strength of the SOI layer is weak. There's a problem.</p><p>Further, since the flexible substrate is thin and easily bent, it is difficult to fix the flexible substrate and it is difficult to handle it. Therefore, there is a problem that the yield of the semiconductor device using the flexible substrate is low.</p><p>In view of these problems, when a flexible substrate such as a glass substrate or plastic is used. In addition, we provide a method for producing high yields of SOI substrates with an SOI layer that can withstand practical use. One of the purposes is to do. In addition, we are walking through thin semiconductor devices using such SOI substrates. One of the purposes is to provide a method for producing a staying high.</p>

<p>A single crystal semiconductor substrate is bonded to a substrate having flexibility and an insulating surface to prepare an SOI substrate. After activating one or both of the joint surfaces, it is flexible and has an insulating surface. The substrate to be used is crimped to the single crystal semiconductor substrate. For example, it is flexible and has an insulating surface. Atomic beam or ion on at least one junction surface of the substrate or single crystal semiconductor substrate Irradiate the beam. Alternatively, plasma irradiation or radical treatment is performed. Also flexible A substrate having an insulating surface or at least one bonding surface of a single crystal semiconductor substrate , It may be hydrophilized by treatment with oxygen plasma or washing with ozone water. Such a surface It is possible to join dissimilar materials even at temperatures of 250 ° C or higher and lower than 400 ° C by treatment. It will be easy.</p><p>Further, when joining a single crystal semiconductor substrate to a substrate having a flexible and insulating surface, A silicon oxide layer formed from organic silane as a raw material is used for one or both of the surfaces to be bonded. There is. Examples of organic silane gas include ethyl silicate (TEOS) and tetramethylsilane (chemical formula). Si (CH₃)₄), Tetramethylcyclotetrasiloxane (TMCTS), Octamethi Lucyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), tri Silicon-containing compounds such as ethoxysilane and trisdimethylaminosilane are applied. Su That is, a single crystal semiconductor layer (SOI layer) is bonded to a substrate having a flexible and insulating surface. In an SOI substrate having such a structure, a smooth surface is provided on one or both of the surfaces forming a bond. A silicon oxide layer having a formed and activated surface is provided as a bonding surface.</p><p>The SOI layer bonded to a substrate having a flexible and insulating surface is formed into a single crystal semiconductor substrate. It is obtained by separating and peeling in the formed fragile area. The vulnerable area is the source gas Plasma excitation using halogen gas typified by hydrogen, helium or fluorine It is formed by irradiating the single crystal semiconductor substrate with the generated accelerated ions. in this case , Multiple ions with different masses consisting of one atom or Ions with different masses consisting of multiple atoms It is preferable to irradiate. When irradiating hydrogen ions, H⁺, H₂⁺, H₃⁺I Including on and H₃⁺It is preferable to increase the ratio of ions. Also, helium When ionizing and irradiating the membrane, even if it is ion doping without mass separation, it is actually Qualitatively He⁺Only ions can be doped. Substantial means the source of atmospheric components It also means that the element is ionized and slightly doped.</p><p>Further, the SOI layer bonded to the substrate having flexibility and an insulating surface is a single crystal semiconductor group. A substrate that is flexible and has an insulating surface for separation in the fragile regions formed on the plate. Before joining the single crystal semiconductor substrate with the single crystal semiconductor substrate, the single crystal semiconductor substrate is heat-treated to make the fragile region fragile. To do. In this case, the single crystal semiconducting is to prevent the ions from becoming a gas and desorbing from the fragile region. Heat treatment is performed while applying pressure to the surface of the body substrate with a crimping member. Or on a single crystal semiconductor substrate An insulating layer is formed and heat treatment is performed.</p>

<p>Before joining the single crystal semiconductor layer peeled from the single crystal semiconductor substrate and the base substrate, A single crystal semiconductor group is heated by heating the crystalline semiconductor substrate and irradiating the single crystal semiconductor substrate with accelerated ions. A flexible substrate with low heat resistance and a single crystal by forming a fragile region in which a part of the plate is fragile. Semiconductor substrates can be joined to produce SOI substrates. According to this configuration, plastic Even if the heat resistant temperature is low, such as a substrate, it is joined to the substrate by a joint with strong bonding force. A high yield can be obtained for an SOI substrate having an excellent SOI layer. In addition, the SOI group A semiconductor device using a plate can be manufactured.</p>

<figref num="1">It is sectional drawing which shows the structure of the SOI substrate.</figref><figref num="2">It is sectional drawing which shows the structure of the SOI substrate.</figref><figref num="3">It is sectional drawing which shows the structure of the SOI substrate.</figref><figref num="4">It is sectional drawing which shows the structure of the SOI substrate.</figref><figref num="5">It is sectional drawing explaining the manufacturing method of the SOI substrate.</figref><figref num="6">It is sectional drawing explaining the manufacturing method of the SOI substrate.</figref><figref num="7">It is sectional drawing explaining the manufacturing method of the SOI substrate.</figref><figref num="8">It is sectional drawing explaining the manufacturing method of the SOI substrate.</figref><figref num="9">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="10">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="11">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="12">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="13">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="14">It is sectional drawing explaining the manufacturing method of the semiconductor device using an SOI substrate.</figref><figref num="15">It is a block diagram which shows the structure of the microprocessor obtained by the SOI board.</figref><figref num="16">It is a block diagram which shows the structure of RFCPU obtained by the SOI board.</figref><figref num="17">It is a top view which illustrates the case where the SOI layer is bonded to the mother glass for manufacturing a display panel.</figref><figref num="18">It is a figure which shows an example of the display panel in which a pixel transistor is formed by the SOI layer.</figref><figref num="19">It is a figure which shows the energy diagram of a hydrogen ion species.</figref><figref num="20">It is a figure which shows the mass spectrometry result of an ion.</figref><figref num="21">It is a figure which shows the mass spectrometry result of an ion.</figref><figref num="22">It is a figure which shows the profile (measured value and calculated value) in the depth direction of a hydrogen element when the acceleration voltage is 80 kV.</figref><figref num="23">It is a figure which shows the profile (measured value, calculated value, and fitting function) in the depth direction of a hydrogen element when the acceleration voltage is 80 kV.</figref><figref num="24">It is a figure which shows the profile (measured value, calculated value, and fitting function) in the depth direction of a hydrogen element when the acceleration voltage is 60 kV.</figref><figref num="25">It is a figure which shows the profile (measured value, calculated value, and fitting function) in the depth direction of a hydrogen element when the acceleration voltage is 40 kV.</figref><figref num="26">It is the figure which summarized the ratio (hydrogen element ratio and hydrogen ion species ratio) of a fitting parameter.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention has many It can be carried out in different embodiments and does not deviate from the gist of the present invention and its scope. It is easily understood by those skilled in the art that the form and details of the damn can be changed in various ways. Therefore , The interpretation is not limited to the description of the present embodiment and the examples.

(Embodiment 1) The configuration of the SOI substrate according to the present invention is shown in FIG. In FIG. 1, the base substrate 100 is an SOI. A substrate on which an SOI layer is provided, which is flexible and has an insulating surface. It is a substrate, typically an insulating substrate having flexibility, and has flexibility in which an insulating layer is formed on the surface. It is a metal substrate or the like. PET (polyethylene terephthalate) is used as a flexible insulating substrate. Tarate), PEN (polyethylene naphthalate), PES (polyether sulfone), Polypropylene, polypropylene sulfide, polycarbonate, polyetherimide , Polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthale There is a plastic substrate made of ruamide or the like, or paper made of a fibrous material.

Further, SO to be produced later by using a prepreg as a flexible insulating substrate. It is possible to prevent destruction of I-boards and semiconductor devices due to point pressure and linear pressure. Representative of prepreg Examples include polyvinyl alcohol fibers, polyester fibers, polyamide fibers, and po. Liethylene fiber, aramid fiber, polyparaphenylene benzobisoxazole fiber, Epoxy resin, unsaturated polyester resin, po. Impregnated with a composition obtained by diluting a matrix resin such as a reimide resin or a fluororesin with an organic solvent. After that, it was dried to volatilize the organic solvent to semi-cure the matrix resin.

As the flexible insulating substrate, aluminosilicate glass and aluminosilicate glass are used. For various glass substrates used in the electronics industry, such as acid glass and barium borosilicate glass Can be

Examples of the flexible metal substrate having an insulating layer formed on its surface include a silicon oxide layer and a silicon nitride layer. A metal on which an insulating layer such as a silicon nitride layer, an aluminum nitride layer, or an aluminum oxide layer is formed. There is a film or a metal sheet. The insulating layer is not limited to the above-listed insulating layers. It can be applied as appropriate.

The SOI layer 102 is a single crystal semiconductor layer, and single crystal silicon is typically applied. Also Silicon and hydrogen that can be stripped from polycrystalline semiconductor substrates by hydrogen ion implantation stripping method Can be peeled from a single crystal semiconductor substrate or a polycrystalline semiconductor substrate by the ion implantation peeling method. Germanium can also be applied. In addition, silicon germanium and gallium Crystalline semiconductor substrates made of compound semiconductors such as arsenic and indium phosphide can also be applied. To.

In addition, in this embodiment and the second and subsequent embodiments Te is a typical example SOI layer 102 Although the single crystal semiconductor layer is used, a polycrystalline semiconductor substrate is used instead of the single crystal semiconductor substrate. If so, the SOI layer 102 becomes a polycrystalline semiconductor layer. Also, instead of a single crystal semiconductor substrate When a crystalline semiconductor substrate is used, the SOI layer 102 becomes a crystalline semiconductor layer.

Further, as shown in FIG. 2, the space between the base substrate 100 and the SOI layer 102 is smooth. A bonding layer (layer formed at the bonding interface) 104 having an activated surface may be provided. Figure 2 forms a bonding layer 104 with a smooth and activated surface on the surface of the SOI layer 102. The base substrate 100 and the bonding layer 104 having a smooth and activated surface are bonded together. This is the manufactured SOI substrate. The surface of the base substrate 100 was smooth and activated. Bonding layer 104 with a smooth and activated surface forming a bonding layer 104 with a surface And the SOI layer 102 may be joined to prepare an SOI substrate.

A silicon oxide layer is suitable as the bonding layer 104. Chemical vapor phase using organic silane gas in particular A silicon oxide layer produced by the growth method is preferable. As an organic silane gas, ethyl silicate, Tetramethylsilane, tetramethylcyclotetrasiloxane, octamethylcyclotetra Siloxane, hexamethyldisilazane, triethoxysilane, trisdimethylaminosila Silicon-containing compounds such as silicon can be used. In addition, as the bonding layer 104, the single crystal semiconducting It is also possible to apply a thermal oxide layer formed by heat-treating the body substrate at a high temperature or a chemical oxide. it can. The chemical oxide is, for example, a single crystal semiconductor substrate that becomes an SOI layer in ozone-containing water. It can be formed by treating the surface. Chemical oxide is a single crystal semiconductor substrate It is preferable because it is formed to reflect the flatness of the surface.

The bonding layer 104 having a smooth and activated surface is preferably 1 nm to 600 nm. It is provided with a thickness of 5 nm to 500 nm, more preferably 5 nm to 200 nm. .. With this thickness, the surface roughness of the surface to be formed (the surface that forms the bond) is smoothed, and at the same time, It is possible to ensure the smoothness of the growth surface of the layer. In addition, a bonding layer 104 is provided. Therefore, the thermal strain between the base substrate to be joined and the SOI layer can be alleviated. Flexible When joining the SOI layer 102 to the base substrate 100 using a substrate having an insulating surface Then, acid is applied to one or both of the joint surface of the base substrate 100 and the joint surface of the SOI layer 102. It was formed by treating the surface of a siliconized silicon layer, preferably a thermal oxide layer, or a single crystal semiconductor substrate with ozone water. A bonding layer 104 made of a silicon oxide layer or a silicon oxide layer formed from organic silane as a raw material. By providing the base substrate 100 and the SOI layer 102, the base substrate 100 and the SOI layer 102 can be firmly joined.

3 and 4 show at least the barrier layer 105 between the base substrate 100 and the SOI layer 102. The configuration in which the bonding layer 104 is provided is shown. When the SOI layer 102 is joined to the base substrate 100 In addition, by providing the barrier layer 105, the flexibility used as the base substrate 100 From an insulating substrate having an insulating substrate, a flexible metal substrate, and a flexible substrate having an insulating surface. Impurities such as mobile ions such as alkali metals or alkaline earth metals diffuse and SOI It is possible to prevent the layer 102 from being contaminated. The barrier layer 105 includes nitrogen-containing insulation. The layer is preferable, and typically a silicon nitride layer, a silicon oxide layer, a silicon oxide layer, and an aluminum nitride. One layer selected from the um layer, the aluminum nitride layer, or the aluminum nitride layer Alternatively, it is formed by laminating a plurality of layers. For example, from the SOI layer 102 side, the silicon oxide nitride layer and nitriding The silicon oxide layer can be laminated to form the barrier layer 120. Also, as a barrier layer 105 By using a dense layer with a slow etching rate, the barrier function can be further enhanced. As a dense layer that is possible and has a slow etching rate, the above-mentioned nitrogen-containing insulating layer and silicon oxide are used. A layer, a silicon nitride layer, a silicon nitride layer, an aluminum nitride layer and the like can be formed.

Here, the silicon oxide layer has a composition having a higher oxygen content than nitrogen. Rutherford Backscat (RBS) Tering Spectrometry) and Hydrogen Forward Scattering (HFS) When measured using en Forward Scattering), the concentration range Oxygen 50-70 atomic%, nitrogen 0.5-15 atomic%, Si 25-35 atomic%, hydrogen Those contained in the range of 0.1 to 10 atomic%. The composition of the silicon nitride layer is As, it has a higher nitrogen content than oxygen and was measured using RBS and HFS. In this case, the concentration range is 5 to 30 atomic% for oxygen, 20 to 55 atomic% for nitrogen, and 25 for Si. It refers to those containing ~ 35 atomic% and hydrogen in the range of 10 ~ 30 atomic%. However, oxidative nitriding When the total number of atoms that make up recon or silicon nitride oxide is 100 atomic%, nitrogen, It is assumed that the content ratios of oxygen, Si and hydrogen are within the above range.

FIG. 3A shows another configuration of the SOI substrate according to the present invention. FIG. 3 (A) shows the bonding layer 104. The configuration in which the barrier layer 105 is provided between the base substrates 100 is shown. Here, the base board 10 A barrier layer 105 is provided at 0, a bonding layer 104 is provided on the surface of the SOI layer 102, and the barrier layer 105 is provided. And the structure in which the bonding layer 104 is bonded are shown. Instead of this, it is joined to the base substrate 100. A layer 104 is provided, a barrier layer 105 is provided on the surface of the SOI layer 102, and the barrier layer 105 and the bonding are provided. It can be configured by joining layers 104. Furthermore, the base board 100 or SOI The barrier layer 105 and the bonding layer 104 are laminated in this order on one surface of the layer 102, and the base substrate 10 is laminated. It can be configured by joining 0 or the other surface of the SOI layer 102 and the bonding layer 104. ..

FIG. 3B shows a bonding layer 104 and a plurality of layers between the base substrate 100 and the SOI layer 102. The configuration in which the rear layers 105 and 120 are provided is shown. Here, the barrier layer 10 is attached to the base substrate 100. 5 and 120 are provided, and the barrier layer 120 and the bonding layer 104 are laminated in order on the surface of the SOI layer 102. , The structure in which the barrier layer 105 and the bonding layer 104 are bonded is shown. Instead of this, the base The barrier layer 105 and the bonding layer 104 are laminated on the substrate 100 in this order, and burrs are formed on the surface of the SOI layer 102. A layer 120 may be provided, and the barrier layer 120 and the bonding layer 104 may be bonded to each other. ..

FIG. 4 shows the barrier layer 105 and the contact between at least the base substrate 100 and the SOI layer 102. The configuration in which the insulating layer 121 is provided together with the laminated layer 104 is shown. The insulating layer 121 is the SOI layer 102. And between the bonding layers 104, between the bonding layers 104 and the barrier layer 105, and the base substrate 100 And can be provided between the barrier layers 105.

FIG. 4 (A) shows the bonding layer 104 and the barrier layer 1 between the base substrate 100 and the SOI layer 102. The configuration in which 05 and the insulating layer 121 are provided is shown. Here, the barrier layer 1 is attached to the base substrate 100. 05 is provided, and the insulating layer 121 and the bonding layer 104 are laminated in order on the surface of the SOI layer 102 to form a barrier. The structure which joined the layer 105 and the joining layer 104 is shown. Instead of this, the base board 10 The barrier layer 105 and the bonding layer 104 are laminated in this order on 0, and the insulating layer 121 is formed on the surface of the SOI layer 102. Is provided, and the bonding layer 104 and the insulating layer 121 can be bonded to each other.

FIG. 4 (B) shows the SOI layer 102 in addition to the surface of the base substrate 100 in FIG. 4 (A). The configuration in which the barrier layer 120 is provided is also shown above. Here, the barrier layer 10 is attached to the base substrate 100. 5 is formed, and the insulating layer 121, the barrier layer 120, and the bonding layer 104 are formed on the surface of the SOI layer 102. The structure in which the barrier layer 105 and the bonding layer 104 are joined by stacking them in order is shown. In addition, instead of this The barrier layer 105 and the bonding layer 104 are laminated in this order on the base substrate 100, and the SOI layer 102 The insulating layer 121 and the barrier layer 120 are laminated on the surface in this order, and the bonding layer 104 and the barrier layer 120 are laminated in this order. Can be joined.

The insulating layer 121 is preferably a thermal oxide layer formed by heat-treating a single crystal semiconductor substrate at a high temperature. Ma In addition, silica oxide deposited by the chemical vapor deposition method using organic silane gas as in the bonding layer 104. A bare layer may be used. It is also possible to apply a chemical oxide as the insulating layer 121. Wear. The chemical oxide is, for example, a single crystal semiconductor substrate surface in which ozone-containing water forms an SOI layer. It can be formed by treating the surface. Chemical oxide is a table of single crystal semiconductor substrates Since it is formed reflecting the shape of the surface, if the single crystal semiconductor substrate is flat, the chemical oxide It is also preferable because it also flattens.

In the SOI substrate shown in this embodiment, an SOI layer is bonded onto a flexible substrate. Therefore, it is flexible. It is also thin.

(Embodiment 2) The method for manufacturing the SOI substrate shown in the first embodiment will be described with reference to FIGS. 5 to 8.

The single crystal semiconductor substrate 101 shown in FIG. 5 (A) is cleaned and accelerated by an electric field from its surface. Irradiate the single crystal semiconductor substrate with the generated ions, and bring the ions to a predetermined depth on the single crystal semiconductor substrate. Ion doping layer (specifically, fragile containing accelerated ionic elements Layer, including halogens typified by hydrogen, helium or fluorine, for example. Refers to the area. Hereinafter, the vulnerable area 103) is formed. Accelerated ion irradiation is based This is done in consideration of the thickness of the SOI layer to be transposed to the substrate. The SOI layer is 5 nm to 50. 0 nm, preferably 10 nm to 200 nm, more preferably 10 nm to 100 nm, More preferably, the thickness is 10 nm to 50 nm. Ions on the single crystal semiconductor substrate 101 The acceleration voltage at the time of irradiation is set in consideration of such thickness. After peeling (separation), S The thickness of the SOI layer immediately after peeling (separation) to flatten the surface of the OI layer by polishing or melting. Is preferably set to 50 nm to 500 nm.

The fragile region 103 is a haloge represented by hydrogen, helium or fluorine as a source gas. The accelerated ions generated by plasma excitation are illuminated on the single crystal semiconductor substrate. It is formed by shooting. In this case, a plurality of ions or multiple ions having different masses consisting of one atom. It is preferable to irradiate ions having different masses consisting of several atoms. Illumination of such ions As a shooting method, there are an ion doping method, an ion implantation method and the like. Accelerated hydrogen ions When irradiating a single crystal semiconductor substrate, H⁺, H₂⁺, H₃⁺In addition to containing ions H₃⁺It is preferable to increase the ratio of ions. H₃⁺Derivation by increasing the ratio of ions The input efficiency can be increased and the irradiation time can be shortened. Like this H⁺, H₂⁺H than ion₃⁺When the ratio of ions is increased and the ions are irradiated, H₃⁺Ion ratio More hydrogen ions on the single crystal semiconductor substrate 101 than when irradiating ions without increasing By incorporating it in a large amount, it is possible to use a small amount of ion irradiation in the fragile area 103, which will be performed later. Can be easily peeled off (separated).

When irradiating the single crystal semiconductor substrate 101 with accelerated ions, the surface of the single crystal semiconductor substrate is exposed. , It is necessary to irradiate ions at a high concentration, so the surface of the single crystal semiconductor substrate 101 is rough. It may get messy. Therefore, on the surface irradiated with accelerated ions, a silicon oxide layer, A protective layer against the single crystal semiconductor substrate 101 by a silicon nitride layer, a silicon nitride oxide layer, or the like. By providing a thickness of 50 nm to 200 nm, the surface irradiated with ions will be damaged. It is preferable because it can prevent the flatness from being impaired.

In the present specification, the ion doping method refers to ionization generated from a raw material gas. The element of the gas that is ionized by irradiating the object by accelerating it with an electric field as it is without separating the mass of the gas. Refers to the method of including in the object. With an ion doping device, it is a large area substrate It is also possible to perform high dose ion doping with high efficiency.

The acceleration voltage of ion doping is 20 kV or more and 100 kV or less, preferably 20 k. V or more and 70 kV or less, and the dose is 1 x 10¹⁶ions / cm²More than 4 × 10¹⁶i ons / cm²Below, preferably 1 × 10¹⁶ions / cm²Above 2.5 × 10¹⁶i ons / cm²It may be as follows. In this embodiment, the acceleration voltage is 80 kV and the dose is 2. × 10¹⁶ions / cm²Ion doping is performed as.

Next, as shown in FIG. 5 (B), a crimping member 122 is provided on the surface of the single crystal semiconductor substrate 101. , The single crystal semiconductor substrate 101 and the crimping member 122 are brought into close contact with each other and heated, that is, heat treatment and pressurization. By performing the treatment, the single crystal semiconductor substrate 101 is formed with the fragile region 103 as a cleavage surface in a later process. It facilitates peeling (separation) from the base substrate 100. The cleavage plane here is The region where the single crystal semiconductor substrate is separated is referred to, and the cleavage plane is hereinafter referred to as a separation region. Heating process The temperature of the sword is lower than the temperature at which the fragile area 103 separates, and the vulnerable area 103 is vulnerable. It is preferable that the temperature is as high as possible. For example, 250 ° C or higher, preferably 300 ° C or higher, 400 Formed in fragile region 103 by heat treatment below ° C, preferably below 350 ° C Although the volume of the small cavity changes, a crimping member 122 is provided on the surface of the single crystal semiconductor substrate. Therefore, the surface of the single crystal semiconductor substrate can be kept flat. As a result, vulnerable areas Due to the volume change of the minute cavity in the region 103, the fragile region 103 is distorted and along the fragile region. Can be vulnerable. In the pressure treatment, the base substrate 100 and the single crystal semiconducting Considering the pressure resistance of the body substrate 101, the pressure is applied in the direction perpendicular to the joint surface.

As shown in FIG. 5 (C), the base substrate 100 and the single crystal semiconductor substrate 101 are brought into close contact with each other. The mode in which both of the above are joined is shown. The surface to be joined should be thoroughly cleaned. And bee The base by bringing the substrate 100 and the single crystal semiconductor substrate 101 into close contact with each other while pressurizing them. The substrate 100 and the single crystal semiconductor substrate 101 are joined. This joint is van der Waals A force is acting, and water is formed by pressure-welding the base substrate 100 and the single crystal semiconductor substrate 101. It is possible to perform stronger bonding than bonding by van der Waals force by elemental bonding. Is.

In order to perform good bonding, it is preferable to activate the surface forming the bonding. For example, joining Irradiate the surface to be subjected to an atomic beam or an ion beam. Atomic beam or ion bee When using the gas, a neutral atom beam of an inert gas such as argon or an inert gas ion is used. Beam can be used. In addition, plasma irradiation or radical treatment is performed. Also, at least one of a substrate having a flexible and insulating surface, or a single crystal semiconductor layer. The joint surface may be hydrophilized by treatment with oxygen plasma or washing with ozone water. this Due to such surface treatment, even if the temperature of the subsequent heat treatment is 250 ° C or more and less than 400 ° C, it is different. It becomes easy to improve the bonding strength between materials.

Instead of the heat treatment performed before joining the base substrate 100 and the single crystal semiconductor substrate 101. After joining the base substrate 100 and the single crystal semiconductor substrate 101, the base substrate 100 is reached. Or, the single crystal semiconductor substrate is irradiated with a laser beam from the single crystal semiconductor substrate 101, and the fragile region 1 03 may be heated. A place to irradiate a laser beam from the single crystal semiconductor substrate 101 side. In that case, an infrared laser beam is used. As a result, a vulnerable area is formed, and the vulnerable area is defined. The single crystal semiconductor substrate 101 can be separated from the base substrate 100 as a separation region. it can.

As shown in FIG. 5 (D), after the base substrate 100 and the single crystal semiconductor substrate 101 are bonded together. , The single crystal semiconductor substrate 101 is peeled off from the base substrate 100 with the fragile region 103 as the separation region. By (separating), an SOI substrate can be obtained. The surface of the single crystal semiconductor substrate 101 is Since it is bonded to the base substrate 100, the single crystal semiconductor substrate 101 is placed on the base substrate 100. The SOI layer 102 having the same crystallinity as the above remains.

The single crystal semiconductor substrate 101 is peeled off from the base substrate 100 with the fragile region 103 as the separation region ( Before (separation), it is preferable to create a trigger for easy peeling (separation). Ingredients Physically, it selectively (partially) reduces the adhesion of the fragile region 103 and the SOI layer 102. By performing the pretreatment, peeling (separation) defects are reduced, and the yield is also improved. representative Specifically, the laser beam is transferred from the base substrate 100 or the single crystal semiconductor substrate 101 to the fragile region 103. There is an example of forming a groove with a mesh or a dicer.

Further, when the single crystal semiconductor substrate 101 is peeled (separated) from the base substrate 100, the base substrate is separated. Peeled by light or heat on at least one surface of 100 or single crystal semiconductor substrate 101 Provide a possible adhesive sheet and fix either the base substrate 100 or the single crystal semiconductor substrate 101. However, by peeling off the other side, peeling (separation) becomes easier. At this time, the base substrate By providing a support member on the other side of the 100 or the single crystal semiconductor substrate 101, the peeling process can be performed. It will be easy.

The SOI layer obtained by peeling (separation) is a chemical machine to flatten its surface. Perform Chemical Mechanical Polishing (CMP) It is preferable. In addition, a laser is applied to the surface of the SOI layer without using physical polishing means such as CMP. It may be flattened by irradiating a beam. When irradiating the laser beam, the oxygen concentration It is preferable to carry out in a nitrogen atmosphere of 10 ppm or less. This is a laser in an oxygen atmosphere This is because the surface of the SOI layer may be roughened when the beam is irradiated. Also, the obtained SO CMP or the like may be performed for the purpose of thinning the I layer.

Further, before the crimping member 122 is provided on the surface of the single crystal semiconductor substrate 101 shown in FIG. 5 (B), The bonding layer 104 may be formed on the surface of the single crystal semiconductor substrate 101. In addition, it is shown in Fig. 5 (B). A crimping member 122 is provided on the surface of the single crystal semiconductor substrate 101, and the single crystal semiconductor substrate 101 and the pressure are provided. After the landing member 122 is brought into close contact and heated, the bonding layer 104 is formed on the surface of the single crystal semiconductor substrate 101. You may. After that, as shown in FIG. 5 (C), the bonding layer 104 and the base substrate 100 are densely packed. By bringing them into contact with each other, the two can be easily joined.

According to this embodiment, a flexible substrate having low heat resistance and a single crystal semiconductor substrate are joined to form an SOI substrate. Can be produced. According to this configuration, a substrate with a low heat resistant temperature such as a plastic substrate can be used. Even if there is, an SOI substrate having an SOI layer bonded to the substrate by a joint having a strong bonding force. Can be obtained with a high yield. In addition, a flexible and thin SOI substrate is produced. Can be

(Embodiment 3) Next, a method for producing an SOI substrate different from that of the above embodiment will be shown with reference to FIG. In FIG. 6, a form in which the base substrate 100 and the single crystal semiconductor substrate 101 are bonded using a bonding layer is used. Is shown. In addition, the base substrate 100 and the single crystal semiconductor substrate 101 are joined without using a crimping member. Indicates the form to be used.

Similar to FIG. 5 (A), as shown in FIG. 6 (A), the cleaned single crystal semiconductor substrate 101 By irradiating the surface with ions accelerated by an electric field, the ions reach a predetermined depth on the single crystal semiconductor substrate. The fragile region 103 is formed by containing the elements of.

Next, as shown in FIG. 6 (B), at least the cap layer 123 is formed on the single crystal semiconductor substrate 101. And the bonding layer 104 is formed. Here, the cap layer 1 is on the surface of the single crystal semiconductor substrate 101. 23 is formed and the bonding layer 104 is formed on the cap layer 123.

Here, it is preferable that at least one of the bonding layer 104 and the cap layer 123 is thicker. I'm sorry. Volume of minute cavities formed in fragile region 103 by heat treatment in a later step Although changes occur, the cap layer 123 is provided on the surface of the single crystal semiconductor substrate, and the single crystal Since the surface of the semiconductor substrate can be kept flat, the bonding layer 104 provided on the surface of the semiconductor substrate can be kept flat. Flatness can also be maintained. As a result, due to the volume change of the minute cavity in the fragile region 103 , The vulnerable area 103 is distorted, and it becomes possible to weaken along the vulnerable area. In particular, By increasing the thickness of the cap layer 123, the surface of the single crystal semiconductor substrate 101 is displayed during heat treatment. Since a force is applied in the direction perpendicular to the surface, the single crystal semiconductor substrate is brittle while maintaining the flatness of the irradiated surface. It has the effect of forming a weak region.

The cap layer 123 can be a single layer or a laminated layer of a nitrogen-containing insulating layer or a silicon oxide layer. To. By forming a part or all of the cap layer 123 with a nitrogen-containing insulating layer, the cap layer 123 can be formed. The up layer 123 is preferable because it also functions as a barrier layer.

It is then heated to change the volume of the tiny cavities in the fragile region 103. As a result, the later process The single crystal semiconductor substrate 101 is peeled off (separated) from the base substrate 100 with the fragile region as the separation region. ) Make it easy to do. The temperature of the heat treatment is not the temperature at which the fragile region 103 peels (separates). It is preferably above the temperature at which the fragile region 103 is formed. For example, 2 Heat treatment above 50 ° C, preferably above 300 ° C, below 400 ° C, preferably below 350 ° C Is preferable.

FIG. 6C shows a single crystal semiconductor substrate 101 on which the cap layer 123 and the bonding layer 104 are formed. The process of bringing the bonding layer 104 and the base substrate 100 into close contact with each other is shown. Single crystal semiconduct The bonding layer 104 on the body substrate 101 and the base substrate 100 are brought into close contact with each other to be bonded.

At least one surface of the bonding layer 104 or the base substrate 100 for good bonding May be activated. For example, an atomic beam or an ion beam is applied to the surface to be joined. Irradiate. When using an atomic beam or an ion beam, an inert substance such as argon is used. A neutral atom beam or an inert gas ion beam can be used. Besides, Perform razuma irradiation or radical treatment. Also, the base substrate 100 or the bonding layer 104 At least one of the joint surfaces is hydrophilized by treatment with oxygen plasma or washing with ozone water. You may. Such surface treatment allows bonding between dissimilar materials even at temperatures below 400 ° C. Will be easier to do.

After that, as shown in FIG. 6 (D), the single crystal semiconductor substrate 101 is peeled off (separated) to form S. An OI substrate can be obtained. The surface of the SOI layer obtained by peeling (separation) is It is preferable to flatten. In addition, for the purpose of thinning the obtained SOI layer, CMP, etc. May be done. In addition, the single crystal semiconductor substrate 101 is used as the separation region with the fragile region 103 as the separation region. Before peeling (separating) from the substrate 100, a trigger is provided to facilitate peeling (separation). You may come. Furthermore, the single crystal semiconductor substrate 101 is peeled off (separated) from the base substrate 100. When doing so, the surface of at least one of the base substrate 100 or the single crystal semiconductor substrate 101 is illuminated. A base substrate 100 or a single crystal semiconductor substrate 1 is provided with an adhesive sheet that can be peeled off by heat. By fixing one of 01 and peeling off the other, peeling (separation) becomes easier. this By providing a support member on the other side of the base substrate 100 or the single crystal semiconductor substrate 101. The peeling process becomes easy.

Instead of the heat treatment performed before joining the base substrate 100 and the single crystal semiconductor substrate 101. After joining the base substrate 100 and the single crystal semiconductor substrate 101, the base substrate 100 is reached. Or, the single crystal semiconductor substrate is irradiated with a laser beam from the single crystal semiconductor substrate 101, and the fragile region 1 03 may be heated. A place to irradiate a laser beam from the single crystal semiconductor substrate 101 side. In that case, a laser beam having a wavelength absorbed by a single crystal semiconductor substrate, typically an infrared laser beam. Use As a result, the single crystal semiconductor substrate 101 is used as the base substrate with the fragile region as the separation region. It can be peeled (separated) from 100.

According to this embodiment, a flexible substrate having low heat resistance and a single crystal semiconductor substrate are joined to form an SOI substrate. Can be produced. According to this configuration, a substrate with a low heat resistant temperature such as a plastic substrate can be used. Even if there is, an SOI substrate having an SOI layer bonded to the substrate by a joint having a strong bonding force. Can be obtained with a high yield. In addition, a flexible and thin SOI substrate is produced. Can be

(Embodiment 4) Next, a method for producing an SOI substrate different from the above embodiment will be shown with reference to FIG. 7. Here, a release layer is formed on the support substrate, an SOI layer is formed on the release layer, and a layer is formed on the SOI layer. After attaching the insulator substrate, the base substrate is peeled off from the support substrate to prepare an SOI substrate.

As shown in FIG. 7A, a release layer 131 is formed on the support substrate 130, and the release layer 131 is formed on the release layer 131. The insulating layer 132 is formed. Here, as the support substrate 130, for forming a release layer. A heat treatment temperature (typically 400 ° C to 60) that is a substrate and causes cracks in fragile areas. A substrate having heat resistance that can withstand 0 ° C) is preferable, and typically, a glass substrate, a quartz substrate, etc. Ceramic substrates, metal substrates, silicon wafers and the like can be used.

The release layer 131 may be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. , Tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirc Nium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon An element selected from the above, an alloy material containing the element as the main component, or a compound containing the element as the main component A layer made of a composite material is formed by laminating a single layer or a plurality of layers. As a peeling layer 131 When forming a layer containing silicon, the crystal structure of the layer containing silicon is amorphous, microcrystal, or polycrystalline. It may be a deviation. Here, the coating method is a method of forming by discharging a solution onto an object to be treated. This includes, for example, a spin coating method and a droplet ejection method. What is the droplet ejection method? This is a method of forming a pattern having a predetermined shape by ejecting droplets of a composition containing ..

When the release layer 131 has a single layer structure, preferably tungsten, molybdenum, or tongue. A layer containing a mixture of stainless steel and molybdenum is formed. Or an oxide of tungsten or A layer containing an oxide nitride, a layer containing a molybdenum oxide or an oxide nitride, or a tongue stee A layer containing an oxide or oxide nitride of a mixture of molybdenum and molybdenum is formed. In addition, tongue The mixture of stainless steel and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. ..

When the release layer 131 has a laminated structure, a metal layer is preferably formed as the first layer, and the second layer is formed. To form a metal oxide layer. Typically, the first layer is tungsten, molybdenum, or Formed a layer containing a mixture of tungsten and molybdenum, and as a second layer, tungsten, Molybdenum, or oxides of tungsten and molybdenum, tungsten, molybdenum Nitride, or a mixture of tungsten and molybdenum, tungsten, molybdenum, or Nitride oxide of a mixture of tungsten and molybdenum, or tungsten, molybdenum, or A layer containing a nitride oxide of a mixture of tungsten and molybdenum is formed.

As the release layer 131, a laminated structure of a metal layer as the first layer and a metal oxide layer as the second layer is formed. When formed, a metal layer, for example a layer containing tungsten, is formed, and an oxide is formed on the upper layer. By forming an insulating layer 132, for example, a silicon oxide layer, a layer containing tungsten and an insulating layer Utilizing the fact that a metal oxide layer, for example, a layer containing an oxide of tungsten is formed at the interface with You may use it. Furthermore, the surface of the metal layer is treated with thermal oxidation, oxygen plasma, ozone water, etc. The metal oxide layer may be formed by treating with a solution having a strong oxidizing power.

Further, as the release layer 131, the first layer is a metal layer, the second layer is a metal nitride layer, and a metal. An oxide nitride layer may be formed. Typically, a layer containing tungsten is formed as the first layer. After that, a tungsten nitride layer and a tungsten oxide layer may be formed as the second layer. ..

The insulating layer 132 is formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. , Formed in a single layer or multiple layers using an inorganic compound. Silicon oxide is a typical example of an inorganic compound. , Silicon nitride, silicon oxide, silicon oxide and the like. An insulating layer that functions as a base layer By using silicon nitride, silicon oxide, silicon oxide, etc. for 132, from the outside later It is possible to prevent water, gas such as oxygen, and the like from entering the formed element layer.

Further, the insulating layer 132 may have a laminated structure. For example, laminating with an inorganic compound Also, typically two or more of silicon oxide, silicon nitride oxide, silicon nitride, or silicon oxide. The tops may be laminated to form.

Next, a single unit having a vulnerable region 103 vulnerable by the steps shown in the second or third embodiment. The crystalline semiconductor substrate 101 and the insulating layer 132 are brought into close contact with each other to be joined.

At least one of the insulating layer 132 or the single crystal semiconductor substrate 101 for good bonding The surface of the surface may be activated. For example, an atomic beam or ionbi on the surface to be joined Irradiate the room. When using an atomic beam or an ion beam, it is not possible to use argon, etc. An active gas neutral atom beam or an inert gas ion beam can be used. Other Is subjected to plasma irradiation or radical treatment. In addition, the insulating layer 132 or the single crystal semiconducting At least one of the joint surfaces of the body substrate is treated with oxygen plasma or washed with ozone water. It may be made hydrophilic. Due to such surface treatment, the temperature is 250 ° C or higher and lower than 400 ° C. Also makes it easy to join between dissimilar materials.

As shown in FIG. 7 (B), the fragile region 103 is formed by performing heat treatment and further pressure treatment. The single crystal semiconductor substrate 101 is peeled (separated) from the support substrate 130 as a separation region. Heating process The temperature is preferably equal to or lower than the heat resistant temperature of the support substrate 130. For example, 400 ° C Volume change of minute cavities formed in fragile region 103 by heat treatment up to 600 ° C It becomes possible to separate along the vulnerable area 103.

At this time, instead of the heat treatment, a laser beam is irradiated from the single crystal semiconductor substrate 101, The volume of the minute cavity formed in the fragile region 103 may be changed. As a laser beam Uses a wavelength that penetrates the single crystal semiconductor substrate and is absorbed by the elements contained in the fragile region 103. Infrared light can be typically used.

After peeling (separating) the single crystal semiconductor substrate, it is preferable to flatten the surface of the SOI layer. Further, CMP or the like may be performed for the purpose of thinning the obtained SOI layer. Also, vulnerable areas The single crystal semiconductor substrate 101 is peeled (separated) from the support substrate 130 with the region 103 as the separation region. Before this, a trigger may be created to facilitate peeling (separation). Furthermore, a single crystal When the semiconductor substrate 101 is peeled (separated) from the support substrate 130, the support substrate 130 or a single unit is connected. An adhesive sheet that can be peeled off by light or heat on at least one surface of the crystalline semiconductor substrate 101. Is provided, one of the support substrate 130 or the single crystal semiconductor substrate 101 is fixed, and the other is peeled off. By doing so, peeling (separation) becomes easier. At this time, the support substrate 130 or a single crystal half By providing a support member on the other side of the conductor substrate 101, the peeling process becomes easy.

Next, as shown in FIG. 7 (C), the base substrate 100 is thermocompression bonded to the SOI layer 102. Therefore, the base substrate 100 can be fixed to the SOI layer 102. Also. SOI layer 1 The base substrate 100 can be fixed to 02 using an adhesive (not shown). Also, As shown in the second embodiment, the SOI layer 102 and the base substrate 100 are brought into close contact with each other and joined. May be good.

Next, as shown in FIG. 7 (D), the base to which the SOI layer 102 is fixed from the support substrate 130. The substrate 100 is peeled off by physical means. Physical means are mechanical or mechanical means Refers to a means of changing some mechanical energy (mechanical energy). , The means is typically applying mechanical force (eg, peeling off with a human hand or grip). Processing to separate while rotating the roller). At this time, the base substrate 10 Adhesive coating that can be peeled off by light or heat on at least one surface of 0 or the support substrate 130 If a mat is provided, the peeling becomes easier.

In addition, the liquid is permeated into the interface between the release layer 131 and the insulating layer 132 to allow the support substrate 130 to penetrate. The booth substrate 100 may be peeled off.

Here, the interface between the release layer 131 and the insulating layer 132, the release layer 131, or the support substrate 130. And peeling occurs at any of the interfaces of the peeling layer 131, and the element layer is peeled from the support substrate 130. be able to.

In addition, before the peeling step, a trigger is made in the peeling layer 131 in order to easily perform the peeling. You may. Furthermore, when the single crystal semiconductor substrate 101 is peeled off from the support substrate 130, the support group Peeled by light or heat on at least one surface of plate 130 or single crystal semiconductor substrate 101 Provide a detachable adhesive sheet, fix one of the base board 100 or the support board 130, and the other By peeling off the side, the peeling becomes easier. At this time, the support substrate 130 or single connection By providing a support member on the other side of the crystalline semiconductor substrate 101, the peeling step becomes easy.

After this, the insulating layer 132 bonded to the surface of the SOI layer 102 may be removed. In the above process Therefore, the SOI substrate can be manufactured. According to this embodiment, a single unit in which a fragile area is formed After the crystalline semiconductor substrate is heated to peel off the SOI layer, the base substrate is fixed to the SOI layer. In addition, once the SOI layer is held on a support substrate that is easy to handle, the SOI layer is applied to the SOI layer. The base substrate is fixed and the SOI layer is peeled off from the support substrate. Therefore, a base with low heat resistance An SOI substrate having an SOI layer provided on the substrate can be manufactured with a high yield.

According to this embodiment, a flexible substrate having low heat resistance and a single crystal semiconductor substrate are joined to form an SOI substrate. Can be produced. According to this configuration, a substrate with a low heat resistant temperature such as a plastic substrate can be used. Even if there is, an SOI substrate having an SOI layer bonded to the substrate by a joint having a strong bonding force. Can be obtained with a high yield. In addition, the support substrate is handled as compared with the flexible substrate. Because it is easy, it is easy to handle in the manufacturing process, and the yield can be increased. .. In addition, a flexible and thin SOI substrate can be produced.

(Embodiment 5) Next, a method for producing an SOI substrate different from that of the above embodiment will be shown with reference to FIG. Here, as the base substrate 100, the base substrate 100 having a heat resistant temperature of 700 ° C or less is used. Use to make an SOI substrate.

Similar to FIG. 5 (A), as shown in FIG. 8 (A), on the cleaned single crystal semiconductor substrate 101. Irradiate the ions accelerated by the electric field to include them in a predetermined depth of the single crystal semiconductor substrate, and make the fragile region 10 Form 3.

Next, as shown in FIG. 8 (B), at least the bonding layer 104 is formed on the single crystal semiconductor substrate 101. To be done. Here, the barrier layer 105 is formed on the surface of the single crystal semiconductor substrate 101, and the barrier layer is formed. A bonding layer 104 is formed on the 105.

The barrier layer 105 preferably includes at least a nitrogen-containing insulating layer. Nitriding-free The edge layer is typically a silicon nitride layer, a silicon oxide layer, a silicon oxide layer, or an aluminum nitride layer. , One or more selected from aluminum nitride layer, or aluminum nitride layer It is formed by laminating layers. For example, from the single crystal semiconductor substrate 101 side, a silicon oxide nitride layer and an acid nitride. The siliconized silicon layer can be laminated to form the barrier layer 105. The barrier layer 105 is plasma C. It can be formed by using the VD method, the sputtering method, or the like.

In FIG. 8C, the bonding layer 104 of the single crystal semiconductor substrate 101 and the base substrate 100 are brought into close contact with each other. The process of joining is shown. Bonding layer 104 on single crystal semiconductor substrate 101 and base substrate Join by bringing 100 into close contact. Here, the heat resistant temperature of the base substrate 100 is 700 ° C. It is preferably the following, typically a flexible glass substrate, flexible and flexible. A metal film or the like having an insulating layer can be used. By having such heat resistance , Can be heat treated to allow separation along the fragile region 103 ..

At least one surface of the base substrate 100 or the bonding layer 104 for good bonding May be activated. For example, an atomic beam or an ion beam is applied to the surface to be joined. Irradiate. When using an atomic beam or an ion beam, an inert substance such as argon is used. A neutral atom beam or an inert gas ion beam can be used. Besides, Perform razuma irradiation or radical treatment. Also, a substrate that is flexible and has an insulating surface. , Or at least one of the bonding surfaces of the single crystal semiconductor substrate can be treated with oxygen plasma. It may be hydrophilized by washing with zon water. With such surface treatment, 250 ° C or more and 400 ° C Even if the temperature is lower than that, it becomes easy to join between different materials.

After that, by performing heat treatment and further pressure treatment, as shown in Fig. 8 (D), the fragile area The single crystal semiconductor substrate 101 is peeled (separated) from the base substrate 100 with 103 as the separation region. Can be The temperature of the heat treatment is preferably equal to or lower than the heat resistant temperature of the base substrate 100. I'm sorry. For example, it is formed in the fragile region 103 by heat treatment at 400 ° C to 600 ° C. The volume change of the minute cavity that was created occurs, and it is possible to separate along the fragile region 103. To. In the pressurization process, the pressure resistance of the base substrate 100 and the single crystal semiconductor substrate 101 is taken into consideration. Then, the pressure is applied in the direction perpendicular to the joint surface.

At this time, instead of the heat treatment, a laser beam is irradiated from the single crystal semiconductor substrate 101, The volume of the minute cavity formed in the fragile region 103 may be changed. As a laser beam Uses a wavelength that penetrates the single crystal semiconductor substrate and is absorbed by the elements contained in the fragile region 103. Infrared light can be typically used.

After joining the base substrate 100 and the single crystal semiconductor substrate 101 instead of the heat treatment. , The single crystal semiconductor substrate is irradiated with a laser beam from the base substrate 100, and the fragile region 103 is added. You may heat it. As a result, the single crystal semiconductor substrate 101 is used as the base group with the fragile region as the separation region. It can be peeled (separated) from the plate 100.

The surface of the SOI layer obtained by peeling (separation) is preferably flattened. Further, CMP or the like may be performed for the purpose of thinning the obtained SOI layer. Also, vulnerable areas The single crystal semiconductor substrate 101 is separated from the base substrate 100 with the region 103 as the separation region (separation). Before this, a trigger may be created to facilitate peeling (separation). Furthermore, it is single When peeling (separating) the crystalline semiconductor substrate 101 from the base substrate 100, the base substrate 100 also Is an adhesive material that can be peeled off by light or heat on at least one surface of the single crystal semiconductor substrate 101. One of the base substrate 100 or the single crystal semiconductor substrate 101 is fixed, and the other is pulled. By peeling off, peeling (separation) becomes easier. At this time, the base board 100 or By providing a support member on the other side of the single crystal semiconductor substrate 101, the peeling step becomes easy.

As described above, according to this embodiment, the base substrate 10 having a heat resistant temperature of 700 ° C or less such as a glass substrate 10 Even if it is 0, it is possible to obtain an SOI layer 102 having a strong bonding force at the joint with the base substrate. To. As the base substrate 100, aluminosilicate glass, aluminoborosilicate glass, Various types used for the electronic industry called non-alkali glass such as barium borosilicate glass It becomes possible to apply a glass substrate. That is, on a board with a side of more than 1 meter A single crystal semiconductor layer can be formed. Liquid crystal display using such a large area substrate Not only display devices such as a, but also semiconductor integrated circuits can be manufactured.

Further, the semiconductor device of the present embodiment is joined to a support substrate having a flexible and insulating surface. By forming an integrated circuit with the formed single crystal semiconductor layer, the processing speed can be increased and the consumption can be reduced. It is possible to manufacture a semiconductor device with reduced power consumption. It is also flexible and thin. A semiconductor device can be manufactured.

(Embodiment 6) Next, FIGS. 9 and 1 show the semiconductor devices using the SOI substrates shown in the first to fifth embodiments. This will be explained with reference to 0. Here, as shown in FIGS. 6 and 8, the bonding layer 104 is used as a simple material. A form in which a semiconductor device is manufactured using an SOI substrate in which a crystalline semiconductor substrate and a base substrate are joined. As shown, as shown in FIGS. 5 and 7, a single crystal semiconductor substrate and a base substrate are used without using a bonding layer. A bonded SOI substrate can be used. In addition, a support board is attached to the base board of the SOI board. You can paste it. In addition, the SOI substrate is held by a holding member that holds the SOI substrate. As a result, a semiconductor device with a high yield can be manufactured even with a flexible substrate that is easily bent. Protect The holding member includes a roller, a gripping tool, and the like.

In FIG. 9 (A), SO is applied to the base substrate 100 via the bonding layer 104 and the barrier layer 105. The I layer 102 is provided. Silicon nitride on the SOI layer 102 according to the element formation region The layer 124 and the silicon oxide layer 125 are formed. Silicon oxide layer 125 is SOI for element separation Used as a hard mask when etching layer 102. Silicon nitride layer 124 is etched Used as a stopper.

The thickness of the SOI layer 102 is 5 nm to 500 nm, preferably 10 nm to 200 nm. To. The thickness of the SOI layer 102 is determined by controlling the depth of the fragile region 103 described in FIG. Can be set as appropriate. The SOI layer 102 has boron and aluminum to control the threshold voltage. Add p-type impurities such as um and gallium. For example, 5 × 10 boron as a p-type impurity¹⁶cm^-3Above 1 × 10¹⁸cm^-3It may be added at the following concentration.

In FIG. 9B, the SOI layer 102 and the bonding layer 104 are etched with the silicon oxide layer 125 as a mask. This is the process of Next, for the exposed end faces of the SOI layer 102 and the bonding layer 104, Nitriding is performed by performing a razor treatment. By this nitriding treatment, at least SOI layer 102 A silicon nitride layer 107 is formed at the peripheral end of the surface. The silicon nitride layer 107 is insulating and SO It has the effect of preventing leakage current from flowing at the end face of layer I 102. In addition, it has an oxidation resistance Since there is, an oxide layer grows from the end face between the SOI layer 102 and the barrier layer 105, and birds It is possible to prevent the formation of peaks.

FIG. 9C shows a step of depositing the element separation insulating layer 108. On the element separation insulating layer 108 , A silicon oxide film deposited by chemical vapor deposition using TEOS is used. Element separation insulation layer 10 8 is thickly deposited so that the SOI layer 102 is embedded.

FIG. 9D shows a process of removing the element separation insulating layer 108 until the silicon nitride layer 124 is exposed. doing. This removal step can be performed by dry etching or by a chemical machine. It may be performed by polishing treatment. The silicon nitride layer 124 serves as an etching stopper. element The separate insulating layer 108 remains so as to be embedded between the SOI layers 102. Silicon nitride layer 12 4 is then removed.

In FIG. 9 (E), after the SOI layer 102 is exposed, the gate insulating layer 109 and the gate electrode 1 10. The side wall insulating layer 111 is formed, and the first impurity region 112 and the second impurity region 1 are formed. Form 13. The insulating layer 114 is formed of a silicon nitride layer, and the gate electrode 110 is etched. It is used as a hard mask when

In FIG. 10A, the interlayer insulating layer 115 is formed. The interlayer insulating layer 115 is BPSG (B). oron Phosphorus Silicon Glass) Forming a layer and reflowing Flatten with. In addition, TEOS is used to form a silicon oxide layer for chemical mechanical polishing. Therefore, it may be flattened. In the flattening process, the insulating layer 114 on the gate electrode 110 is Functions as a ching stopper. A contact hole 116 is formed in the interlayer insulating layer 115. To do. The contact hole 116 is self-aligned by utilizing the side wall insulating layer 111. It has a contact structure.

After that, as shown in Fig. 10 (B), using tungsten hexafluoride, the contact was performed by the CVD method. Form the top plug 117. Further, an insulating layer 118 is formed and fits into the contact plug 117. An opening is formed and wiring 119 is provided. Wiring 119 is aluminum or aluminum Formed from um alloy, molybdenum, chromium, titanium, etc. as barrier metals in the upper and lower layers Form a metal layer of.

Here, the element layer 135 is a laminate from the SOI layer 102 to the insulating layer 118 and the wiring 119. Is shown.

After that, when the element layer 135 includes a plurality of semiconductor devices, the element layer 135 and the base substrate A plurality of semiconductor devices may be cut out by dividing 100. By such a process, a plurality The semiconductor device can be manufactured.

In this way, a semiconductor element, typically, using the SOI layer 102 bonded to the base substrate 100. Can be made into a field effect transistor. The SOI layer 102 according to this embodiment is formed. Since it is a single crystal semiconductor with a constant crystal orientation, a uniform and high-performance field-effect transistor can be obtained. Can be done. That is, non-existence of characteristic values that are important as transistor characteristics such as threshold voltage and mobility. It is possible to suppress uniformity and achieve high performance such as high mobility. Furthermore, the base group Since the barrier layer 105 is provided between the plate 100 and the SOI layer 102, is it a base substrate? Since it is possible to prevent these impurities from entering the SOI layer, they are formed in the device layer. Variations in transistor characteristics can be suppressed. It is also flexible and thin. A conductor device can be manufactured.

(Embodiment 7) Next, regarding the method for manufacturing the semiconductor device using the SOI substrate shown in the above-described first to fifth embodiments. This will be described with reference to FIGS. 11 and 12. Here, as shown in FIGS. 6 and 8, the bonding layer 1 A semiconductor device using an SOI substrate in which a single crystal semiconductor substrate and a base substrate are bonded using 04. The produced form is shown, but as shown in FIGS. 5 and 7, a single crystal semiconductor substrate and a single crystal semiconductor substrate without using a bonding layer are shown. And an SOI substrate to which the base substrate is bonded can be used. Also, the base base of the SOI substrate A support substrate may be attached to the board. In addition, the SOI is provided by a holding member that holds the SOI substrate. By holding the substrate, it is possible to manufacture a semiconductor device with a high yield even with a flexible substrate that is easily bent. Can be done. The holding member includes a roller, a gripping tool, and the like.

Similar to FIG. 6 (A), as shown in FIG. 11 (A), is it the surface of the single crystal semiconductor substrate 101? Irradiate the ions accelerated by the electric field to include them in a predetermined depth of the single crystal semiconductor substrate, and make the fragile region 1 Form 03. Next, the cap layer 123 and the bonding layer 1 are placed on the surface of the single crystal semiconductor substrate 101. 04 are stacked in order. After this, it is heated to further weaken the fragile region 103. Also, Instead of the up layer 123, a crimping member is provided in the joint layer 104 as shown in the second embodiment. It may then be heated to further weaken the vulnerable region 103.

FIG. 11B shows the insulating layer 132 and the single crystal semiconductor substrate 101 formed on the support substrate 130. The aspect in which the surface of the bonding layer 104 of the above is brought into close contact with each other and the two are bonded to each other is shown.

The release layer 131 is formed on the support substrate 130, and the insulating layer 132 is formed on the release layer 131. Next, the insulating layer 132 formed on the support substrate 130 and the surface of the single crystal semiconductor substrate 101 are formed. The bonding layer 104 to be formed is brought into close contact with each other, and the insulating layer 132 and the bonding layer 104 are bonded. This joint is Van der Waals force is acting, and the support substrate 130 and the single crystal semiconductor substrate 101 It is possible to make a strong bond by hydrogen bonding by pressure welding.

In addition, the surface may be activated for good bonding. For example, join Irradiate the surface with an atomic beam or an ion beam. Use atomic beam or ion beam When used, an inert gas such as argon is used as a neutral atom beam or an inert gas ion bee. Can be used. In addition, plasma irradiation or radical treatment is performed. This Bonding between dissimilar materials is performed even at temperatures of 250 ° C or higher and lower than 400 ° C by such surface treatment. It becomes easy.

In FIG. 11 (C), after the support substrate 130 and the single crystal semiconductor substrate 101 are bonded together, they are simply attached. The crystalline semiconductor substrate 101 is heat-treated at 400 ° C to 600 ° C to generate cracks in the fragile region 103. The single crystal semiconductor substrate 101 is transferred from the support substrate 130 with the fragile region 103 as the separation region. Peel (separate). Since the bonding layer 104 is bonded to the support substrate 130, the support substrate 130 The SOI layer 102 having the same crystallinity as the single crystal semiconductor substrate 101 remains on the top. To.

Instead of the above heat treatment, the support substrate 130 and the single crystal semiconductor substrate 101 were bonded. After that, the single crystal semiconductor substrate is irradiated with a laser beam from the support substrate 130, and the fragile region 103 is added. You may heat it. As a result, the single crystal semiconductor substrate 101 is supported by the fragile region as the separation region. It can be peeled (separated) from 130.

After this, it is preferable to flatten the surface of the SOI layer 102. As a flattening method, CM P can be used. Alternatively, the surface of the SOI layer 102 is irradiated with a laser beam to form the surface. Can be melted and flattened.

Next, through the steps of FIGS. 9 and 10, the element layer including the transistor is used by using the SOI layer 102. Form 135. Next, the base substrate 136 is provided on the element layer 135. Base board 13 The base substrate 136 is fixed to the element layer 135 by thermocompression bonding 6 and the element layer 135. Can be made. Also. Base substrate 13 using an adhesive (not shown) on the element layer 135 6 can be fixed. (See Figure 11 (D)). As the base board 136, the above-mentioned Those listed in the representative examples of the booth substrate 100 can be appropriately used.

After that, in order to easily perform the subsequent peeling step, the element layer 135 and the peeling are performed from the base substrate 136. A groove may be formed by irradiating the separation layer 131 with a laser beam. Irradiate to form a groove As the laser beam, either the release layer 131 or the layer constituting the element layer 135 is used. A laser beam having a wavelength to absorb is preferable, and typically, an ultraviolet region, a visible region, or a laser beam is used. A laser beam in the infrared region is appropriately selected and irradiated.

Next, as shown in FIG. 12 (A), the element layer 135 is removed from the support substrate 130 by physical means. Peel off. Alternatively, the support substrate 1 is provided by allowing a liquid to permeate the interface between the release layer 131 and the insulating layer 132. The element layer 135 is peeled off from 30.

Here, the interface between the release layer 131 and the insulating layer 132, the release layer 131, or the support substrate 130. And peeling occurs at any of the interfaces of the peeling layer 131, and the element layer 135 is peeled from the support substrate 130. Can be separated.

When the element layer 135 and the base substrate 136 are separated from the support substrate 130, the support substrate 1 is used. Adhesive that can be peeled off by light or heat on at least one surface of 30 or base substrate 136 A sheet is provided, one of the support board 130 or the base board 136 is fixed, and the other is peeled off. By doing so, peeling becomes easier. At this time, the support board 130 or the base board 136 By providing a support member on the other side of the above, the peeling process becomes easy.

Next, as shown in FIG. 12 (B), the flexible substrate 137 is fixed to the insulating layer 132. flexible The same material and fixing method as the base substrate 136 can be applied to the sex substrate 137. To.

After that, when the element layer 135 includes a plurality of semiconductor devices, the element layer 135, the base substrate 1 A plurality of semiconductor devices may be cut out by dividing the 36 and the flexible substrate 137. like this A plurality of semiconductor devices can be manufactured by these steps.

In this way, the field effect transistor using the SOI layer 102 bonded to the support substrate 130 After producing the element layer containing the above, the element layer is used to make a flexible and thin semiconductor device. A stand can be made. The SOI layer 102 according to this embodiment is a single crystal half having a constant crystal orientation. Since it is a conductor, a uniform and high-performance field-effect transistor can be obtained. That is, High mobility by suppressing non-uniformity of characteristic values that are important as transistor characteristics such as threshold voltage and mobility It is possible to achieve high performance such as conversion. Furthermore, the base substrate 136 and the SOI layer 1 Since the barrier layer 105 is provided between 02, impurities from the base substrate enter the SOI layer. Since it is possible to prevent intrusion, the characteristics of the transistors formed in the element layer vary. It is possible to suppress sticking.

Further, after forming a field effect transistor using the SOI layer bonded on the support substrate, the support is performed. A flexible and thin semiconductor device is provided by peeling off the element layer having a field effect transistor from the substrate. Make a stand. Therefore, the support substrate can be easily handled in the manufacturing process, and the yield can be increased. Can be enhanced.

(Embodiment 8) 13 and 14 of the semiconductor device using the SOI substrate shown in the above embodiments 1 to 5. Will be described with reference to. Here, as shown in FIGS. 6 and 8, the bonding layer 104 is used for single connection. Shows a form in which a semiconductor device is manufactured using an SOI substrate in which a crystalline semiconductor substrate and a base substrate are bonded. However, as shown in FIGS. 5 and 7, the single crystal semiconductor substrate and the base substrate are contacted without using a bonding layer. A combined SOI substrate can be used. In addition, a support board is placed on the base board side of the SOI board. You can paste it. In addition, the SOI substrate is held by a holding member that holds the SOI substrate. As a result, a semiconductor device with a high yield can be manufactured even with a flexible substrate that is easily bent. Protect The holding member includes a roller, a gripping tool, and the like.

Similar to FIG. 6 (A), as shown in FIG. 13 (A), is it the surface of the single crystal semiconductor substrate 101? Irradiate the ions accelerated by the electric field to include them in a predetermined depth of the single crystal semiconductor substrate, and make the fragile region 1 Form 03. Next, the cap layer 123 and the bonding layer 1 are placed on the surface of the single crystal semiconductor substrate 101. 04 are stacked in order. Next, the single crystal semiconductor substrate 101 is placed at 250 ° C. or higher, preferably 300. Heat treatment above ° C and below 400 ° C, preferably below 350 ° C to further expand the fragile region 103 Make it vulnerable. Here, the cap layer 123 is formed on the surface of the single crystal semiconductor substrate 101. Therefore, while maintaining the flatness of the surface of the single crystal semiconductor substrate 101 and the surface of the bonding layer 104, the fragile area Region 103 can be made even more vulnerable.

As shown in FIG. 13 (B), the release layer 131 is formed on the support substrate 130, and is on the release layer 131. An insulating layer 132 is formed on the surface. Further, the bonding layer 140 is formed on the flexible substrate 141. next, The insulating layer 132 and the bonding layer 140 formed on the flexible substrate 141 are brought into close contact with each other, and both of them are brought into close contact with each other. Join and bond the support substrate 130 and the flexible substrate 141.

Next, as shown in FIG. 13 (C), the flexible substrate 141 and the single crystal semiconductor substrate 101 are formed. The bonded layer 104 was brought into close contact with each other, and the two were bonded to each other to form a flexible substrate 141 and a single crystal semiconductor group. Stick the boards 101 together.

The surface may be activated for good bonding. For example, an atom on the surface to be joined Irradiate a beam or ion beam. A place to use an atomic beam or an ion beam In that case, use an inert gas neutral atom beam such as argon or an inert gas ion beam. Can be In addition, plasma irradiation or radical treatment is performed. Also flexible A substrate having and having an insulating surface, or at least one bonding surface of a single crystal semiconductor substrate, It may be hydrophilized by treatment with oxygen plasma or washing with ozone water. Such a surface treatment By reason, it is easy to join dissimilar materials even at temperatures of 250 ° C or higher and lower than 400 ° C. Will be.

In FIG. 13 (D), the single crystal semiconductor substrate 101 is supported with the fragile region 103 as the separation region. It is peeled (separated) from the substrate 130 and the flexible substrate 141. The joint layer 104 is a support substrate 130. Since it is bonded to the support substrate 130, it has the same crystallinity as the single crystal semiconductor substrate 101. The SOI layer 102 will remain.

Instead of the heat treatment performed before joining the flexible substrate 141 and the single crystal semiconductor substrate 101. After joining the flexible substrate 141 and the single crystal semiconductor substrate 101, the single crystal semiconductor substrate 1 The single crystal semiconductor substrate may be irradiated with a laser beam from 01 to heat the fragile region 103. As a result, the single crystal semiconductor substrate 101 is peeled from the flexible substrate 141 with the fragile region as the separation region. Can be separated (separated).

After this, it is preferable to flatten the surface of the SOI layer 102. As a flattening method, CM P can be used. Alternatively, the surface of the SOI layer 102 is irradiated with a laser beam to form the surface. Can be melted and flattened.

Further, the single crystal semiconductor substrate 101 is peeled off from the support substrate 130 with the fragile region 103 as the separation region. Before separation (separation), a trigger may be created for easy separation (separation). Furthermore When the single crystal semiconductor substrate 101 is peeled (separated) from the support substrate 130, the support substrate 13 is used. Detachable by light or heat on at least one surface of 0 or single crystal semiconductor substrate 101 An adhesive sheet is provided to fix one of the support substrate 130 or the single crystal semiconductor substrate 101, and the other. By peeling off, peeling (separation) becomes easier. At this time, the support board 130 By providing a support member on the other side of the single crystal semiconductor substrate 101, the peeling process becomes easy. ..

Next, through the steps of FIGS. 9 and 10, the element layer including the transistor is used by using the SOI layer 102. Form 135. Next, the flexible substrate 142 is provided on the element layer 135. Flexible substrate 14 The flexible substrate 142 is fixed to the element layer 135 by thermocompression bonding 2 and the element layer 135. Can be made. Also. Flexible substrate 14 using an adhesive (not shown) on the element layer 135 2 can be fixed. (See Figure 14 (A)). As the flexible substrate 142, the above-mentioned Those listed in the representative examples of the booth substrate 100 can be appropriately used.

Next, as shown in FIG. 14 (B), from the support substrate 130 to the flexible substrate 141 and the element layer 135. , And the laminate of the flexible substrate 142 is peeled off by physical means. Alternatively, the release layer 131 and And the flexible substrate 141, 14 from the support substrate 130 by infiltrating the liquid into the interface of the insulating layer 132. 2 and the laminated body of the element layer 135 are peeled off.

Here, the interface between the release layer 131 and the insulating layer 132, the release layer 131, or the support substrate 130. And peeling occurs at any of the interfaces of the peeling layer 131, and the element layer 135 is peeled from the support substrate 130. Can be separated.

In the release layer 131, the element layer 135 and the flexible substrate 142 are peeled from the support substrate 130. Before releasing, a trigger may be created for easy peeling. Furthermore, the element layer 13 When peeling 5 and the flexible substrate 142 from the support substrate 130, the support substrate 130 or the flexible substrate 130 An adhesive sheet that can be peeled off by light or heat is provided on at least one surface of the substrate 142 to support it. By fixing one of the holding substrate 130 or the flexible substrate 142 and peeling off the other, further Easy to peel off. At this time, the support member is on the other side of the support substrate 130 or the flexible substrate 142. The peeling process is facilitated by providing the above.

After that, when the element layer 135 includes a plurality of semiconductor devices, the element layer 135 and the flexible substrate A plurality of semiconductor devices may be cut out by dividing 141 and 142. By such a process Therefore, a plurality of semiconductor devices can be manufactured.

Further, after forming a field effect transistor using the SOI layer bonded on the support substrate, the support is performed. A flexible and thin semiconductor device is manufactured by peeling off an element layer having an electric field effect from a substrate. .. Therefore, it is easy to handle in the manufacturing process, and the yield can be increased. ..

Thus, the field effect transistor using the SOI layer 102 bonded to the flexible substrate 141 Can be produced. The SOI layer 102 according to this embodiment is a single crystal half having a constant crystal orientation. Since it is a conductor, a uniform and high-performance field-effect transistor can be obtained. That is, High mobility by suppressing non-uniformity of characteristic values that are important as transistor characteristics such as threshold voltage and mobility It is possible to achieve high performance such as conversion. Furthermore, the base substrate 100 and the SOI layer 1 Since the barrier layer 105 is provided between 02, impurities from the base substrate enter the SOI layer. Since it is possible to prevent intrusion, the characteristics of the transistors formed in the element layer vary. It is possible to suppress sticking. Also, to manufacture a semiconductor device that is flexible and thin. Can be done.

(Embodiment 9) FIG. 15 shows embodiments 1 to 5 as an example of the semiconductor devices shown in embodiments 6 to 8. The configuration of a microprocessor manufactured using an insulator substrate is shown. This micro processor The sensor 200 is an arithmetic circuit 201 (Arithmetic logic unit. ALU). Also called. ), Arithmetic circuit control unit 202 (ALU Controller), instruction analysis unit 2 03 (Instruction Decoder), Interrupt Control Unit 204 (Inter rupt Controller), Timing Control Unit 205 (Timing Cont) roller), register 206 (Register), register control unit 207 (Reg) ister Controller), Bus Interface 208 (Bus I / F) , Read-only memory 209 (ROM), and memory interface 210 (ROM) I / F).

Instructions entered into the microprocessor 200 via bus interface 208 are life-threatening. After being input to the command analysis unit 203 and decoded, the arithmetic circuit control unit 202 and interrupt control unit It is input to 204, register control unit 207, and timing control unit 205. Arithmetic circuit control unit 202, interrupt control unit 204, register control unit 207, timing control unit 205 Various controls are performed based on the coded instructions. Specifically, the arithmetic circuit control unit 202 is a arithmetic circuit. Generates a signal to control the operation of 201. Further, the interrupt control unit 204 is a microphone. Interrupts from external I / O devices and peripheral circuits during program execution of the processor 200 The request is processed based on its priority and mask status. The register control unit 207 is a cash register. Generates the address of the star 206 and registers 20 depending on the state of the microprocessor 200. Read and write 6 The timing control unit 205 includes an arithmetic circuit 201 and an arithmetic circuit. Operation of control unit 202, instruction analysis unit 203, interrupt control unit 204, and register control unit 207 Generates a signal that controls the timing of. For example, the timing control unit 205 has a reference clock. It has an internal clock generator that generates the internal clock signal CLK2 based on the clock signal CLK1. The clock signal CLK2 is supplied to the above-mentioned various circuits. The micro shown in FIG. 15 The processor 200 is just one example of a simplified configuration, depending on its application. It can have a wide variety of configurations.

Such a microprocessor 200 is in contact with a substrate having a flexible and insulating surface. An integrated circuit is formed by a single crystal semiconductor layer (SOI layer) with a constant combined crystal orientation. Therefore, not only the processing speed can be increased but also the power consumption can be reduced.

(Embodiment 10) Next, as an example of the semiconductor device shown in the sixth to eighth embodiments, data is transmitted and received in a non-contact manner. The SOI group shown in Embodiments 1 to 5 as a semiconductor device having an arithmetic function capable of performing the above. The configuration of the RF CPU obtained from the board will be described with reference to FIG. Figure 16 is wireless A computer that operates by sending and receiving signals to and from an external device via communication (hereinafter, "RFCPU") ") Is shown as an example. RFCPU211 has an analog circuit section 212 and a digital circuit section. Has 213. As the analog circuit unit 212, the resonance circuit 214 having a resonance capacitance, Rectifier circuit 215, constant voltage circuit 216, reset circuit 217, oscillation circuit 218, demodulation circuit 2 It has 19, a modulation circuit 220, and a power management circuit 230. Digital circuit unit 213 is R F interface 221, control register 222, clock controller 223, interface -Face 224 (CPU interface), central processing unit 225 (CPU), It has an underground access memory 226 (RAM) and a read-only memory 227 (ROM). There is.

The operation of RFCPU211 with such a configuration is as follows. Antenna 228 receives An induced electromotive force is generated by the resonant circuit 214 based on the transmitted signal. Induced electromotive force is rectifier circuit 2 After 15, the capacity unit 229 is charged. This capacitance part 229 is a ceramic capacitor or electric It is preferably formed of a capacitor such as an electric double layer capacitor. Capacity part 229 Does not need to be integrally formed with RFCPU211, RFCPU211 as a separate component It suffices if it is attached to a substrate having a constituent insulating surface.

The reset circuit 217 generates a signal to reset and initialize the digital circuit unit 213. For example, a signal that rises after a delay in the rise in power supply voltage is generated as a reset signal. oscillation The circuit 218 rotates the clock signal according to the control signal generated by the constant voltage circuit 216. Change the wave number and duty ratio. Demodulation circuit 219 formed by a low-pass filter is an example. For example, the fluctuation of the amplitude of the received signal of the amplitude modulation (ASK) method is binarized. The modulation circuit 220 Amplitude modulation (ASK) transmission The amplitude of the signal is varied and transmitted. The modulation circuit 220 is a common The amplitude of the communication signal is changed by changing the resonance point of the vibration circuit 214. Clockco The controller 223 depends on the power supply voltage or the current consumption in the central processing unit 225. A control signal for changing the frequency and duty ratio of the lock signal is generated. Power supply The pressure is monitored by the power management circuit 230.

After the signal input from antenna 228 to RFCPU211 is demodulated by demodulation circuit 219 , RF interface 221 decomposes into control commands and data. Control command Is stored in the control register 222. The control command is described in read-only memory 227. Read stored data, write data to random access memory 226, It contains arithmetic instructions to the central processing unit 225. Central processing unit 225 Read-only memory 227, random access memory 2 via interface 224 26, Access control register 222. Interface 224 is a central processing unit Read-only memory 227, random access memory from the address requested by 225 It has a function to generate an access signal to either 226 or control register 222. To.

The calculation method of the central processing unit 225 is the read-only memory 227 and the OS (operation). The system is stored, and the program is read and executed at startup. Can be used. In addition, the arithmetic circuit is configured with a dedicated circuit, and the arithmetic processing is hardware-like. It is also possible to adopt a method of processing. With a method that uses both hardware and software Performs some processing with a dedicated arithmetic circuit, and centrally processes the remaining arithmetic using a program. The method executed by 225 can be applied.

Such RFCPU211 is bonded to a substrate having a flexible and insulating surface. Since the integrated circuit is formed by a single crystal semiconductor layer (SOI layer) with a constant crystal orientation, it is processed. Not only can the speed be increased, but the power consumption can be reduced. It supplies power Even if the capacitance unit 229 is miniaturized, long-term operation can be guaranteed.

(Embodiment 11) Next, as an example of the semiconductor device shown in Embodiments 6 to 8, S shown in Embodiments 1 to 5 The configuration of the display panel obtained by the OI substrate is shown with reference to FIG.

The SOI layer 102 exemplified in embodiments 1 to 5 is a large flexible group for manufacturing a display panel. It can also be joined to a board. FIG. 17 shows a flexible and insulating table as the base substrate 100. The case where the SOI layer 102 is bonded to the large area substrate having a surface is shown. Flexible and insulated table A plurality of display panels are cut out from a large-area substrate having a surface, and the SOI layer 102 is a display panel. It is preferable to join them according to the formation region of flannel 231. Compared to single crystal semiconductor substrates Since a large area substrate having a flexible and insulating surface has a large area, the SOI layer 102 is shown in the figure. It is preferable to divide and arrange as in 17. The display panel 231 has a scanning line drive circuit. There are a region 232, a signal line drive circuit region 233, and a pixel formation region 234, which include these regions. Base substrate 100 (flexible and large with insulating surface) so that the SOI layer 102 is rarely used. It is joined to the area substrate).

FIG. 18 shows an example of the pixels of the display panel in which the pixel transistor is formed by the SOI layer 102. Shown. FIG. 18A shows a plan view of the pixels. In pixels, intersect on the SOI layer Gate wiring 235 and source wiring 236 are formed. In addition, the source distribution is in the SOI layer. The wire 236 and the drain electrode 242 are connected, and the pixel electrode 237 is connected to the drain electrode 242. To do. A cross-sectional view corresponding to the JK cutting line shown in FIG. 18 (A) is shown in FIG. 18 (B). ..

In FIG. 18B, the base substrate 100 has a silicon nitride layer and silicon oxide as a barrier layer 105. The element layers are laminated. The SOI layer 102 is flexible and insulated by the bonding layer 104. It is bonded to the base substrate 100 having a surface. Pixel electrode 237 is provided on the insulating layer 118 Has been done. There is a contact hole that connects the SOI layer 102 and the source wiring 236. A columnar spacer 240 is provided to fill the space. Opposing electrode 239 on the opposing substrate 238 Is formed, and the liquid crystal layer 241 is formed in the gap formed by the columnar spacer 240. To.

In this way, SO is applied to a large-area substrate having a flexible and insulating surface for manufacturing a display panel. It is possible to form an I layer and form a transistor using the SOI layer. SOI Transistors formed by layers have more current drive capability than amorphous silicon transistors. Since all the operating characteristics are excellent, the size of the transistor can be reduced. .. Thereby, the aperture ratio of the pixel portion in the display panel can be improved. Also, the figure 15 A microprocessor such as the one described above can also be formed, so it can be displayed in the display panel. It can also be equipped with an computer function. In addition, data can be input and output without contact. You can also create an display.

(Embodiment 12) Hereinafter, an ion irradiation method, which is one of the features of the present invention, will be considered.

In the present invention, an ion derived from hydrogen (H) (hereinafter referred to as "hydrogen ion species") is a single crystal half. Irradiates the conductor substrate. More specifically, hydrogen gas or a gas containing hydrogen in the composition Used as a raw material, hydrogen plasma is generated, and the hydrogen ion species in the hydrogen plasma are single crystal. Irradiates the semiconductor substrate.

(Ions in hydrogen plasma) In hydrogen plasma as above, H⁺, H₂⁺, H₃⁺There are hydrogen ion species such as To do. Here, regarding the reaction process (generation process, annihilation process) of each hydrogen ion species, the reaction is as follows. Enumerate the expressions. e + H e + H⁺+ e (1) e + H₂ e + H₂⁺+ e (2) e + H₂ e + (H₂)^* e + H + H (3) e + H₂⁺ e + (H₂⁺)^* e + H⁺+ H (4) H₂⁺+ H₂ H₃⁺+ H ····· (Five) H₂⁺+ H₂ H⁺+ H + H₂ (6) e + H₃⁺ e + H⁺+ H + H (7) e + H₃⁺ H₂+ H (8) e + H₃⁺ H + H + H ・・・・・ (9)

FIG. 19 shows an energy diagram schematically showing a part of the above reaction. In addition, it should be noted. The energy diagram shown in Fig. 19 is only a schematic diagram, and shows the relationship of energy related to the reaction. Please note that it is not strictly defined.

(H₃⁺Generation process) As mentioned above, H₃⁺Is mainly produced by the reaction process represented by the reaction formula (5). Is done. On the other hand, as a reaction that competes with the reaction formula (5), the reaction overreaction represented by the reaction formula (6) There is a degree. H₃⁺In order for the reaction formula to increase, at least the reaction of the reaction formula (5) must be the reaction formula. It needs to occur more than the reaction of (6) (Note that H₃⁺Other reactions that reduce Because there are 7), (8), and (9), the reaction of (5) is more than the reaction of (6). Not necessarily H₃⁺Does not always increase. ). On the contrary, the reaction of the reaction formula (5) is a reaction. If less than the reaction of equation (6), H in plasma₃⁺Percentage decreases.

The amount of increase in the product on the right side (rightmost side) in the above reaction formula is shown by the left side (leftmost side) of the reaction formula. It depends on the density of raw materials and the rate coefficient related to the reaction. Where H₂⁺Exercise d When the energy is less than about 11 eV, the reaction of (5) becomes the main reaction (that is, the reaction formula). The rate coefficient related to (5) is sufficiently larger than the rate coefficient related to reaction equation (6)), H₂⁺When the kinetic energy of is greater than about 11 eV, the reaction of (6) is the main one. Has been confirmed experimentally.

Charged particles receive kinetic energy from an electric field. The kinetic energy depends on the electric field. Corresponds to the amount of decrease in potential energy. For example, one charged particle with another The kinetic energy obtained before the collision is the potential energy of the potential difference passed during that time. Equal to energy. That is, in an electric field, it travels a long distance without colliding with other particles. In a movable situation, the kinetic energy of the charged particle (average) compared to a non-movable situation. Tends to grow. Such an increasing tendency of kinetic energy related to charged particles is a grain. It can occur in situations where the mean free path of the offspring is high, i.e., where the pressure is low.

Moreover, even if the mean free path is small, a large amount of kinetic energy can be obtained during that period. Under the circumstances, the kinetic energy of the charged particles increases. That is, the mean free path is small At the very least, if the potential difference is large, the kinetic energy of the charged particles will increase. Eh.

This is H₂⁺Try to apply to. Existence of electric field as in the chamber related to plasma generation Assuming that, in the situation where the pressure in the chamber is low, H₂⁺Kinetic energy is large In the situation where the pressure in the chamber is high, H₂⁺Kinetic energy becomes smaller. Tsuma Therefore, when the pressure in the chamber is low, the reaction of (6) is the main reaction, so H₃⁺Decreases In the situation where the pressure in the chamber is high, the reaction of (5) is the main reaction, so H₃⁺Tends to increase. Also, a situation where the electric field (or electric field) in the plasma generation region is strong. That is, in a situation where the potential difference between two points is large, H₂⁺Kinetic energy increases , In the opposite situation, H₂⁺Kinetic energy becomes smaller. In other words, in a situation where the electric field is strong H because the reaction of (6) is the main₃⁺Tends to decrease, and in situations where the electric field is weak (5) Because the reaction of H is the main₃⁺Tends to increase.

(Difference depending on ion source) Here, the proportion of ionic species (especially H)₃⁺An example is shown in which the ratio of) is different. Figure 20 is 100% Hydrogen gas (ion source pressure: 4.7 × 10^-2Mass spectrometric analysis of ions generated from Pa) It is a graph which shows the fruit. In the above mass spectrometry, the ions extracted from the ion source are measured. I went by doing. The horizontal axis is the mass of ions. Pis with masses 1, 2 and 3 in the spectrum Each is H⁺, H₂⁺, H₃⁺Corresponds to. The vertical axis is the intensity of the spectrum , Corresponds to the number of ions. In FIG. 20, the number of ions having different masses and the number of ions having mass 3 are shown. It is expressed as a relative ratio when it is set to 100. From FIG. 20, a. On percentage is H⁺: H₂⁺: H₃⁺It can be seen that it is about = 1: 1: 8. In addition, this Ions of such a proportion are the plasma source part (ion source) that generates plasma and the plastic. Ion doping device consisting of an extraction electrode for drawing an ion beam from the Zuma It can also be obtained by placing.

FIG. 21 shows a case where an ion source different from that in FIG. 20 is used, and the pressure of the ion source is high. So 3x10^-3At the time of Pa, PH₃It is a graph showing the mass spectrometry result of the ion generated from To. The above mass spectrometry results focus on hydrogen ion species. In addition, mass spectrometry is performed by Io. This was done by measuring the ions extracted from the source. Similar to Fig. 20, the horizontal axis is ions The peaks of mass 1, 2, and 3 are H, respectively.⁺, H₂⁺, H₃⁺Corresponds to. The vertical axis is the intensity of the spectrum corresponding to the number of ions. From Fig. 21, Io in the plasma The ratio of⁺: H₂⁺: H₃⁺It turns out that it is about = 37: 56: 7. In addition, Fig. 2 1 is the source gas PH₃As for the data in the case of, 100% hydrogen gas is used as the source gas. Even when used, the proportion of hydrogen ion species is about the same.

In the case of the ion source for which the data shown in Fig. 21 was obtained, H⁺, H₂⁺And H₃⁺Of which, H₃⁺But Only about 7% is generated. On the other hand, in the case of the ion source for which the data shown in Fig. 20 was obtained, H₃⁺It is possible to set the ratio of 50% or more (about 80% under the above conditions). is this, It is considered to be caused by the pressure and electric field in the chamber revealed in the above discussion. To.

(H₃⁺Irradiation mechanism) Generate a plasma containing multiple ion species as shown in Fig. 20, and divide the generated ion species by mass. When irradiating the single crystal semiconductor substrate without separating it, H is applied to the surface of the single crystal semiconductor substrate.⁺, H₂⁺, H₃⁺Each ion of is irradiated. From ion irradiation to iontophoresis region formation In order to reproduce canism, consider the following five types of models. 1. The ion species to be irradiated is H⁺And even after irradiation, H⁺If (H) 2. The ion species to be irradiated is H₂⁺And even after irradiation, H₂⁺(H₂) Remains 3. The ion species to be irradiated is H₂⁺So, after irradiation, 2 H (H)⁺) 4. The ion species to be irradiated is H₃⁺And even after irradiation, H₃⁺(H₃) Remains 5. The ion species to be irradiated is H₃⁺So, after irradiation, 3 H (H)⁺)

(Comparison between simulation results and measured values) Simulation when irradiating a Si substrate with hydrogen ion species based on the above model Was done. As software for simulation, SRIM (the Stopp) ing and Range of Ions in Matter: In Monte Carlo TRIM (the Transp), simulation software for iontophoresis process An improved version of ort of Ions in Matter)) is used. In addition, of calculation Due to the relationship, model 2 is H₂⁺The mass of H is doubled⁺It was calculated by replacing it with. Also in model 4 Is H₃⁺The mass of 3 times H⁺It was calculated by replacing it with. In addition, in Model 3, H₂⁺Exercise Energy 1/2 H⁺Replaced with, H in model 5₃⁺The kinetic energy 1/3 of H⁺To I replaced it and calculated.

Although SRIM is software for amorphous structures, it has high energy and high energy. SRIM can be applied when irradiating hydrogen ion species under the condition of dose. Hydrogen Io This is because the crystal structure of the Si substrate changes to a non-single crystal structure due to the collision between the species and the Si atom. ..

Figure 22 shows the case of irradiating hydrogen ion species using models 1 to 5 (10 in H conversion). The calculation result (when irradiating 10,000 pieces) is shown. In addition, the water in the Si substrate irradiated with the hydrogen ion species shown in FIG. 20 Elementary concentration (SIMS (Secondary Ion Mass Spectroscopy) ) Data) is also shown. About the result of calculation performed using model 1 to model 5 Is represented by the number of hydrogen atoms on the vertical axis (right axis), and for SIMS data, the vertical axis is hydrogen. It is represented by the concentration of atoms (left axis). The horizontal axis is the depth from the Si substrate surface. Measured value When comparing the SIMS data with the calculation results, model 2 and model 4 are clearly SIM It is off the peak of S data, and some SIMS data corresponds to model 3. I can't even see it. From this, the contribution of models 2 to 4 is relatively small. I understand. While the kinetic energy of ions is in the keV range, the binding energy of HH Considering that is only a few eV, the contribution of model 2 and model 4 is small in S. Most H due to collision with element i₂⁺And H₃⁺But H⁺I think it is because it is separated into H and H Is done.

Based on the above, models 2 to 4 will not be considered below. Figures 23 to 25 When irradiating hydrogen ion species using model 1 and model 5 (irradiation of 100,000 in H conversion) The calculation result of hour) is shown. In addition, the hydrogen concentration in the Si substrate irradiated with the hydrogen ion species shown in FIG. 20 ( SIMS data) and the above simulation results are fitted to SIMS data The set (hereinafter referred to as the fitting function) is also shown. Here, FIG. 23 shows the acceleration voltage. Is 80 kV, FIG. 24 shows the case where the acceleration voltage is 60 kV, and FIG. 25 shows the case where The case where the acceleration voltage is 40 kV is shown. In addition, it is performed using model 1 and model 5. Regarding the result of the calculation, the vertical axis is represented by the number of hydrogen atoms (right axis), SIMS data and For the fitting function, the vertical axis is represented by the concentration of hydrogen atoms (left axis). The horizontal axis is Depth from the Si substrate surface.

The fitting function should be calculated by the following formula in consideration of model 1 and model 5. And said. In the calculation formula, X and Y are parameters related to fitting, and V is the volume. is there. [Fitting function] = X / V × [Data of model 1] + Y / V × [Data of model 5]

Percentage of ion species actually irradiated (H⁺: H₂⁺: H₃⁺= 1: 1: 8) H₂⁺Contribution (ie, Model 3) should also be considered, but for the following reasons: Therefore, I excluded it here. -Hydrogen introduced by the irradiation process shown in model 3 is compared with the irradiation process of model 5. Since it is small, there is no big effect even if it is excluded (even in SIMS data, Does not appear). Model 3 whose peak position is close to that of model 5 is the channeling (crystal) that occurs in model 5. There is a high possibility that it will be hidden due to the movement of elements due to the lattice structure of. That is, the model It is difficult to estimate the fitting parameters of 3. This is this simulation Is premised on amorphous Si and does not consider the effect of crystallinity. Is.

FIG. 26 summarizes the above fitting parameters. At any acceleration voltage , The ratio of the number of H to be introduced is about [Model 1]: [Model 5] = 1: 42 ~ 1:45 (Mo) Assuming that the number of Hs in Dell 1 is 1, the number of Hs in model 5 is about 42 or more and 45 or less. ), And the ratio of the number of ion species irradiated is [H⁺(Model 1)]: [H₃⁺(Model 5 )] = 1: 14 ~ 1: 15 (H in model 1)⁺If the number of is 1, then model 5 H in₃⁺The number of is 14 or more and 15 or less). Not considering Model 3 or not Considering that the calculation is based on the assumption that it is crystalline Si, the ratio of ion species related to actual irradiation ( H⁺: H₂⁺: H₃⁺It can be said that a value close to (= 1: 1: 8) is obtained.

(H₃⁺Effect of using) H as shown in Figure 20₃⁺By irradiating the substrate with hydrogen ion species with an increased proportion of H₃⁺You can enjoy multiple benefits due to. For example, H₃⁺Is H⁺And H etc. Mainly H because it is separated and introduced into the substrate.⁺And H₂⁺Ion compared to the case of irradiating It is possible to improve the introduction efficiency of. This will improve the productivity of the SOI substrate. Can be done. Also, similarly, H₃⁺H after separation⁺And H have less kinetic energy Since there is a tendency, it is suitable for manufacturing thin semiconductor layers.

In this specification, H₃⁺Hydrogen ion as shown in Fig. 20 in order to irradiate efficiently The method of using an ion doping device capable of irradiating the species is described. Ion Do Since the ping device is inexpensive and excellent in large area processing, such an ion doping device is used. Using H₃⁺By irradiating with, the semiconductor characteristics are improved, the area is increased, the cost is reduced, and the productivity is improved. It is possible to obtain a remarkable effect such as. On the other hand, H₃⁺If you think about the irradiation of , It is not necessary to interpret only using an ion doping device.