Semiconductor device, display device, and electronic device

The present invention relates to a semiconductor device provided with a function of controlling a current supplied to a load by a transistor, and in particular, a semiconductor device including a pixel formed of a current-driven light emitting element whose brightness changes depending on the current and a signal line drive circuit thereof. Regarding.

In recent years, so-called self-luminous display devices in which pixels are formed of light emitting elements such as light emitting diodes (LEDs) have attracted attention. Organic light emitting diodes (OLED (Organic Light Emitting Diode), organic EL elements, Electro Luminescence (EL) elements, etc.) are attracting attention as light emitting elements used in such self-luminous display devices. It has come to be used for organic EL displays and the like.

Since a light emitting element such as an OLED is a self-luminous type, it has advantages such as higher pixel visibility than a liquid crystal display, no need for a backlight, and a fast response speed. The brightness of the light emitting element is controlled by the value of the current flowing through the light emitting element.

In a display device using such a self-luminous light emitting element, a simple matrix method and an active matrix method are known as its driving method. The former has a simple structure, but has problems such as difficulty in realizing a large and high-brightness display. In recent years, it is an active matrix method in which the current flowing through a light emitting element is controlled by a thin film transistor (TFT) provided inside a pixel circuit. Development is being actively carried out.

In the case of such an active matrix type display device, there is a problem that the current flowing through the light emitting element changes due to the variation in the current characteristics of the drive TFT, and the brightness varies.

That is, in the case of such an active matrix type display device, a drive TFT that drives a current flowing through the light emitting element is used in the pixel circuit, and the current flowing through the light emitting element is caused by variations in the characteristics of these drive TFTs. There was a problem that it changed and the brightness varied. Therefore, even if the characteristics of the drive TFT in the pixel circuit vary, the current flowing through the light emitting element does not change, and various circuits have been proposed for suppressing the variation in brightness.<patcit num="1"><text>Special Table 2002-517806 Gazette</text></patcit><patcit num="2"><text>International Publication No. 01/06484 Pamphlet</text></patcit><patcit num="3"><text>Special Table 2002-514320</text></patcit><patcit num="4"><text>International Publication No. 02/39420 Pamphlet</text></patcit>

Patent Documents 1 to 4 all disclose the configuration of an active matrix type display device, and Patent Documents 1 to 3 describe a current flowing through a light emitting element due to variations in the characteristics of a drive TFT arranged in a pixel circuit. A circuit configuration that does not change is disclosed. This configuration is called a current writing type pixel, a current input type pixel, or the like. Further, Patent Document 4 discloses a circuit configuration for suppressing a change in signal current due to a variation in TFT in a source driver circuit.

FIG. 31 shows a first configuration example of the conventional active matrix type display device disclosed in Patent Document 1. The pixel of FIG. 31 has a source signal line 3101, first to third gate signal lines 3102 to 3104, a current supply line 3105, TFT 3106 to 3109, a holding capacity 3110, an EL element 3111, and a signal current input current source 3112. ..

The gate electrode of TFT3106 is connected to the first gate signal line 3102, the first electrode is connected to the source signal line 3101, and the second electrode is the first electrode of TFT3107, the first electrode of TFT3108, And is connected to the first electrode of TFT3109. The gate electrode of TFT3107 is connected to the second gate signal line 3103, and the second electrode is connected to the gate electrode of TFT3108. The second electrode of the TFT 3108 is connected to the current supply line 3105. The gate electrode of the TFT 3109 is connected to the third gate signal line 3104, and the second electrode is connected to the anode of the EL element 3111. The holding capacity 3110 is connected between the gate electrode and the input electrode of the TFT 3108 to hold the gate-source voltage of the TFT 3108. Predetermined potentials are input to the cathodes of the current supply line 3105 and the EL element 3111, respectively, and have potential differences from each other.

The operation from writing the signal current to emitting light will be described with reference to FIG. In the figure, the drawing numbers indicating each part are based on FIG. 31. FIGS. 32 (A) to 32 (C) schematically show the current flow. FIG. 32 (D) shows the relationship of the currents flowing through each path when the signal current is written, and FIG. 32 (E) shows the voltage accumulated in the holding capacity 3110 when the signal current is written, that is, TFT3108. The voltage between the gate and source of is shown.

First, a pulse is input to the first gate signal line 3102 and the second gate signal line 3103, and the TFTs 3106 and 3107 are turned on. At this time, the current flowing through the source signal line, that is, the signal current is defined as Idata.

Since the current Idata flows through the source signal line, as shown in FIG. 32 (A), the current path is divided into I1 and I2 in the pixel. These relationships are shown in Fig. 32 (D). Needless to say, Idata = I1 + I2.

At the moment when the TFT3106 is turned on, the electric charge is not yet held in the holding capacity 3110, so the TFT3108 is turned off. Therefore, I2 = 0 and Idata = I1. That is, during this period, only the current due to the accumulation of electric charges in the holding capacity 3110 is flowing.

After that, charges are gradually accumulated in the holding capacity 3110, and a potential difference begins to occur between the two electrodes (Fig. 32 (E)). When the potential difference between the two electrodes reaches Vth (Point A in Fig. 32 (E)), TFT3108 turns ON and I2 occurs. As mentioned earlier, since Idata = I1 + I2, I1 gradually decreases, but current is still flowing, and charges are accumulated in the holding capacity.

In the holding capacity 3110, charge accumulation continues until the potential difference between the two electrodes, that is, the voltage between the gate and source of the TFT 3108, becomes a desired voltage, that is, a voltage (VGS) that allows the TFT 3108 to carry the current Idata. When the charge accumulation is completed (Fig. 32 (E) point B), the current I1 stops flowing, and the current corresponding to the VGS at that time flows in the TFT 3108, and Idata = I2 (Fig. 32 (B)). .. In this way, the steady state is reached. This completes the signal writing operation. Finally, the selection of the first gate signal line 3102 and the second gate signal line 3103 is completed, and the TFTs 3106 and 3107 are turned off.

Then, the light emitting operation is started. A pulse is input to the third gate signal line 3104, and TFT 3109 turns ON. Since the VGS written earlier is held in the holding capacity 3110, the TFT 3108 is ON, and the current Idata flows from the current supply line 3105 to the EL element 3111. As a result, the EL element 3111 emits light. At this time, if the TFT3108 is operated in the saturation region, Idata can flow unchanged even if the voltage between the drain and the source of the TFT3108 changes.

The operation of outputting the set current in this way is referred to as an output operation. As an advantage of the current writing type pixel shown above as an example, even if the characteristics of the TFT 3108 vary, the holding capacity 3110 holds the gate-source voltage required for passing the current Idata. Therefore, it is possible to accurately supply a desired current to the EL element, and thus it is possible to suppress the variation in brightness caused by the variation in the characteristics of the TFT.

The above example relates to a technique for correcting a change in current due to a variation in the drive TFT in the pixel circuit, but the same problem occurs in the source driver circuit. Patent Document 4 discloses a circuit configuration for preventing a change in signal current due to a variation in manufacturing of a TFT in a source driver circuit.

<p>In this way, the current input type circuit uses the current as a signal. Then, when the steady state is reached, the signal writing is completed. Here, noise may occur in the wiring that supplies the current. In that case, the potential at the place where the noise is placed fluctuates greatly. Since the signal is input using a current source, if the potential fluctuates greatly due to noise or the like, it will take a lot of time to return to the original potential, so it is in a steady state. It will take a lot of time to become.</p>

<p>When operating normally as usual, it can be expected that the wiring that supplies the current has a potential in a certain range. Therefore, when the potential exceeds the range due to noise or the like, the current is supplied from a place other than the current source that supplies the signal so that the normal range can be quickly returned. As a result, it is possible to prevent the signal writing time from becoming long.</p><p>The first configuration of the present invention is Transistors, current sources, The wiring that connects the drain terminal of the transistor and the current source, the capacitive element that holds the gate potential of the transistor, and The semiconductor device is characterized by having a means for setting the potential of the wiring to a potential within the set range when the potential of the wiring exceeds a set range.</p><p>The second configuration of the present invention is Transistors, current sources, The wiring that connects the source terminal of the transistor and the current source, the capacitive element that holds the voltage between the gate and source of the transistor, and The semiconductor device is characterized by having a means for setting the potential of the wiring to a potential within the set range when the potential of the wiring exceeds a set range.</p><p>The third configuration of the present invention is Transistor and With the current source The wiring connected between the drain terminal of the transistor and one terminal of the current source, A capacitive element in which one terminal is connected to the gate terminal of the transistor and the other terminal is connected to a power line equipotential with the source terminal of the transistor. The switch connected between the gate terminal and the drain terminal of the transistor, A first rectifying element with one terminal connected to the wiring and the other terminal connected to the first power line, A second rectifying element with one terminal connected to the wiring and the other terminal connected to the second power line, Have, A semiconductor characterized in that when a wiring potential exceeds a set range, a current flows through a first rectifying element or a second rectifying element until the wiring potential reaches a potential within the set range. It is a device.</p><p>The fourth configuration of the present invention is In the third configuration, the semiconductor device is characterized in that the potential of the first power supply line is higher than the potential of the second power supply line.</p><p>The fifth configuration of the present invention is In the fourth configuration, the set range is a semiconductor device characterized in that it is a range from the potential of the second power supply line to the potential of the first power supply line.</p><p>The sixth configuration of the present invention is It has a transistor, a current source, wiring, a capacitance element, a switch, a first rectifying element, and a second rectifying element. The current source and the drain terminal of the transistor are connected by wiring, One electrode of the capacitive element is connected to the gate terminal of the transistor, The gate terminal and drain terminal of the transistor are connected via a switch, In the first rectifying element, one terminal is connected to the first power line and the other terminal is connected to the wiring. In the second rectifying element, one terminal is connected to the second power line and the other terminal is connected to the wiring. The forward current of the first rectifying element is the direction in which it flows from the first power line to the wiring. The forward current of the second rectifying element is a semiconductor device characterized in that it flows from the wiring to the second power supply line.</p><p>The seventh configuration of the present invention is It has an N-channel transistor, a current source, wiring, a capacitance element, a switch, and a rectifying element. The current source and the drain terminal of the N-channel transistor are connected by wiring. One electrode of the capacitive element is connected to the gate terminal of the transistor, The gate terminal and drain terminal of the transistor are connected via a switch, In the rectifying element, one terminal is connected to the power line and the other terminal is connected to the wiring. The forward current of the rectifying element is a semiconductor device characterized in that it flows from the power supply line to the wiring.</p><p>The eighth configuration of the present invention is It has a P-channel transistor, a current source, wiring, a capacitance element, a switch, and a rectifying element. The current source and the drain terminal of the P-channel transistor are connected by wiring. One electrode of the capacitive element is connected to the gate terminal of the transistor, The gate terminal and drain terminal of the transistor are connected via a switch, In the rectifying element, one terminal is connected to the power line and the other terminal is connected to the wiring. The forward current of the rectifying element is a semiconductor device characterized in that it flows from the wiring to the power supply line.</p><p>The ninth configuration of the present invention is In the above configuration, the semiconductor device is characterized in that the rectifying element is a diode-connected transistor.</p><p>The tenth configuration of the present invention is It has pixels arranged in a matrix corresponding to a first wire for selecting pixels provided in the row direction and a second wire for inputting a signal current provided in the column direction. A display device characterized in that a rectifying element is connected to each of the second wirings.</p><p>The eleventh configuration of the present invention is It has pixels arranged in a matrix corresponding to a first wire for selecting pixels provided in the row direction and a second wire for inputting a signal current provided in the column direction. Each of the second wires is connected to a rectifying element through which a current flows so that when the second wire exceeds a certain set range, the potential of the second wire is returned to the potential within the set range. It is a display device characterized by being</p><p>The twelfth configuration of the present invention is It has pixels arranged in a matrix corresponding to a first wire provided in the row direction to select pixels and a second wire provided in the column direction to which a signal current is input. The pixel has a current source circuit in which the signal current is written, Each of the second wires is connected to a rectifying element through which a current flows so that when the second wire exceeds a certain set range, the potential of the second wire is returned to the potential within the set range. It is a display device characterized by being</p><p>The thirteenth configuration of the present invention is It has pixels arranged in a matrix corresponding to the gate line and the source signal line, and the signal current is input to the source signal line. A display device characterized in that a rectifying element is connected to each of the source signal lines.</p><p>The fourteenth configuration of the present invention is It has pixels arranged in a matrix corresponding to the gate line and the source signal line, and the signal current is input to the source signal line. Each source signal line is connected to a rectifying element through which a current flows so that when the source signal line exceeds a certain set range, the potential of the source signal line returns to the potential within the set range. It is a display device characterized by.</p><p>The fifteenth configuration of the present invention is It has pixels arranged in a matrix corresponding to the gate line and the source signal line, and the signal current is input to the source signal line. The pixel has a current source circuit in which the signal current is written, Each source signal line is connected to a rectifying element through which a current flows so that when the source signal line exceeds a certain set range, the potential of the source signal line returns to the potential within the set range. It is a display device characterized by.</p><p>The sixteenth configuration of the present invention is Pixels arranged in a matrix corresponding to the gate line and the source signal line, With a signal line drive circuit, The signal line drive circuit includes a current source, a current source circuit, and wiring connecting the current source and the current source circuit. The display device is characterized in that a rectifying element is connected to the wiring.</p><p>The seventeenth configuration of the present invention is Pixels arranged in a matrix corresponding to the gate line and the source signal line, With a signal line drive circuit, The signal line drive circuit includes a current source, a current source circuit, and wiring connecting the current source and the current source circuit. Current source circuits are provided corresponding to each of the source signal lines. The wiring is a display device characterized in that a rectifying element is provided corresponding to the current source circuit.</p><p>The eighteenth configuration of the present invention is In the above configuration, the rectifying element is a display device characterized by being a diode-connected transistor.</p><p>The nineteenth configuration of the present invention is It is an electronic device characterized by having a display device having the above configuration in a display unit.</p><p>In the present invention, being connected is synonymous with being electrically connected. Therefore, another element, switch, or the like may be arranged between them.</p><p>Further, the types of transistors applicable in the present invention are not limited. For example, it may be a thin film transistor (TFT). Among the TFTs, the semiconductor layer may be amorphous, polycrystalline, or single crystal. As other transistors, a transistor formed on a single crystal substrate, a transistor formed on an SOI substrate, a transistor formed on a glass substrate, a transistor formed on a plastic substrate, or the like may be used. It may be a transistor formed on any substrate. In addition, a transistor formed of an organic substance or carbon nanotube may be used. Further, it may be a MOS type transistor or a bipolar type transistor.</p><p>Further, in the present invention, the semiconductor device means a device including a circuit having a transistor, a capacitive element, or the like.</p>

<p>According to the present invention, in a wiring through which a signal current flows when a signal is written to a current source circuit, the potential can be quickly returned to the normal range even if the potential exceeds the potential range during normal operation. Therefore, the signal writing time can be shortened.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention can be carried out in many different modes, and the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the interpretation is not limited to the description of the present embodiment.

The present invention can be applied not only to pixels having a light emitting element such as an EL element, but also to various analog circuits having a current source. Therefore, first, in the present embodiment, the basic principle of the present invention will be described.

First, FIG. 1 shows the configuration of a current source circuit based on the basic principle of the present invention. One of the wiring 110 is connected to the wiring 105 via the basic current source 101. The other end of the wiring 110 is connected to the drain terminal of the transistor 102, and further to one terminal of the gate terminal of the transistor 102 and the capacitance element 103 via the switch 104. The other terminal of the capacitive element is connected to the wiring 107, and the source terminal of the transistor 102 is connected to the wiring 106. Therefore, the capacitive element 103 can hold the potential of the gate terminal of the transistor 102. The wiring 110 is connected to the wiring 112 via the rectifying element 108 and the wiring 113 via the rectifying element 109 at the point 111. The potential of the wiring 112 to which one terminal of the rectifying element 108 is connected is equal to that of the wirings 106 and 107. The forward direction of the rectifying element 108 is the direction from the wiring 112 to the point 111. The potential of the wiring 113 to which one terminal of the rectifying element 109 is connected is equal to the potential of the wiring 105. The forward direction of the rectifying element 109 is from the point 111 to the wiring 113. That is, in the normal state, 108 and 109 are in a non-conducting state.

In the present embodiment, the potentials of the wirings 106, 107 and 112 are GND, but these wirings may be the same wiring or different, and the potential is not GND. It does not matter, and each potential may be different. That is, the potential may be lower than the wirings 105 and 113. Further, depending on the characteristics of the rectifying element 108, it may be preferable that the potential of the wiring 112 is slightly higher than the potential of the wirings 106 and 107, but conversely, the potential may be slightly lower. That is, the potential may be such that the rectifying element 108 is turned on when the potential of the point 111 deviates from the normal range. Further, although the potentials of the wirings 105 and 113 are VDD, these wirings may be the same wiring or different, and the potentials may not be VDD, and the potentials are different from each other. It doesn't matter. Further, depending on the characteristics of the rectifying element 109, it may be preferable that the potential of the wiring 113 is slightly lower than the potential of the wiring 105, but conversely, the potential may be slightly higher. That is, the potential may be such that the rectifying element 109 is turned on when the potential of the point 111 deviates from the normal range. Both the rectifying element 109 and the rectifying element 108 are connected at a point 111, but the present invention is not limited to this. They may be connected at different points. It suffices if it is connected to the wiring 110.

The operating principle of the current source circuit shown in FIG. 1 will be described. First, the state when the current source circuit is operating in the range where the potential of the wiring 110 is normal will be described with reference to FIG. When writing a signal to the current source circuit, switch 104 is turned on as shown in FIG. Then, since the electric charge is not accumulated in the capacitive element 103 immediately after it is turned on, the gate-source voltage of the transistor 102 is 0, and the transistor 102 is in the off state. Therefore, the current from the basic current source 101 flows only through the capacitive element 103 (see FIG. 2 (a)). Then, a current flows through the capacitance element 103, and the gate potential of the transistor 102 is accumulated in the capacitance element 103. When the difference between the potential of the wiring 106 to which the source terminal of the transistor 102 is connected and the gate potential of the transistor 102 stored in the capacitive element 103 reaches the threshold voltage, the transistor 102 is turned on. In other words, current begins to flow through the transistor 102 (see Fig. 2 (b)). Eventually, no current flows through the capacitive element 103, and current flows only through the transistor 102 (see FIG. 2 (c)). That is, it becomes a steady state. The gate potential of the transistor 102 stored in the capacitive element 103 at this time becomes a magnitude required for the signal current from the basic current source to flow. In this way, the writing of the signal current is completed.

In this way, when the potential of the wiring 110 is operating in the normal range, no current flows through the rectifying elements 108 and 109.

Here, noise may be added to the wiring 110. This noise is caused, for example, by a parasitic capacitance (cross capacitance) formed at a portion where the wiring 110 intersects with another wiring. Due to this noise, the potential of the wiring 110 becomes higher or lower than the potential under normal operation. Then, the potential of the wiring 110 does not easily return to the normal value, the time until the writing is completed is delayed, and the gate potential of the transistor 102 for passing a desired signal current cannot be obtained. This is because after the set write time has passed, the next operation is started before the signal writing is completed. For example, when writing to a pixel, writing to the next pixel is started. In this case, since the pixel cannot write the desired signal, the desired display cannot be performed. In this way, noise on the wiring causes malfunction. This becomes a more pronounced problem, especially when the wiring potential is no longer in the normal range.

Here, the operation of the rectifying elements 108 and 109 when noise is applied to the wiring 110 will be described with reference to FIG. When noise is applied to the wiring 110 and the potential of the point 111 becomes lower than that of the wiring 112, a current flows from the wiring 112 to the point 111 as shown in FIG. 3A, and the potential of the point 111 is equal to the potential of the wiring 112. Supply current until This is due to the action of the rectifying element 108 becoming conductive. When noise is applied to the wiring 110 and the potential of the point 111 becomes higher than the potential of the wiring 113, a current flows from the point 111 to the wiring 113 as shown in FIG. 3 (b), and the potential of the point 111 becomes the potential of the wiring 113. Continue to emit current until equal to. This is due to the action of the rectifying element 109 becoming conductive.

In this way, when the potential of the wiring 110 in normal operation is exceeded due to noise, the potential can be quickly returned to the normal range.

In addition, static electricity can be mentioned as noise on the wiring 110. Even if the potential of the wiring 110 becomes an abnormal value due to static electricity, it can be returned to the normal range. In addition, it is possible to prevent the transistor from being destroyed by static electricity.

As the rectifying element, for example, a diode-connected transistor can be used. Therefore, FIG. 13 (a) shows a configuration in which a diode-connected N-channel transistor is applied as a rectifying element of the current source circuit shown in FIG. 1, and FIG. 13 (b) shows a configuration in which a P-channel transistor is applied. ..

The transistor 1301 and the transistor 1302 shown in FIG. 13A correspond to the rectifying element 108 and the rectifying element 109 of FIG. 1, respectively. The gate terminal of the transistor 1301 is connected to the terminal connected to the wiring 112. In other words, when the current source circuit is operating in the range of normal potential at point 111, the gate terminal of transistor 1301 is short-circuited with the source terminal because the potential of wiring 112 is lower than that of point 111. Become. Therefore, the transistor 1301 is turned off and no current flows. However, when the potential of the point 111 becomes lower than the potential of the wiring 112, the gate terminal of the transistor 1301 is connected to the drain terminal, a potential difference occurs between the gate and source of the transistor 1301, and the transistor 1301 is turned on. , Current will flow.

Further, the gate terminal of the transistor 1302 is connected to the terminal connected to the wiring 110. That is, when the current source circuit is operating in the range of the normal potential at the point 111, the gate terminal of the transistor 1302 is short-circuited with the source terminal because the potential of the wiring 113 is higher than that of the point 111. become. Therefore, the transistor 1302 is turned off and no current flows. However, when the potential of point 111 becomes higher than the potential of wiring 113, the gate terminal of transistor 1302 is connected to the drain terminal, a potential difference occurs between the gate and source of transistor 1302, transistor 1302 turns on, and the current flows. It will flow.

Further, as shown in FIG. 13B, P-channel type transistors 1303 and transistors 1304 can be applied to the rectifying elements 108 and 109 of FIG. The gate terminal of transistor 1303 is short-circuited with the terminal connected to wiring 110. In other words, when the current source circuit is operating in the range of normal potential at point 111, the gate terminal of transistor 1303 is short-circuited with the source terminal because the potential of wiring 112 is lower than that of point 111. Become. Therefore, the transistor 1303 is turned off and no current flows. However, when the potential of the point 111 becomes lower than the potential of the wiring 112, the gate terminal of the transistor 1303 is connected to the drain terminal, a potential difference occurs between the gate and source of the transistor 1303, the transistor 1303 is turned on, and the current is turned on. It will flow.

Further, the gate terminal of the transistor 1304 is short-circuited with the terminal connected to the wiring 113. That is, when the current source circuit is operating in the range of the normal potential at the point 111, the gate terminal of the transistor 1304 is short-circuited with the source terminal because the potential of the wiring 113 is higher than that of the point 111. become. Therefore, the transistor 1304 is turned off and no current flows. However, when the potential of point 111 becomes higher than the potential of wiring 113, the gate terminal of transistor 1304 is connected to the drain terminal, a potential difference occurs between the gate source of transistor 1304, transistor 1304 is turned on, and the current is turned on. It will flow.

In some cases, the combination of these transistors replaces the transistor 1302 with the transistor 1304 shown in FIG. 13 (b) in the configuration shown in FIG. 13 (a), or the transistor 1301 is shown in the configuration shown in FIG. 13 (a). It may be replaced with the transistor 1303 shown in 13 (b). Further, a rectifying element may be formed by appropriately combining these and using a plurality of them. For example, as shown in FIG. 33 (a), a diode-connected N-channel transistor and a diode-connected P-channel transistor may be connected in parallel, or as shown in FIG. 33 (b), the N-channel transistor and the N-channel transistor may be connected. A diode-connected P-channel transistor may be connected in series.

The switch shown in FIG. 1 or the like may be an electric switch or a mechanical switch. Anything that can control the current flow will do. It may be a transistor, a diode, or a logic circuit combining them. Therefore, when a transistor is used as a switch, the polarity (conductive type) of the transistor is not particularly limited because the transistor operates as a mere switch. However, when it is desirable that the off-current is small, it is desirable to use a transistor having the polarity with the smaller off-current. As a transistor having a small off current, there is a transistor provided with an LDD region. In addition, the potential of the source terminal of the transistor that operates as a switch is the low potential side power supply (Vss, V)._GND, 0V, etc.), it is desirable to use the n-channel type, and conversely, when the potential of the source terminal is close to the high potential side power supply (Vdd, etc.), it is desirable to use the p-channel type. .. This is because the absolute value of the voltage between the gate and source can be increased, so that it is easy to operate as a switch. A CMOS type switch may be used by using both an n-channel type and a p-channel type.

Further, as the rectifying element applied to the present invention, in addition to the diode-connected transistor, a PN-junction or PIN-junction diode, a Schottky-type diode, a diode using carbon nanotubes, or the like may be used. Further, these may be combined with a diode-connected transistor.

Further, when the wiring 112 is set to the same potential as the wiring 106 and the wiring 107, or when the wiring 113 is set to the same potential as the wiring 105, the lower the threshold voltage Vth of the transistors 1301 to 1304 is. Good. This is because the current flows through the transistors 1301 to 1304 so that the potential at point 111 exceeds the normal range and immediately returns to the normal range.

Further, since the capacitive element 103 holds the voltage between the gate and source of the transistor 102, it is desirable that the capacitive element 103 is connected between the gate and source of the transistor 102. This is because the Vgs of the transistor 102 does not change even if the potential on the source terminal side of the transistor fluctuates.

Further, the capacitance element 103 can be omitted by using the gate capacitance of the transistor 102.

Diode-connected transistors should have less off-current. This is because if the off current is large, accurate current will not flow. Therefore, a multi-gate structure or an LDD structure may be used.

Further, the present invention can be applied even when the direction of the signal current from the basic current source is opposite, and the configuration at that time is shown in FIG.

At this time, one of the wiring 810 is connected to the wiring 805 via the basic current source 801. The other end of the wiring 810 is connected to the drain terminal of the transistor 802, and further to one terminal of the gate terminal of the transistor 802 and the capacitance element 803 via the switch 804. The other terminal of the capacitive element is connected to the wiring 807, and the source terminal of the transistor 802 is connected to the wiring 806. Therefore, the capacitive element 803 can hold the potential of the gate terminal of the transistor 802. Then, at the point 811 of the wiring 810, the wiring 812 is connected to the wiring 812 via the rectifying element 808, and the wiring 813 is connected to the wiring 813 via the rectifying element 809. The potential of the wiring 812 to which one terminal of the rectifying element 808 is connected is equal to that of the wiring 805. The forward direction of the rectifying element 808 is from the wiring 812 to the point 811. The potential of the wiring 813 to which one terminal of the rectifying element 809 is connected is equal to the potential of the wirings 806 and 807. The forward direction of the rectifying element 809 is from the point 811 to the wiring 813. That is, in the normal state, the rectifying elements 808 and 809 are in a non-conducting state.

In the present embodiment, the potentials of the wirings 806, 807 and 813 are VDD, but these wirings may be the same wiring or different, and the potential is not VDD. It does not matter, and each potential may be different. That is, the potential may be higher than the wirings 805 and 812. Further, depending on the characteristics of the rectifying element 809, it may be preferable that the potential of the wiring 813 is slightly higher than the potential of the wirings 806 and 807, but conversely, the potential may be slightly lower. That is, the potential may be such that the rectifying element 809 turns on when the potential of point 811 deviates from the normal range. Further, although the potentials of the wirings 805 and 812 are GND, these wirings may be the same wiring or different, and the potentials may not be GND, and their respective potentials are different. It doesn't matter if you have it. Further, depending on the characteristics of the rectifying element 808, it may be preferable that the potential of the wiring 812 is slightly lower than the potential of the wiring 805, but conversely, the potential may be slightly higher. That is, the potential may be such that the rectifying element 808 turns on when the potential of point 811 deviates from the normal range.

Even with this configuration, when the potential range of the wiring 810 in normal operation is exceeded due to noise, the potential can be quickly returned to the normal range.

As the rectifying element, for example, a diode-connected transistor can be used. Therefore, FIG. 14 (a) shows a configuration in which a diode-connected P-channel transistor is applied as a rectifying element of the current source circuit shown in FIG. 8, and FIG. 14 (b) shows a configuration in which an N-channel transistor is applied.

The transistor 1401 and the transistor 1402 shown in FIG. 14A correspond to the rectifying element 808 and the rectifying element 809 of FIG. 8, respectively. The gate terminal of the transistor 1401 is connected to the terminal connected to the wiring 810. In other words, when the current source circuit is operating in the range of normal potential at point 811, the gate terminal of transistor 1401 is short-circuited with the source terminal because the potential of wiring 812 is lower than that of point 811. Become. Therefore, the transistor 1401 is turned off and no current flows. However, when the potential of point 811 becomes lower than the potential of wiring 812, the gate terminal of transistor 1401 is connected to the drain terminal, a potential difference occurs between the gate source of transistor 1401, transistor 1401 turns on, and the current Will flow.

The gate terminal of transistor 1402 is short-circuited with the terminal connected to wiring 813. In other words, when the current source circuit is operating in the range of normal potential at point 811, the gate terminal of transistor 1402 is short-circuited with the source terminal because the potential of wiring 813 is higher than that of point 811. become. Therefore, the transistor 1402 is turned off and no current flows. However, when the potential of point 811 becomes higher than the potential of wiring 813, the gate terminal of transistor 1402 is connected to the drain terminal, a potential difference occurs between the gate source of transistor 1402, transistor 1402 turns on, and the current flows. It will flow.

Further, as shown in FIG. 14B, N-channel transistors 1403 and transistors 1404 can be applied to the rectifying elements 808 and 809 of FIG. The gate terminal of transistor 1403 is short-circuited with the terminal connected to wiring 810. In other words, when the current source circuit is operating in the range of normal potential at point 811, the gate terminal of transistor 1403 is short-circuited with the source terminal because the potential of wiring 812 is lower than that of point 811. Become. Therefore, the transistor 1403 is turned off and no current flows. However, when the potential of point 811 becomes lower than the potential of wiring 812, the gate terminal of transistor 1403 is connected to the drain terminal, a potential difference occurs between the gate source of transistor 1403, transistor 1403 is turned on, and the current is turned on. It will flow.

The gate terminal of transistor 1404 is short-circuited with the terminal connected to wiring 810. In other words, when the current source circuit is operating in the range of normal potential at point 811, the gate terminal of transistor 1404 is short-circuited with the source terminal because the potential of wiring 813 is higher than that of point 811. become. Therefore, the transistor 1404 is turned off and no current flows. However, when the potential of point 811 becomes higher than the potential of wiring 813, the gate terminal of transistor 1404 is connected to the drain terminal, a potential difference occurs between the gate source of transistor 1404, transistor 1404 is turned on, and the current is turned on. It will flow.

As the rectifying element applied to the present invention, in addition to the diode-connected transistor, a PN-junction or PIN-junction diode, a Schottky-type diode, a diode using carbon nanotubes, or the like may be used. Further, these may be combined with a diode-connected transistor.

When the wiring 112 is set to the same potential as the wiring 106 and the wiring 107, or when the wiring 113 is set to the same potential as the wiring 105, the lower the threshold voltage Vth of the transistors 1401 to 1404 is. Good. This is because the current flows so as to return to the potential in the normal range as soon as the potential at point 811 exceeds the normal range.

Further, since the capacitive element 803 holds the voltage between the gate and source of the transistor 802, it is desirable that the capacitive element 803 is connected between the gate and source of the transistor 802. This is because the Vgs of the transistor 802 does not change even if the potential on the source terminal side of the transistor 802 fluctuates.

Further, the capacitive element 803 can be omitted by using the gate capacitance of the transistor 802.

Diode-connected transistors should have less off-current. This is because if the off current is large, accurate current will not flow. Therefore, the diode-connected transistor may have a multi-gate structure or an LDD structure.

In some cases, the combination of these transistors replaces the transistor 1402 with the transistor 1404 shown in FIG. 14 (b) in the configuration shown in FIG. 14 (a), or the transistor 1401 is shown in the configuration shown in FIG. 14 (a). It may be replaced with the transistor 1403 shown in 14 (b). Further, a rectifying element may be formed by appropriately combining these and using a plurality of them. For example, as shown in FIG. 34 (a), a diode-connected N-channel transistor and a diode-connected P-channel transistor may be connected in parallel, or as shown in FIG. 34 (b), the N-channel transistor and the N-channel transistor may be connected. A diode-connected P-channel transistor may be connected in series.

(Embodiment 1) As the basic current source 101 shown in FIG. 1, a transistor that operates in the saturation region is often used. Therefore, in the present embodiment, the principle of the present invention when a transistor operating in the saturation region is applied to the basic current source 101 will be described.

FIG. 4 shows the configuration of the current source circuit when the transistor 401 operated in the saturation region is applied to the basic current source 101 shown in FIG. The source terminal of the transistor 401 is connected to the wiring 105, and the drain terminal is connected to the wiring 110. Then, a predetermined potential is input to the gate terminal 402 of the transistor 401. Since this transistor 401 operates in the saturation region, the magnitude of the current value is generally determined by the potential difference between the gate terminal 402 and the source terminal, and is not so affected by the potential of the drain terminal. That is, since the source terminal is connected to the wiring 105 and has a constant potential, the current value is generally determined by the value of the gate potential, so that the source terminal operates as a current source. Therefore, by applying the transistor 401 that operates in the saturation region, it can play a role as a basic current source. The common reference numerals are used for the parts common to the configuration shown in FIG.

A voltage of a certain magnitude may be applied to the gate terminal of the transistor 401. Alternatively, the gate potential of the transistor 401 may be determined by short-circuiting the gate and drain terminals of the transistor 401 and passing a predetermined current through the drain terminal of the transistor 401 to generate a gate voltage having an optimum magnitude. is there.

Here, noise may occur in the wiring 110 of the current source circuit itself. This noise is caused, for example, by a parasitic capacitance (cross capacitance) at the intersection of the wiring 110 and another wiring. Alternatively, it is caused by static electricity. Due to this noise, the electric potential of the wiring goes up or down beyond the range of the electric potential in normal operation.

Here, the operation of the rectifying elements 108 and 109 when noise is applied to the wiring 110 will be described. When noise is applied to the wiring 110 and the potential of the point 111 becomes lower than that of the wiring 112, a current is supplied from the wiring 112 to the point 111 until the potential of the point 111 becomes equal to the potential of the wiring 112. This is due to the action of the rectifying element 108 becoming conductive. Then, when noise is applied to the wiring 110 and the potential of the point 111 becomes higher than the potential of the wiring 105, a current is discharged from the point 111 to the wiring 113, and a current is discharged until the potential of the point 111 becomes equal to the potential of the wiring 113. Continue. This is due to the action of the rectifying element 109 becoming conductive.

The problem when this noise occurs during writing by the conventional current source circuit will be described with reference to FIGS. 5 and 6. The common reference numerals are used for the parts common to the configuration shown in FIG.

FIG. 5 describes a phenomenon in which the potential of the point 111 of the wiring 110 becomes lower than the potential of the wiring 106, and the operation of the conventional current source circuit at that time.

In FIG. 5A, a parasitic capacitance is formed at the point 111 of the wiring 110 so as to intersect with the other wiring 501. Then, the gate potential of the transistor 102 that is turned off is accumulated in the capacitive element 103. FIG. 5 (c) shows the equivalent circuit of the current source circuit of FIG. 5 (a) when the current source circuit is written in the state where the potential of the wiring 501 intersecting the wiring 110 and the point 111 is VDD. It is the figure shown schematically. At this time, the signal current is written from the wiring 105 to the wiring 107, and at the same time, the current flows from the wiring 501 to the point 111, and the electric charge is accumulated in the parasitic capacitance 503. Then, the potential difference between the wiring 501 and the point 111 is maintained by the parasitic capacitance. The resistor 504 represents the wiring resistance of the wiring 110, the internal resistance of the transistor 401, etc., and the resistor 505 represents the wiring resistance of the wiring 110, the contact resistance of the switch 104 (the internal resistance of the transistor when formed by the transistor), etc. ing. Further, although the resistors 504 and 505 are actually considered to be variable resistors, they are schematically represented by constant resistors in the present embodiment.

Here, when the potential of the wiring 501 changes from VDD to GND as shown in FIG. 5 (d), the point 111 on the low potential side becomes the point 111 on the low potential side because the parasitic capacitance 503 holds the potential difference between the wiring 501 and the point 111. It is lowered by (VDD-GND), and the potential is lower than GND.

In this way, noise is applied to the point 111 of the wiring 110, and the potential of the wiring 110 becomes lower than that of the wiring 106. At this time, since the source terminal of the transistor 401 is connected to the wiring 105, there is no change in the gate-source voltage of the transistor 401. Although the voltage between the drain and source of the transistor 401 increases, the current from the wiring 105 hardly increases because the transistor 401 operates in the saturation region. Therefore, the point 111 does not easily rise from a potential lower than GND. Further, regarding the transistor 102, since the terminal connected to the wiring 110 side of the transistor 102 is the source terminal, the gate terminal and the source terminal are equipotential. That is, the Vgs of the transistor 102 becomes 0V, and the transistor 102 turns off. Therefore, no current flows from the wiring 106 to the point 111. Therefore, point 111 does not easily rise from a potential lower than GND.

That is, when the potential of the wiring 110 becomes low, the current from the wiring 105 hardly increases. Further, since the potential of the terminal connected to the wiring 110 side is lower than the terminal connected to the wiring 106 side of the transistor 102, the source terminal of the N-channel type transistor 102 is a terminal connected to the wiring 110 side. It becomes. Then, since the source terminal and the gate terminal of the transistor 102 are short-circuited via the switch 104, the transistor 102 is also turned off, so that no current is supplied from the wiring 106 either. Therefore, it takes time to bring the potential of the point 111 to the potential in the normal range.

On the other hand, FIG. 6 describes a phenomenon in which the potential of the point 111 of the wiring 110 becomes higher than the potential of the wiring 107, and the operation of the conventional current source circuit at that time.

FIG. 6B shows the equivalent of the current source circuit when the current source circuit is written while the potential of the wiring 501 intersecting at the point 111 of the wiring 110 of the current source circuit shown in FIG. 5 is GND. It is a figure which showed the circuit schematically. At this time, the signal current is written from the wiring 105 to the wiring 107, and at the same time, the current also flows from the point 111 to the wiring 501, and the electric charge is accumulated in the parasitic capacitance 503. Then, the potential difference between the wiring 501 and the point 111 is maintained by the parasitic capacitance. The resistor 504 represents the wiring resistance of the wiring 110, the internal resistance of the transistor 401, etc., and the resistor 505 represents the wiring resistance of the wiring 110, the contact resistance of the switch 104 (the internal resistance of the transistor when formed by the transistor), etc. ing. Further, although the resistors 504 and 505 are actually considered to be variable resistors, they are schematically represented by constant resistors in the present embodiment.

Here, when the potential of the wiring 501 changes from GND to VDD as shown in FIG. 6 (c), the point 111 on the high potential side becomes the point 111 on the high potential side because the parasitic capacitance 503 holds the voltage between the wiring 501 and the point 111. It is higher by (VDD-GND) and has a higher potential than VDD.

When noise is applied to the point 111 of the wiring 110 and the potential becomes higher than that of the wiring 105, the source terminal of the transistor 401 becomes the terminal connected to the wiring 110, and the gate-source voltage of the transistor 401 becomes high. Absolute value rises. As a result, as shown in FIG. 6A, a current flows from the point 111 to the wiring 105, and the potential at the point 111 drops. However, as the potential at point 111 decreases, the absolute value of Vgs of transistor 401 decreases. Therefore, the current flowing through the transistor 401 becomes small. Therefore, the potential at point 111 returns to normal later. On the other hand, since the voltage between the gate and source of the transistor 102 becomes large, a current flows from the point 111 to the wiring 106. Therefore, the potential at point 111 drops. However, when the potential of the point 111 decreases, the Vgs of the transistor 102 also decreases, so that the current flowing through the transistor 102 decreases. Therefore, the potential at point 111 returns to normal later. In this way, when the potential at point 111 becomes high, the current easily flows through the transistor 102, and the current also flows through the transistor 401, so that the potential of the wiring 110 becomes lower than the potential of the wiring 105. It is easy to return to the normal potential.

Therefore, in the present embodiment, by setting the current drive capability of the rectifying element 108 shown in FIG. 4 to be larger than the current driving capability of the rectifying element 109, noise is applied to the wiring 110 and the potential during normal operation is increased. When the range is exceeded, the potential can be effectively returned to the normal level. For example, the current drive capability of the rectifying element 108 is increased by two times or more, more preferably five times or more, that of the rectifying element 109. Therefore, in some cases, only the rectifying element 108 may be inserted as shown in FIG. With this structure as well, it is possible to return the potential beyond the normal range due to noise to the normal range in a shorter time than with the conventional structure.

(Embodiment 2) In the configuration described in the first embodiment, the transistor acting as the basic current source uses the P channel type, but the transistor is not limited to this. In contrast to the circuit of FIG. 4, in the circuit of FIG. 9, an example in which the polarity (conductive type) of the transistor acting as a basic current source is changed and the connection structure of the circuit is not changed is shown in FIG. Note that FIG. 9 corresponds to an N-channel transistor applied to the basic current source 801 of FIG.

The source terminal of the transistor 901 is connected to the wiring 805, and the drain terminal is connected to the wiring 810. Then, a predetermined potential is input to the gate terminal of the transistor 901. Since this transistor 901 is operated in the saturation region, the magnitude of the current value is generally determined by the potential difference between the gate terminal 902 and the source terminal, and is not so affected by the potential of the drain terminal. That is, since the source terminal is connected to the wiring 805 and has a constant potential, the current value is generally determined by the value of the gate potential, so that the source terminal operates as a current source. Therefore, by applying the transistor 901 that operates in the saturation region, it can play a role as a basic current source. The common reference numerals are used for the parts common to the configuration shown in FIG.

A voltage of a certain magnitude may be applied to the gate terminal of the transistor 901. Alternatively, the gate potential of the transistor 901 may be determined by short-circuiting the gate and drain terminals of the transistor 901 and passing a predetermined current through the drain terminal of the transistor 901 to generate a gate voltage having an optimum magnitude. is there.

Here, noise may occur in the wiring 810 of the current source circuit itself. This noise is caused, for example, by parasitic capacitance (cross capacitance) at the intersection of the wiring 810 and other wiring. Or it is caused by static electricity. Due to this noise, the electric potential of the wiring becomes higher or lower than the electric potential in normal operation.

Here, the operation of the rectifying elements 808 and 809 when noise is applied to the wiring 810 will be described. When noise is applied to the wiring 810 and the potential of the point 811 becomes lower than that of the wiring 812, a current is supplied from the wiring 812 to the point 811 until the potential of the point 811 becomes equal to the potential of the wiring 812. This is due to the action of the rectifying element 808 becoming conductive. Then, when noise is applied to the wiring 810 and the potential of the point 811 becomes higher than the potential of the wiring 813, a forward voltage is applied to the rectifying element 809, a current is discharged from the point 811 to the wiring 813, and the potential of the point 811 becomes the wiring 813. Continue to emit current until it becomes equal to the potential of. This is due to the action of the rectifying element 809 becoming conductive.

The problem when this noise occurs during writing by the conventional current source circuit will be described with reference to FIGS. 10 and 11. The common reference numerals are used for the parts common to the configuration shown in FIG.

FIG. 10 describes the phenomenon that the potential of the point 811 of the wiring 810 becomes lower than the potential of the wiring 805, and the operation of the conventional current source circuit at that time.

In FIG. 10A, at point 811 of the wiring 810, it intersects with another wiring 1001 to form a parasitic capacitance. Then, the gate potential of the off transistor 802 is accumulated in the capacitive element 803. In FIG. 10 (c), the equivalent circuit of the current source circuit of FIG. 10 (a) is shown when the current source circuit is written in the state where the potential of the wiring 1001 intersecting the wiring 810 and the point 811 is VDD. It is the figure shown schematically. At this time, a current flows from the wiring 807 to the wiring 805, and at the same time when the signal current is written, the current also flows from the wiring 1001 to the point 811 and the electric charge is accumulated in the parasitic capacitance 1003. Then, the potential difference between the wiring 1001 and the point 811 is maintained by the parasitic capacitance. The resistor 1004 represents the wiring resistance of the wiring 810 and the internal resistance of the transistor 901, and the resistor 1005 represents the wiring resistance of the wiring 810 and the contact resistance of the switch 804 (the internal resistance of the transistor when formed by the transistor). ing. Although these resistors are schematically shown, the transistor 901 that actually operates in the saturation region has properties like a variable resistor, and is designed so that there is almost no resistance due to the switch 804.

Here, as shown in FIG. 10 (d), when the potential of the wiring 1001 changes from VDD to GND, the parasitic capacitance 1003 holds the potential difference between the wiring 1001 and the point 811. Has a lower potential than GND.

When noise is applied to the point 811 of the wiring 810 and the potential becomes lower than that of the wiring 805, the source terminal of the transistor 901 becomes the terminal connected to the wiring 810, and the voltage between the gate and source of the transistor 801 becomes high. Absolute value rises. As a result, as shown in FIG. 10 (b), a current flows from the wiring 805 to the point 811 and the potential at the point 811 rises. However, as the potential of point 811 rises, the absolute value of Vgs of transistor 901 decreases. Therefore, the current flowing through the transistor 901 becomes small. Therefore, the potential at point 811 returns to normal later. On the other hand, since the absolute value of the gate-source voltage of the transistor 802 rises, a current flows from the wiring 806 to the point 811. Therefore, the potential at point 811 rises. However, when the potential of the point 811 rises, the Vgs of the transistor 802 also becomes smaller, so that the current flowing through the transistor 802 becomes smaller. Therefore, the potential at point 811 returns to normal later. As described above, when the potential of the point 811 becomes low, the current easily flows through the transistor 802, and the current also flows through the transistor 901, so that the potential returns to the normal potential more easily than when the potential becomes high.

FIG. 11 describes a phenomenon in which the potential of the point 811 of the wiring 810 becomes higher than the potential of the wiring 807, and the operation of the conventional current source circuit at that time.

In FIG. 11 (b), the current source when the current source circuit is written while the potential of the wiring 1001 intersecting the wiring 810 of the current source circuit shown in FIG. 10 (a) at point 811 is GND. It is a figure which showed the equivalent circuit of a circuit schematically. At this time, a current flows from the wiring 807 to the wiring 805, and at the same time the signal current is written, the current also flows from the point 811 to the wiring 1001, and the electric charge is accumulated in the parasitic capacitance. Then, the potential difference between the wiring 1001 and the point 811 is maintained by the parasitic capacitance. The resistor 1004 represents the wiring resistance of the wiring 810 and the internal resistance of the transistor 902, and the resistor 1005 represents the wiring resistance of the wiring 810 and the contact resistance of the switch 804 (the internal resistance of the transistor when formed by the transistor). ing. Although these resistors are schematically represented, the transistor 901 that actually operates in the saturation region has properties like a variable resistor, and is designed so that there is almost no resistance due to the switch 804.

Here, when the potential of the wiring 1001 changes from GND to VDD as shown in FIG. 11 (c), the point 811 on the high potential side becomes the point 811 on the high potential side because the parasitic capacitance 1003 holds the potential difference between the wiring 1001 and the point 811. It is higher by (VDD-GND) and has a higher potential than VDD. In this way, the signal of the wiring 1001 becomes noise, and the potential of the point 811 becomes higher than VDD, which is the operating range of the normal current source circuit.

In this way, noise is added to the point 811 of the wiring 810, and the potential of the wiring 810 becomes higher than that of the wiring 805. At this time, since the source terminal of the transistor 901 is 805, there is no change in the gate-source voltage of the transistor 901. Although the voltage between the drain and source of the transistor 901 increases, the current discharged to the wiring 805 hardly increases because the transistor 901 operates in the saturation region. Therefore, point 811 does not easily descend from a potential higher than VDD. Further, regarding the transistor 802, since the terminal connected to the wiring 811 side of the transistor 802 is the source terminal, the gate terminal and the source terminal are equipotential. That is, the Vgs of the transistor 802 becomes 0V and the transistor 802 is turned off. Therefore, no current flows from the point 811 to the wiring 806. Therefore, point 811 does not easily descend from a potential higher than VDD.

That is, when the potential of the wiring 810 becomes high, the current discharged to the wiring 805 does not increase so much. Further, since the potential of the terminal connected to the wiring 110 side is higher than the terminal connected to the wiring 806 side of the transistor 802, the source terminal of the P-channel type transistor 802 is on the wiring 811 side. Then, since the source terminal and the gate terminal of the transistor 802 are short-circuited via the switch 804, the transistor 802 is also turned off, so that no current is discharged to the wiring 806. Therefore, it takes time to bring the potential of point 811 to the potential in the normal range.

Therefore, in the present embodiment, by setting the current capacity of the rectifying element 809 shown in FIG. 9 to be larger than the current capacity of the rectifying element 808, noise is generated in the wiring 810 and the potential range during normal operation is increased. When it exceeds, it can effectively return to the normal potential. For example, the current supply capacity of the rectifying element 809 is increased by two times or more, more preferably five times or more, that of the rectifying element 808. Therefore, in some cases, only the rectifying element 809 may be inserted as shown in FIG. With this structure as well, it is possible to return the potential beyond the normal range due to noise to the normal range in a shorter time than with the conventional structure.

(Embodiment 3) Other configurations of the applicable current source circuit of the present invention will be described. The current source TFT of the current source circuit of the present embodiment has a configuration in which the source terminal is not connected to a fixed potential. That is, the present invention is also effective in a current source circuit having a configuration in which the potential of the source terminal of the current source TFT fluctuates, as in the configuration shown in the present embodiment.

First, FIG. 35 shows the configuration of the current source circuit of this embodiment. One of the wires 3510 is connected to the wire 3505 via a basic current source 3501. The other end of the wiring 3510 is connected to the source terminal of the transistor 3502 and further to the gate terminal of the transistor 3502 via the capacitive element 3503. Further, the gate terminal of the transistor 3502 is connected to the drain terminal of the transistor 3502 and the wiring 3506 via the switch 3504. Therefore, the capacitive element 3503 can hold the potential of the gate terminal of the transistor 3502. Then, at the point 3511 of the wiring 3510, the wiring 3512 is connected to the wiring 3512 via the rectifying element 3508, and the wiring 3513 is connected to the wiring 3513 via the rectifying element 3509. The potential of the wiring 3512 to which one terminal of the rectifying element 3508 is connected is equal to that of the wiring 3506. And the forward direction of the rectifying element 3508 is the direction from the wiring 3512 to the point 3511. The potential of the wiring 3513 to which one terminal of the rectifying element 3509 is connected is equal to the potential of the wiring 3505. The forward direction of the rectifying element 3509 is from the point 3511 to the wiring 3513. That is, in the normal state, 3508 and 3509 are in a non-conducting state.

The operation when writing a signal to the current source circuit in this configuration will be briefly described. Switch 3504 is turned on when writing a signal to the current source circuit. Then, the signal current from the basic current current 3501 flows to the capacitive element 3503, and the potential of the transistor 3502 is accumulated in the capacitive element 3503. Then, when the current stops flowing through the capacitive element 3503, the writing is completed and the steady state is reached. Then turn off switch 3504. In this way, the gate-source voltage required to pass the signal current through the transistor 3502 is held in the capacitive element 3503.

At the time of this writing, if noise is generated at the point 3511 of the wiring 3510 and the potential changes beyond the range of the potential during normal operation of the current source circuit, a current flows through the rectifying element 3508 or the rectifying element 3509, which is quick and normal. The potential can be returned to the range.

As the basic current source 3501, a P-channel transistor 3601 that operates in the saturation region is often used as shown in FIG.

Here, when writing a signal to the current source circuit, noise may be added to the wiring 3510 and the potential may deviate from the normal range.

Noise is added to the point 3511 of the wiring 3510, and the potential becomes lower than that of the wiring 3506. At this time, since the source terminal of the transistor 3501 is 3505, there is no change in the gate-source voltage of the transistor 3501. Although the voltage between the drain and source of the transistor 3501 becomes large, the current from the wiring 3505 hardly increases because the transistor 3501 operates in the saturation region. Therefore, point 3511 does not easily rise from a potential lower than GND. As for the transistor 3502, the terminal connected to the wiring 3506 side of the transistor 3502 is the source terminal. Since the switch 3504 is on when writing to the current source circuit, the gate terminal and the source terminal are short-circuited, so that the potentials are equipotential. That is, the Vgs of the transistor 3502 becomes 0V, and the transistor 3502 turns off. Therefore, no current flows from the wiring 3506 to the point 3511. Therefore, point 3511 does not easily rise from a potential lower than GND.

That is, when the potential of the wiring 3510 becomes lower than the potential of the wiring 3505, the current from the wiring 3505 hardly increases. Also, since the potential of the terminal connected to the wiring 3510 side is lower than the terminal connected to the wiring 3506 side of the transistor 3502, the source terminal of the P-channel type transistor 3502 is a terminal connected to the wiring 3506 side. It becomes. Then, since the source terminal and the gate terminal of the transistor 3502 are short-circuited via the switch 3504, the transistor 3502 is also turned off, so that no current is supplied from the wiring 3506. Therefore, it takes time to bring the potential of point 3511 to the potential in the normal range.

On the other hand, when the potential of the wiring 3510 becomes higher than that of the wiring 3505, the source terminal of the transistor 3501 becomes the terminal connected to the wiring 3510, and the absolute value of the gate-source voltage of the transistor 3501 rises. .. As a result, a current flows from the point 3511 to the wiring 3505, and the potential at the point 3511 drops. However, as the potential at point 3511 decreases, the absolute value of Vgs of transistor 3501 decreases. Therefore, the current flowing through the transistor 3501 becomes small. Therefore, the potential at point 3511 slows back to normal. On the other hand, the current flows through the transistor 3502 from the point 3511 to the wiring 3506. Therefore, the potential at point 3511 drops. However, when the potential at point 3511 decreases, the Vgs of the transistor 3502 also decreases, so the current flowing through the transistor 3502 decreases. Therefore, the potential at point 3511 is delayed in returning to normal. In this way, when the potential at point 3511 becomes high, the current easily flows through the transistor 3502, and the current also flows through the transistor 3501, so the potential of the wiring 3510 is normalr than when it becomes lower than the potential of the wiring 3505. It is easy to return to the potential of.

Therefore, in the present embodiment, by setting the current drive capability of the rectifying element 3508 shown in FIG. 36 to be larger than the current driving capability of the rectifying element 3509, noise is applied to the wiring 3510 and the potential during normal operation is increased. When the range is exceeded, it can be effectively returned to the normal potential. For example, the current supply capacity of the rectifying element 3508 is increased by 2 times or more, more preferably 5 times or more that of the rectifying element 3509. Therefore, in some cases, only the rectifying element 3508 may be inserted. With this structure as well, it is possible to return the potential beyond the normal range due to noise to the normal range in a shorter time than with the conventional structure.

In the configuration described with reference to FIG. 36, the transistor acting as the basic current source uses the P-channel type, but the transistor is not limited to this. In contrast to the circuit of FIG. 36, in the circuit of FIG. 38, an example is shown in which the polarity (conductive type) of the transistor acting as a basic current source is changed and the connection structure of the circuit is not changed. Note that FIG. 38 corresponds to the basic current source 3701 of FIG. 37 to which an N-channel transistor is applied.

When writing to this current source circuit, if noise is applied to the point 3711 of the wiring 3710 and the potential becomes lower than that of the wiring 3705, the source terminal of the transistor 3801 is the terminal on the side connected to the wiring 3710. Therefore, the absolute value of the gate-source voltage of the transistor 3801 rises. As a result, a current flows from the wiring 3705 to the point 3711, and the potential at the point 3711 rises. However, as the potential of point 3711 rises, the absolute value of Vgs of transistor 3801 becomes smaller. Therefore, the current flowing through the transistor 3801 becomes small. Therefore, the potential at point 3711 returns to normal later. On the other hand, a current flows through the transistor 3702 from the wiring 3706 to the point 3711. Therefore, the potential at point 3711 rises. However, when the potential of the point 3711 rises, the Vgs of the transistor 3702 also becomes smaller, so that the current flowing through the transistor 3702 becomes smaller. Therefore, the potential of point 3711 returns to normal later. In this way, when the potential at point 3711 becomes low, the current easily flows through the transistor 3702, and the current also flows through the transistor 3801.

In addition, noise may be added to the point 3711 of the wiring 3710, resulting in a higher potential than the wiring 3706. At this time, since the source terminal of the transistor 3801 is 3705, there is no change in the gate-source voltage of the transistor 3801. Although the voltage between the drain sources of the transistor 3801 increases, the current discharged to the wiring 3705 hardly increases because the transistor 3801 operates in the saturation region. Therefore, point 3711 does not easily descend from a potential higher than VDD. As for the transistor 3702, the terminal connected to the wiring 3706 side of the transistor 3702 is the source terminal, so that the gate terminal and the source terminal have the same potential. That is, the Vgs of the transistor 3702 becomes 0V and the transistor 3702 turns off. Therefore, no current flows from the point 3711 to the wiring 3706. Therefore, point 3711 does not easily descend from a potential higher than VDD.

That is, when the potential of the wiring 3710 becomes high, the current discharged to the wiring 3705 does not increase so much. Further, since the potential of the terminal connected to the wiring 3710 side is higher than the terminal connected to the wiring 3706 side of the transistor 3702, the source terminal of the N-channel type transistor 3702 is on the wiring 3706 side. Then, since the source terminal and the gate terminal of the transistor 3702 are short-circuited via the switch 3704, the transistor 3702 is also turned off, so that no current is discharged to the wiring 3706. Therefore, it takes time to bring the potential of point 3711 to the potential in the normal range.

Therefore, in the present embodiment, by setting the current capacity of the rectifying element 3709 shown in FIG. 38 to be larger than the current capacity of the rectifying element 3708, noise is applied to the wiring 3710 and the potential range during normal operation is increased. When it exceeds, it can effectively return to the normal potential. For example, the current supply capacity of the rectifying element 3709 is increased by 2 times or more, more preferably 5 times or more, that of the rectifying element 3708. Therefore, in some cases, only the rectifying element 3709 may be inserted. With this structure as well, it is possible to return the potential beyond the normal range due to noise to the normal range in a shorter time than with the conventional structure.

(Embodiment 4) In the present embodiment, when the wiring connected to the current source circuit deviates from the potential in the normal range, a method of supplying and discharging current from another wiring without using a rectifying element is shown.

First, FIG. 39 shows the configuration of current supply and discharge according to the present embodiment. One of the wires 3910 is connected to the wire 3905 via the basic current source 3901. The other end of the wiring 3910 is connected to the drain terminal of the transistor 3902, and further to one terminal of the gate terminal of the transistor 3902 and the capacitance element 3903 via the switch 3904. The other terminal of the capacitive element 3903 is connected to the wiring 3907. Therefore, the capacitive element 3903 can hold the potential of the gate terminal of the transistor 3902. The source terminal of the transistor 3902 is connected to the wiring 3906. Then, at point 3917, the potential detection circuit 3915 is connected to the wiring 3910, and the potential detection circuit 3916 is connected to the wiring 3910. Then, the potential detection circuit 3915 and the potential detection circuit 3916 detect the potential of the point 3917 of the wiring 3910. Then, when this potential becomes lower than the potential of the wiring 3912, the output from the potential detection circuit 3915 turns on the switch 3908. Then, a current is supplied from the wiring 3912 to the point 3911, and the potential of the wiring 3910 can be quickly returned to the potential in the normal range. Also, when the potential at point 3911 is higher than the potential at wiring 3913, the output of the potential detection circuit 3916 turns on switch 3909. Then, a current is discharged to the wiring 3913, and the potential of the wiring 3910 can be quickly returned to the potential in the normal range.

As this potential detection circuit, a voltage comparator can be used as shown in FIG. 40. The potential detection circuit 3915 corresponds to the voltage comparator 4001 shown in FIG. 40, and the potential detection circuit 3916 corresponds to the voltage comparator 4002 shown in FIG. 40. The potential of GND is input to the non-inverting input terminal of the voltage comparator 4001, and the potential of VDD is input to the inverting input terminal of the voltage comparator 4002. Then, the potential of the point 3917 of the wiring 3910 is input to the inverting input terminal of the voltage comparator 4001 and the non-inverting input terminal of the voltage comparator 4002. When the potential of point 3917 is lower than the potential of GND, an H level signal is input to switch 3908 from the output of voltage comparator 4001 and switch 3908 is turned on. On the other hand, when the potential of point 3917 is higher than the potential of VDD, the H level signal is input from the output of the voltage comparator 4002 to switch 3909, and switch 3909 is turned on. In this way, the voltage comparator can fulfill the function of the potential detection circuit.

A combination of the potential detection circuit 3915 and the switch 3908 and the potential detection circuit 3916 and the switch 3909 of FIG. 39 corresponds to the respective rectifying elements 108 and 109 of the first embodiment.

In addition, FIG. 41 shows other configurations of current supply and discharge according to the present embodiment. One of the wiring 4110 is connected to the wiring 4105 via the basic current source 4101. The other end of the wiring 4110 is connected to the drain terminal of the transistor 4102, and further to one terminal of the gate terminal of the transistor 4102 and the capacitance element 4103 via the switch 4104. The other terminal of the capacitive element 4103 is connected to the wiring 4107. Therefore, the capacitive element 4103 can hold the potential of the gate terminal of the transistor 4102. The source terminal of the transistor 4102 is connected to the wiring 4106. Then, at point 4111, the potential detection circuit 4108 is connected to the wiring 4110. Further, at the point 4112, the reference potential wiring 4112 is connected to the wiring 4110 via the switch 4109.

The description of the writing operation of the current source circuit of this configuration is as described with reference to FIG. 1, and is omitted here.

In the present embodiment, when the potential of the wiring 4110 deviates from the potential in the normal range, the potential detection circuit 4108 detects the potential, and by turning on the switch 4109, the current is supplied from the reference potential wiring 4112. To do. In this way, when the potential of the wiring 4110 deviates from the normal range, it can be quickly returned to the normal range.

The reference potential is preferably set to a potential between GND and VDD so that when the potential of the wiring 4110 becomes a potential that is difficult to return, it can be quickly returned. Of course, the potential may be set between the upper limit and the lower limit of the normal range so that the potential can be quickly returned to the normal range both when the potential becomes too high and when the potential becomes too low.

A variable power supply can also be used instead of the reference potential wiring 4112. FIG. 42 shows an example of the configuration when a variable power supply is used instead of the reference potential wiring 4112. The same reference numerals as those in FIG. 41 are used.

The variable power supply has a second basic current source 4201, wiring 4206, transistors 4202 and voltage follower 4203. The wiring 4206 is connected to the wiring 4204 via the second basic current source 4201, and the other end is connected to the drain terminal and the gate terminal of the transistor 4202. The drain terminal and the gate terminal are connected to this transistor 4202. That is, they are diode-connected. The source terminal of the transistor 4202 is connected to the wiring 4204, and the wiring 4206 connected to the drain terminal of the transistor 4202 is connected to the non-inverting input terminal of the voltage follower 4203. Therefore, the voltage follower 4203 can output the same potential as the potential of the drain terminal of the transistor 4202. The current supplied by the first basic current source 4101 is I1, the current supplied by the second basic current source is I2, the channel length of the transistor 4104 is L1, the channel width is W2, and the channel length of the transistor 4202 is L2. , When the channel width is W2, it is better to satisfy I1: W1 / L1 = I2: W2 / L2. Also, when I1 = I2, it is better to set W1 / L1 = W2 / L2.

Further, the voltage follower may be another circuit as long as it has a similar function. For example, it may be a source follower. In other words, any circuit that can convert impedance is sufficient (input Imp large, output Imp small).

Therefore, when the potential of the wiring 4110 deviates from the potential in the normal range, the potential detection circuit 4108 detects this potential and turns on the switch 4109. Then, a current is supplied from the voltage follower 4203, and the potential of the wiring 4110 can be quickly returned to the potential in the normal range.

Here, an example of the configuration of the potential detection circuit 4108 is shown in FIG. 43.

The potential detection circuit 4108 can be configured by using the first voltage comparator 4301, the second voltage comparator 4302, and the OR gate. The potential at point 4111 is input to the non-inverting input terminal of the first voltage comparator 4301 and the inverting input terminal of the second voltage comparator 4302, and the potential VDD is input to the inverting input terminal of the first voltage comparator 4301. The potential GND is input to the non-inverting input terminal of the voltage comparator 4302 of 2. Here, when a potential higher than VDD is input to the non-inverting input terminal of the voltage comparator 4301, the H level is output from the output terminal of the voltage comparator 4301. On the other hand, when a potential lower than GND is input to the inverting input terminal of the voltage comparator 4302, the H level is output from the output terminal of the voltage comparator 4302. When the input potential is between GND and VDD, the L level is input to both input terminals of the OR gate, so that the L level is output from the output terminal of the OR gate. When the input potential deviates from the potential between GND and VDD, an H level signal is input to one of the input terminals of the OR gate, so that the output of the OR gate becomes H level. In this way, it can operate as a potential detection circuit. Of course, the present invention is not limited to such a configuration, and the potential detection circuit having any configuration may be used. For example, a chopper inverter comparator as shown in FIG. 44 may be used.

The configuration and operation of the potential detection circuit 4108 shown in FIG. 44 will be briefly described.

The chopper inverter comparator 4401a has a switch 4402a, a switch 4403a, a capacitive element 4404a, a switch 4405a and an inverter 4406a, and a chopper inverter comparator 4401b has a switch 4402b, a switch 4403b, a capacitive element 4404b, a switch 4405b and an inverter 4406b. The output terminal of the chopper inverter comparator 4401a is connected to the input terminal of the inverter 4407, and the output terminal of the inverter 4407 is connected to one input terminal of the OR gate 4408. The output terminal of the chopper inverter comparator 4401b is connected to the other input terminal of the OR gate.

When inputting a comparative potential to the chopper inverter comparator 4401a and chopper inverter comparator 4401b (that is, when sampling), switches 4402a and 4405a and switches 4402b and 4405b are turned on. At this time, since the input terminal and the output terminal of the inverter 4406a and the inverter 4406b are short-circuited, the offset is canceled. Then, the capacitive element 4404a holds a voltage (VDD-Va) that is the difference between the comparative input potential VDD and the potential (Va) on the input side (and output side) of the offset-cancelled inverter 4406a. Further, the capacitive element 4404b holds a voltage (GND-Vb) that is the difference between the comparative input potential GND and the potential (Vb) on the input side (and output side) of the inverter 4406b whose offset has been canceled. Then, during the input potential detection period, the switch 4402a and the switch 4405a of the chopper inverter comparator 4401a and the switch 4402b and the switch 4405b of the chopper inverter comparator 4401b are turned off. Then turn on switch 4403a and switch 4403b.

When the input potential fluctuates, the potentials on the input side of the inverter 4406a and the inverter 4406b fluctuate while the capacitive element 4404a holds the potential difference (VDD-Va) and the capacitive element 440b holds the potential difference (GND-Vb). To do.

In this state, if a potential larger than VDD (VDD + α) is input to the input potential, Since the capacitance element 4404a raises the potential on the high potential side by α while maintaining the potential difference (VDD-Va), the potential on the low potential side also rises by α, and the potential on the low potential side of the capacitance 4404a rises by α. It becomes + α. Therefore, the H level is input to the inverter 4406a, the L level is output to the output, the level is inverted by the inverter 4407, and the H level signal is input to the OR gate. That is, an H level signal is output from the OR gate. On the other hand, when a potential lower than GND (GND-β) is input to the input potential, the capacitance element 4404b lowers the potential on the low potential side by β while maintaining the potential difference (GND-Vb), so that the potential on the low potential side drops by β. The potential of the capacitance element 4404b also drops by β, and the potential on the high potential side of the capacitive element 4404b becomes Vb-β. Therefore, the L level is input to the inverter 4406b, the H level is output to the output, this signal is input to the OR gate, and the H level is output.

When the input potential is between GND and VDD, the potential on the input side of the inverter 4406a does not rise above Va, so no H-level signal is input to the inverter 4406a, that is, to the OR gate 4408. No H level signal is input. Further, since the input potential of the inverter 4406b does not drop below Vb, the L level signal is not input to the inverter 4406b. That is, no H-level signal is input to the OR gate 4408. Therefore, when the input potential is between GND and VDD, the H level signal is not output from the OR gate.

Therefore, when the potential of the wiring 4110 deviates from the potential in the normal range, the potential detection circuit 4108 detects this potential and turns on the switch 4109. Then, a current is supplied from the voltage follower 4203, and the potential of the wiring 4110 can be quickly returned to the potential in the normal range.

(Embodiment 5) In the present embodiment, the configuration and operation of the display device, the signal line drive circuit, and the like will be described. The current source circuit shown in the first and second embodiments can be applied to a part or a pixel of the signal line drive circuit.

As shown in FIG. 15, the display device includes a pixel array (Pixels) 1501, a gate line drive circuit (Gate Driver) 1502, and a signal line drive circuit 1510. The gate line drive circuit 1502 sequentially outputs selection signals to the pixel array 1501. The signal line drive circuit 1510 sequentially outputs video signals to the pixel array 1501. In the pixel array 1501, an image is displayed by controlling the state of light according to a video signal. The video signal input from the signal line drive circuit 1510 to the pixel array 1501 is often a current. That is, the display elements arranged in each pixel and the elements that control the display elements change their states according to the video signal (current) input from the signal line drive circuit 1510. Examples of display elements arranged in pixels include EL elements and elements used in FED (field emission display).

A plurality of gate line drive circuits 1502 and signal line drive circuits 1510 may be arranged.

The signal line drive circuit 1510 can be divided into a plurality of parts. Roughly, as an example, it is divided into a shift register 1503, a first latch circuit (LAT1) 1504, a second latch circuit (LAT2) 1505, and a digital-to-analog conversion circuit 1506. The digital-to-analog conversion circuit 1506 also has a function of converting a voltage into a current, and may also have a function of performing gamma correction. That is, the digital-to-analog conversion circuit 1506 has a circuit that outputs a current (video signal) to the pixels, that is, a current source circuit, to which the present invention can be applied.

Further, the pixel has a display element such as an EL element. The display element has a circuit that outputs a current (video signal), that is, a current source circuit, and the present invention can be applied thereto.

Therefore, the operation of the signal line drive circuit 1510 will be briefly described. The shift register 1503 is configured by using a plurality of rows of flip-flop circuits (FF) and the like, and a clock signal (S-CLK), a start pulse (SP), and a clock inversion signal (S-CLKb) are input to these signals. Sequential sampling pulses are output according to the timing of.

The sampling pulse output from the shift register 1503 is input to the first latch circuit (LAT1) 1504. A video signal is input to the first latch circuit (LAT1) 1504 from the video signal line 1508, and the video signal is held in each column according to the timing at which the sampling pulse is input. When the digital-to-analog conversion circuit 1506 is arranged, the video signal is a digital value. Also, the video signal at this stage is often a voltage.

However, when the first latch circuit 1504 and the second latch circuit 1505 are circuits that can store analog values, the digital-to-analog conversion circuit 1506 can often be omitted. In that case, the video signal is often an electric current. Further, when the data output to the pixel array 1501 is a binary value, that is, a digital value, the digital-to-analog conversion circuit 1506 can often be omitted.

When the holding of the video signal to the last row is completed in the first latch circuit (LAT1) 1504, a latch pulse is input from the latch control line 1509 during the horizontal return period, and the first latch circuit (LAT1) The video signals held in the 1504 are transferred to the second latch circuit (LAT2) 1505 all at once. After that, the video signal held in the second latch circuit (LAT2) 1505 is input to the digital-to-analog conversion circuit 1506 at the same time for one line. Then, the signal output from the digital-to-analog conversion circuit 1506 is input to the pixel array 1501.

While the video signal held in the second latch circuit (LAT2) 1505 is input to the digital-to-analog conversion circuit 1506 and input to the pixel 1501, the shift register 1503 outputs the sampling pulse again. That is, two operations are performed at the same time. As a result, line sequential drive becomes possible. After that, this operation is repeated.

If the current source circuit of the digital-to-analog conversion circuit 1506 is a circuit that performs setting operation and output operation, a circuit that allows current to flow is required in the current source circuit. In such cases, a reference current source 1514 is located.

As already described, the transistor in the present invention may be any type of transistor or may be formed on any substrate. Therefore, all the circuits as shown in FIG. 15 may be formed on a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. It may be formed on top or on any substrate. Alternatively, a part of the circuit in FIG. 15 may be formed on one substrate, and another part of the circuit in FIG. 15 may be formed on another substrate. That is, not all of the circuits in FIG. 15 need be formed on the same substrate. For example, in FIG. 15, the pixel array 1501 and the gate line drive circuit 1502 are formed on a glass substrate by using a TFT, and the signal line drive circuit 1510 (or a part thereof) is formed on a single crystal substrate. The IC chip may be connected by COG (Chip On Glass) and placed on a glass substrate. Alternatively, the IC chip may be connected to a glass substrate using a TAB (Tape Auto Bonding) or a printed circuit board.

The configuration of the signal line drive circuit and the like is not limited to FIG.

For example, if the first latch circuit 1504 or the second latch circuit 1505 is a circuit capable of storing analog values, a video signal is transmitted from the reference current source 1514 to the first latch circuit (LAT1) 1504 as shown in FIG. (Analog current) may be input. Further, in FIG. 16, the second latch circuit 1505 may not exist. In such a case, more current source circuits are often arranged in the first latch circuit 1504.

The present invention can be applied to the current source circuit.

(Embodiment 6) In the present embodiment, a configuration in which the present invention is applied to a part of a signal line drive circuit will be described.

A configuration in which the current source circuit of FIG. 13 (a) shown in the first embodiment is applied to a part of the signal line drive circuit will be described with reference to FIG. Note that FIG. 17 shows one of the current source circuits that supply current to the signal lines in each row.

The basic current source 101 in FIG. 13 (a) corresponds to the reference current source 1701 in FIG. 17, with the wiring 110 being the wiring 1710, the switch 104 being the switch 1704, the transistor 102 being the transistor 1702, and the capacitive element 103 being the capacitive element. In 1703, the transistor 1301 and the transistor 1302 correspond to the transistor 1708 and the transistor 1709, respectively. The wiring 105 and the wiring 113 shown in FIG. 13 correspond to one wiring 1705 in the case of FIG. Similarly, the wiring 112, the wiring 106, and the wiring 107 shown in FIG. 13 correspond to the wiring 1706 in the case of FIG. A switch 1707 is connected between the wiring 1710 and the drain terminal of the transistor 1702. The drain terminal of the transistor 1702 is also connected to one terminal of the switch 1711, and the other terminal of the switch 1711 is connected to the signal line Si. The dotted line represents a configuration of current source circuit 1712 that supplies current to the signal lines in each row.

Here, the operation of the signal line drive circuit of FIG. 17 will be briefly described. First, in order to supply the signal current to the signal line Si, the signal from the reference current source 1701 is written to the current source circuit 1712. At this time, the switch 1704 and the switch 1707 are turned on, and the switch 1711 is turned off. And referencing the current from Reference current source 1701 flows to the capacitor 1703, the gate potential of the transistor 1702 is accumulated. At the time of this writing, if the potential of the wiring 1710 exceeds the normal range due to noise or the like, the transistor 1708 or the transistor 1709 operates so as to return the potential to the normal range. That is, when the potential of the wiring 1710 becomes higher than the potential of the wiring 1705, a current is discharged from the wiring 1710 to the wiring 1705 by the action of the transistor 1709. That is, the transistor 1709 functions to lower the potential of the wiring 1710 to the potential of the wiring 1705. When the potential of the wiring 1710 becomes lower than the potential of the wiring 1706, the current is supplied from the wiring 1706 to the wiring 1710 by the action of the transistor 1708. That is, the transistor 1708 functions to raise the potential of the wiring 1710 to the potential of the wiring 1706. In this way, the delay of the writing operation due to noise can be reduced.

When the writing of the current source circuit 1712 is completed and the signal current is supplied from the current source circuit 1712 to the signal line Si, the switch 1704 and the switch 1707 are turned off to hold the gate-source voltage of the transistor 1702 in the capacitive element 1703. .. Then, when the switch 1711 is turned on, the signal current can be passed through the signal line Si.

The current source circuit used in the signal line drive circuit is not limited to the configuration shown in FIG. 17, and various configurations shown in the first and second embodiments can be used in combination.

Next, various arrangement examples of the current supply transistor and the current emission transistor in which the present invention is introduced into a part of the signal line drive circuit will be described.

In FIG. 18, a set of the current supply transistor 1708 and the current emission transistor 1709 shown in FIG. 17 is arranged via the current source circuit 1712 in each row. By arranging in this way, due to noise, the action for returning the potential beyond the normal range to normal can be made substantially equal in each row. In particular, when the wiring resistance and crossing capacitance of the wiring 1710 are large, it is difficult for the potential of the wiring 1710 to return in a place far from the transistor 1708 or the transistor 1709. Therefore, by arranging a large number of transistors 1708 and 1709 in the wiring 1710 at regular intervals, it is possible to quickly return the potential of the wiring 1710 at any position of the wiring 1710.

If the current supply transistor 1708 and the current discharge transistor 1709 cannot be placed in each row due to placement restrictions, only the current supply transistor 1708 is placed in each row of the current source circuit 1712 as shown in FIG. It may be configured as such. Even in this case, as described in the first embodiment, it acts when it is difficult to return to the normal potential. That is, it is effective because it acts when the potential of the wiring 1710 becomes lower than the normal range and can be returned to the potential in the normal range. That is, by widely distributing the transistor 1708, which has a large effect, on the wiring 1710, it is possible to easily restore the potential of the wiring 1710.

Further, as shown in FIG. 20, a set of current supply transistors 1708 and current emission transistors 1709 may be arranged for several rows of current source circuits 1712. In Fig. 20, one transistor 1708 for current supply and one transistor 1709 for current emission are arranged for the current source circuit 1712 in three rows, but of course, the number of rows and one combination can be appropriately selected. You can.

Further, as shown in FIG. 21, only the current supply transistor 1708 may be arranged in each row of the current source circuit 1712, and the current supply transistor 1708 and the current discharge transistor 1709 may be arranged at both ends. .. In this way, it is possible to increase the current driving ability for acting when the potential of the wiring 1710 becomes lower than the normal range and returning to the potential in the normal range.

The current drive capability of the transistor 1708 and the transistor 1709 can also be set by the ratio of the channel length L and the channel width W of the transistor. To increase the current drive capacity, increase the W / L, and decrease the W / L to decrease the current capacity.

Therefore, the number of current supply transistors 1708 and current discharge transistors 1709 to be arranged and the W / L ratio can be appropriately set to further enhance the effect of the present invention. Even if the W / L is increased, almost no current flows through the transistors 1709 and 1708 during normal operation, so it is better to increase it as much as possible. However, the off-current of the transistors 1709 and 1708 should not be too large. Therefore, in order to reduce the off-current, the transistor 1709 and the transistor 1708 may have a multi-gate structure or may be provided with a low-concentration impurity region (also referred to as LDD).

For example, it is desirable to arrange the current supply transistors 1708 and the current emission transistors 1709 as many as the number of current source circuits. Alternatively, depending on the current source circuit, it is preferable to arrange as many transistors as the number of current source circuits in which the current flows when the potential of the wiring in the current source circuit is difficult to return to the potential in the normal range. Alternatively, it may be arranged as many as the number of source signal lines. Specifically, it is preferable to arrange 100 to 2000 current supply transistors 1708 and current emission transistors 1709. More preferably, 300 to 1000 current supply transistors 1708 and current emission transistors 1709 are arranged, and more preferably 600 to 700 current supply transistors 1708 and current emission transistors 1709 are arranged. More specifically, a current supply transistor 1708 and a current discharge transistor 1709 are provided according to the resolution of the display device. For example, the resolution is VGA (Video Graphics) In the case of Array), the number of dots in the horizontal direction x the number of dots in the vertical direction = 640 x 480, and since there is an RGB source signal line for each dot, 1920 current supply transistors 1708 and current emission transistors 1709 are provided. .. Similarly, 528 for QCIF (Quater Common Intermediate Format), 3072 for XGA (eXtended Graphics Array), and UXGA (Ultra). For XGA), install 4800 pieces. Or provide more. However, for example, in the case of VGA, 1920 current source circuits are not always connected to one wiring. For example, 640, 320, or 160 current source circuits may be connected. In that case, 640 current supply transistors 1708 and current discharge transistors 1709 may be arranged, or only an integral fraction of the number (320, 160, 80, etc.). Therefore, in the case of QCIF, 176, 88, 44, or 22 pieces, in the case of XGA, 1024 pieces, 512 pieces, 256 pieces, or 128 pieces, in the case of UXGA, 1600 pieces, 800 pieces, 400 pieces, or Only 200 may be placed. Alternatively, it is preferable to arrange only the transistor through which the current flows when the potential of the wiring in the current source circuit is difficult to return to the potential in the normal range.

Further, for example, W is 5 to 800 μm, preferably 50 to 800 μm, L is 5 μm to 20 μm, preferably 5 to 10 μm, and W / L is 1 to 150, preferably 50 to 150. preferable.

Although only one current source circuit is described in each row of the signal lines in FIGS. 17 to 21, a plurality of current source circuits are arranged in parallel and switched to operate to perform setting operation and the like. Output operation can be performed at the same time. Further, not limited to these configurations, various configurations shown in the first and second embodiments can be applied.

Further, when the analog current is output to the load (pixel), the configuration is as shown in FIG. Note that FIG. 22 describes the case of 3 bits for the sake of simplicity. That is, there are reference current sources 2201A, 2201B, and 2201C, and the magnitudes of the currents at the time of setting operation are Ic, 2 × Ic, and 4 × Ic. The current source circuits 2202A, 2202B, and 2202C are connected to each other. The current source circuit 1712 shown in FIG. 17 can be applied to the current source circuits 2202A, 2202B, and 2202C. Therefore, during the output operation, the current source circuits 2202A, 2202B, and 2202C output currents having the magnitudes of Ic, 2 × Ic, and 4 × Ic. The switches 2203A, 2203B, and 2203C are connected in series with each current source circuit. This switch is controlled by the video signal output from the second latch circuit (LAT2) 1505 shown in FIG. Then, the total of the currents output from each current source circuit and the switch is output to the load, that is, the pixel. By operating as described above, an analog current is output to the pixels as a video signal.

By arranging the current sources in parallel as in the case of FIG. 17, the setting operation and the output operation can be performed at the same time.

In FIG. 22, for the sake of simplicity, the case of 3 bits has been described, but the present invention is not limited to this. If it is configured in the same manner, the number of bits can be easily changed.

(Embodiment 7) In the present embodiment, the case where the present invention is applied to the source signal line drive circuit and the current source circuit provided between the pixels will be described.

FIG. 23 shows a first pixel configuration to which the present invention is applied.

Pixel 2313 is the first gate signal line 2314 and the second gate signal line 2315, the current supply line 2310, the source signal line 2316, the power supply line 2306, the switching TFT2311, the erasing TFT2309, the first holding capacity 2312, and the driving TFT2308. It has a current source TFT2302, a second holding capacity 2303, a first switch 2304, a second switch 2318, a light emitting element 2307, and a reference current source 2301.

The pixel configuration and operation of this embodiment will be briefly described. In this configuration, an image is displayed depending on whether or not the current supplied by the current source TFT2302 is passed through the light emitting element 2307. The current from the reference current source 2301 is supplied to the current source TFT2302 and the second holding capacity 2303 to set an appropriate voltage between the gate and source of the current source TFT2302. In this way, the current supplied by the second current source TFT2302 is set. Then, when the gate line 2315 is selected, the switching transistor 2311 is turned on, and a digital image signal (usually a voltage value) is input from the signal line 2316 to the first holding capacitance 2312. The first holding capacitance 2312 can be omitted by using the gate capacitance of the transistor or the like. Then, the switching transistor 2311 is turned on and off using the stored digital image signal. That is, the switching TFT2311 controls whether or not the current supplied by the current source TFT2302 flows through the light emitting element 2307. Thereby, the image can be expressed.

Further, in the present embodiment, one of the current supply lines 2310 is connected to the wiring 2305 via the reference current source 2301, and the other is connected to the wiring 2305 via the second switch 2318. , The source terminal of the current source TFT2302 and the source terminal of the drive TFT2308 are connected. A current supply TFT2321 and a current release TFT2320 are connected to this current supply line 2310. These TFTs are diode-connected TFTs, and the gate terminal of the current supply TFT2321 is short-circuited with the source terminal and further connected to the wiring 2317. The drain terminal of the current discharge TFT2320 is connected to the wiring 2306. The other terminal of the holding capacity 2303 is connected to the power line 2306 via the gate terminal of the current source TFT2302 and the first switch 2304. The drain terminal of the current source TFT2302 is connected to the power line 2306. The drain terminal of the drive TFT 2308 is connected to the anode of the light emitting element 2307, and the cathode of the light emitting element is connected to the wiring 2319. The source terminal of the switching TFT 2311 is connected to the source signal line 2316, and the gate terminal is connected to the first gate signal line 2314. The drain terminal is connected to the gate terminal of the drive TFT2308, the source terminal of the erasing TFT2309, and one terminal of the first holding capacity 2312. The other terminal of the holding capacity 2312 and the drain terminal of the erasing TFT 2309 are connected to the power line 2306, and the gate terminal of the erasing TFT 2309 is connected to the second gate wiring 2315.

Here, the operation of writing the signal current from the reference current source 2301 to the pixel 2301 will be described.

When writing the signal current from the reference current source 2301 to the current source circuit of pixel 2313, the first switch 2304 and the second switch 2318 are turned on. Then, a current flows from the wiring 2306 to the holding capacity 2303, and the gate potential of the current source TFT2302 is accumulated. Then, when the steady state is reached, the writing is completed, and the switch 2304 and the switch 2318 are turned off. In this way, the gate-source voltage of the current source TFT2302 is held in the holding capacity 2303. That is, the gate-source voltage for passing the signal current through the current source TFT2302 is maintained.

It is assumed that the reference current source 2301 writes to the current source TFT2302 in the next line, and the first line shifts to the output operation (light emitting operation) while writing to the pixel 2313n in the nth line. When the output operation is not performed, the first gate signal line 2314 is the potential of GND. When performing output operation, a VDD signal is input to the first gate signal line 2314, the switching TFT 2311 is turned on, and current starts to flow from the second power supply line 2306 to the first holding capacity 2312. Then, the gate potential of the drive TFT2308 is accumulated in the first holding capacity 2312, and when the threshold voltage of the drive TFT2308 is exceeded, the drive TFT2308 is turned on, and a signal current flows from the current source TFT2302 to the light emitting element 2307 to emit light.

Here, when a VDD signal enters the first gate signal line 2314, the potential of the current supply line 2310 intersecting the wiring 2314 and forming a parasitic capacitance as described in FIG. 6 of the first embodiment. Is higher than VDD.

Then, when the potential of the current supply line 2310 is higher than VDD, the source terminal of the current source TFT2302n becomes the terminal on the side connected to the power supply line 2306. At this time, since writing is performed to the current source circuit of pixel 2313n, the gate terminal of the current source TFT2302n and the terminal connected to the power supply line 2306 are short-circuited by the first switch 2304n. Therefore, when the potential of the current supply line 2310 becomes higher than VDD, the current source TFT2302n is turned off and no current flows. Further, as the current source 2301, an N-channel transistor is often used as shown in FIG. 9 of the first embodiment. Then, since the potential of the source terminal of the N-channel transistor is fixed to the constant potential wiring 2305, even if the potential of the wiring 2310 on the drain terminal side becomes high, the current flowing in the direction opposite to the signal current becomes too large. There is no.

Therefore, it takes time to return the current supply line 2310 to the potential in the normal range. Then, the writing is completed before the writing of the nth line is completed (before the steady state is reached), and the writing of the next line is started. Therefore, the desired data cannot be written in the second holding capacity 2303n that stores the gate potential of the desired current source TFT2302n, and correct display cannot be performed.

However, when the current discharge TFT 2320 is connected to the current supply line 2310 as shown in FIG. 23, the potential can be immediately returned to the normal potential. When the potential of the current supply line 2310 becomes higher than the potential of the power supply line 2306, the diode-connected current emission TFT2320 becomes the source terminal because the terminal connected to the power supply line 2306 side becomes the source terminal. A potential difference is generated, a current flows through the current emission TFT2320, and the potential of the current supply line 2310 is returned to VDD. Therefore, since the potential of the current supply line 2310 can be quickly returned to the normal range, the delay in writing the signal current can be reduced.

Further, in reality, a large number of wires intersect and the VDD and GND signals are switched in a complicated manner, so that the potential of the current supply line 2310 becomes lower or higher than the normal range.

When the potential of the current supply line 2310 becomes lower than GND, a current flows through the second holding capacity 2303, the current source TFT2302 is turned on, a current flows through the current source TFT2302, and the potential of the current supply line 2310 is returned. Can be done. Also, when an N-channel transistor is used for the reference current source 2301, the terminal on the side connected to the current supply line 2310 becomes the source terminal, so the gate-source voltage is higher than when the signal current is flowing. Therefore, a large current flows through the N-channel transistor in the direction opposite to that of the signal current. In addition, since the terminal connected to the current supply line 2310 side of the current supply TFT2321 becomes the source terminal, the current flows through the current supply TFT2321, and the potential of the current supply line is quickly returned to the potential of GND. ..

Therefore, when the potential of the current supply line 2310 is lower than GND, it is easier to return to the potential in the normal range than when it is higher than the potential of VDD.

Therefore, in the configuration shown in FIG. 23, it is preferable to set the current drive capability of the current emission TFT2320, which has the effect of returning the potential to the normal range when the potential becomes higher than the normal range, to be larger than that of the current supply TFT2321. Of course, depending on the case, only the current discharge TFT2320 may be arranged and the current supply TFT2321 may not be provided, or a set of the current supply TFT2321 and the current discharge TFT2320 may be provided at the upper end and the lower end of the pixel portion. , Only the current emission TFT 2320 may be provided. Further, each pixel may be provided with one set of current supply TFT2321 and one set of current discharge TFT2320, or only one of them may be provided. In this pixel configuration, only the current emission TFT 2320 may be provided.

Here, FIG. 28 shows a schematic diagram of a display device having a plurality of pixels. The display device includes a substrate 2801, an FPC (flexible printed circuit) 2802, a gate line drive circuit 2803, a source signal line drive circuit 2804, a pixel unit 2805, pixels 2806, and rectifying elements 2807 and 2808. The pixels 2806 are arranged in a matrix corresponding to the gate line and the source signal line.

Further, as shown in FIG. 28, each of the source signal lines may be provided with a current emission transistor 2807 at the upper end of the pixel portion and a current supply transistor 2808 at the lower end. Of course, the configuration may be reversed, or a set of a current emission transistor 2807 and a current supply transistor 2808 may be arranged at the upper end and the lower end. As the current emission transistor 2807 and the current supply transistor 2808, a diode-connected transistor can be used. However, other rectifying elements may be used instead of the current emission transistor 2807 and the current supply transistor 2808.

In this embodiment, a diode-connected TFT is used as a current supply TFT and a current discharge TFT, but any rectifying transistor may be used, and a PN junction or PIN junction diode or a Schottky type diode may be used. Or a diode using carbon nanotubes or the like may be used.

FIG. 24 shows a second pixel configuration to which the present invention is applied.

The pixels in FIG. 24 are source signal line 2410, first gate signal line 2414 and second gate signal line 2415, power supply line 2416, switching TFT2411, holding TFT2412, driving TFT2404, current source TFT2402, holding capacity 2403, It has a light emitting element 2417 and a current source 2401 for inputting a video signal.

The gate terminal of the switching TFT 2411 is connected to the second gate signal line 2415, the source terminal is connected to the source signal line 2410, and the drain terminal is connected to the source terminal of the drive TFT 2404 and the drain terminal of the current source TFT 2402. Has been done. The gate terminal of the holding TFT2412 is connected to the first gate signal line 2414, the source terminal is connected to the gate terminal of the driving TFT2411 and the gate terminal of the current source TFT2402, and the drain terminal is connected to the source signal line 2410. It is connected. The drain terminal of the driving TFT 2424 is connected to the anode of the light emitting element 2417. The source terminal of the current source TFT2402 is connected to the power line 2403. The holding capacity 2403 is connected between the gate terminal and the source terminal of the current source TFT2402, and holds the gate-source voltage of the current source TFT2402. Predetermined potentials are input to the power line 2416 and the cathode 2407 of the light emitting element 2417, respectively, and have potential differences from each other.

Here, the details of the driving method are as shown in Japanese Patent Application Laid-Open No. 2004-054200 and will be omitted here.

During the writing operation to the pixel, the gate potential of the current source TFT2402 is accumulated in the capacitive element 2403 by writing by the video signal input current source 2401. At this time, a case where noise is applied to the source signal line 2410 and the potential of the source signal line 2410 exceeds the normal range will be described. First, when the potential of the source signal line 2410 becomes lower than the normal range, the voltage between the gate and source of the current source TFT2402 rises and the current is supplied from the wiring 2416, so that the potential of the source signal line 2410 is relatively high. Easy to return.

On the other hand, when the source signal line 2410 has a high potential beyond the normal range, the video signal input current source 2401 connected to the low potential side is in the saturation region as described in the second embodiment. An operating N-channel transistor is often used. Therefore, as described above, the current flowing through the N-channel transistor does not change much when the source signal line 2410 becomes high potential. During the write operation, the switching TFT 2411 and the holding TFT 2412 are in the ON state. Therefore, in the current source TFT2402, the terminal on the side connected to the switching TFT2411 becomes the source terminal, so that the gate and source are short-circuited. Therefore, the current source TFT2402 is turned off and no current flows. A current flows through the holding capacity 2403 in the opposite direction to the writing of the signal current. Therefore, even if the potential of the source signal line 2410 returns to the normal range, writing is delayed.

However, in the configuration of Fig. 24, the current supply TFT2409 that supplies current when the potential of the source signal line 2410 is lower than the potential of the wiring 2413 and the current is released when the potential of the source signal line 2410 is higher than the potential of the wiring 2406. Since the current release TFT2408 is connected to the source signal line 2410, if the potential of the source signal line exceeds the normal range, current will flow through the current supply TFT2409 and current release TFT2408, and it will be normal immediately. It is possible to return to the potential of. Then, it is advisable to increase the current drive capability of the current discharge TFT2408. The current drive capacity may be increased overall, and in addition to increasing the W / L value of the TFTs, for example, a large number of TFTs may be arranged. Further, the configuration is not limited to that shown in FIG. 24, and the current emission TFT2408 may be arranged at the upper part of the pixel and the current supply TFT2409 may be arranged at the lower part, or the current emission TFT2408 and the current supply may be arranged at the upper part and the lower part. One set of TFT2409s may be arranged, or only the TFT2408 for current emission may be provided. Further, each pixel may be provided with one set of current supply TFT2409 and one set of current discharge TFT2408, or only one of them may be provided. In this pixel configuration, only the current emission TFT 2408 may be provided.

Next, the third configuration will be described with reference to FIG.

FIG. 25 shows a third configuration example. The pixels in FIG. 25 are the source signal line 2507, the first gate signal line 2510, the second gate signal line 2509, the third gate signal line 2517, the power supply line 2518, the first TFT 2514, the second TFT 2506, and the second. It has 3 TFT2508, 4th TFT2504, holding capacity 2503, light emitting element 2505, and video signal input current source 2501.

The gate terminal of the first TFT 2514 is connected to the first gate signal line 2510, the source terminal is connected to the source signal line 2507, and the drain terminal is the drain terminal of the second TFT 2506 and the source terminal of the third TFT 2508. Is connected to. The gate terminal of the second TFT 2506 is connected to the second gate signal line 2509, and the source terminal is connected to the power line 2518. The gate terminal of the fourth TFT2504 is connected to the third gate signal line 2517, the source terminal is connected to the gate terminal of the third TFT2502, and the drain terminal is the drain terminal of the third TFT2508 and the light emitting element 2505. It is connected to the anode of. The holding capacity 2503 is connected between the gate terminal and the source terminal of the third TFT 2508 to hold the gate-source voltage of the third TFT 2508. Predetermined potentials are input to the cathodes of the power supply line 2518 and the light emitting element 2505, respectively, and have potential differences from each other.

Here, the details of the driving method are as shown in Japanese Patent Application Laid-Open No. 2004-054200 and will be omitted here.

During the writing operation to the pixels, the gate potential of the third TFT 2502 is accumulated in the holding capacity 2503 by writing by the video signal input current source 2501. At this time, a case where noise is applied to the source signal line 2507 and the potential of the source signal line 2507 exceeds the normal range will be described. First, a case where the potential of the source signal line 2507 becomes lower than the normal range will be described. As described in the first embodiment, the video signal input current source 2501 connected to the high potential side often uses a P-channel transistor that operates in the saturation region. Therefore, as described above, the current flowing from the P-channel transistor does not change much at this time. Also, since the source terminal of the second TFT 2506 remains the terminal connected to the power supply line 2508, the current flowing through the second TFT 2506 does not increase so much. Then, since the holding capacity 2503 that has accumulated the gate potential of the third TFT 2508 is also discharged, the third TFT 2502 is turned off and no current flows through the third TFT 2302. Also, since the fourth TFT 2504 is on at the time of writing, a current flows through the holding capacity 2503 in the opposite direction to that at the time of writing the signal current. Therefore, even if the potential of the source signal line 2507 returns to the normal range, writing is delayed. However, in FIG. 25 to which the present invention is applied, since the current supply TFT 2513 is provided, when the potential of the source signal line 2507 becomes lower than the normal range in this way, until it becomes the potential of GND. It can supply current and quickly return to the normal range of potential.

On the other hand, a case where the potential of the source signal line 2507 becomes higher than the normal range will be described. When the potential becomes high, a current flows through the holding capacity 2503, the gate potential of the current source TFT2502 is accumulated, and the third TFT2502 is turned on. Then, a current flows through the third TFT 2502, and the voltage between the gate and source of the second TFT 2506 also increases, so that the current flowing through the second TFT 2506 also increases. Since the P-channel transistor used as the current source for video signal input is also the terminal on the side where the source terminal is connected to the source signal line 2507, the voltage between the gate and source increases and the current flowing through the P-channel transistor also increases. growing. Therefore, when the potential of the source signal line 2507 becomes higher than the normal range, it is easier to return to the potential in the normal range than when it becomes lower. Furthermore, since the current emission TFT2511 is arranged, the current flows so as to return the potential of the source signal line 2507 to the potential of VDD, so that the potential can be returned to the normal range more quickly.

Therefore, in the configuration shown in FIG. 25, the current drive capability of the current supply TFT 2513 is increased. The current drive capacity may be increased overall, and in addition to increasing the W / L value of the TFTs, for example, a large number of TFTs may be arranged. Further, the configuration is not limited to that shown in FIG. 25, and the current emission TFT2511 may be arranged at the upper part of the pixel and the current supply TFT2512 may be arranged at the lower part, or the current emission TFT2511 and the current supply may be arranged at the upper part and the lower part. One set of TFT2512s may be arranged, or only the TFT2512 for current supply may be provided. Further, each pixel may be provided with one set of the current supply TFT2512 and one set of the current discharge TFT2511, or only one of them may be provided. In this pixel configuration, only the current supply TFT 2512 may be provided.

Next, the fourth configuration will be described with reference to FIG.

The pixels in FIG. 26 are the source signal line 2608, the first gate signal line 2610 and the second gate signal line 2616, the power line 2609, the first TFT2606, the second TFT2605, the third TFT2604, and the fourth TFT2602. It has a holding capacity of 2603, a light emitting element of 2607, and a current source for video signal input 2601.

The gate terminal of the first TFT 2606 is connected to the first gate signal line 2610, the source terminal is connected to the source signal line 2608, and the drain terminal is the drain terminal of the second TFT 2605 and the drain terminal of the third TFT 2604. Is connected to. The gate terminal of the third TFT2604 is connected to the second gate signal line 2616, and the source terminal is connected to the gate terminal of the second TFT2605 and the gate terminal of the T fourth TFT2602. The source terminals of the second TFT2605 and the fourth TFT2602 are both connected to the power supply line 2609, and the drain terminal of the fourth TFT2602 is connected to the anode of the light emitting element 2607. The holding capacity 2603 is connected between the gate terminals of the second TFT2605 and the fourth TFT2602 and the source terminals of the second TFT2605 and the fourth TFT2602, and the gate source of the second TFT2605 and the fourth TFT2602. Holds the voltage between. Predetermined potentials are input to the cathodes of the power supply line 2609 and the light emitting element 2607, respectively, and have potential differences from each other.

Here, the details of the driving method are as shown in Japanese Patent Application Laid-Open No. 2004-054200 and will be omitted here.

During the writing operation to the pixels, the gate potentials of the second TFT2605 and the fourth TFT2602 are accumulated in the holding capacity 2603 by writing by the video signal input current source 2601. First, when the potential of the source signal line 2608 becomes lower than the normal range, the gate terminal of the second TFT 2605 is connected to the source signal line 2608 via the first TFT 2606 and the third TFT 2604. The gate potential is lower than the normal range. Since the source terminal of the second TFT 2605 is connected to the power supply line 2609, the gate-source voltage of the second TFT 2605 rises, and the current flowing from the power supply line 2609 to the second TFT 2605 increases. Therefore, the potential of the source signal line 2608 is relatively easy to return.

On the other hand, when the source signal line 2608 has a high potential beyond the normal range, the video signal input current source 2601 connected to the low potential side is in the saturation region as described in the second embodiment. An operating N-channel transistor is often used. Therefore, as described above, the current flowing through the N-channel transistor does not change much when the source signal line 2608 becomes high potential. During the writing operation, the first TFT2606 and the third TFT2604 are in the ON state. Therefore, since the source terminal of the second TFT2605 is a terminal connected to the drain terminal of the first TFT2606, the gate and source are short-circuited via the third TFT2604 which functions as a switch. Therefore, the second TFT2605 is turned off and no current flows. Further, a current flows through the holding capacity 2603 in the opposite direction to the writing of the signal current. Therefore, even if the potential of the source signal line 2608 returns to the normal range, writing is delayed.

However, in the configuration of FIG. 26, the current supply TFT2611 that supplies a current when the potential of the source signal line 2608 becomes lower than the potential of the wiring 2613 and the current is released when the potential of the source signal line 2608 becomes higher than the potential of the wiring 2614. Since the current release TFT2612 is connected to the source signal line 2608, when the potential of the source signal line exceeds the normal range, a current flows through the current supply TFT2611 and the current release TFT2608, and the normal potential is immediately obtained. It can be returned to. .. Then, the current drive capability of the current emission TFT2612 is increased. The current drive capacity may be increased overall, and in addition to increasing the W / L value of the TFTs, for example, a large number of TFTs may be arranged. Further, the configuration is not limited to that shown in FIG. 26, and the current emission TFT2612 may be arranged at the upper part of the pixel and the current supply TFT2611 may be arranged at the lower part, or the current emission TFT2612 and the current supply may be arranged at the upper part and the lower part. One set of TFT2611 may be arranged, or only the TFT2612 for current emission may be provided. Further, each pixel may be provided with a set of a current supply TFT2611 and a current release TFT2612, or only one of them may be provided. In this pixel configuration, only the current emission TFT2612 may be provided.

Next, the fifth configuration will be described with reference to FIG. 27.

FIG. 27 shows a fifth configuration example. The pixels of FIG. 27 are the source signal line 2708, the first gate signal line 2709, the second gate signal line 2710, the third gate signal line 2711, the power supply line 2712, the first TFT2706, the second TFT2704, and the second. It has 3 TFT2705, 4th TFT2702, holding capacity 2703, light emitting element 2707, and video signal input current source 2701.

The gate terminal of the first TFT 2706 is connected to the first gate signal line 2709, the source terminal is connected to the source signal line 2708, and the drain terminal is the drain terminal of the second TFT 2704 and the drain terminal of the third TFT 2705. , And is connected to the source terminal of the 4th TFT 2702. The gate terminal of the second TFT 2704 is connected to the second gate signal line 2710, and the source terminal is connected to the gate terminal of the TFT 2702 of strike 4. The source terminal of the fourth TFT 2702 is connected to the power line 2712. The gate terminal of the third TFT 2705 is connected to the third gate signal line 2711, and the drain terminal is connected to the anode of the light emitting element 2707. The holding capacity 2703 is connected between the gate terminal of the fourth TFT 2702 and the power line 2712 to hold the gate-source voltage of the fourth TFT 2702. Predetermined potentials are input to the cathodes of the power supply line 2712 and the light emitting element 2707, respectively, and have potential differences from each other.

Here, the details of the driving method are as shown in Japanese Patent Application Laid-Open No. 2004-054200 and will be omitted here.

During the writing operation to the pixel, the gate potential of the fourth TFT 2702 is accumulated in the holding capacity 2703 by writing by the video signal input current source 2701. First, when the potential of the source signal line 2708 becomes lower than the normal range, the gate terminal of the fourth TFT 2702 is connected to the source signal line 2708 via the first TFT 2706 and the second TFT 2704. The gate potential is lower than the normal range. Since the source terminal of the fourth TFT 2702 is connected to the power supply line 2712, the gate-source voltage of the fourth TFT 2702 rises, and the current flowing from the power supply line 2712 to the fourth TFT 2702 increases. Therefore, the potential of the source signal line 2708 is relatively easy to return.

On the other hand, when the source signal line 2708 has a high potential beyond the normal range, the video signal input current source 2701 connected to the low potential side is in the saturation region as described in the second embodiment. An operating N-channel transistor is often used. Therefore, as described above, the current flowing through the N-channel transistor does not change much when the source signal line 2708 reaches a high potential. During the writing operation, the first TFT2706 and the second TFT2704 are in the ON state. Therefore, since the source terminal of the fourth TFT 2702 is a terminal connected to the drain terminal of the first TFT 2706, the gate source is short-circuited via the second TFT 2704 that acts as a switch. .. Therefore, the 4th TFT 2702 is turned off and no current flows. Further, a current flows through the holding capacity 2703 in the opposite direction to the writing of the signal current. Therefore, even if the potential of the source signal line 2708 returns to the normal range, writing is delayed.

However, in the configuration of Fig. 27, the current supply TFT2715 that supplies current when the potential of the source signal line 2708 is lower than the potential of the wiring 2716 and the current is released when the potential of the source signal line 2708 is higher than the potential of the wiring 2716. Since the current release TFT2713 is connected to the source signal line 2708, when the potential of the source signal line exceeds the normal range, a current flows through the current supply TFT2715 and the current release TFT2713, and the normal potential immediately occurs. It can be returned to. Then, the current drive capability of the current release TFT 2713 is increased. The current drive capacity may be increased overall, and in addition to increasing the W / L value of the TFTs, for example, a large number of TFTs may be arranged. Further, the configuration is not limited to that shown in FIG. 27, and the current emission TFT2713 may be arranged at the upper part of the pixel and the current supply TFT2715 may be arranged at the lower part, or the current emission TFT2713 and the current supply may be arranged at the upper part and the lower part. One set of TFT2715 may be arranged, or only the TFT2713 for current emission may be provided. Further, each pixel may be provided with a set of a current supply TFT2715 and a current release TFT2713, or only one of them may be provided. In this pixel configuration, only the current emission TFT 2713 may be provided.

(Embodiment 8) The present invention can be applied to various electronic devices. Specifically, it can be applied to pixels and signal line drive circuits that form a display unit of an electronic device. Such electronic devices include video cameras, digital cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebook computers, game devices, and personal digital assistants (mobile computers). , A mobile phone, a portable game machine, an electronic book, etc.), an image playback device equipped with a recording medium (specifically, a display capable of playing back a recording medium such as a Digital Versatile Disc (DVD) and displaying the image). Equipment) and the like. In particular, it is desirable to use the display device of the present invention for a portable information terminal in which the screen is often viewed from an oblique direction because a wide viewing angle is regarded as important. Specific examples of these electronic devices are shown in FIG.

FIG. 30A shows a display, which includes a housing 13001, a support base 1302, a display unit 1303, a speaker unit 13004, a video input terminal 13005, and the like. A display using the present invention for the power supply circuit of the display unit 13003 can reduce malfunction due to noise. As a result, display unevenness can be suppressed. The display device can be a liquid crystal display device or a light emitting device. The display includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 30B is a digital still camera, which includes a main body 13101, a display unit 13102, an image receiving unit 13103, an operation key 13104, an external connection port 13105, a shutter 13106, and the like. A display using the present invention for the power supply circuit of the display unit 13102 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

FIG. 30C shows a notebook computer, which includes a main body 13201, a housing 13202, a display unit 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. A display using the present invention for the power supply circuit of the display unit 13203 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

FIG. 30 (D) is a mobile computer, which includes a main body 13301, a display unit 13302, a switch 13303, an operation key 13304, an infrared port 13305, and the like. A display using the present invention for the power supply circuit of the display unit 13302 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

FIG. 30 (E) shows a portable image playback device (specifically, a DVD playback device) equipped with a recording medium, which includes a main body 13401, a housing 13402, a display unit A13403, a display unit B13404, and a recording medium (DVD, etc.). Includes reading unit 13405, operation key 13406, speaker unit 13407, etc. The display unit A13403 can mainly display image information, and the display unit B13404 can mainly display character information. A display in which the present invention is used in the power supply circuit of the display unit A13403 or the display unit B13404 can reduce malfunction due to noise. As a result, display unevenness can be suppressed. The image reproduction device provided with the recording medium also includes a home-use game device and the like.

FIG. 30F is a goggle-type display (head-mounted display), which includes a main body 13501, a display unit 13502, and an arm unit 13503. A display using the present invention for the power supply circuit of the display unit 13502 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

FIG. 30 (G) is a video camera, which includes a main body 13601, a display unit 13602, a housing 13603, an external connection port 13604, a remote control receiver 13605, an image receiving unit 13606, a battery 13607, an audio input unit 13608, an operation key 13609, and the like. .. A display using the present invention for the power supply circuit of the display unit 13602 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

FIG. 30 (H) is a mobile phone, which includes a main body 13701, a housing 13702, a display unit 13703, a voice input unit 13704, a voice output unit 13705, an operation key 13706, an external connection port 13707, an antenna 13708, and the like. A display using the present invention for the power supply circuit of the display unit 13703 can reduce malfunction due to noise. As a result, display unevenness can be suppressed.

As described above, the present invention can be applied to any electronic device.

In this embodiment, the mask layout of the diode-connected transistors 1708 and 1709 having the configuration shown in FIG. 21 of the fourth embodiment will be described with reference to FIG. 29.

The transistor 2912 shown in FIG. 29 corresponds to the transistor 1709 located at the end of the last row of the current source circuit 1712 shown in FIG. 18, and the transistor 2913 corresponds to the transistor 1708 located at the end of the last row of the current source circuit 1712. The transistor 2912 shown in this embodiment has a semiconductor layer 2904, a gate electrode 2905, a source electrode 2907, and a drain electrode 2906. The gate electrode 2905 and the source electrode 2907 are connected via a contact hole. Further, the drain electrode 2906 is connected to the high potential (VDD) power line 2902 via a contact hole. The gate electrode 2905 has a so-called double gate structure, and one gate width is 6 μm. That is, the channel length of the transistor 2912 is 12 μm. And the channel width is 10 μm.

Transistor 2913 has a semiconductor layer 2908, a gate electrode 2909, a source electrode 2910, and a drain electrode 2911. The gate electrode 2909 and the source electrode 2910 are connected via a contact hole. Further, the drain electrode 2906 is connected to the low potential (GND) power line 2901 via a contact hole. The gate electrode 2909 has a so-called double gate structure, and one gate width is 6 μm. That is, the channel length of the transistor 2913 is 12 μm. And the channel width is 100 μm.

The source electrode 2907 of the transistor 2912, the drain electrode 2911 of the transistor 2913, and the wiring 2903 are formed by patterning the same conductive film, and are continuous.

Then, when noise is added to the wiring 2903 and the potential exceeds the normal range, a current flows through the transistors 2912 and 2913 so as to return the potential of the wiring 2903 to the normal range. That is, when the potential of the wiring 2903 is higher than the high potential (VDD) power line 2902, a current flows through the transistor 2912. That is, the transistor 2912 has the function of returning the potential of the wiring 2903 to the potential of VDD. On the other hand, when the potential of the wiring 2903 becomes lower than the low potential (GND) power line 2901, a current flows through the transistor 2913. That is, the transistor 2913 has the function of returning the potential of the wiring 2903 to the potential of GND.

The mask layout diagram of this embodiment shows an example, and the present invention is not limited thereto.

Further, the cross section between the broken lines AB shown in FIG. 29 is shown in FIG. 50 (a), and the cross section between the broken lines CD is shown in FIG. 50 (b).

It has a base film 5002 on the substrate 5001. As the substrate 5001, an insulating substrate such as a glass substrate, a quartz substrate, a plastic substrate, a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used. The base film 5002 can be formed by a CVD method or a sputtering method. For example SiH₄, N₂O, NH₃A silicon oxide film, a silicon nitride film, a silicon nitride film, or the like formed by a CVD method using the above as a raw material can be applied. Moreover, you may use these layers. The base film 5002 is provided to prevent impurities from diffusing from the substrate 5001 into the semiconductor layer, and when a glass substrate or a quartz substrate is used for the substrate 5001, the base film 5002 may not be provided.

It has an island-shaped semiconductor layer on the base film 5002. A channel formation region 5003 in which an N-type channel is formed, an impurity region 5004 which is a source region or a drain region of an N-type transistor, a low-concentration impurity region (LDD region) 5005, and a P-type channel are formed in the semiconductor layer. A channel forming region 5011 and an impurity region 5012 serving as a source region or a drain region of a P-type transistor are formed. Then, a gate electrode 5007 is formed on the channel forming region 5003 and the channel forming region 5011 via the gate insulating film 5005. It also has a first wire 5014 and a second wire 5015 extended from the gate electrode 5007. As the gate insulating film 5006, a silicon oxide film, a silicon nitride film, a silicon nitride film formed by a CVD method or a sputtering method can be used. The gate electrode 5007, the first wiring 5014, and the second wiring 5015 include an aluminum (Al) film, a copper (Cu) film, a thin film containing aluminum or copper as a main component, a chromium (Cr) film, and tantalum (Ta). ) Film, tantalum nitride (TaN) film, titanium (Ti) film, tungsten (W) film, molybdenum (Mo) film and the like can be used.

A sidewall 5008 is formed beside the gate electrode 5007. After forming a silicon compound, for example, a silicon oxide film, a silicon nitride film, or a silicon oxide nitride film so as to cover the gate electrode 5007, the sidewall 5008 can be formed by etching back.

The LDD area 5005 is located below the sidewall 5008. That is, the LDD region 5005 is formed in a self-aligned manner.

An interlayer insulating film 5009 is provided on the gate electrode 5007, the first wiring 5014, the second wiring 5015, the sidewall 5008, and the gate insulating film 5006. The interlayer insulating film 5009 has an inorganic insulating film in the lower layer and a resin film in the upper layer. As the inorganic insulating film, a silicon nitride film, a silicon oxide film, a silicon oxide film, or a film obtained by laminating these can be used. As the resin film, polyimide, polyamide, acrylic, polyimideamide, epoxy or the like can be used.

Further, a third wiring 5010 and a fourth wiring 5013 are provided on the interlayer insulating film 5009. The third wiring 5010 is electrically connected to the impurity region 5004 via a contact hole. Further, the third wiring 5010 is connected to the impurity region 5004 and the first wiring 5014 via a contact hole. Further, the fourth wiring 5013 is connected to the impurity region 5012 and the second wiring 5015 via a contact hole. Further, as the third wiring 5010 and the fourth wiring 5013, a titanium (Ti) film, an aluminum (Al) film, a copper (Cu) film, an aluminum film containing Ti, or the like can be used. When wiring such as a signal line is provided in the same layer as the third wiring 5010 and the fourth wiring 5013, it is preferable to use low resistance copper.

In this embodiment, the configuration of the display panel of the display device having the current source circuit of the present invention as a pixel or a part of the signal line drive circuit will be described with reference to FIGS. 46 (a) and 46 (b).

FIG. 46 (a) is a top view showing a display panel, and FIG. 46 (b) is a cross-sectional view of FIG. 46 (a) cut along an A-A'. It has a signal line drive circuit 4601 shown by a dotted line, a pixel unit 4602, and a scanning line drive circuit 4606. Further, it has a sealing substrate 4604 and a sealing material 4605, and the inside surrounded by the sealing material 4605 is a space 4607.

The wiring 4608 is a wiring for transmitting a signal input to the scanning line driving circuit 4606 and the signal line driving circuit 4601, and is a video signal, a clock signal, and a video signal and a clock signal from the FPC (flexible print circuit) 4609 which is an external input terminal. Receives a start signal, etc. An IC chip (semiconductor chip in which a memory circuit, a buffer circuit, etc. are formed) 4646 is mounted on the junction between the FPC 4609 and the display panel by COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The display device in the present specification includes not only the display panel main body but also a state in which an FPC or PWB is attached to the display panel main body. In addition, it shall include those on which an IC chip or the like is mounted.

Next, the cross-sectional structure will be described with reference to FIG. 46 (b). A pixel unit 4602 and its peripheral drive circuits (scanning line drive circuit 4606 and signal line drive circuit 4601) are formed on the substrate 4610. Here, the signal line drive circuit 4601 and the pixel unit 4602 are shown. There is.

The signal line drive circuit 4601 is composed of unipolar transistors such as the N-channel type TFT4620 and the N-channel type TFT4621. The scanning line drive circuit 4606 is also preferably composed of N-channel transistors. By applying the pixel configuration of the present invention to the pixel configuration, a unipolar transistor can be formed, so that a unipolar display panel can be manufactured. Further, in the present embodiment, a display panel in which a peripheral drive circuit is integrally formed on a substrate is shown, but it is not always necessary, and all or a part of the peripheral drive circuit is formed on an IC chip or the like and mounted by COG or the like. You may. In that case, the drive circuit does not need to be unipolar and can be used in combination with P-channel transistors.

Further, the pixel unit 4602 has a plurality of circuits constituting pixels including a switching TFT 4611 and a driving TFT 4612. The source electrode of the drive TFT 4612 is connected to the first electrode 4613. Further, an insulator 4614 is formed so as to cover the end portion of the first electrode 4613. Here, it is formed by using a positive type photosensitive acrylic resin film.

Further, in order to improve the coverage, a curved surface having a curvature is formed at the upper end or the lower end of the insulator 4614. For example, when positive photosensitive acrylic is used as the material of the insulator 4614, it is preferable that only the upper end of the insulator 4614 has a curved surface having a radius of curvature (0.2 μm to 3 μm). Further, as the insulator 4614, either a negative type that becomes insoluble in the etchant by photosensitive light or a positive type that becomes soluble in the etchant by light can be used.

A layer 4616 containing an organic compound and a second electrode 4617 are formed on the first electrode 4613, respectively. Here, it is desirable to use a material having a large work function as the material used for the first electrode 4613 that functions as an anode. For example, in addition to single-layer films such as ITO (indium tin oxide) film, indium zinc oxide (IZO) film, titanium nitride film, chromium film, tungsten film, Zn film, and Pt film, titanium nitride and aluminum are the main components. A three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film can be used. In addition, when the laminated structure is used, the resistance as wiring is low, good ohmic contact can be obtained, and the structure can further function as an anode.

Further, the layer 4616 containing the organic compound is formed by a vapor deposition method using a vapor deposition mask or an inkjet method. For the layer 4616 containing the organic compound, a metal complex of Group 4 of the Periodic Table of the Elements is used as a part thereof, and other materials that can be used in combination are polymer materials even if they are low molecular materials. It may be. Further, as the material used for the layer containing the organic compound, the organic compound is usually used as a single layer or in a laminated state, but in the present embodiment, the inorganic compound is used as a part of the film made of the organic compound. Will also be included. Furthermore, it is also possible to use a known triplet material.

Further, as the material used for the second electrode (cathode) 4617 formed on the layer 4616 containing the organic compound, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof (MgAg, MgIn,) AlLi, CaF₂, Or CaN) may be used. When the light generated in the layer 4616 containing the organic compound is transmitted through the second electrode 4617, the second electrode (cathode) 4617 is a thin metal thin film and a transparent conductive film (ITO (ITO). Indium tin oxide alloy), indium zinc oxide alloy (In₂O₃-It is better to use a laminate with (ZnO), zinc oxide (ZnO), etc.).

Further, by bonding the sealing substrate 4604 with the substrate 4610 with the sealing material 4605, the light emitting element 4618 is provided in the space 4607 surrounded by the substrate 4610, the sealing substrate 4604, and the sealing material 4605. In addition to the case where the space 4607 is filled with an inert gas (nitrogen, argon, etc.), the space 4607 also includes a configuration in which the space 4607 is filled with the sealing material 4605.

It is preferable to use an epoxy resin for the sealing material 4605. Further, it is desirable that these materials are materials that do not allow moisture or oxygen to permeate as much as possible. Further, as a material used for the sealing substrate 4604, in addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester, acrylic or the like can be used.

As described above, a display panel having the pixel configuration of the present invention can be obtained.

Although the configuration in which the pixel portion and the peripheral drive circuit are integrally formed when a crystalline semiconductor (for example, polysilicon (P-Si: H)) is applied to the semiconductor layer of the pixel portion has been described, the current source circuit of the present invention has been described. The display device included in the pixel portion or a part of the signal line drive circuit can also apply an amorphous semiconductor (for example, amorphous silicon (a-Si: H)) to the semiconductor of the pixel portion. In that case, as shown in FIG. 45, the pixel portion 4502 is formed on the substrate 4500 and sealed by the substrate 4500 and the sealing substrate 4508 using the sealing material 4509. In addition, peripheral drive circuits (signal line drive circuit 4501 and scanning line drive circuit 4504) are formed on an IC chip and mounted on a substrate by COG or the like. Also, connect the board 4500 and FPC. By mounting the IC chips 4506 and 4507 on the joint between the substrate 4500 and the FPC 4505, the frame can be narrowed.

The partial cross-sectional view of the pixel portion when a non-crystalline semiconductor is applied to the semiconductor layer of the pixel portion is shown below.

FIG. 47 shows the case of the top gate transistor, and FIGS. 48 and 49 show the case of the bottom gate transistor.

FIG. 47 (a) shows a cross section of a transistor having a top gate structure using an amorphous semiconductor as a semiconductor layer. As shown in, the base film 4702 is formed on the substrate 4701. Further, a pixel electrode 4703 is formed on the base film 4702. Further, a first electrode 4704 made of the same material is formed in the same layer as the pixel electrode 4703.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. The base film 4702 includes aluminum nitride (AlN) and silicon oxide (SiO).₂), Silicon oxide (SiO)_xN_y) And other single layers or laminates of these can be used.

Further, the wiring 4705 and the wiring 4706 are formed on the base film 4702, and the end portion of the pixel electrode 4703 is covered with the wiring 4705. An N-type semiconductor layer 4707 and an N-type semiconductor layer 4708 having an N-type conductive type are formed on the wiring 4705 and the wiring 4706. Further, a semiconductor layer 4709 is formed on the base film 4702 between the wiring 4706 and the wiring 4705. A part of the semiconductor layer 4709 extends onto the N-type semiconductor layer 4707 and the N-type semiconductor layer 4708. This semiconductor layer is formed of a non-crystalline semiconductor film such as amorphous silicon (a-Si: H) and microcrystalline semiconductor (μ-Si: H). Further, a gate insulating film 4710 is formed on the semiconductor layer 4709. In addition, an insulating film 4711 made of the same material as the gate insulating film 4710 is also formed on the first electrode 4704. As the gate insulating film 4710, a silicon oxide film, a silicon nitride film, or the like is used.

Further, a gate electrode 4712 is formed on the gate insulating film 4710. Further, a second electrode 4713 made of the same material as the gate electrode is formed on the first electrode 4704 via an insulating film 4711. A capacitive element 4719 in which an insulating film 4711 is sandwiched between the first electrode 4704 and the second electrode 4713 is formed. Further, an interlayer insulating film 4714 is formed by covering the end of the pixel electrode 4703, the drive transistor 4718 and the capacitive element 4719.

A region in which a layer 4715 containing an organic compound and a counter electrode 4716 are formed on the interlayer insulator 4714 and the pixel electrode 4703 located at the opening thereof, and the layer 4715 containing an organic compound is sandwiched between the pixel electrode 4703 and the counter electrode 4716. Then, the light emitting element 4717 is formed.

Further, the first electrode 4704 shown in FIG. 47 (a) may be formed by the first electrode 4720 as shown in FIG. 47 (b). The first electrode 4720 is made of the same material in the same layer as the wirings 4705 and 4706.

Further, FIG. 48 shows a partial cross section of a display panel using a transistor having a bottom gate structure using an amorphous semiconductor as a semiconductor layer.

A base film 4802 is formed on the substrate 4801. Further, a gate electrode 4803 is formed on the base film 4802. Further, a first electrode 4804 made of the same material is formed in the same layer as the gate electrode. Polycrystalline silicon to which phosphorus has been added can be used as the material for the gate electrode 4803. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

Further, a gate insulating film 4805 is formed so as to cover the gate electrode 4803 and the first electrode 4804. As the gate insulating film 4805, a silicon oxide film, a silicon nitride film, or the like is used.

Further, a semiconductor layer 4806 is formed on the gate insulating film 4805. Further, a semiconductor layer 4807 made of the same material is formed on the same layer as the semiconductor layer 4806.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. The base film 4802 includes aluminum nitride (AlN) and silicon oxide (SiO).₂), Silicon oxide (SiO)_xN_y) And other single layers or laminates of these can be used.

N-type semiconductor layers 4808 and 4809 having N-type conductivity are formed on the semiconductor layer 4806, and N-type semiconductor layers 4810 are formed on the semiconductor layer 4807.

Wiring 4811 and 4812 are formed on the N-type semiconductor layers 4808, 4809 and 4810, respectively, and a conductive layer 4813 made of the same material as the wiring 4811 and 4812 is formed on the N-type semiconductor layer 4810.

A second electrode composed of a semiconductor layer 4807, an N-type semiconductor layer 4810, and a conductive layer 4813 is configured. A capacitive element 4820 having a structure in which a gate insulating film 4802 is sandwiched between the second electrode and the first electrode 4804 is formed.

Further, one end of the wiring 4811 extends, and the pixel electrode 4814 is formed in contact with the upper portion of the extending wiring 4811.

Further, an insulator 4813 is formed so as to cover the end of the pixel electrode 4814, the drive transistor 4819, and the capacitive element 4820.

A layer 4816 containing an organic compound and a counter electrode 4817 are formed on the pixel electrode 4814 and the insulator 4815, and a light emitting element 4818 is formed in a region where the layer 4816 containing an organic compound is sandwiched between the pixel electrode 4814 and the counter electrode 4817. Has been done.

The semiconductor layer 4807 and the N-type semiconductor layer 4810, which are a part of the second electrode of the capacitive element, need not be provided. That is, the second electrode may be the conductive layer 4813, and may be a capacitive element having a structure in which the gate insulating film is sandwiched between the first electrode 4804 and the conductive layer 4813.

In addition, in FIG. 48 (a), by forming the pixel electrode 4814 before forming the wiring 4811, as shown in FIG. 48 (b), the second electrode 4821 and the first electrode composed of the pixel electrode 4814 are formed. A capacitive element 4822 having a structure in which a gate insulating film 4805 is sandwiched between 4804 can be formed.

Although FIG. 48 shows a transistor having an inverted staggered channel-etch structure, it may of course be a transistor having a channel protection structure. The case of a transistor having a channel protection structure will be described with reference to FIGS. 49 (a) and 49 (b).

The transistor of the channel protection type structure shown in FIG. 49 (a) is an insulator 4901 that serves as an etching mask on the region where the channel of the semiconductor layer 4806 of the drive transistor 4819 of the channel etch structure shown in FIG. 48 (a) is formed. The difference is that is provided, and the common code is used for other common points.

Similarly, the transistor of the channel protection type structure shown in FIG. 49 (b) has an etching mask on the region where the channel of the semiconductor layer 4806 of the drive transistor 4819 of the channel etch structure shown in FIG. 48 (b) is formed. The difference is that the insulator 4901 is provided, and the other common points are the same code.

By using an amorphous semiconductor film for the semiconductor layer (channel forming region, source region, drain region, etc.) of the transistor constituting the pixel of the present invention, the manufacturing cost can be reduced.

The structure of the transistor to which the pixel configuration of the present invention can be applied and the structure of the capacitive element are not limited to the above-mentioned configurations, and the structure of the transistor having various configurations and the structure of the capacitive element can be used. ..

<figref num="1">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="2">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="3">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="4">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="5">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="6">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="7">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="8">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="9">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="10">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="11">The figure explaining the operation of the current source circuit of this invention.</figref><figref num="12">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="13">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="14">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="15">The figure explaining the structure of the display device of this invention.</figref><figref num="16">The figure explaining the structure of the display device of this invention.</figref><figref num="17">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="18">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="19">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="20">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="21">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="22">The figure explaining a part of the structure of the signal line drive circuit of this invention.</figref><figref num="23">The figure explaining the structure of the pixel of this invention.</figref><figref num="24">The figure explaining the structure of the pixel of this invention.</figref><figref num="25">The figure explaining the structure of the pixel of this invention.</figref><figref num="26">The figure explaining the structure of the pixel of this invention.</figref><figref num="27">The figure explaining the structure of the pixel of this invention.</figref><figref num="28">The schematic diagram of the display device of this invention.</figref><figref num="29">The mask layout figure of the diode connection transistor which can apply to this invention.</figref><figref num="30">The figure explaining the electronic device to which this invention is applied.</figref><figref num="31">The figure explaining the structure of the conventional pixel.</figref><figref num="32">The figure explaining the structure of the conventional pixel.</figref><figref num="33">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="34">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="35">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="36">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="37">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="38">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="39">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="40">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="41">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="42">The figure explaining the structure of the current source circuit of this invention.</figref><figref num="43">The figure which shows the potential detection circuit which can apply to this invention.</figref><figref num="44">The figure which shows the potential detection circuit which can apply to this invention.</figref><figref num="45">The figure explaining the display device of this invention.</figref><figref num="46">The figure explaining the display panel of this invention.</figref><figref num="47">Partial sectional view of a pixel part.</figref><figref num="48">Partial sectional view of a pixel part.</figref><figref num="49">Partial sectional view of a pixel part.</figref><figref num="50">Partial sectional view of a diode connection transistor.</figref>