Optimized switching configurations for reconfigurable arrays of sensor elements

The invention generally relates to a reconfigurable array of sensors (eg, optical, thermal, pressure, ultrasound). More specifically, the present invention relates to reconfigurable micromachined ultrasonic transducer (MUT) arrays. One particular use for MUT is in medical diagnostic ultrasound imaging systems. Another particular example is for non-destructive evaluation (NDE) of members such as castings, forgings or pipelines.

Conventional ultrasound imaging systems have an array of ultrasound transducers used to deliver the ultrasound beam and receive the reflected beam from the object being inspected. Such scans include a series of measurements, in which focused ultrasound is delivered and the system is switched to receive mode after a short time interval to receive reflected ultrasound, form a beam, and for display. To process. Typically, transmissions and receptions are focused in the same direction during each measurement to obtain data from a series of points along the acoustic beam or scan line. The receiver continuously refocuses along the scan line when receiving the reflected ultrasound.

For ultrasound imaging, the array typically has a large number of transducers arranged in a row or rows, which are driven by separate voltages during transmission. By selecting the time delay (or phase) and amplitude of the applied voltage, the individual transducers can each be controlled to generate ultrasonic waves, which in combination are along the preferred vector direction. It forms a net ultrasound that travels and is focused in a selected area along the beam.

The same principle applies when the transducer probe is used to receive reflected sound waves in receive mode. The voltage generated by the receiving transducer is added so that the net signal represents the ultrasound reflected from a single focal area within the object. As in the transmit mode, this focused reception of ultrasonic energy is achieved by giving the signals from each receiving transducer a separate time delay (and / or phase shift) and gain. The time delay is adjusted as the depth of the reflected signal increases to provide dynamic focusing on reception.

The quality or resolution of the image formed is, in part, a function of the number of transducers that make up the transmit and receive apertures of the transducer array, respectively. Therefore, in order to obtain high image quality, it is desirable to provide a large number of transducers for both 2D and 3D imaging applications. Typically, the ultrasonic transducer is placed inside a handheld transducer probe, the probe is connected to the electronic device unit by a flexible cable, and the electronic device unit processes the transducer signal to generate an ultrasonic image. To do. The ultrasonic probe can support both an ultrasonic transmitting circuit and an ultrasonic receiving circuit.

The reconfigurable ultrasonic array can dynamically connect multiple groups of subelements so that the shape of the resulting element can be made to match the shape of the crest. This can improve performance and / or reduce the number of channels. Such reconfigurability can be achieved using switching networks.

Little research has been directed to algorithms to improve the performance of switching networks required for beam formation. However, switching or multiplexing has been used in some situations where reconfigurability is severely limited. Examples of this include multiplexing for synthetic apertures to increase aperture size, multiplexing used for scanning in multi-row arrays, and linear arrays. In all of these cases, the reconfigurable nature is extremely limited, avoiding the need for optimizing the switching network.

In recent years, the use of semiconductor processing technology has produced a type of ultrasonic transducers known as micromachined ultrasonic transducers (MUTs), which are capacitive (cMUT) or piezoelectric (pMUT). It's okay. A MUT is a small diaphragm-like device with electrodes that convert the acoustic vibration of a received ultrasonic signal into a modulated capacitance. In the case of transmission, the capacitive charge is modulated to vibrate the diaphragm of the device, which delivers sound waves. One advantage of MUTs is that they can be made using semiconductor manufacturing processes such as microfabrication processes, which are grouped under the item "micromachining". The system resulting from such a micromachining process is typically referred to as a micromachining electromechanical system (MEMS).

The cMUT is usually a hexagonal structure with a diaphragm extending across it. This diaphragm is held close to the substrate surface by the applied bias voltage. By applying a vibration signal to this already biased cMUT, the diaphragm can be vibrated, which can radiate acoustic energy. Similarly, when an acoustic wave enters the diaphragm, the resulting vibration can be detected as a voltage change on the cMUT. "CMUT cell" is a term that describes one of the hexagonal "drum" structures described above. The cMUT cell can have a very small structure. Typical cell dimensions are 25-50 microns between the flat edges of the hexagon. The dimensions of the cell are variously dictated by the designed acoustic response. It may not be possible to make larger cells that work well with respect to the desired frequency response and sensitivity.

Unfortunately, it is difficult to make an electronic device capable of individual control for such a small cell as described above. In terms of the acoustic performance of the array as a whole, small sized cells are excellent and flexible, but control is limited to larger structures. By grouping multiple cells together and connecting them electrically, it is possible to generate larger partial elements, which can be individually controlled while maintaining the desired acoustic response. Therefore, a partial element is a group of electrically connected cells and cannot be reconstructed. For the purposes of the disclosure in this document, a subelement is the smallest independently controlled acoustic unit. Thereby, a ring or an element can be formed by connecting a plurality of partial elements together using a switching network. Therefore, the element Can be reconstructed by changing the state of the switching network. However, the partial element is composed of connected cells that cannot be separated by a switch and therefore cannot be reconstructed. If the array is manufactured with PZT or some other more common or future transducer technology, all of the following analyzes are also valid.

Reconstructability with the use of silicon-based ultrasonic transducer subelements is described in US Patent Application No. 10/383990. One form of reconfigurable form is a mosaic annular array, which is also described in the patent. The concept of a mosaic annular array involves constructing an annular element by grouping multiple subelements together using a reconfigurable electronic switching network. The goal is to reduce the number of beam forming channels while maintaining image quality and improving slice thickness. To reduce system channels, the mosaic annular array takes advantage of the fact that the contour of the delay on the surface of the underlying 2D transducer array is circular when the beam is not steered. In other words, the equal delay curve becomes a ring around the center of the beam. This circular symmetry of delay allows for clear grouping of subelements with a common delay and also provides the concept of an annular array. Reconstructibility can be utilized to step the beam along a larger underlying two-dimensional transducer array to scan or form an image. Reconfigurability can also be utilized to improve performance for multiplex transmission applications by allocating multiple channels with smaller active apertures in the near field. The usefulness of reconfigurable properties can also be demonstrated in a number of other applications.<patcit num="1"><text>U.S. Pat. No. 6733454</text></patcit><patcit num="2"><text>WO2004 / 079654</text></patcit>

<p> Reconfigurable ultrasonic arrays require complex switching networks that are difficult or impossible to embody with currently available electronic devices. Therefore, a simplified switching network that maintains optimum performance by carefully selecting the switching configuration is required.</p>

<p> The present invention relates to reconfigurable sensor arrays and methods for optimizing switching configurations for such arrays (ie, maximizing the performance of such arrays). The sensor may be an optical sensor, a thermal sensor, a pressure sensor or an ultrasonic transducer. In the embodiments disclosed herein, a two-dimensional array of capacitive micromachined ultrasonic transducers (cMUTs) is used as the underlying grid for constructing larger devices. However, the present invention is not limited to cMUT structures and is equally applicable to other conventional or future transducer techniques.</p><p> One aspect of the present invention is a method for embodying a switching configuration that minimizes errors introduced by the switch network during control of a reconfigurable sensor element array. The method was derived from the steps of (a) generating the initial switching configuration, (b) (i) the switching network error, the initial switching configuration input at the start, and the subsequent input one after another. The stage of inputting a switch configuration into a system model that calculates the response of the system taking into account all of the modified switching configurations, (ii) using the model with the input switch configuration to generate an image or radiation pattern. Steps, (iii) the step of calculating the value for the cost function based at least in part on the data representing the generated pattern, (iv) whether the calculated value substantially represents the minimum value for the cost function. These steps include the step of determining and (v) modifying the current switching configuration as a function of the result of the value calculation to reach the modified switching configuration if the calculated value is not the minimum value for the cost function. Switching between the stage of executing an iterative algorithm that repeats i) to (v) for each switching configuration and (c) a modified switching configuration that minimizes the value of the cost function when the calculated value is the minimum value for the cost function. It has a stage of constructing a network.</p><p> Another aspect of the invention is a method for embodying a switching configuration that minimizes errors introduced by the switch network during control of a reconfigurable sensor element array. The method consists of (a) generating an initial switching configuration and (b) (i) inputting the switch configuration to the system, where the initial switching configuration is input at the start and is subsequently derived. The value for the cost function based on the stage where the modified switching configurations are input one after another, (ii) the stage where the input switch configuration determines the performance of the system, and (iii) the stage where the determined performance of the system is at least partially based. The stage of calculating, (iv) the stage of determining whether the calculated value substantially represents the minimum value for the cost function, and (v) the stage of calculating the value if the calculated value is not the minimum value for the cost function. As a function of the result, the current switching configuration is modified to include the stage of reaching the modified switching configuration, and these stages (i) to (v) are repeated for each switching configuration to carry out an iterative algorithm, and (c) calculation. When the value obtained is the minimum value for the cost function, the switching network is configured by a modified switching configuration in which the value of the cost function is minimized.</p><p> Yet another aspect of the present invention is a method of operating an ultrasonic imaging system having an array of ultrasonic transducer elements that can be reconstructed by controlling the respective states of the switches in the switch network. , (A) the stage of optimizing the first switching configuration for use in the first operating state of the ultrasound imaging system, and (b) the second for use in the second operating state of the ultrasound imaging system. It has two stages of optimizing the switching configuration, and these optimizing stages include using an iterative algorithm to minimize the cost function.</p><p> Yet another aspect of the present invention is a method of operating an ultrasonic imaging system having an array of ultrasonic transducer elements that can be reconfigured by controlling the respective states of the switches in the switch network. (A) The step of optimizing the first switching configuration for use in the first operating state of the ultrasound imaging system by using the first iterative algorithm to minimize the first cost function. And (b) the step of optimizing the second switching configuration for use in the second operating state of the ultrasound imaging system by using a second iterative algorithm to minimize the second cost function. The second cost function is different from the first cost function.</p><p> Yet another aspect of the present invention is a method of operating an ultrasonic imaging system having an array of ultrasonic transducer elements that can be reconstructed by controlling the respective states of the switches in the switch network. , (A) the step of optimizing the first switching configuration to set the first aperture with the first set of selected ultrasonic transducer elements, and (b) the second set of selected ultrasonic transducer elements. The beam center of the second aperture is relative to the beam center of the first aperture, including the step of optimizing the second switching configuration to set the second aperture with the ultrasonic transducer element 1 Step forward in increments of fractions.</p><p> Other aspects of the invention are disclosed and claimed below.</p><p> In the drawings referenced in the following description, similar elements in the various drawings are given the same reference numbers.</p>

The present invention is directed to reconfigurable switching matrices and methods for optimizing switching configurations for such matrices and their associated sensor element arrays. For illustrative purposes, reconfigurable arrays and optimization methods will be described for capacitive micromachining ultrasonic transducers (cMUTs). However, it is understood that the various aspects of the invention disclosed herein are not limited to probes using cMUT in their applications, but rather can be applied to probes using pMUT or even diced piezoelectric ceramic arrays. I want to be. In that case, each of the diced partial elements is connected to the lower switching layer by an interconnect means. The same aspects of the invention also apply to reconfigurable arrays of optical, thermal or pressure sensors.

FIG. 1 shows a typical cMUT transducer cell 2 in cross section. Arrays of such cMUT transducer cells are typically manufactured on a substrate 4 such as a heavily doped silicon (and thus semiconductor) wafer. In each cMUT transducer cell, a thin membrane or diaphragm 8 made of silicon nitride is suspended above the substrate 4. The peripheral edge of the film 8 is supported by the insulating support 6, and the insulating support 6 can be made of silicon oxide or silicon nitride. The cavity 14 between the membrane 8 and the substrate 4 can be filled with air or gas, or can be completely or partially evacuated. Typically, the cMUT is evacuated as completely as the process allows. Forming an electrode 12 on a film 8 with a film or layer of a conductive material such as an aluminum alloy or other suitable conductive material, and forming an electrode 10 on a substrate 4 with a film or layer made of a conductive material. Can be done. Instead, the bottom electrode can be formed by proper doping of the semiconductor substrate 4.

The two electrodes 10 and 12 separated by the cavity 14 form a capacitance. When the membrane 8 vibrates due to an incident acoustic signal, associated electrodes can be used to detect capacitance fluctuations (not shown in FIG. 1), which converts the acoustic signal into an electrical signal. Conversely, when an AC signal is applied to one of the electrodes, it modulates the charge on the electrodes, which modulates the electrostatic force between the electrodes, which moves the diaphragm to send out an acoustic signal.

Each cell can have a round, rectangular, hexagonal or peripheral shape. The hexagon allows tight packing of the cMUT cell of the transducer subelement. The cMUT cell can have different dimensions, just as a transducer sub-element has a composite characteristic of different cell dimensions, which makes the transducer broadband characteristic.

Unfortunately, it is difficult to make an electronic device that can individually control such a small cell. In terms of the acoustic performance of the array as a whole, small sized cells are excellent and flexible, but control is limited to larger structures. By grouping multiple cells together and connecting them electrically, it is possible to generate larger partial elements, which can be individually controlled while maintaining the desired acoustic response. Rings or elements can be formed by connecting multiple subelements together using a switching network. Therefore, the element can be reconstructed by changing the state of the switching network. However, individual partial elements cannot be reconfigured to form different partial elements.

Multiple MUT cells can be connected together (without intervening switches) in the micromachining process to form partial elements. In the following description, the term "acoustic component" is used to describe such a group. These acoustic components are interconnected by microelectronic switches that are larger by placing such switches in a silicon layer or on different substrates provided immediately adjacent to the transducer array. To form.

As used herein, the term "acoustic component" is a single cell, or a group of electrically connected cells that cannot be reconstructed. That is, the partial element is the smallest independently controlled acoustic unit. Further, the term "partial element" means an acoustic partial element and its related integrated electronic device. Further, the "element" is formed by connecting a plurality of partial elements together using a switching network. The element can be reconstructed by changing the state of the switching network. At least some of the switches included in the switching network are part of the "related integrated electronics", as described in more detail below.

For illustrative purposes, FIG. 2 shows a "daisy" transducer subelement 16 consisting of seven hexagonal cMUT cells 2, with the central cell surrounded by a ring of six cells and each cell within the ring. Is adjacent to each side of the central cell and adjacent cells in the ring. The top electrode 12 of each cMUT cell 2 is electrically coupled together by a connection that cannot be cut by a switch. In the case of a hexagonal array, six conductors radiate from the top electrode 12 and are connected to the top electrode of the adjacent cMUT cell (but not six) in the peripheral cells. Connected to one other cell). Similarly, the bottom electrodes 10 of each cell 2 are electrically coupled together by a connection that cannot be cut by a switch, forming a capacitive transducer component 16 that is seven times larger.

The types of subelements seen in FIG. 2 can be arranged to form a two-dimensional array on a semiconductor (eg, silicon) substrate. These partial elements can be reconfigured to form an annular ring-like element using a switching network. Reconstructability with the use of silicon-based ultrasonic transducer subelements is described in US Patent Application No. 10/383990. One form of reconfigurable form is a mosaic annular array, which is also described in the patent. The concept of a mosaic annular array involves constructing an annular element by grouping multiple subelements together using a reconfigurable electronic switching network. The goal is to reduce the number of beam forming channels while maintaining image quality and improving slice thickness. To reduce system channels, the mosaic annular array takes advantage of the fact that the contour of the delay on the surface of the underlying 2D transducer array is circular when the beam is not steered. In other words, the equal delay curve becomes a ring around the center of the beam. This circular symmetry of delay allows for clear grouping of subelements with a common delay. Reconstructibility can be utilized to traverse the beam along a larger underlying 2D transducer array to scan or form an image.

There are numerous methods in which transducer arrays can be formed using MUT cells and acoustic components. FIG. 3 shows an example of mosaic work of acoustic partial elements forming a mosaic array. In the embodiment shown in FIG. 3, four substantially annular elements (represented by reference numerals 18A to 18D, respectively) are configured to have approximately equal areas per element, and each element has a "daisy" shape. Has a mosaic of acoustic partial elements (each partial element consists of seven together-connected MUT cells). Mosaic work in each case can be made from multiple types of partial elements. The array pattern does not have to be mosaic and can have areas without acoustic components. For example, a via (through connection path) may be provided to bring the acoustic partial element or the top electrode connection portion of the cell under the array.

The configuration of the present invention can be modified to optimize various acoustic parameters such as beam width, side lobe level, or depth of focus. Alternatively, the acoustic components may be grouped to form one aperture for the transmitting operation and immediately switched to another opening for the receiving operation. Although FIG. 3 shows a portion of each of the plurality of nearly annular elements, it can be configured in other shapes, such as a discontinuous ring, an octagonal ring, or an arc. The choice of pattern depends on the requirements of the application.

Most openings form a single larger element, such as the annular elements shown in FIG. 3 consists of successive grouped subelements which are sea urchin interconnected. In this case, it is not necessary to connect each of all the subelements directly to their respective bus lines. It suffices to connect a limited number of partial elements within a given group and then connect the remaining partial elements to each other. In this way, the transmitted signal propagates from the system along the bus line into elements along a limited number of access points. From there, the signal spreads within the device via local connections.

Given a particular geometry, the reconfigurable array maps acoustic components to system channels. This mapping is designed to improve performance. Mapping is done via a switching network, ideally placed directly in the board on which the cMUT cells are created, but on different boards integrated adjacent to the transducer board. be able to. Since the cMUT array is built directly on a silicon substrate, switching electronics can be incorporated on that substrate. For PZT or more traditional implementations, the switch network may be easy to manufacture on a separate silicon substrate and mounted on a PZT array.

FIG. 4 shows a cross-sectional view of a co-integrated cMUT and ASIC array to illustrate how to make an ASIC to cMUT connection. As shown, one via 56 is used to connect each cMUT sub-element 32 to its corresponding CMOS sub-element (or cell) 50. These vias 56 connect the signal electrode 65 to each conductive pad 66 formed on the ASIC of the switch and can be embedded in the acoustic backing layer 62.

It is also possible to form cMUTs on separate wafers and connect them separately to the ASIC switch matrix, as shown in FIG. In this case, for example, solder bumps 64 and conductive pads 66 are used to connect the individual cMUT partial elements 32 to their corresponding switch electronics 50. Other mounting techniques such as anisotropic conductive film (ACF) or flexible interconnect means may also be used.

For optimum packing density, tile the cMUT subelement 32 and related electronics on a hexagonal grid, as illustrated in Figure 6 (which shows the top view of the ASIC switch matrix). It is useful to stretch. In this case, the CMOS unit switch cells 50 are arranged in columns, and every other column is arranged so as to be offset by half the height of the cells. This results in a complete hexagonal array of pads 66, as shown, when the cell dimensions are properly selected. The vias 56, which are also arranged in a hexagonal array, then each pad (shown in FIG. 4) that forms the basis for the connection to the upper transducer layer with the hexagonal array of subelements. Not connected to). A more direct example of ASIC implementation is illustrated in Figure 7. In this case, the CMOS unit switch cells 50 are arranged in horizontal rows and vertical columns to form a rectangular grid, and the hexagonal subelements 32 above them form a hexagonal grid. As shown in FIG. 7, the unit switch cell pads 66 are arranged vertically and horizontally to form a rectangular array, and the unit switch cells 50 are electrically connected to the respective hexagonal partial elements 32. It is still properly aligned to produce such connections. In each case, the hexagonal grid pattern of the partial elements allows the realization of a mosaic annular array beam pattern as shown in FIG.

In typical operation, the reconfigurable array is programmed to have an initial aperture pattern similar to that shown in FIG. This pattern allows the beamformer to generate a beam on the front side of the array. During imaging, the aperture is scanned across array 60, as illustrated in FIG. 8, where the ring moves from ring 1 at t = 1 to ring 2 at t = 2, and finally at t =. Move to ring N at N. Where t is time and N is a positive integer greater than 2. In this way, the beam is swept in the space in front of the array, and the beam-formed echoes are used to create a series of lines in the image. The purpose of the reconfigurable array is to be able to electronically achieve the imaging operation illustrated in FIG. 8 for any complex array pattern. Earlier ultrasonic scanners can perform electronic scanners, but the complexity of the aperture is limited due to the lack of fine distribution of sensor component elements in the elevation direction and the fixed geometry.

A fully reconfigurable array, as illustrated in Figure 8, represents a number of key challenges in realization. The sensor array is subdivided into tens of thousands of subelements. The beam pattern is constructed by grouping the partial elements and connecting them to a finite number of system transmit / receive and beam forming channels. The reconfigurable array forms multiple rings that are electronically translated across the array when used to embody the mosaic annular array concept. At each new step in translation, the entire ring pattern is reprogrammed into the array to create a new configuration. It can also provide the ability to update the ring pattern between transmission and reception and at multiple intervals during reception to reduce beam distortion when formed and improve image quality. Is.

A typical system uses 128 or more channels. Current ultrasound systems use a multiplexing architecture that can route 128 system channels to a fixed number of transducer elements. Thus, with careful design of the multiplexer network, it is possible to generate standard scanning patterns with a limited amount of electronics. However, in most cases, the scanning pattern is fixed and cannot be reconstructed due to network constraints. Fully reconfigurable arrays are not affected by these constraints, but they require a very dense switching matrix to realize them.

As illustrated in FIG. 8, the basic properties of reconfigurable arrays require that any component can be arbitrarily connected to any system channel. For example, when the opening is scanned from the first location to the next, the partial element S2 must first be part of the internal ring (not shown) and then part of ring 2. .. This means that the partial element must be switched from being connected to the first system channel to being connected to a different system channel within a short period of time. This generally applies to a large number of partial elements in the array during the scanning operation.

The simplest way to embody this requirement would be to distribute all system channels across the array so that each component has access to each of all system channels. This architecture is illustrated in Figure 9. In this case, only five system channels are shown for illustration. Each system channel is connected to all subelements by a local switch that selects which subelement captures which system channel.

In systems where the matrix electronics are provided directly behind the transducer array, the space for the switching electronics of each component is reduced to the size of the device. In a typical ultrasonic system, this size is on the order of hundreds of microns, but it can be smaller. Since the size of the switch is inversely proportional to its on-time resistance, it faces the antinomy that increasing the number of switches increases the on-time resistance, or decreasing the number of switches reduces the on-time resistance. However, it is quickly clear that even in the extreme case of making the switches as small as possible, current semiconductor technology cannot easily fit more than 16 switches into the allocated space. The fully loaded architecture of Figure 9 would be difficult to solve in the current state of the art, as the actual array would include more switches.

Future technological advances may make it possible to integrate more switches in the same space, but ultrasound advances are related to the wavelength of the imager that needs to be shortened to improve image quality. Therefore, the size of the allocated cells tends to be reduced. In addition, more components such as digital control and transmit / receive circuits are about to be placed within this same confined area. Therefore, the fully loaded architecture described above is attractive because of its simplicity, but it is not immediately supportable or feasible.

A better solution to the interconnect problem described above is to limit the number of switches in each component and at the same time provide the flexibility required for reconfigurable arrays. This can be achieved by using a limited number of bus lines and making them reconfigurable, as illustrated in FIG. In this case, the multiplexer 70 arbitrarily selects which bus line 74 should be connected to which system channel 38 (CH.1 to CH.N), and at that time, the subelement 32 of each row (row) Only a single bus line works. The cMUT cell 2 of each subelement (the figure shows only one cMUT cell for each subelement) is connected to the bus line by the respective access switch 30. An important feature of this architecture is that many switches are located outside the array and are therefore not constrained by the geometry of the transducer. Using this architecture, one-dimensional patterns can be scanned across an array by sequentially selecting which subelement sequence to connect to which system channel. Further improvements to this architecture are illustrated in Figure 11. In this case, a plurality of bus lines 74 and 76 are passed through each row of the partial element 32. The cMUT cell 2 of each partial element 32 can be connected to the bus line 74 via the access switch 30'or to the bus line 76 via the access switch 30. This architecture provides horizontal flexibility as it is possible to group elements on different system channels in the same row.

Further improvements to the architecture can be made by noticing that most openings consist of continuous grouped subelements interconnected to form a single larger element. .. In this case, it is not necessary to connect each of all the subelements directly to their respective bus lines. It suffices to connect a limited number of partial elements within a given group and then connect the remaining partial elements to each other. In this way, the transmitted signal propagates from the system along the bus line and enters the device along a limited number of access points. From there, the signal spreads within the device via local connections. This architecture is illustrated in Figure 12. In this case, the subelements 32 can be connected to the bus lines associated with the rows of those subelements via the access switch 30 and to the bus lines associated with the adjacent rows via the matrix switch 36. Can be connected. The matrix switch 36 connects one subelement to an adjacent subelement.

In one embodiment of the invention shown in FIG. 13, all of the above improvements are incorporated. In this case, the access switch 30 is used to connect a given subelement 32 to a row bus line within the bus 34. This architecture is directly applicable to mosaic circular arrays. In such devices, the architecture can be used to form multiple rings. In that case, each ring is connected to one system channel using one or more access switches, each access switch is connected to one bus line, and that bus line is one system channel. Connected to.

Access switches are staggered as shown in Figure 13 to reduce the number required for a given number of bus lines (more on this below. To do). Also, the order of access switches to the bus line can be randomized (not shown) to reduce artifacts caused by repeating patterns. The flexibility of the array can be improved by using two or more access switches within each subelement. In such an architecture, a compromise is found between flexibility and the number of access switches per partial element when the number is still significantly less than the number of bus lines and system channels. .. It is also possible to use two or more access switches per bus line within each element. This is thought to improve the yield of the device because it is possible to sidewalk a non-functioning access switch with a redundant access switch.

The column bus lines are connected to the system channels using an intersection switching matrix as shown in Figure 13. It is also possible to use sparse intersection switches, which reduces the number of multiplexers required. While such an architecture is space efficient, it will require careful selection of switch configurations to ensure proper connection of all bus lines. As shown in Figure 12, multiple bus lines can be used per column. Increasing the number of bus lines increases the number of multiplexers and increases the path formation area within the array, but improves the flexibility of the array. It is possible to skip columns or use different numbers of bus lines for different columns. For example, it may be advantageous to share a group of bus lines between all adjacent subelement trains of each pair in order to save area.

So far, only horizontal bus lines have been described, but it is also possible to place both vertically and horizontally extending bus lines in the array. Bus lines can be arranged vertically as illustrated in Figure 14 (see Bus Lines 72,74,76). As can be seen in FIG. 15, one set of bus lines 82 can be arranged horizontally and another set of bus lines 84 can be arranged vertically. In this case, each sub-element or group of sub-elements can be connected to a vertical bus line via one access switch and further to a horizontal bus line through a different access switch. .. However, if the bus lines extend in both directions, the electronic area available for the bus lines is scarce and more bus lines are needed, and only one in one subelement. Since there is an access switch, the access switch for each component can be connected to either the horizontal bus line or the vertical bus line, not both. Finally, the bus lines can be arranged diagonally as illustrated in FIG. These lines 76,80 extend along the two natural axes of the hexagonal array, respectively, thus simplifying the addressing of subelements.

The number of access switches and column bus lines is determined by size constraints and applications. To give a exemplary example (shown in FIG. 13) for mere disclosure purposes, a single access switch 30 for each component 32 and four row bus lines 34a-34d for each row of the array. Is provided. Another type of switch is the matrix switch 36, which is used to connect the connection point 42 of one subelement (see Figure 17) to the connection point of a neighboring subelement. This makes it possible to connect a single acoustic component to a system channel via an integrated electronic device associated with a neighboring acoustic component. This also means that the acoustic component can be connected to the system channel even if the acoustic component is not directly connected to the system channel via the access switch. Figure 13 shows three matrix switches per subelement, but can be reduced to a smaller number to save area, or switches with lower on-time resistance and therefore larger area. It is also possible to provide. In addition, matrix switches can be used to bypass known defective partial elements for a given array. Finally, although a hexagonal subelement is illustrated, a rectangular subelement is also possible.

With respect to FIG. 17, each partial element is connected to a common connection point 42 in the electronic device associated with the acoustic partial element 32. The common connection point 42 is electrically connected to eight components in each component. The common connection point 42 connects the acoustic sub-element or transducer 32 to the access switch 30 for that sub-element, to the three matrix switches 36 associated with that sub-element, and to three neighbors via the connection line 46. Connect to the three matrix switches associated with the partial elements of. The signal that has passed through the matrix switch is connected to a common connection point of neighboring subelements.

FIG. 13 shows how a switching network can work for a particular subelement. This is just an exemplary configuration. The bus 34 includes four row bus lines 34a-34d and extends below the row of subelements 32. It should be understood that FIG. 13 shows only three subelements in this column, but not the other subelements in this column. The row bus line of bus 34 is multiplexed to the system channel bus line of stem channel bus 38 by the multiplexing switch 40 at the end of the row. These multiplexing switches 40 form an intersection switching matrix. As can be seen in FIG. 3, each row bus line 34a-34d can be connected to any one of the system channel bus lines of bus 38, for which the appropriate multiplexing switch 40 Turns on and turns off the multiplexing switch that connects a particular row bus line to another system channel bus line. These multiplexed electronic devices can be placed laterally apart and are therefore not constrained by size. FIG. 13 shows a fully loaded intersection switch. However, if it is not necessary to provide a switch to connect all bus lines to all system channels, then sparse intersections to connect only some system channels to a given bus line. Switches can be used, in which case only some of the switches 40 shown in FIG. 13 will be present.

The access switch is so named because it allows the partial elements to directly access the bus line. In the exemplary embodiment shown in FIG. 13, there are six other switch connections for each subelement. These connections are in the form of a matrix switch 36. Matrix switches allow subelements to be connected to neighboring subelements. In this hexagonal pattern, each sub-element has six connections to neighboring sub-elements, but each sub-element has only three switches and the other three connections are within the neighboring sub-element. It is controlled by the switch of. Therefore, there are a total of four switches and associated digital logic devices within each subelement. This is just one exemplary embodiment. The number of bus lines, the number of access switches, and the number and topology of matrix switches can all be different, but the overall concept remains the same.

Access switches and matrix switches can be packaged components, but these switches can be manufactured within the same semiconductor substrate on which the MUT array is to be manufactured. These switches can include the types of high voltage switching circuits disclosed in U.S. Patent Application No. 10/248968 (Invention title "Integrated High Voltage Switching Circuits for Ultrasonic Transducer Arrays"). Each switch has two DMOS-FETs connected back-to-back (with source electrodes connected together) capable of bipolar operation. Whenever both FETs are turned on, current flows through the switch terminals. The state of the switch is controlled by each switch control circuit. The state of the switch control circuit is defined by the output from the programming circuit. The programming circuit programs the switch control circuit according to the optimized switching configuration derived using the algorithms disclosed in this document. The scan controller loads the optimized switching configuration into the programming circuit. Although the use of CMOS high voltage switches is a preferred embodiment, the present invention is directly applicable to other switching technologies such as low voltage switches, MEMS switches and other future switch technologies under development.

FIG. 18 shows that the acoustic component 32 is connected to the access switch 30 via the common connection point 42. The other six lines connecting to connection point 42 are not shown. In this example, the access switch 30 has the pair of back-to-back DMOS-FETs described above. The control circuit 52 turns on or off the switch 30 as a function of the control signal sent from the programming circuit 54. When the access switch 30 is turned on, the acoustic component 32 (ie, the partial array of interconnected cMUT cells) is connected to the column bus line 34a. In this configuration, the electronics associated with each acoustic component are one access switch, three matrix switches, their respective control circuits for each of these four switches, and three neighboring components (figure). Each has a conductor that connects a common connection point to the matrix switch (not shown).

The signal traveling from the partial element to the row bus line is an electrically received signal. In this case, the received signal is an electrical response signal generated by the acoustic component when the sound wave interacts with the transducer. The transmitted signal, which is an electrical pulse generated by the ultrasonic system, travels from the column bus line to the matrix switch. For a given channel, this electrical excitation pulse travels through the system channel bus line to the column bus line. The signal then travels from the row bus line to the acoustic component via the access switch and to another device via the matrix switch.

The number of switches that fit behind an acoustic component is limited. The size of the switch determines the on-time resistance of the switch, and the smaller the switch, the greater the on-time resistance. The delay and distortion caused by switching increases as the on-time resistance of the switch increases. This means that there is an antinomy between the number of switches behind the acoustic component and the delay introduced by those switches. One solution to that antinomy is to reduce the number of switches to a small number, while maintaining as much flexibility as possible. To achieve this reduction, matrix switches are used to allow the acoustic component to be connected to the system channel via other components and limit the number of access switches to a small number. To do.

Minimizing the number of bus lines is also beneficial because the bus lines that connect the access switches to the system channels also take up space in the layers of the electronics. The number of unique channels that can be directly connected to acoustic components in the same row is determined by the number of bus lines. However, the number of channels in one row is increased by the matrix switch because the matrix switch allows the subelements in one row to be connected to the subelements in the other row. This allows the number of bus lines to be kept small while keeping a large number of channels available. Of course, a larger number of bus lines increases flexibility, but requires more space.

The use of matrix switches means that the number of access switches behind each component can be reduced. In extreme cases, there is only one access switch for each component. However, if you have more than one bus line, you must decide which bus line to connect each access switch to. One solution is to stagger the connections so that the bus lines are repeatedly connected for each of the N subelements in a row. Here, N is a number determined by the minimum signal distortion requirement as described below. Referring to FIG. 13, each subelement 32 in the row is connected to one row bus line in the row bus 34 via their respective access switches 30. The pattern of the connecting portion in this staggered arrangement is repeated for each of the four subelements. The staggered arrangement allows for more bus lines with fewer access switches, and the combination of matrix switches can provide greater flexibility as to which system channels can be connected to each component. it can. Of course, having more than one access switch per cell increases the flexibility of the connection, but requires the switch to be smaller, which in turn increases resistance on-time.

Generally speaking, the number N of columns for repeating a pattern is determined by the maximum number of matrix switches that can be connected together while maintaining proper signal integrity. This number arises from the understanding that the resistance of the matrix switch and the capacitance of the cMUT form an RC delay line, and the time constant of the delay changes exponentially with the number N of taps in series. This concept will be discussed further below. The staggered arrangement of access switches on multiple row bus lines makes it possible to increase the number of elements that can be supported within the constraints of the delay line. Worst case of design when multiple rings (part of which are represented by dotted arcs), each with the width of one partial element, are densely packed, as illustrated in FIG. Occurs. In the worst case, the bass line 74 in this design, Since 76 extends horizontally, it is caused by the vertical part of the ring. The horizontal part of the ring is all the same when the bus lines extend parallel to the ring, so it is possible to use one access switch for each partial element. However, in the vertical section, each row of subelements 32 is associated with different bus lines connected to different system channels. Therefore, the partially spaced vertically spaced partial elements in this area can only be supported using the matrix switch 36 (represented by a thick short line). In Figure 19, there are two bus lines per row, and the pattern for access switch 30 (indicated by black dots) repeats every four rows. In each row, two rings are supported by two access switches and their associated set of subelements grouped by matrix switches. Since the pattern repeats every 4 columns, this particular architecture supports up to 2 x 4 = 8 rings. In general, an array with M bus lines in each row and N taps for each series of subelements can support up to K = M × N system channels. Of course, most parts of the ring are neither perfectly horizontal nor perfectly vertical. Therefore, the challenge for system designers is to optimize the array configuration at all points within the aperture under architectural constraints.

Given a particular desired mapping between a component and a system channel, the goal is to determine the optimal switching network configuration that provides or nearly provides that mapping. There can be no configuration that exactly matches the desired mapping. This depends on the flexibility of a given design, which is controlled by the number of bus lines and the number of access switches. If the desired mapping cannot be produced, a close approximation must be selected. A more likely situation for reconfigurability in a mosaic annular array is the presence of multiple configurations that provide the desired subelement-channel mapping. Also, if the desired mapping cannot be generated accurately, there may be a plurality of approximate configurations. In these cases, if multiple configurations provide the same subelement-system channel mapping, one configuration may be preferable to another in terms of delay and amplitude performance. One aspect of the invention presented herein includes using an optimization procedure to improve the performance of an imaging system by selecting a configuration with better performance.

The connection between the system channel and a given component can be complicated. The switching network configuration defines a complex network of connections between subelements and system channels. The result is that there is no simple connection from the subelement to the system channel, but rather through a series of switches (both access and matrix switches) that form a complex delay line structure. is there. At the time of transmission, multiple signals connected to the same system channel should see the same transmit pulse synchronously. However, in reality, the switch network delays the signal and also changes the amplitude and shape of the pulse at each component that sees a different path to the system transmitter.

A simple simulation of the delay line can be used to gain knowledge of how much delay is present and how the pulse is distorted. The transducer array and its associated switch matrix can be modeled as a distribution network of resistors and capacitances. The signal propagates through this network, and the delay time at that time is related to the unit resistance and capacitance of the network. A simple example of such a network is a one-dimensional RC delay line as shown in FIG. In this network, the signal propagating from the input undergoes a delay, which is a function of resistance R and capacitance C, as shown. Waveforms at each node or tap in the network have different shapes because they are subject to different amounts of delay with respect to the input signal. The worst delay in a finite RC delay line is RCN²It can be shown as changing according to / 2. Where N is the number of taps in the delay line. FIG. 21 shows measured data for a 20-tap RC delay line similar to the network shown in FIG. The graph shows a group of curves measured at each tap on the delay line, with tap numbers increasing from left to right. This graph clearly shows the distortion of the voltage waveform that occurs as it propagates through the network. The worst delay (defined as the time from the step input to the midpoint of the output) is RCN²It can be seen that it is approximated by / 2. That is about 25 microseconds in this experiment. Therefore, a good rule of thumb for the design of reconfigurable ultrasonic arrays is RCN.²Design the transducer capacitance and switch on resistance so that / 2 is always less than the worst delay that the system can tolerate. In this case, the number N of taps (or switches) allowed in any given path is limited by the imaging requirements of the system and the RC time constant of the network.

The result of the above discussion is that the delay in a particular subelement depends on the number of switches that the signal must pass through, the number of paths that the signal must pass through, and the mode in which multiple connections are distributed. Indicates that it depends. It can be expected that there will be different delay patterns depending on the particular aperture. In addition, simulation and successive approximation methods can improve the placement of access switches to reduce delays. FIG. 22 illustrates a mode in which the delay changes depending on the topology of the device. In this example, reference numeral 86 represents a drive, and the rest of the figure represents a row of partial elements 32 (forming linear elements) connected in series by their respective matrix switches 36. The first partial element in the row is connected to the drive 86. First, signal propagation in the delay line can be equated with heat diffusion from a point heat source. With this similarity in mind, FIG. 22 shows that the delay and attenuation increase in two dimensions as the distance from the forced node or access switch 30 increases.

It is clear that it is best to distribute the access switches as uniformly and as densely as possible in order to reduce the signal distortion for each partial element in the aperture. More specifically, the switches can be configured to ensure that different access switches 30 are connected to both ends of a long row of matrix switch connections, as shown in FIG. In the case of a linear element, especially if all the partial elements are connected by a matrix switch along the linear element so that there is a continuous path from one end to the other end of the linear element, at both ends of the linear element. Significant improvements can be made by arranging the access switch 30. The improvement obtained by connecting both ends of a continuously connected linear element is better than splitting the same element into two short elements, each with its own access switch connection. However, the degree of improvement is large. Further, as shown in FIG. 24, further improvement can be obtained when the access switches 30 are distributed inside the device.

For circular arrays, the simplest architecture is as shown in Figure 25. In this case, a single access switch 30 is connected to one complete ring of partial elements (individual partial elements not shown), and each partial element is put together by a matrix switch (not shown). It is connected. It is easy to embody because it requires only one access switch, but this architecture causes a considerable delay depending on the size of the matrix switch. Thus, multiple access switches can be connected to a complete ring as shown in FIG. 26, so that the matrix switches between the subelements (not shown) form each part of the ring. Has an access switch 30 to. These access switches are equidistantly distributed along the ring to reduce signal delay for the partial elements between the switches. Thus, by forming a single ring with a plurality of redundant matrix switch connections, the series resistance can be reduced and the delay can be reduced. As shown in Figure 27, the access switches are equidistant from both edges of the ring to minimize delay inside the ring if only one access switch is used. Can be selected as. The edge of the ring represents a partial element near the inner and outer edges of the ring. In this way, the delay pattern in the ring is improved. If multiple access switches are used across the width of the ring, they should be placed on the inner and outer edges to improve the delay pattern by minimizing the 2D switch distance. FIG. 28 shows such an example. The circle 30 represents an access switch, which is arranged in pairs near the inner and outer edges of each ring of the subelements (individual subelements not shown). If the access switch 30 is located on the edge of the ring, the signal is driven from both directions, reducing the overall error. Figure 28 also shows the access in the square Shows switches 30', which are located in the center of the ring (ie, in the middle between the inner and outer edges of the ring). This causes a large error at the edge of the ring because the access switch does not drive the ring from both edges.

Although the architecture aims at the concept of mosaic annular arrays, it is possible to form patterns other than rings while choosing the placement of access switches to minimize latency, as will be apparent to those skilled in the art. Is. Therefore, the invention described herein is applicable to other types of imaging means including phase adjustment arrays, linear arrays and two-dimensional arrays.

The methods of the present invention can be used to select switching configurations that minimize errors introduced by complex switching networks. The goal is to reduce errors in a way that does not compromise beam formation. There are many ways this can be achieved. Some specific examples of algorithms that attempt to achieve this goal are shown below. These embodiments should not be viewed as limiting the invention, but rather as examples used to represent the potential of such algorithms.

For example, if a complete model of the system is available, this model can be used to determine the best configuration for the switch network. To be able to achieve this, some random or quasi-random processing is used to generate the switching configuration. The switch configuration is then input to the model. The model considers all errors in the switching network and calculates the response of the system. The model can be used to generate certain forms of images or radiation patterns, based on which specific criteria or cost functions are calculated. Modify the configuration by using the result of the cost function. An iterative algorithm is then generated to try and minimize the cost function using simulated annealing or some other arithmetic method.

The parameters calculated depend on the complexity of the model chosen and the particular cost function chosen to minimize it. The complete model can calculate the acoustic output (pressure as a function of space and time) in the plane of the transducer given a particular switching configuration and input excitation. Such a model would need to include the effects of switching networks and the response of individual transducer cells. Given the acoustic output, a number of cost functions can be evaluated. For example, the beam width of the resulting radiation pattern can be minimized and at the same time the level of side lobes of the pattern can be minimized. In this case, the model would need to calculate beamwidth and sidelobe levels.

In an alternative aspect, the actual hardware can be used to perform this optimization process if the hardware is available. In this case, a configuration is generated and applied to the system control device. Create an image or get simplified data. Again, the cost function is based on this data and used to modify the configuration. However, in this case, no modeling is relevant. Performance can also be evaluated by measuring voltage directly on the underlying CMOS electronic device using a probe array designed to match the switching array. In this case, the speed at which the switching network can be programmed and the speed at which data can be collected and processed limits the number of configurations that can be considered. However, this number is probably quite high, which may be a good way to determine the actual response without forming an image.

In some cases, complete modeling of the system's acoustic response, including all switching topology errors, is difficult and computationally expensive. Practical hardware prototypes may not be available for use in collecting data about the configuration. Even if the hardware is available, it will take longer to collect and process data for many configurations. So, to determine the effectiveness of using this type of algorithm, evaluate a large number of configurations very quickly, based on insight and understanding of how networks can affect acoustic response. You can adopt a simpler model that allows you to. For example, it is known that the greater the number of switches that a signal must pass through, the greater the delay and distortion introduced.

First, it turns out that a good way to try and place a switching network is to make the distance between the connection and the subelements as small as possible. Here, the connection is defined as an access switch that is turned on, thus connecting a partial element with that switch directly to the column bus line for a particular channel. The distance also represents the number of switches that the signal must pass through from the acoustic component to reach the row bus line. In addition, the connected access switches should be distributed as much as possible to avoid creating a continuous, very long row of some partial elements by reducing the local distance. .. Therefore, the simplified model uses the number of matrix switches that the signal must pass through as a metric for the performance of the configuration. Although this is not completely accurate, simulations have shown that this simple model improves the performance of switching networks. This is true even though we are trying to model 2D reduction with 1D metrics.

The specific realizations of reconfigurable properties disclosed in this document are subject to the constraints imposed by electronic devices. There is a set of rules that regulate switching configurations for a system. In addition to this strict rule, there are guiding principles such as shortening the distance between the acoustic component and the connection point. The rules must be followed and the guiding principles can be used to improve performance. The rules are as follows.

[1] Each column has n column bus lines. In the example disclosed in this document, n = 4. This means that there are only four system channel bus lines to which access switches can be connected across the row.

[2] Each subelement in the row is connected to only one of the n row bus lines. This arises from the fact that there is only one access switch in the subelement. This also means that a given component can be directly connected to only a single system channel, which channel is determined by the multiplexer between the system channel bus line and the column bus line. ..

[3] Each row bus line is connected to a single system channel bus line. The system channel bus line is multiplexed with respect to the column bus line, but this connection cannot be modified for a given configuration.

[4] The pattern in which a column bus line is connected to a given access switch is repeated for that column. In the case described in this book, the pattern is repeated for each of the four subelements.

[5] For a given circuit implementation, the total number of access switches connected to the same column bus line is a small finite number. In certain cases, which will be described later, the limit is 4. This arises from the current draw limit imposed by the limited size of the row bus line. The limit value is based on simulation and can be increased by increasing the size of the column bus line, and thus the current draw can be increased, but this will make the partial element larger. You may need to.

The guiding principle has been described earlier, but will be explained more specifically below. According to one embodiment of the invention, the goal is to minimize delay errors introduced by switching networks. This can be achieved by keeping the distance from the connection point to the partial element as small as possible. In this connection, the connection point is a partial element in which the access switch is on. Further, it is more preferable that the connection points are evenly distributed.

To determine the switching network configuration, determine which access switch is on, and the multiplexer between the column bus line and the system channel bus line (partially shown in Figure 13). It is necessary to determine how a group of multiplexer switches 40) are configured. Once the desired pattern is known, the state of the matrix switch is easy to determine. A matrix switch is set by simply determining whether the neighboring components to which the switch is connected should be on the same system channel. So the task is to determine how to connect the system channels to the multiplexed column bus lines. Once this is known, the access switch will be easier to assign again.

It is difficult to determine the optimum switch configuration. First, we developed a simple algorithmic strategy for assigning switches. The algorithm was designed with some rules and guiding principles in mind, but it is by no means the optimal solution, but rather the solution to the benchmark. The solution sought is based on a particular desired configuration. In one example, the desired configuration was a monospaced annular array with 20 rings. The algorithm is as follows.

Start row by row across the array, starting at one edge of the array. For each row and for each bass line in that row: [1] Determines which ring (ie, which system channel) is possible for a given column bus line. For example, near the top of the array, only the outer elements can be present. In that case, a single ring is possible. All rings are present towards the center, but only some rings are possible for a given row bus line.

[2] For each ring, the number of access switches that can be turned on for a given column bus line if the multiplexer configures a given column bus line for the system channel corresponding to that ring. decide.

[3] Assign a column bus line to a ring that can turn on most access switches. However, this should be done under the following constraints: that is, [a] The same ring cannot be assigned to more than one bus line in a row, and [b] If the same ring has already been assigned in the previous four columns, then that same ring cannot be assigned to a column bus line.

In some cases, condition [b] may be met and the ring may not be assigned to a particular column bus line. For example, if there are only three candidate rings assigned to a particular column bus line, and those three rings are assigned to the previous three column bus lines, then this particular column bus line There are no rings that can be assigned. In this case, and in all cases where condition [b] prevents the column bus line from being connected to any ring, the constraint must be removed. With this algorithm, constraints can be removed in a way that does not interfere with the intent of the algorithm. Therefore, if condition [b] cannot be satisfied, start from the farthest column and remove the restrictions on the columns one by one. Therefore, if the condition [b] cannot be satisfied, the column bus line is assigned to the same ring assigned to the fourth previous column bus line. If this still does not work, until the column bus line can be assigned, such that the column bus line allocation will be the same ring assigned to the third previous column bus line, and so on. repeat.

The above algorithm can be used to assign multiplexer and access switch settings for a particular desired ring shape. It seeks to maximize the number of active access switches, which helps to reduce the distance between the connection point and the subelements. This algorithm is a useful benchmark.

With respect to the switching network configuration, it is important to determine how effective the configuration is in the imaging situation. The final criterion to be used to determine if one configuration is better than another is the quality of the image produced by such a configuration. However, without a working prototype, this is nearly impossible to do. Also, determining image quality is a difficult metric, and even with a working prototype, this is because it selects each of all possible configurations due to the time and effort that may be required. Could not be used for. For a particular configuration, it is possible to simulate the beam distribution using a complete computer model of the electronics. However, this simulation is very time consuming and should therefore be limited to only a few configurations, not for a large amount of sorting. It is also possible to use a simplified electrical model to simulate only delay and amplitude changes and use them as inputs to a simpler beamformer model, but this is also required. It takes more time than desired to screen a large number of inputs. A slightly faster way is to use a simplified equation to estimate the delay, but this is not a very fast simulation that can significantly select a large number of possible configurations.

A way to allow a very quick evaluation of a large number of configurations is to assume that the main effect on delay comes from the distance from the subelement to the connection point. Calculating the distance from each component to the nearest connection point can be done very quickly using a look-up table. This makes it possible to design an iterative algorithm that can search for a large number of configurations. The present invention is not limited to this embodiment, but this evaluation speed is an important advantage that makes optimization practically available.

Iterative algorithms have been developed that significantly improve delay errors over the simple method of determining switch configurations already mentioned. This algorithm is as follows.

[1] The initial configuration is given. In one example, the output of a simple algorithm was used. This may also be a random configuration.

[2] A look-up table (LUT) is created for a particular geometry. This LUT gives the distance in the switch from any subelement in the ring to any other subelement in the ring. To improve the calculation speed of the LUT, a maximum distance is used and no calculation is performed, labeling that distances greater than that maximum are simply greater than the threshold.

[3] For the current configuration, the algorithm does the following:

[a] Using the LUT, calculate the distance (number of switches) from each subelement to the nearest connection point.

[b] Classify the distances and hold M partial elements with the worst (ie, largest) distances. In one example, M = 10, where 10 worst distances were held.

[c] Randomly select one of the subelements with one of the M worst distances. In this case, an integer between 1 and 10 is randomly created to select the partial element.

[d] Turn on the access switch for randomly selected subelements. In most cases, in this connection, the other access switches are turned off and the multiplexer between the system channel bus line and the row bus line of the row of the subelements is modified.

[e] Evaluate the global cost function for this newly generated configuration. The particular cost function used was the number of subelements with a switch distance greater than the threshold. The threshold used was set to 4 based on some simulations with a single row of switches.

[f] If the cost function is smaller than the cost function of the old configuration, this new configuration is currently adopted as the best one.

[g] If the cost function is larger with a switch change, it can be kept intact. This is a simulated annealing type algorithm. A temperature function is defined, and the temperature decreases slowly with many iterations. Initially, the temperature function is high, so it is more likely to maintain the configuration despite its larger cost function. As the number of iterations increases, the temperature decreases and the probability of retaining an inferior configuration decreases. This type of algorithm allows the system to jump out of the local minimum, thus giving the system the opportunity to find a better minimum (perhaps not global).

[h] This process is repeated up to a given number of iterations, or until all distances are below the threshold.

Simulated annealing is a well-known arithmetic method for optimizing parameter selection when 100% retrieval of possible set values is not feasible. Annealing represents the physical process by which a metal crystallizes as it cools. The final state of this cooling process depends on the rate at which the object is cooled. If the cooling is done very slowly, the system can reach a minimum energy state. Also, if the object cools very quickly, the energy is only locally minimized. Simulated annealing is a mathematical algorithm that mimics the cooling process. The cost function is defined for the process being considered, and simulated annealing algorithms try to minimize this cost function. In this case, the cost function is similar to the energy in the physical process of annealing. Simulated annealing algorithms start with a specific configuration. Make random changes to the configuration (ie, make random changes to the optimizing parameters). These changes may require you to follow certain rules or regulations. After making any configuration changes, the cost function is evaluated again. If the cost function decreases, the configuration is changed to the new configuration. When the cost function becomes high, the configuration may or may not change depending on the value of the random variable. As the algorithm progresses, the likelihood of maintaining the higher cost configuration is reduced. However, by producing the higher cost configuration, the algorithm can prevent local minimums and approach more absolute minimums. The probability that the higher cost configuration will be maintained is high at first and decreases as the algorithm progresses. This probability is similar to the temperature in physical annealing. The speed at which the probability decreases determines the speed of the algorithm. If the rate is high, the answer is quick, but it may not be close to the true minimum. If the rate is low, it will take longer to get the answer, but the answer is likely to be the minimum.

A simple algorithm was used to determine the switching configuration for the mosaic circular array. Due to a simple algorithm, 172 of the 7015 subelements had a distance of 5 switches or more. This means that 97.5% or more of the partial elements were below the threshold. This configuration was used as an input to the iterative algorithm to determine a new switching configuration. In this case, only 12 of the 7015 subelements had 5 or more switches to advance to the connection point, that is, 99.8% or more of the elements were below the threshold. The 12 subelements that did not meet the threshold criteria were at the distance of all 5 switches. This indicates that improvements were made to the simple algorithm by reducing the number of partial elements that do not meet the threshold criteria from 172 to 12. However, the iterative algorithm does not take into account the rule of limiting the system to four active access switches per column bus line. An additional processing step was used to remove the extra switch. This process removes the switch in a way that attempts to minimize the increase in average distance. As a result of removing these extra switches, significant improvements have been made to the simple algorithm. Most of the extra switches were near the top and bottom. There is a high density of connections and therefore little is lost.

The above distances were compared to the actual delays derived from the simulation of the electronic device. When switching configurations are generated using iterative algorithms, delays can be simulated using simplified models and electronic simulation software (eg, HSPICE). This accurately reflects the two-dimensional nature of the delay problem, which translates into a single scalar for computational speed. The result of simulating the delay for the same switch configuration using a commercially available electronic simulation package is that the actual delay peak always occurred at the peak in the distance metric (used to optimize). there were. This proves the fact that the distance metric is a good metric to use for optimization. However, some peaks in the distance metric did not have a corresponding peak in the delay. This is related to the two-dimensional nature of the delay relative to the one-dimensional nature of the distance metric.

The realization of the switch matrix described above was the output of an iterative algorithm. However, the results can be different for different runs and depend on the temperature parameters used, the thresholds and the cost function. It may be possible to improve the current design by increasing the optimization time. Also note that this is just one exemplary algorithm for minimizing errors. Other algorithms can also be used to improve performance.

To form a linear scan, it is necessary to step the active aperture of the mosaic annular array across the underlying 2D array. This stepping requires restructuring the switching network. There are several ways in which this step can be made. If the required beam spacing, as determined by the resolution of the array and the requirements of the application at hand, is such that a step of one subelement can be tolerated, then each beam will have the same switch configuration derived by the algorithm. Can be used for. In this case, the switching configuration simply steps over one or several subelements for each beam. Avoid transmitting the switch state directly from one subelement to the next subelement and externally reprogramming the entire array to minimize power used by the system to reprogram and reconfigure. It is possible. However, in addition to translating the access and matrix switch patterns, the multiplexer that connects the column bus line to the system channel bus line must also be modified. When the beam is stepped in the direction of the row bus line in increments of all subelements, this change is simply one revolution of the channel. For example, if four system channels, represented by A, B, C, and D, respectively, are connected to four column bus lines in a particular column for a particular configuration, the switching pattern scans to the next beam position. When so, the state of the system channel / column multiplexer is such that the system channels rotate between the four column bus lines, for example, system channels B, C, D and A are the same 4 in this order. It must be adjusted to connect to each of the two row bus lines. Instead, rather than changing the multiplexing between the system channels and the column bus lines, the system beamformer directly considers the changes in geometry and thus adjusts the delay of the four channels. And consider the new delay

As mentioned earlier, if the annular ring is stepped so that the movement is an integral multiple of the partial element, there is no need to reoptimize for each beam (although the lower switch matrix is on the lower side). Has uniform electrical properties throughout the two-dimensional array of). However, there are cases where a beam density is desired so that the line spacing is denser than that of one partial element. In this case, the center of the beam is stepped in fractional increments of one subelement, for example, the aperture is deformed to effectively steer the beam by half a step during the full step of the aperture. Increase the resolution of. In such cases, the optimization does not simply translate, but each fractional step. Must be optimized for. However, these fractional step configurations may occur again as the annular array is stepped over the underlying two-dimensional array to form a linear scan. In such cases, wherever the same fractional step is required, the optimization is the same and can be reused. Therefore, even in the case of fractional steps, a small number of optimizations are required. In such cases, it may be possible to fire all beams for a particular configuration and step through the array at coarse beam intervals to save programming time and power consumption. In this case, it is possible to pass the configuration directly from one subelement to a neighboring subelement. After the rough scan is complete, a new configuration that represents a fractional step from the old configuration can be programmed to step across the array. This can be repeated for each fractional step. The coarsely spaced beams resulting from each configuration can be interleaved by scan transducers to the desired fine beam spacing. Also, when mixing beams from different configurations, it may be necessary to adjust the gain for each beam and mix the lines from those configurations to ensure a difference in beam forming gain. Please note.

The numerical optimization algorithm disclosed above improves the beam forming performance of the reconfigurable array. The problem to be solved was that in the case of a simplified switching network for reconfigurable arrays, delays, amplitude changes and waveform distortion were all caused by the simplified switching network. The use of numerical optimization can help minimize errors and maintain good beam formation performance. We explored a specific example of such optimization. In doing so, a simple metric was defined and used to characterize the performance of various configurations. The simple metric used in this example was the number of switches between a given subelement and the closest access switch connected (ie, closed) to the column bus line. .. The results obtained show that simple metrics can improve the performance of switching networks, despite a rough approximation. Simple metrics also allow you to consider multiple configurations, which increases your chances of success.

The optimization techniques disclosed in this document improve imaging performance with a simplified switching network for reconfigurable arrays. Reduction of delay errors and distortion immediately leads to improved beam formation, including improved resolution and contrast.

The optimization algorithm can be used with either a complete or sparse multiplexer. This algorithm can generate the data in advance for storage and subsequent use, or it can be generated locally during imaging for incremental improvement due to changes in array resistance. The algorithm assumes temperature-induced variation during the design phase, assuming ideal resistance values, when manufacturing using the measured actual resistance, or as a calibration step to be used over time in the system. Periodically in the field to compensate (eg, every time the ultrasound imaging device is turned on, or during use, whenever it is determined that calibration needs to be performed, or when the array configuration is changed. It is possible to carry out (always). For example, the system can be automatically calibrated in response to detecting a given change in temperature. In addition, variations in the capacity of manufactured cMUTs also affect the performance of the array. Such variability can be addressed by repeating the optimization procedure after measuring the exact cMUT capacitance for each of all the components in the manufactured array.

The calibration data is unique to each probe, and the calibration data can be stored in ROM or EPROM by each probe, or can be stored locally in RAM, EEPROM, FRAM, etc. in the probe itself. It can be stored on the imaging system as a file downloaded to the probe via the data link in. This data is read from the local (probe) memory during the scan, and each new scan reads new required configuration data. Instead, the calibration data can be calculated and downloaded to the probe during use of the system.

Incorporating access and matrix switches to connect the sensor elements to the bus line increases flexibility. According to various embodiments of the present invention, one or more of the following features can be used.

(1) Access switches can be staggered to reduce the number of access switches required for a given number of bus lines.

(2) A single access switch can be used for one subelement in the staggered arrangement pattern.

(3) The order of mapping access switches to bus lines can be randomized to reduce artifacts caused by repetition patterns.

(4) Two or more access switches can be used in each subelement, but still less than the number of bus lines and system channels.

(5) Bus lines can be connected to system channels using an intersection switching matrix.

(6) Bus lines can be connected to system channels using sparse intersection switches.

(7) The switches can be configured to ensure that different access switches are connected to both ends of a long row of matrix switch connections. These access switches are connected to the same bus line to reduce latency.

(8) A switching configuration can be used in which there is a set of matrix switches and a limited number of access switches. The matrix switch dynamically connects adjacent subelements. The access switch connects to a bus line that is multiplexed into the system channel.

According to various embodiments of the present invention, one or more of the following additional features may be present in the system.

(1) One access switch per bus line is used for each subelement.

(2) Multiple bus lines can be used per row.

(3) Bus lines can be placed in both vertical and horizontal directions within the array. According to one embodiment, one set of bus lines is arranged horizontally and another set is arranged vertically, with each sub-element or each group of sub-elements being vertical via an access switch. It can be connected to a bus line and can be connected to a horizontal bus line via different access switches. However, if the bus lines extend in both directions, the electronic area available for the bus lines is scarce and more bus lines are needed, and only one in one subelement. Since there is an access switch, the access switch for each component can be connected to either the horizontal bus line or the vertical bus line, not both. This also has an effect when the number of switches that can be turned on for a given bus line is limited by current flow and line size.

(4) Access switches can be selected equidistant from both edges of the ring (or other shape) to minimize delay inside the ring. "Ring edge" refers to the case where reconfigurability is used to approximate an annular array. In this case, there is some desired annular array or ring structure that is intended to be mimicked by connecting the partial elements. The edge of the ring represents a partial element near the boundary of the ring to be approximated. That is, it is the edge of a larger element formed by connecting the partial elements. Access switches are all selected to be on both sides of the device, not on one side. The shape does not have to be a ring, other shapes can be used, and it is considered best to provide access switches on both edges of the shape approximated by connecting the partial elements.

(5) Two or more access switches per bus line can be used for each component. This redundant connection improves the yield of the device.

(6) It is possible to provide the ability to update the ring pattern between transmission and reception and at multiple intervals during reception.

(7) A single access switch can be connected to one complete ring consisting of multiple sub-elements, and each sub-element is connected together by a matrix switch.

(8) Multiple access switches can be connected to one complete ring, and the matrix switches between the subelements have access switches to form each part of the ring.

(9) Multiple access switches can be connected to one complete ring, and the switches are equidistant along the ring to reduce signal delay for the partial elements between the switches. And distribute it.

(10) Multiple rings can be formed. In that case, each ring is connected to one system channel using one or more access switches, each access switch is connected to one bus line, and that bus line is one system channel. Connected to.

(11) By forming a single ring using multiple redundant matrix switch connections, the series resistance can be reduced and the delay can be reduced.

(12) Matrix switches can be used to bypass known defective partial elements for a given array.

(13) Patterns other than rings can be formed while choosing the placement of access switches to minimize delay.

(14) By repeatedly using the minimum delay algorithm at each new step in translation, the complete ring pattern can be translated to produce a moving beam.

(15) The center of the element can be advanced in increments smaller than one partial element by changing the shape of the element.

Switching electronics can be constructed using CMOS or BiCMOS, or SOI, or MEMS, or switching technologies that have not yet been identified.

Although the present invention has been described with respect to exemplary embodiments, those skilled in the art will be able to make various modifications and replace components with equivalents without departing from the scope of the invention. Will be understood. Moreover, numerous modifications can be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed as the best or only embodiment of the invention, and the present invention includes all embodiments that fall within the scope of the claims.

<figref num="1">It is sectional drawing of a typical cMUT cell.</figref><figref num="2">A "daisy" shaped portion, as described in US Patent Application No. 10/383990, formed from seven hexagonal MUT cells that connect the top and bottom electrodes together without the intervention of a switch. It is a perspective view which shows the element.</figref><figref num="3">As described in U.S. Patent Application No. 10/383990, four annular elements, each consisting of a mosaic-worked "daisy" -shaped partial element and configured to have approximately equal area per element. It is a top view which shows a part of the mosaic array which has.</figref><figref num="4">FIG. 3 is a cross-sectional view of a co-integrated cMUT and an application specific integrated circuit (ASIC) array.</figref><figref num="5">FIG. 6 is a cross-sectional view of a cMUT wafer connected to an ASIC switch matrix.</figref><figref num="6">FIG. 5 is a plan view of the hexagonal array of cMUT subelements placed on top of the hexagonal array of associated unit switch cells.</figref><figref num="7">FIG. 5 is a plan view of a hexagonal array of cMUT subelements placed on top of a rectangular array of related unit switch cells.</figref><figref num="8">It is a schematic diagram which shows the state of translation of an annular transducer element across an array.</figref><figref num="9">FIG. 6 illustrates an architecture in which all system channels are distributed throughout the array so that each transducer subelement has access to each of all system channels.</figref><figref num="10">Demonstrates an architecture in which the number of switches in each subelement is limited by providing one bus line per row of subelements, and those bus lines are connected to the system channel via a multiplexer. It is a schematic diagram.</figref><figref num="11">It is a schematic diagram showing an architecture in which a plurality of bus lines are provided for each row of subelements so that subelements on different system channels in the same row can be grouped.</figref><figref num="12">By connecting the partial elements in the first row to the access switches of the adjacent partial elements in the second row via the matrix switch of the partial elements in the first row, the partial elements in the first row are for the partial elements in the second row. It is a schematic diagram which shows the architecture by one Embodiment of this invention which made it possible to connect to a bus line.</figref><figref num="13">FIG. 6 illustrates an architecture according to another embodiment of the invention that allows a particular component within a particular row of a cMUT array to be connected to any one of a number of system channel bus lines. ..</figref><figref num="14">FIG. 6 is a schematic diagram showing a hexagonal array of subelements with multiple bus lines connected to each subelement in each column via an access switch (represented by black dots).</figref><figref num="15">It is a schematic diagram showing a hexagonal array of subelements in which several subelements are connected to vertical and horizontal bus lines via their respective access switches (represented by black dots).</figref><figref num="16">FIG. 6 is a schematic diagram showing a hexagonal array of partial elements, with bus lines arranged diagonally along the natural axis of the hexagonal array and access switches represented by black dots.</figref><figref num="17">FIG. 5 is a schematic diagram showing a connection to a common connection point in an electronic circuit associated with a particular acoustic component according to the embodiment shown in FIG.</figref><figref num="18">FIG. 6 is a schematic circuit diagram showing an access switch and a circuit for controlling the state of the access switch, as described in US Patent Application No. 10/248968.</figref><figref num="19">Access switches (indicated by black dots) and matrix switches (thick and short lines) for use with a large number of tightly packed rings with the width of a single partial element (some of which are represented by dotted arcs). It is a schematic diagram which shows the arrangement (represented by).</figref><figref num="20">It is a schematic circuit diagram which shows the distributed type RC delay line.</figref><figref num="21">It is a graph of the measured delay data for the RC delay line of 20 taps.</figref><figref num="22">It is a schematic diagram showing a row of subelements connected in series by a matrix switch, with the subelements at one end of the row connected to the bus line by an access switch.</figref><figref num="23">Part of a row in which the partial elements at both ends of the row are connected to the bus line by their respective access switches and the remaining partial elements are connected to one or the other access switch via a matrix switch. It is a schematic diagram which shows the element.</figref><figref num="24">The partial elements at both ends of the row and one partial element near the center of the row are connected to the bus line by their respective access switches, and the remaining partial elements are connected to their respective access switches via the matrix switch. It is a schematic diagram which shows the partial element of a row which made it connected.</figref><figref num="25">FIG. 5 is a schematic showing that the delay along the annular ring of a partial element increases as the distance from a single access switch increases.</figref><figref num="26">It is a schematic diagram which shows that the delay along the annular ring of a partial element increases as the distance from the access switch arranged in each quadrant increases.</figref><figref num="27">It is a schematic diagram which shows that when the annular ring of a partial element has a width larger than the width of one partial element, the delay increases as the distance from the access switch increases in the annular ring.</figref><figref num="28">Schematic diagram showing the use of multiple access switches across the width of an annular ring, with black dots representing acoustic components, white circles representing access switches, and squares representing differently designed access switch arrangements. Is.</figref>

Code description

2 cMUT Transducer Cell 4 board 6 Insulation support 8 membrane 10 electrodes 12 electrodes 14 cavities 16 Transducer partial element 18A, 18B, 18C, 18D annular element 30 access switch 30'access switch 32 cMUT partial element 34 bus 34a ~ 34d row bus line 36 Matrix switch 38 system channels 40 connection points 42 Common connection point 46 Connection line 50 CMOS cell 56 Bahia 60 array 62 Acoustic backing layer 64 Solder bump 65 Signal electrode 66 Conductive pad 70 multiplexer 72 bus line 74 bass line 76 bus line 80 bus line 82 bus line 84 bus line 86 drive unit