Epitaxial seal (episeal) pressure sensor

The present invention relates to a pressure sensor device and a method for manufacturing the same, and generally relates to episeal technology. More specifically, the present invention relates to a pressure sensor using episeal technology, in which an episeal film is applied to a cavity in a wafer.

The pressure sensor can be used in an automobile, for example, for measuring oil pressure, measuring tire pressure, and measuring brake fluid pressure. In addition to these, there are many non-automotive applications for pressure sensors.

Pressure sensors have been made using wafers according to conventional micromachining techniques. For example, a pressure sensor has been formed by thinning the back surface of a wafer to form a sensor film. Although this technique can be said to be reliable and mature, backside processing is costly and wastes a large amount of die area. The sensor film can be formed by etching the back surface of the wafer until it reaches a predetermined distance from the surface of the wafer, and stopping the etching there. The distance from the surface can be several tens of μ, up to 100μ. In this case, a sensor that often forms a piezoelectric resistance can be placed on top of the silicon to bridge the holes, which allows the displacement of the silicon to be measured as a function of the pressure exerted across the silicon. One problem with this technique is that it wastes a lot of space on the die by cutting the back of the garment to form holes. An etching technique often used in this application is anisotropic silicon etching, such as KOH etching, which generally cannot carve perfectly vertical holes. The holes are usually pyramidal in shape, so a die of several millimeters is required at the bottom of the wafer to form holes ranging from hundreds of μs to 0.5 mm at the top of the wafer. As the size of the die increases, so does the cost of the pressure sensor.

The strength of the sensor film with respect to displacement is approximately proportional to the cube of the thickness of the sensor film. Therefore, a 10% error in thickness causes an error of about 30% in the strength of the sensor membrane, which in turn causes an error of about 30% in the sensitivity of the pressure sensor device using that sensor membrane. Can be triggered. In other words, a small error in thickness causes a large error in pressure measurement. Stiffness with respect to displacement is approximately proportional to the fourth power of size (ie to lateral dimensions). The pyramid-shaped depressions created by KOH etching have sloping edges, in which case the tip of the pyramid is at the back of the sensor membrane. As the thickness of the wafer changes, so does the size of the tip of the pyramid below the film. Therefore, it is difficult to control the size (ie, diameter) and thickness of the membrane, which can compromise the accuracy of pressure sensors constructed according to conventional techniques.

A technique for forming a pressure sensor exclusively using the front surface of the wafer has also been developed. According to this, a porous silicon region is formed on the upper surface of the wafer, covered with a single crystal film of epitaxial silicon, and the embedded porous silicon is melted to form a sealed and exhausted cavity. The displacement of the film is detected by the piezoelectric resistance provided on the silicon surface above those cavities. However, this technique can be constrained by crystal defects that occur in epitaxial silicon grown on porous silicon.

<p> Therefore, an object of the present invention is to provide a pressure sensor and a method for manufacturing the same, which can eliminate the drawbacks of the prior art.</p>

<p> According to one method of manufacturing a pressure sensor, a wafer having a base silicon layer, an embedded sacrificial layer, and an upper silicon layer is prepared. In this case, the upper silicon layer is placed on top of the embedded sacrificial layer and the embedded sacrificial layer is placed on top of the base silicon layer. Vents are formed by etching through the upper silicon layer and toward the embedded sacrificial layer, and a part of the embedded sacrificial layer is removed. Silicon is epitaxially deposited to seal their vents and a strain gauge or capacitive contact is placed on the wafer.</p><p> According to one method of manufacturing a pressure sensor, a bulk wafer is prepared and a sacrificial layer is deposited on the bulk wafer. Silicon is deposited on the sacrificial layer and the bulk wafer to form the encapsulation layer. Vents are formed by etching through the encapsulation layer to the sacrificial layer, and the sacrificial layer is removed. The vents are sealed with epitaxial silicon deposition and a strain gauge or capacitive contact is placed on top of the encapsulation layer.</p><p> The pressure sensor device is provided with a substrate, an encapsulation layer having ventilation holes, and a cavity located between the substrate and the encapsulation layer. The encapsulation layer portion above the cavity forms a membrane and the epitaxially deposited silicon closes the vents. In addition, a strain gauge or top volume contact is placed on top of the membrane.</p>

According to the method of the present invention, a high quality single crystal silicon film for embedding a piezoelectric resistor is formed, and a method for manufacturing a capacitance sensor is provided. The resulting membrane is pure silicone and has no oxide plugs, and this technique avoids the problems that may occur with oxide-sealed membranes.

The cavity inside the silicon for the pressure sensor of the present invention may or may not be open on the back side. A cavity with an open back side allows differential pressure measurement, which may be sealed in a vacuum by bonding this wafer to another wafer, such as a glass wafer. One target of the present invention is to form a cavity under the top of the wafer for use as a vacuum pressure reference.

Pressure can be measured by measuring the strain applied to the top membrane. Alternatively, the pressure can be measured by measuring the capacitance between the top membrane and the bottom of the cavity to measure the displacement of the top membrane.

According to this technique, a sealed film is produced. This allows the sensor to be built on a small die. This is because there is no need for a pyramid-shaped depression facing the deformable membrane. Therefore, the pressure sensor manufacturing cost can be reduced. In addition to this, the method according to the embodiment of the present invention is very good at controlling the film thickness and size of the pressure sensor, which allows a more accurate pressure sensor to be manufactured.

In the case of the embodiment of the present invention, the structure of the pressure sensor device is formed by Episeal technology. The episeal used here is a seal, that is, a seal using an epitaxial reaction vessel. Epitaxial reaction vessels are used to deposit or deposit silicon on epitaxials. The epitaxially deposited silicon produces a deposited silicon shape, which can be single crystal silicon or polycrystalline silicon. Here, epipoly is an epitaxially deposited polycrystal. The application includes a low cost and highly accurate pressure sensor. According to the present invention, sensing using both piezoelectric technology and capacitive technology is supported. The pressure sensor according to one embodiment of the present invention can be generated in at least two ways and may be formed by growth of epitaxial silicon or, for example, SOI (Silicon on). Insulator) It may be formed by laminating wafers such as wafers. According to the method of the present invention, the thickness can be controlled by epitaxial deposition parameters, or by bonding and polishing, and further, according to the method of the present invention, the diameter of the film can be controlled by lithography. These processes are well controlled.

Figures 1A, 1B, and 2 show sensors with piezoelectric elements. FIG. 1A shows a cross-sectional view of the pressure sensor 10, which has an SOI wafer, which contains a base silicon layer 11 with a sacrificial layer 12 on top of it. This can be an oxide. An upper silicon layer 13 is provided above the sacrificial layer 12.

The embodiment of FIG. 1A can start from the bonded wafer. The bonded wafer can have a base silicon layer 11, followed by a sacrificial layer 12, and an upper silicon layer 13. The thickness of the upper silicon layer 13 and the thickness of the sacrificial layer 12 can be specified when purchasing and / or producing the bonded wafer. This can be an SOI wafer, which can be a precursor to the Episeal pressure sensor. The sacrificial layer 12 is about 1μ or 2μ thick and the upper silicon layer 13 is about 2-10μ thick. The base silicon layer 11 can have wafers with a thickness between about 500 μ and 600 μ. Vents 14 can be etched through the upper silicon layer 13 to the sacrificial layer 12. Vents 14 are shown as vertical slots. The vents 14 can be one or more circular holes, or can be oval holes, elongated slots, rounded rectangular slots or other shapes as needed. The intermediate stage product can be etched, for example by exposing it to acid vapors at high frequencies, which can remove the portion of the sacrificial layer 12 around the bottom of the vents 14. Etching can proceed laterally to the sacrificial layer 12 at a controlled rate, which causes the etching to be stopped after a predetermined time to produce a cavity 15 of a known size. This is due to the predictable etching rate used in the process. The intermediate stage product can then be placed in an epitaxial reaction vessel and silicon grows epitaxially on the intermediate stage product.

The epitaxial silicon layer 17 can grow as a single crystal on the side wall of the vent 14 and pinch off the vent 14 (ie, grow from the side wall toward the center and pinch off or block the vent 14). This process can leave gaps at the bottom of those chimneys and can be pinched off near the top, or depending on the degree of similarity of the epitaxial reaction, sealing at the bottom at about the same time as the top. Can be done. In addition, the vents 14 can be tapered so that the top is wider and the bottom is narrower (not shown). This allows the vents 14 to first be pinched off or closed at the bottom, then closed upwards like a zipper, and pinched off from the bottom to the top. In this way, the epitaxial silicon layer 17 can be grown from the time the bottom is pinched off until the top is filled. The taper shape can be subtly applied (eg 10-20% taper) to achieve a clean pinch-off and / or closure of the vents 14.

The epitaxial reaction vessel can be adjusted with respect to pressure, temperature and chemical composition, thereby adjusting the epitaxial silicon to be conformally or non-conformally and selectively or non-selectively deposited. The epitaxial silicon can be deposited by arranging the wafer in the reaction vessel and flowing the silicon-containing gas over the wafer. The reaction vessel can be conditioned by containing other gases, for example (hydrochloric acid, etc.), thereby preventing silicon from depositing on the oxide. Silicon reacts in this situation only when it comes into contact with silicon, and this process is referred to as selective epitaxial deposition. For selective epitaxial deposits, silicon deposits only on the silicon surface, so no epitaxial silicon is deposited on the edge 16 of cavity 15 shown in FIG. 1A. Under selective epitaxial conditions, epitaxial silicon grows only on the bottom of the cavity 15, the top of the vents 14 and the surface of the top silicon layer 13. However, FIG. 1A does not show epitaxial silicon on the surface of the upper silicon layer 13 because in subsequent process steps this surface is polished to remove epitaxial silicon and smooth the surface. .. Alternatively, the reaction vessel can be adjusted so that silicon is deposited on all exposed surfaces (eg, both silicon and oxide), which is referred to as non-selective epitaxial deposition. .. Thus, the epitaxial reaction vessel can be controlled so that silicon is deposited only on silicon (selective deposit) or silicon is deposited on both silicon and oxide (non-selective deposit). ..

In addition, epitaxial silicon can be deposited conformally or non-conformally. For conformal deposits, the deposited silicon follows the shape of the edges. The conformally deposited silicon follows the contours of the object in the reaction vessel, which may be selective or non-selective. Highly conformal depositions have an even thickness wherever growth takes place. In the case of the structure shown in FIG. 1A, the thickness of the sacrificial layer 12 should be more than twice the thickness of the epitaxial silicon layer 17 to avoid filling the cavity 15. Can be done. FIG. 1A shows a conformally deposited epitaxial silicon layer 17, which grows homogeneously from the top and bottom of the cavity 15 (but not on the edge 16 representing the oxide sidewall of the cavity 15). , It has been shown that highly conformal epitaxial growth is also selective). Therefore, the thickness of the sacrificial layer 12 needs to be larger than the diameter of the vent 14 in this embodiment.

Alternatively, the non-conformal deposition allows more silicon to be deposited towards the opening of the vent 14 (and above the top silicon layer 13) than the silicon deposited at the bottom of the vent 14 and into the cavity 15. ) Can be deposited. However, non-conformal deposition tends to pinch off the vents 14 at the top, which can weaken the membrane 19. For example, if the reactants diffused into this structure react completely or almost completely, and the unreacted reactants reach the bottom with little or no reaction, growth will occur in the vents 14 and on the top surface. Although it does occur, little or no growth occurs at the bottom of the cavity 15. Further, non-conformal epitaxial deposition can be selective or non-selective.

The chemistry can be selective so that changing one of the parameters changes all the results. Deposition parameters can be modified to cause epitaxial silicon growth by adjusting, for example, the temperature, pressure, flow rate, material, etc. used in the epitaxial reaction vessel. Their parameters can be adjusted to obtain conformal or non-conformal epitaxial silicon growth as well as selective or non-selective epitaxial silicon growth.

According to one embodiment, non-conformal epitaxial silicon growth can be used when the large vent 14 is etched and the very thin sacrificial layer 12 is underneath and the vent 14 is pinched off. This is when the cavity 15 is held open. According to another embodiment, conformal epitaxial silicon growth can be used by etching the small vents 14 with a thick sacrificial layer 12 underneath and all the vents 14 uniformly closed upwards. If you can. Although not shown in FIG. 1A, epitaxial silicon can also be grown on top of the silicon layer 13 and then polished to remove it. Polishing can be performed to smooth the surface of the silicon layer 13 and remove any indentations that may form in or around the vents 14. In addition, polishing can be performed for the purpose of exposing the original mold (for example, p-type or n-type) on the surface of the silicon layer 13. FIG. 1A shows a p-type piezoelectric resistor 18 and an n-type silicon layer 13. Alternatively, the piezoelectric resistor 18 may be an n-type piezoelectric resistor and the silicon layer 13 may be a p-type.

FIG. 1A shows a cross-sectional view showing the vents 14 penetrating to the sacrificial layer 12. The pattern of the vents 14 viewed from above can be a circular pattern with a grid of those vents 14, or any basis, such as an array, for example, as shown in FIG. 1B. It may be in shape. According to one embodiment, the vent 14 is a slot or elongated hole rather than a circular hole (see, eg, FIG. 3B). With the slot-shaped vents 14, for example, the width can be quadrupled. According to another embodiment, the slot-shaped vents 14 can be oriented in different directions, which makes the silicon harder to bend in one direction and weaker in the direction perpendicular to it. Can be avoided. According to one embodiment, the vents 14 can be arranged in a basket weave pattern, where each slot is arranged orthogonally to adjacent slots (see, eg, FIG. 3B). According to one embodiment, the vents 14 can be arranged in a square array. According to a further alternative embodiment, the vents can be arranged in a circular array or a hexagonal array.

In the case of the embodiment of the present invention shown in FIG. 1B, four piezoelectric resistors 18 can be used. The orientation of the piezoelectric resistor 18 with respect to the strain to be measured affects the measurement. FIG. 1B shows two piezoelectric resistors 18 arranged parallel to the strain and two piezoelectric resistors 18 arranged perpendicular to the strain, which is, for example, a circular film in the silicon layer 13. It is located at 12 o'clock and 3 o'clock on 19. A piezoelectric resistor is placed parallel to the strain at the 12 o'clock position, and a piezoelectric resistor 18 is placed perpendicular to the strain at the 12 o'clock position. In addition to this, a piezoelectric resistor 18 is placed parallel to the strain at the 3 o'clock position, and a piezoelectric resistor 18 is placed perpendicular to the strain at the 3 o'clock position. The field of strain around the cavity under the membrane 19 is approximately perpendicular to the edge of the circular membrane 19, so if the piezoelectric resistors 18 are aligned parallel to the strain, then that resistance when the strain increases. Becomes larger. Alternatively, if the piezoelectric resistors 18 are aligned perpendicular to the strain, the resistance will decrease as the strain increases. Two piezoelectric resistor pairs 18 can be equilibrated in the form of bridges to reduce thermal effects. An alternative position is also possible for the piezoelectric resistor 18.

FIG. 1A shows a piezoelectric resistance sensor formed on an SOI wafer. Embedded cavities can be formed by patterning, etching, sealing and polishing standard SOI wafers. The polishing step can be omitted. Piezoelectric resistors 18 can then be formed along the edges of the film 19 and circuits can be formed on this wafer according to standard processes. The advantage of this approach is that the vents can be arranged so that the piezoelectric resistors can be manufactured in pure, defect-free silicon. The size of the film 19, that is, the sensitivity of the device can be satisfactorily controlled. The thickness of the upper silicon of the first SOI determines the thickness of the film 19 to some extent.

The episeal pressure sensor 10 shown in FIG. 2 can be formed on bulk silicon by forming a sacrificial oxidation region (not shown) to define an implantable cavity. According to this embodiment, starting from one wafer, oxide islands are grown and patterned on the wafer, and then silicon is epitaxially grown on the wafer to form a film 19. Epitaxial silicon that grows on top of single crystal silicon generally grows as single crystal silicon, whereas epitaxial silicon that grows on top of oxide grows as polycrystalline. What is important here is to control the epitaxial growth to cause overgrowth of the single crystal, and a piezoelectric resistor is formed in that portion. The advantage of this method is that the cost can be saved by using bulk wafers, which are less costly than SOI wafers. Moreover, by using this method, it is possible to strengthen the control of the dimensions of this film. The film thickness can be controlled simply by the epitaxial and polishing steps, while the film size can be controlled by the lithography and oxide etching steps, all of which are well controlled. Is.

In the case of the technique shown in FIG. 2, the oxide is grown or deposited on the surface of the base silicon layer 11 and patterned to form oxide islands. Oxide islands are generally circular and can be on the order of μ thickness, and can be on the order of 50 μm to 20 μm in diameter. Silicon can then be epitaxially deposited on the top of the oxide island and the top of the exposed silicon wafer. Epitaxial single crystal silicon can be deposited on single crystal silicon, while epitaxial polycrystalline silicon can be deposited on oxide. The oxide layer can then be removed by etching.

According to FIG. 2, the single crystal epi layer 21 wraps around the edge of the cavity 15. As already mentioned, the cavity 15 can be defined by an oxide layer, which is removed by etching during the process. The polycrystalline silicon layer 20 of FIG. 2 does not start immediately at the corner of the oxide (above the edge 16 of the cavity 15), but instead forms towards the center of the oxide island. Such deposition characteristics can be controlled by adjusting the parameters of the epitaxial reaction vessel. The single crystal epi layer 21 can be laterally grown over the upper edges of the oxide islands (not shown, but the removal of the oxide islands forms the cavity 15). In this way, the piezoelectric resistor 18 can be arranged on the single crystal epi layer 21. Alternatively, the formation of the polycrystalline silicon layer 20 can be initiated wherever the oxide is present.

The thickness of the membrane 19 produced by the method according to the embodiment of the present invention can be changed by changing the parameters of the epitaxial reaction vessel and changing the process time. The film 19 can have a thickness of, for example, several μ, and can be, for example, 10 μ. Also, the size of the membrane 19 can be made dependent on the pressure range in which it will be measured. High-pressure measurement can be performed using a relatively small film 19, whereas low-pressure measurement can be performed using a relatively large film 19. Membrane 19 can have a diameter on the order of 50-200 μm.

According to one embodiment, the membrane 19 can be made thinner and smaller for the purpose of saving die space. Alternatively, the film 19 can be made thicker and larger so that the amount of displacement with respect to a given pressure remains the same. By considering the design, the size and thickness of the film 19 can be determined. The thickness of epipoly can be controlled with high accuracy and predictability. In the case of alternative embodiments where the thickness of the epipoly cannot be easily controlled, the membrane 19 is made relatively thick so that changes in the thickness of the membrane 19 do not significantly affect the pressure measurement. be able to. For example, for a film with a thickness of 10μ, ± 1μ has a 10% error, which can cause a 33% sensing error. However, if the film 19 has a thickness of 40 μm, ± 1 μm has an error of 2.5%, which is a sensing error of about 8%. The size / shape / thickness of the film 19 can be determined according to the error balance analysis.

According to one embodiment of the method according to the invention for forming the pressure sensor 10, the oxide can grow or deposit uniformly and evenly over the entire surface of the base silicon layer 19. The oxide can then be patterned and removed by etching. The silicon can then be epitaxially adhered to form the single crystal epi layer 21 and the polycrystalline silicon layer 20. Then, the vent holes 14 can be formed by penetrating the polycrystalline silicon layer 20 by etching, and in some cases, a part of the single crystal epi layer 21 and the oxide left in the base silicon layer 11 can be removed by etching. it can. The other epitaxial silicon layer 17 can then be deposited to pinch off the vents 14. The surface can then be polished to form a flat surface.

Epipoly technology using silicon wafers instead of SOI wafers can be used because SOI wafers are expensive. If the oxide is etched and the cavity 15 is defined by lithography at that time, the dimensions of the cavity 15 can be defined by epipoly technology. In contrast, the dimensions of the cavity 15 generated from the SOI wafer can be defined by the value of the etching time of the oxide layer. Lithography technology allows for more precise control of cavity dimensions.

An alternative to pressure measurement using a piezoelectric strain sensor on the membrane 19 is to measure the displacement by measuring the capacitance between the membrane 19 and the bottom of the cavity 15. 3A, 3B, 4A, and 4B show the pressure sensor 10 including the capacitive element. As the membrane 19 is displaced downwards, the increased capacitance can be measured. Capacitive measurements require a membrane 19 that is electrically isolated from the bottom of the cavity 15 and generally the rest of the pressure sensor 10. In the case of FIG. 2, the silicon is continuous between the base silicon layer 11 and the surface of the polycrystalline silicon layer 20, so that the bottom of the cavity 15 and the polycrystalline silicon layer 20 are electrically connected. In this case, the capacitance cannot be measured because the bottom and top are short-circuited.

FIG. 3A shows the junction isolation type capacitive sensor 10 formed on the SOI wafer. In the case of this embodiment, the film 19 can be formed on the SOI wafer, which can be surrounded by an isolation ring 30 which can extend downward toward the sacrificial layer 12. The isolation ring 30 shown in FIG. 3A is a slot that traverses the membrane to the sacrificial layer 12 anywhere around the pressure sensor, which allows the membrane 19 to form an upper silicon layer 13 (also known as the field silicon layer). Physically separated from. The film 19 is supported on the oxide support ring 32A. The capacitive episeal pressure sensor 10 of FIG. 3A may be mechanically similar to the piezoelectric resistor of FIG. 2, but has an electrically insulating ring in the form of an isolation ring 30. If the isolation ring 30 is filled with Episeal 17, the membrane 19 can be short-circuited with the base silicon layer 11. However, Episeal 17 can be of the reverse doping type, so that the membrane 19 becomes junction isolation. In the case of this embodiment, Episeal can be grown under the same conditions as used for selective epitaxial silicon growth. The conformal epitaxial silicon growth allows the vents 14 to be sealed and at the same time grow on and inside the upper silicon layer 13 onto the silicon wall of the cavity 15. Appropriate selection of epitaxial parameters can selectively hold silicon growth inside the cavity 14 and thus keep silicon away from internal electrical insulators, such as the edge 16 of the cavity 15. The oxide support ring 32A can be an oxide that maintains the dielectric electrical insulation between the film 19 and the base silicon layer 11. Further, the oxide support ring 32A can be extended anywhere around the membrane 19 to separate the cavity 15.

The ring cavity 31 below the isolation ring 30 can be etched in the same manner as the cavity 15, which allows the film 19 to be separated from the base silicon layer 11. Further, the ring cavity 31 can be etched in the same process step as the cavity 15, which is done by properly setting the spacing between the cavity 15 and the vent 14 close to the isolation ring 30. Since the oxide support ring 32A is left, the etching can be stopped before all the oxides are removed by the etching. Further, etching can be performed so that the oxide layer 12 is processed through the isolation ring 30, and further etching can be performed laterally to form a ring cavity 31 around the outside of the cavity 15.

Therefore, the capacitance can be measured by forming an electrical contact between the membrane 19 and the base silicon layer 11, whereby the pressure can be measured. This technique provides the advantage of capacitive sensing, which is often more stable than piezoelectric sensing. By arranging the vents 14 and the isolation ring 30 at appropriate intervals, the ring cavities 31 and cavities 15 can be etched in one process step. Alternatively, the ring cavities 31 and 15 may be etched in separate process steps, in which case the vents 14 are etched and episealed prior to forming the isolation ring 30, or vice versa. Is done. For example, the cavity 15 may be etched without forming the isolation ring 30, the vents 14 may be sealed, and then the isolation ring 30 may be etched to leave oxides beneath it. In such a case, the isolation ring 30 may be etched to the upper edge of the sacrificial layer 12. The process of producing the isolation ring 30 may be any etching process capable of producing steep sidewalls. This etching may be performed downward to the ring cavity 31 to achieve isolation of the film 19. The isolation ring 30 may be left as is as an air gap, or may optionally be filled with, for example, an oxide or reverse doping type silicon.

FIG. 3B shows a plan view of the pressure sensor shown in FIG. 3A. In this case, the vents 14 are depicted as elliptical holes arranged in a basket weave pattern, but as an alternative, the vents 14 may have other shapes arranged in another alternative pattern. Includes circular holes and rounded rectangular holes. The vent 14 communicates with the cavity. The outer boundary of the cavity determines the size of the membrane 19. An isolation ring 30 is provided around the membrane 19.

FIG. 4A shows the method of the internally opposed electrode. FIG. 4A depicts a junction isolation capacitive sensor formed on a bulk wafer. The apparatus illustrated herein includes a substrate contact 41 connected to a patterned embedding 40 and a silicon support ring 32B acting as an insulated mechanical support member. These contacts and supports allow the counter electrode to be connected from the front surface of the wafer. The isolation ring 30 can be made of single crystal silicon and can be sealed with single crystal silicon, while the vent holes 14 in epipoly can be sealed with polycrystalline silicon. The episeal material can be the reverse doping type field silicon 43, which forms a pn junction around the substrate contact 41. Encapsulation can be done by polishing for the purpose of removing the reverse doping type surface. Since a post-MEMS integrated circuit is formed, standard electronic processing can be performed on this wafer.

Similar to the epipoly membrane with the piezoelectric sensor, the embodiment shown in FIG. 4A also requires control of the interface between epipoly and single crystal silicon. Field Silicon 43 can be grown in three steps. In the first step, single crystal silicon can be grown to the level of the gasket oxide and beyond the gasket oxide until it touches the upper side of the contact oxide ring (which defines the ring cavity 31). This is a selective deposition due to lateral overgrowth. In the second step, non-selective polycrystalline seeds can be deposited on the exposed oxide, while single crystal silicon can grow on the exposed single crystal regions. In the third step, epipoly and single crystal silicon can be grown to the desired encapsulation thickness. This sequence ensures that the substrate contact 41 is covered with single crystal silicon, resulting in minimal electrical leakage of the junction isolation diode formed in the contact.

The device illustrated in FIG. 4A has an anti-doping post 32 relative to the bulk substrate 11, which forms a mechanical support for junction isolation. The substrate contact 41 can be formed by a post of the same type as the patterned embedded portion 40. Internal silicon film accumulation and depletion need to be considered as a function of film and counter electrode bias to manage the problem of the patterned embedding 40 being electrostatically shielded by the internally deposited epitaxial layer 17. There is.

According to the embodiment of FIG. 4A, a capacitance sensor 10 with two front contacts is shown. Techniques for manufacturing the sensor 10 of FIG. 4A include growing reverse doping type epitaxial silicon 21,41,43 on top of the base silicon layer 11. In the case of FIGS. 1A, 1B, 2, 3A and 3B, the same type of silicon is used, whereas in FIG. 4A, the p-type is formed on the n-type layer (for example, the base silicon layer 11). How to form a layer (eg field silicon 43) is shown. The n-type silicon wafer can be used as the base silicon layer 11 (that is, the handle wafer). The patterned p-type embedding portion 40 is embedded in the n-type handle wafer (base silicon layer 11). Then, a p-type single crystal is grown on the upper surface, thereby forming a p-type contact with the p-type embedded portion as the substrate contact 41. The p-type allows junction isolation to be formed on top of the n-type substrate. The substrate contact 41 can be brought into contact with the patterned embedding 40, while the rest is electrically insulated from the substrate silicon layer 11 and / or field silicon 43. Thus, two contacts for measuring the capacitance between the membrane 19 and the bottom of the cavity 15 can be obtained at each of the polycrystalline layer 20 (forming the membrane 19) and the substrate contact 41.

FIG. 4B shows a plan view of the capacitive pressure sensor 10 of FIG. 4A. Isolation ring 30, vents 14 and / or electrical contacts Isolation trench 42 is filled with epitaxially deposited silicon, which is doped in reverse with field silicon 43, membrane 19 and / or substrate contacts. It can be 41.

The following process steps can be included in the omitted steps for forming the sensor 10 in FIGS. 4A and 4B. That is, starting from an n-type wafer, implanting a p-type embedding, depositing or growing one complete oxide layer, etching the oxide layer to form an island shape, and placing the product in an epitaxial reaction vessel. Put in to make the top layer, polish the top layer, etch using an appropriate etching method to create vents that penetrate the oxide layer, remove all or some of the oxide islands by etching, vents Seal and polish the surface. The dopant type may be reversed.

FIG. 5 shows a cross-sectional view of the pressure sensor according to an embodiment of the present invention, which is provided with a contact for a capacitance sensor separated from the others on the upper side. The pressure sensor element of FIG. 5 can be formed by the following method. That is, first the oxide layer is deposited on the silicon wafer, then the oxide layer is patterned, then the silicon is deposited and patterned to form the bottom sensor element, and then the oxide is deposited and patterned. .. The silicon encapsulation layer is then deposited and the layer is patterned to form vents (which may be tapered or straight) and rings that separate the top of the film, followed by oxides and other oxide layers. Some are removed through the vents, leaving at least one oxide pillar, the silicon layer located at the bottom of the cavity is dielectric insulated, and finally the vents are sealed with silicon. The final sealing step prevents silicon from forming on the oxide pillars. The silicon layer arranged below the cavity is separated from the silicon wafer and the surrounding silicon layer. FIG. 5 shows an insulating layer 51 (which can be an oxide), which is deposited on top of the base silicon layer 11. The insulating layer 51 can be etched and / or patterned prior to the deposition of the silicon sensor element layer 52. The silicon sensor element layer 52 can be etched and / or patterned prior to deposition of the second oxide layer, which can also be etched and / or patterned. The silicon encapsulation layer 54 is then deposited and etched and / or patterned to form vents 14 and / or isolation rings 30. The second oxide is removed by etching through the vents 14 and / or the isolation ring 30. The portion of the insulating layer 51 can also be removed in this etching step, which allows silicon. The sensor element layer 52 is undercut to form pillars 60 in the insulating layer 51. The vents 14 and / or the isolation ring 30 are then sealed with silicone. Even if the cavity 15 is sealed, an epitaxial reaction vessel can be used to seal the vents 14 and / or the isolation ring 30. Adjust the steps to seal the vents 14 and / or the isolation ring 30 to prevent silicon from depositing on the pillars 60, thereby maintaining dielectric separation of the silicon sensor element layer 52. The silicon encapsulation layer 54 forms the upper sensor element contact 57 and the lower sensor element contact 58.

FIG. 6A shows the vents 14 arranged within the membrane 19. The vents 14 can be closed by a fully conformal epitaxial process, which deposits the epitaxial layer 17 so that the vents are evenly closed from bottom to top. The vent 14 shown in FIG. 6B can be closed by a partially conformal or non-conformal epitaxial process. The vents 14 arranged in the membrane 19 as shown in FIG. 6B are initially closed near the top, thereby stopping the deposition of the epitaxial layer 17 inside. The notch 61 is formed by the pinch-off of the epitaxial layer 17 near the upper portion of the ventilation hole 14. The notch 61 then causes stress concentration, which weakens the membrane. The vent 14 in the membrane 19 shown in FIG. 6C has a tapered cross section, in which the width of the bottom cross section of the vent 14 is narrower than the width of the top cross section. In this case, the smaller cross-sectional width at the bottom is closed faster than at the top, which allows the epitaxial layer 17 to be continuously deposited towards the outer surface of the upper membrane. As a result, a homogeneous seal is possible, so that the notch 61 is eliminated and a stronger and / or more predictable flexible film 19 can be formed. The tapered vents 14 are suitable for non-conformal or partially conformal deposition processes. Alternatively, FIGS. 6A, 6B, and 6C show how various epitaxial processes can be used to close the trench.

FIG. 7 shows a flowchart showing an embodiment according to the present invention. This process starts at Circle 72 and proceeds to Question 71 where the wafer is asked if it is an SOI wafer. If the answer is negative, the process flow proceeds to action 72, which deposits or grows over the area defining the pressure sensor membrane. The process flow from action 72 to action 73, which covers the area with epitaxial polysilicon (epipoly). The process flow from Action 73 to Action 74, where patterning and etching takes place to form vents through the epipoly to the embedded oxide. If the answer to question 71 is affirmative, the process flow goes directly from there to action 74. The process flow goes from action 74 to action 75, which removes the embedded oxide. Action 75 can generally include HF vapor phase etching. In addition to this, according to Action 75, the embedded oxide is completely etched if the oxide was lithographically patterned, but the etching time is limited if SOI wafers are used, which results in cavities. The lateral spread of is restricted. The process flow from action 75 to action 76, which fills the vents with epitaxial silicon deposition. From action 76, the process flow proceeds to action 77, where the top silicon surface is polished. From action 77, the process flow proceeds to question 78, where it is inquired whether the sensor to be used is a capacitance sensor. If the answer is negative, the process flow proceeds to action 79, which places a strain gauge on the membrane. As already explained, multiple piezoelectric resistors can be placed when arranging the strain gauge, and some of these piezoelectric resistors are positioned perpendicular to the distortion. On the other hand, some are positioned parallel to the distortion. The process flow goes from action 79 to action 80, which installs electrical contacts. These electrical contacts can be piezoelectric resistors or contacts to other strain gauges, contacts to capacitors that include a back connection, or contacts to a capacitor that has a front connection. If the answer to Question 78 is affirmative, the process flow goes directly to Action 80. From action 80, the process flow ends and proceeds to circle 81.

According to the alternative embodiment, any of the substrates described above can be modified to form an opening from the back to the cavity at any point in the manufacturing process. By providing the opening in this way, the pressure sensor in the device configuration illustrated can be deformed to be a differential pressure sensor, whereby the pressure difference from the front surface of the substrate to the back surface of the substrate can be measured.

Post-MEMS CMOS integrated circuits can also be supported. Although some embodiments have been described so far, other embodiments are also valid within the framework of the idea of the present invention. The epitaxially sealed silicon can be replaced with silicon deposited by CVD (Chemical Vapor Deposition). In addition to this, silicon can contain various concentrations of germanium, carbide, boron, phosphorus, or other suitable material in any of the aforementioned devices and / or in any process step.

Deformations in such a procedure provide a sensor with special advantages. For example, in SOI structures, manufacturing steps can be reduced and the highest quality top silicon can be provided. Episeal silicones that are alternately doped in different types can be used to generate junction isolation contacts, and implants can be used to form patterned counter electrodes. In some embodiments, the dopant form of silicon may be reversed, for example, p-type may be n-type and n-type may be p-type. Although the expression "part" is used in the claims, those "parts" are given serial numbers common to all the pressure sensors according to the present invention. That is, for example, it is expressed as the first part of the sacrificial layer, the second part of the bulk wafer, and the third part of the sacrificial layer, and the serial numbering process is performed focusing on the "part".

<figref num="1A">FIG. 5 is a cross-sectional view showing a pressure sensor according to one embodiment of the present invention utilizing conformal and selective epitaxial growth and a strain gauge on an SOI wafer.</figref><figref num="1B">FIG. 5 is an upper cross-sectional view of the embodiment shown in FIG. 1A cut along line IB.</figref><figref num="2">FIG. 5 is a cross-sectional view showing a pressure sensor according to one embodiment of the present invention utilizing conformal, non-selective epitaxial growth and strain gauges on a silicon wafer.</figref><figref num="3A">FIG. 5 is a cross-sectional view showing a pressure sensor according to one embodiment of the present invention utilizing a conformal and selective epitaxial growth and capacitance sensor on an SOI wafer.</figref><figref num="3B">It is the upper sectional view which cut the embodiment shown in FIG. 3A along the line IIIB.</figref><figref num="4A">FIG. 5 is a cross-sectional view showing a pressure sensor according to one embodiment of the present invention utilizing a conformal, non-selective epitaxial growth and capacitance sensor on a silicon wafer.</figref><figref num="4B">FIG. 5 is an upper cross-sectional view of the embodiment shown in FIG. 4A cut along line IVB.</figref><figref num="5">FIG. 5 is a cross-sectional view showing a pressure sensor according to an embodiment of the present invention having a separate contact for a capacitance sensor on the top side.</figref><figref num="6A">FIG. 5 is a cross-sectional view showing vents of various geometric shapes sealed using conformal and non-conformal epitaxial silicon deposition.</figref><figref num="6B">FIG. 5 is a cross-sectional view showing vents of various geometric shapes sealed using conformal and non-conformal epitaxial silicon deposition.</figref><figref num="6C">FIG. 5 is a cross-sectional view showing vents of various geometric shapes sealed using conformal and non-conformal epitaxial silicon deposition.</figref><figref num="7">It is a flowchart which shows the episeal type pressure sensor manufacturing method by embodiment of this invention.</figref>

Code description

10 Pressure sensor 11 Base silicon layer 12 sacrificial layer 13 Upper silicon layer 14 vents 15 cavities 16 edges 17 epitaxial silicon layer 18 Piezoelectric resistor 19 membrane 30 isolation ring 31 Ring cavity 32A oxide support ring 40 Embedded part 41 Board contacts 42 Contact Isolation Trench 43 Field Silicon