Information security apparatus
24 claims: 10 independent, 14 dependent
- 1予め設定された秘密データを出力する情報セキュリティ装置であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路と、 第1の訂正用データを記憶している訂正用データ記憶手段と、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路と、 前記訂正用データ記憶手段に記憶されている第1の訂正用データと、前記第2の耐タンパー回路から出力される第2の訂正用データとを用いて、誤り訂正情報を生成する訂正情報生成手段と、 前記訂正情報生成手段により生成された誤り訂正情報を用いて、前記第1の耐タンパー回路から出力される秘密データに対して誤り訂正を行い、誤り訂正された前記秘密データを出力する誤り訂正手段と を備えることを特徴とする情報セキュリティ装置。
- 2前記情報セキュリティ装置は、さらに、 入力データを取得する取得手段と、 前記誤り訂正手段から出力される秘密データを鍵として用い、前記鍵により前記入力データを暗号化する暗号化手段とを備える ことを特徴とする請求項1記載の情報セキュリティ装置。
- 3前記第1の耐タンパー回路に設定される秘密データと、前記第2の耐タンパー回路に設定される第2の訂正用データとは、PUF(Physically Unclonable Function)により設定されている ことを特徴とする請求項1記載の情報セキュリティ装置。
- 4前記第1の耐タンパー回路は、1ビットの値を前記秘密データの少なくとも一部として出力する1つ以上の第1のPUF回路を備え、 前記第2の耐タンパー回路は、2ビット以上の値を前記第2の訂正用データの少なくとも一部として出力する1つ以上の第2のPUF回路を備える ことを特徴とする請求項3記載の情報セキュリティ装置。
- 5前記第1の耐タンパー回路は、1つ以上の第1のPUF回路を備え、 前記第1のPUF回路は、 発振信号を出力するN(N≧2)個の発振部と、 前記N個の発振部からM(M≦N)個の発振部を選択する選択部と、 前記選択部により選択されたM個の発振部から出力される発振信号の周波数の大小関係に基づいて出力値を決定して出力する決定部とを備え、 前記選択部は、前記決定部によって決定される出力値が前記予め定められた秘密データの少なくとも一部を示すようにM個の発振部を選択する ことを特徴とする請求項3記載の情報セキュリティ装置。
- 6前記選択部は、前記M個の発振部から出力される発振信号の周波数の差分が第1の閾値以上となるように前記M個の発振部を選択する ことを特徴とする請求項5記載の情報セキュリティ装置。
- 7前記情報セキュリティ装置は、さらに、 前記誤り訂正手段から出力される誤り訂正後の秘密データと、前記第1の耐タンパー回路から出力される秘密データとを比較することにより、前記第1の耐タンパー回路から出力される秘密データに誤りが生じたか否かを判別する誤り判別手段と、 前記誤り判別手段により誤りが生じたと判別されたときには、前記第1の耐タンパー回路に対して、前記予め定められた秘密データの再設定を要求する再設定要求手段とを備え、 前記第1のPUF回路は、さらに、 前記再設定要求手段から再設定の要求を受け付けたときには、前記選択部による選択を再度実行させることにより、前記予め定められた秘密データの再設定を行う再設定部を備える ことを特徴とする請求項6記載の情報セキュリティ装置。
- 8前記第1のPUF回路は、さらに、 前記予め定められた秘密データの少なくとも一部を記憶するための秘密データ用記憶部と、 前記選択部がM個の発振部を選択する際に、前記発振周波数の差分が前記第1の閾値以上となるようなM個の発振部を選択することができないときに、前記秘密データの少なくとも一部を前記秘密データ用記憶部に格納する格納処理部と、 前記秘密データ用記憶部に前記秘密データの少なくとも一部が格納されているときには、前記決定部による出力値の決定を禁止し、前記秘密データ用記憶部に格納されている前記秘密データの少なくとも一部を出力する出力制御部とを備える ことを特徴とする請求項7記載の情報セキュリティ装置。
- 9前記第1の耐タンパー回路は、 複数の前記第1のPUF回路と、 前記複数の第1のPUF回路から出力される出力値を結合することにより秘密データを生成する結合部とを備え、 前記誤り判別手段は、前記第1の耐タンパー回路から出力される秘密データに誤りが生じたと判別するときには、さらに、前記複数の第1のPUF回路のうち、誤った出力値を出力する第1のPUF回路を特定し、 前記再設定要求手段は、誤った出力値を出力していると特定された第1のPUF回路に対して、出力値が前記予め定められた秘密データの一部を示すように、出力値の再設定を要求する ことを特徴とする請求項7記載の情報セキュリティ装置。
- 10前記情報セキュリティ装置は、さらに、 前記誤り訂正手段から出力される誤り訂正後の秘密データと、前記第1の耐タンパー回路から出力される誤り訂正前の秘密データとを比較することにより、前記誤り訂正前の秘密データに誤りが生じたか否かを判別する誤り判別手段と、 前記誤り判別手段により誤りが生じたと判別されたときには、前記第1の耐タンパー回路に対して、前記予め定められた秘密データの再設定を要求する再設定要求手段とを備え、 前記第1のPUF回路は、さらに、 前記予め定められた秘密データの少なくとも一部を記憶するための秘密データ用記憶部と、 前記再設定要求手段から再設定の要求を受け付けたときには、前記秘密データの少なくとも一部を前記秘密データ用記憶部に格納する格納処理部と、 前記秘密データ用記憶部に前記秘密データの少なくとも一部が格納されているときには、前記決定部による出力値の決定を禁止し、前記秘密データ用記憶部に格納されている前記秘密データの少なくとも一部を出力する出力制御部とを備える ことを特徴とする請求項6記載の情報セキュリティ装置。
- 11前記第1のPUF回路は、さらに、 前記M個の発振部から出力される発振信号の周波数の差分が第2の閾値未満であるか否かを判別する差分判別部と、 前記差分判別部によって前記第2の閾値未満であると判別されると、前記選択部による選択を再度実行させることにより、前記予め定められた秘密データの再設定を行う再設定部とを備える ことを特徴とする請求項6記載の情報セキュリティ装置。
- 12前記第1のPUF回路は、さらに、 前記第1および第2の閾値のうちの少なくとも一方を格納している閾値格納部と、 前記閾値格納部に格納されている、前記第1および第2の閾値のうちの少なくとも一方を更新する更新部とを備える ことを特徴とする請求項11記載の情報セキュリティ装置。
- 13前記選択部は、 前記M個の発振部から出力される発振信号の周波数の差分が第1の閾値以上となるような前記M個の発振部を検索する検索部と、 前記検索部によって検索されたM個の発振部を示す選択パラメータを保持するパラメータ保持部と、 前記パラメータ保持部に保持されている選択パラメータの示すM個の発振部を選択すべきM個の発振部と決定して選択する選択決定部とを備える ことを特徴とする請求項6記載の情報セキュリティ装置。
- 14秘密データの誤りを訂正するための第1の訂正用データを生成するデータ生成装置であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から出力される出力値を計測する第1の計測手段と、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から出力される出力値を計測する第2の計測手段と、 前記第1および第2の計測手段によって計測された出力値に基づいて、前記第1の訂正用データを生成するデータ生成手段と、 前記データ生成手段によって生成された前記第1の訂正用データを記憶媒体に格納する格納処理手段と を備えることを特徴とするデータ生成装置。
- 15前記データ生成手段は、 前記第1の計測手段によって計測された出力値と、前記秘密データの示す値との差分を算出することにより、誤り訂正情報を生成する第1の生成手段と、 前記第2の計測手段によって計測された出力値と、前記誤り訂正情報の示す値との差分を算出することにより、前記第1の訂正用データを生成する第2の生成手段とを備える ことを特徴とする請求項14記載のデータ生成装置。
- 16前記第1および第2の計測手段は、出力値の計測を繰り返し行い、 前記第1の生成手段は、繰り返し計測された出力値の分布に基づいて特定される出力値を用いて前記誤り訂正情報を生成し、 前記第2の生成手段は、繰り返し計測された出力値の分布に基づいて特定される出力値を用いて前記第1の訂正用データを生成する ことを特徴とする請求項15記載のデータ生成装置。
- 17前記データ生成装置は、さらに、 前記第1および第2の耐タンパー回路から出力される出力値の計測が行われるごとに、前記第1および第2の耐タンパー回路の周辺環境を変化させる環境変化手段を備える ことを特徴とする請求項16記載のデータ生成装置。
- 18前記環境変化手段は、前記第1および第2の耐タンパー回路の周辺温度を変化させる ことを特徴とする請求項17記載のデータ生成装置。
- 19予め設定された秘密データを出力する情報セキュリティ方法であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から秘密データを出力させる第1の出力ステップと、 第1の訂正用データを記憶している訂正用データ記憶手段から前記第1の訂正用データを出力させる第2の出力ステップと、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から第2の訂正用データを出力させる第3の出力ステップと、 前記第2の出力ステップで出力される第1の訂正用データと、前記第3の出力ステップで出力される第2の訂正用データとを用いて、誤り訂正情報を生成する訂正情報生成ステップと、 前記訂正情報生成ステップで生成された誤り訂正情報を用いて、前記第1の出力ステップで出力される秘密データに対して誤り訂正を行い、誤り訂正された前記秘密データを出力する誤り訂正ステップと を含むことを特徴とする情報セキュリティ方法。
- 20秘密データの誤りを訂正するための第1の訂正用データを生成するデータ生成方法であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から出力される出力値を計測する第1の計測ステップと、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から出力される出力値を計測する第2の計測ステップと、 前記第1および第2の計測ステップで計測された出力値に基づいて、前記第1の訂正用データを生成するデータ生成ステップと、 前記データ生成ステップで生成された前記第1の訂正用データを記憶媒体に格納する格納ステップと を含むことを特徴とするデータ生成方法。
- 21予め設定された秘密データを出力するためのプログラムであって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から秘密データを出力させる第1の出力ステップと、 第1の訂正用データを記憶している訂正用データ記憶手段から前記第1の訂正用データを出力させる第2の出力ステップと、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から第2の訂正用データを出力させる第3の出力ステップと、 前記第2の出力ステップで出力される第1の訂正用データと、前記第3の出力ステップで出力される第2の訂正用データとを用いて、誤り訂正情報を生成する訂正情報生成ステップと、 前記訂正情報生成ステップで生成された誤り訂正情報を用いて、前記第1の出力ステップで出力される秘密データに対して誤り訂正を行い、誤り訂正された前記秘密データを出力する誤り訂正ステップと をコンピュータに実行させることを特徴とするプログラム。
- 22秘密データの誤りを訂正するための第1の訂正用データを生成するためのプログラムであって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から出力される出力値を計測する第1の計測ステップと、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から出力される出力値を計測する第2の計測ステップと、 前記第1および第2の計測ステップで計測された出力値に基づいて、前記第1の訂正用データを生成するデータ生成ステップと、 前記データ生成ステップで生成された前記第1の訂正用データを記憶媒体に格納する格納ステップと をコンピュータに実行させることを特徴とするプログラム。
- 23予め設定された秘密データを出力する集積回路であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路と、 第1の訂正用データを記憶している訂正用データ記憶手段と、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路と、 前記訂正用データ記憶手段に記憶されている第1の訂正用データと、前記第2の耐タンパー回路から出力される第2の訂正用データとを用いて、誤り訂正情報を生成する訂正情報生成手段と、 前記訂正情報生成手段により生成された誤り訂正情報を用いて、前記第1の耐タンパー回路から出力される秘密データに対して誤り訂正を行い、誤り訂正された前記秘密データを出力する誤り訂正手段と を備えることを特徴とする集積回路。
- 24秘密データの誤りを訂正するための第1の訂正用データを生成する集積回路であって、 予め定められた秘密データを出力するように物理特性を利用して設定された耐タンパー性を有する第1の耐タンパー回路から出力される出力値を計測する第1の計測手段と、 第2の訂正用データを出力するように物理特性を利用して設定された耐タンパー性を有する第2の耐タンパー回路から出力される出力値を計測する第2の計測手段と、 前記第1および第2の計測手段によって計測された出力値に基づいて、前記第1の訂正用データを生成するデータ生成手段と、 前記データ生成手段によって生成された前記第1の訂正用データを記憶媒体に格納する格納処理手段と を備えることを特徴とする集積回路。
Independent claims24
211 paragraphs, as filed
The present invention relates to a system that realizes authentication and encryption, and relates to an information security device that securely implements secret data such as a key used in encryption processing and device-specific ID data in a form protected from analysis.
In recent years, there have been many cases in which encryption processing is performed by various consumer devices for the purpose of protecting the copyright of digital contents and concealing communication data on the Internet. In the encryption process, it is necessary to store the key and ID data used for the process in the device, and the security of the copyright protection system and the confidential communication system largely depends on the confidentiality of the key and the ID data. Therefore, it is necessary to securely store such confidential data in a form protected from analysis from outside the device.
Typical conventional methods for securely storing confidential data include storing it in a hardware chip with high tamper resistance (tamper-resistant chip) or embedding it in a software program with tamper resistance. there were. However, although the former method can realize high confidentiality of confidential data, there is a problem that the cost is high because a special dedicated chip is required, and the latter method generally realizes too high confidentiality. It was not possible, and there was a possibility that confidential data would be exposed by conducting analysis over time.
There is a technology called PUF (Physically Uncloanable Function) as a method that can realize high confidentiality of confidential data without requiring special hardware such as anti-tamper chips. PUF is a method of accumulating secret data that is resistant to physical analysis by utilizing the physical characteristics of the device. There are various specific methods of PUF, but among them, the method called Silicon PUF disclosed in Patent Document 1 does not require a special environment or equipment for manufacturing, and therefore has high tamper resistance at low manufacturing cost. It can be said that this method is particularly suitable for consumer equipment that requires low cost.
(Overview of Silicon PUF) FIG. 1 is a diagram showing the configuration of a circuit that realizes a conventional Silicon PUF. In FIG. 1, the PUF circuit 2000 is a circuit that outputs 1-bit secret data when a trigger signal is input.
The PUF circuit 2000 includes eight ring oscillators (first ring oscillator 2001 to eighth ring oscillator 2008) and a ring oscillator selection unit (first ring oscillator selection unit) that selects one of the eight ring oscillators based on input data. 1 Ring oscillator selection unit 2011 and 2nd ring oscillator selection unit 2012) and frequency count unit (1st frequency count unit 2021 and 2nd frequency count unit 2022) that counts the oscillation frequency of the ring oscillator selected by the ring oscillator selection unit. ) And the output bit determination unit 2030 that determines the output bit of the PUF circuit 2000 based on the counted frequency. The operation of the PUF circuit 2000 will be described below.
First, the ring oscillator selection units 2011 and 2012 each select a predetermined one from eight ring oscillators 2001 to 2008. Next, a trigger signal is input to the ring oscillators 2001 to 2008, and the ring oscillator starts an oscillation operation. The frequency counting units 2021 and 2022 measure the output signals from the ring oscillators selected by the ring oscillator selection units 2011 and 2012, respectively, and measure the oscillation frequency of the ring oscillators. Then, the output bit determination unit 2030 compares the two measured oscillation frequencies and determines the output bit of the PUF circuit 2000 according to the magnitude relationship.
When a trigger signal is input to the PUF circuit 2000 by the above series of operations, only one output bit is determined and output inside the PUF circuit 2000. The eight ring oscillators 2001 to 2008 have the same circuit configuration such as the number of ring oscillator stages, but there are slight variations in physical characteristics such as delay time in the manufacturing process. As a result, the oscillation frequency of each ring oscillator becomes a slightly different value. The difference is determined in an unpredictable way when manufacturing a PUF circuit, and it differs from PUF circuit to PUF circuit. The output bit differs depending on the oscillation frequency. The correspondence between the output bits and the input data can be analyzed by measuring the oscillation frequency of each ring oscillator in the PUF circuit. However, if the PUF circuit is subjected to an external analysis operation based on the oscillation frequency, for example, by blowing, the physical characteristics of the ring oscillator will change and the same oscillation frequency as when calculating the output bit cannot be measured. , It is difficult to investigate the correspondence between the output bits and the input data by external analysis. In addition, since the PUF circuit can be realized by a combination circuit such as a ring oscillator, frequency counter, and comparator, it does not require a special manufacturing environment or equipment, and can be manufactured at low cost using a normal LSI manufacturing environment / equipment. It is possible.
(Issues of Silicon PUF) As mentioned above, Silicon PUF technology has made it possible to implement functions that have different input / output relationships for each chip in a form that is difficult to analyze at low cost, but there are also the following problems. The output bit of the PUF circuit is determined by the magnitude relation of the oscillation frequency of the ring oscillator selected based on the input data. As explained earlier, the transmission frequency of the ring oscillator varies due to variations in physical characteristics such as the delay time during circuit manufacturing, but the magnitude relationship between the two ring oscillators, which have only a slight difference in frequency, is the temperature change, etc. There is a risk that it will be reversed depending on the external environment. For example, suppose that two ring oscillators A and B are selected by a certain input data, and the oscillation frequencies are measured as 1256 Hz and 1245 Hz, respectively. At this time, the output bit value is determined to be "1" from [A oscillation frequency]> [B oscillation frequency]. Further, when the same input data is input to this PUF circuit at different timings, the same ring oscillators A and B are selected, but at this time, it is assumed that the external temperature rises more than before. In that case, since the delay time of the ring oscillator increases, the oscillation frequency also decreases, but the degree of decrease also varies slightly depending on the ring oscillator. If the frequency difference between the two is small, the magnitude relationship may be reversed. In the above example, the frequency difference between the ring oscillators A and B is only 9 Hz, so the magnitude relationship of [A oscillation frequency]> [B oscillation frequency] may be reversed due to temperature changes. That is, in some cases, different output bit values may be output for the same input data, and there is a problem in the stability of the output bit values.
(Improvement of Slilicon PUF) In response to the above problem, in the conventional method, an error correction code is introduced to correct an error in the output value (value of the output bit) to improve the stability.
FIG. 2 shows the configuration of the information security device 3000 in the conventional method. The information security device 3000 outputs a keyed hash value using a key generated by using PUF for input data input from the outside. The keyed hash value is generated using the keyed hash function. The keyed hash function is described on pages 189 to 195 of Non-Patent Document 1.
The information security device 3000 uses an input unit 3001 that receives input data from the outside, an output unit 3002 that outputs a keyed hash value, a hash generator 3003 that generates a keyed hash value, and a PUF to generate a key. It includes a PUF unit 3004, an error correction unit 3005 that corrects a key based on error correction information and generates a hash key after correction, and an error correction information storage unit 3006 that stores error correction information.
The PUF unit 3004 includes a plurality of the above PUF circuits 2000, for example, six, and the key is six bits in which the output bits of each PUF circuit are connected.
The operation of the information security device 3000 is shown below. The input unit 3001 accepts the input of external data, thereby inputting the trigger signal to the PUF circuit 2000 in the PUF unit 3004. The PUF circuit 2000 generates output bits, and the PUF unit 3004 uses the concatenation of the output bits of the six PUF circuits 2000 as a key. After that, the error correction unit 3005 corrects the key using the error correction information and generates a corrected hash key. Further, the hash generation unit 3003 uses the corrected hash key to generate a keyed hash value of the input data, and the output unit 3002 outputs this.
The error correction information is determined by measuring the value of the PUF circuit 2000 in the PUF unit 3004 at the time of manufacturing the information security device 3000. Specifically, the key of the PUF unit 3004 is measured multiple times, the value of the key that occurs with the highest probability is obtained, the error correction information is determined for this, and the error correction information storage unit 3006 stores the key. To do.<patcit num="1"><text>U.S. Patent Application Publication No. 2003/2020443</text></patcit><nplcit num="1"><text>Tatsuaki Okamoto, Hirosuke Yamamoto, "Modern Code", Industrial Books (1997)</text></nplcit>
<p> However, in the above-mentioned prior art, by analyzing the error correction information stored in the memory (error correction information storage unit 3006), the key value of the corrected hash key input from the error correction unit 3005 to the hash generation unit 3003 can be obtained. There is a problem that it becomes easy to obtain.</p><p> For example, consider a method of error correction using a repeating code for every 3 bits. In the repeat code, the 3-bit Hamming weight is calculated, and if it is 1 or less, it is decoded as "0", and if it is 2 or more, it is decoded as "1". For example, if it is "011", it is decoded as "1". The output of the above PUF section 3004 is 6 bits, but this is divided into 3 sets of 2 bits, and the error correction information is a total of 3 bits, which is a combination of 3 sets of 1 bit of the 3-bit repeat code. .. At the time of manufacturing the information security device 3000, the output value of the PUF unit 3004 is measured, and the output value that occurs with the highest probability is assumed to be "1100 01". The error correction information is "XYZ" (X, Y, Z are 0 or 1). At this time, the first code is "11X", but when this is decoded, it becomes "1". Set "X" to 1 so that even if an error occurs here, it can be decoded correctly. Similarly, set Y to 0. "Z" can be set to either 0 or 1, but here it is set to "1". Then, the error correction information is "1 0 1", and the decrypted value, that is, the corrected hash key is "1 0". 1 . Therefore, the error correction information and the corrected hash key become equal, and the attacker can know the corrected hash key by analyzing the error correction information.</p><p> The above example is explained in an extreme case, but even if such an error correction method and error correction information are not set, it is easy for an attacker to obtain the key value of the corrected hash key using the error correction information. There is a possibility of becoming. When the key value is obtained, the attacker creates a PUF simulator that stores it in memory and uses it for the keyed hash function, and forgery using it becomes possible, so confidentiality cannot be maintained.</p><p> As described above, the conventional technique has a problem that the safety of PUF is low.</p><p> Therefore, an object of the present invention is to solve the above-mentioned problems, and to provide an information security device in which the security of PUF is not deteriorated even if the information stored in the memory is analyzed by an attacker. That is, it is an object of the present invention to provide an information security device having improved stability and confidentiality of confidential data.</p>
<p> In order to achieve the above object, the information security device according to the present invention is an information security device that outputs preset secret data, and utilizes physical characteristics so as to output predetermined secret data. The first tamper resistance circuit having the set tamper resistance, the correction data storage means for storing the first correction data, and the physical characteristics for outputting the second correction data are used. The second tamper resistance circuit having the tamper resistance set in the above mode, the first correction data stored in the correction data storage means, and the second tamper resistance circuit output from the second tamper resistance circuit. Using the correction information generating means for generating error correction information using the correction data, and the secret data output from the first tamper-resistant circuit using the error correction information generated by the correction information generating means. It is characterized by providing an error correction means for performing error correction on the subject and outputting the error-corrected secret data. For example, the secret data set in the first anti-tamper circuit and the second correction data set in the second anti-tamper circuit are set by PUF (Physically Unclonable Function).</p><p> As a result, the error correction information directly used for error correction of the secret data is not stored in the memory as in the conventional case, but is generated by using the second tamper resistant circuit. The error correction information can be made difficult to find, and as a result, the security and confidentiality of the secret data set in the first tamper-resistant circuit can be improved. Further, in the present invention, even if an error occurs in the secret data output from the first tamper resistant circuit due to environmental changes such as ambient temperature or aging factors, the error is corrected by the error correction information. Data stability can be improved.</p><p> Further, the information security device further includes an acquisition means for acquiring input data and an encryption means for encrypting the input data with the key by using the secret data output from the error correction means as a key. It may be characterized by that.</p><p> For example, the input data is converted into a hash value with a key or a ciphertext. As a result, the security of the hash value with a key and the ciphertext can be enhanced.</p><p> Further, the first anti-tamper circuit includes one or more first PUF circuits that output a 1-bit value as at least a part of the secret data, and the second anti-tamper circuit has 2 bits or more. It may be characterized by including one or more second PUF circuits that output the value of the second correction data as at least a part of the second correction data.</p><p> For example, if only a 1-bit value is output from the second PUF circuit, the value may be incorrect due to noise or the like. However, in the present invention, since the second PUF circuit outputs a value of 2 bits or more, even if an error occurs in one of the bits, the error can be easily corrected, and the second tamper resistant circuit can be used. It is possible to improve the noise resistance of the second correction data output from.</p><p> Further, the first tamper resistant circuit includes one or more first PUF circuits, and the first PUF circuit includes N (N 2) oscillators that output oscillation signals and the N. Output value based on the magnitude relationship between the frequency of the selection unit that selects M (M N) oscillation units from the three oscillation units and the frequency of the oscillation signal output from the M oscillation units selected by the selection unit. The selection unit selects M oscillator units so that the output value determined by the determination unit indicates at least a part of the predetermined secret data. It may be characterized by that. Specifically, the selection unit selects the M oscillation units so that the frequency difference of the oscillation signals output from the M oscillation units is equal to or greater than the first threshold value.</p><p> For example, when the difference in frequency of the oscillation signals output from the two selected oscillators is extremely small, the magnitude relationship of those frequencies is reversed due to the change in the physical characteristics of those oscillators over time. I may end up doing it. However, in the present invention, since M oscillators are selected so that the frequency difference is equal to or greater than the first threshold value, even if the physical characteristics of those oscillators change over time, they are output from the oscillators. It is possible to suppress a change in the magnitude relationship of the frequency of the oscillated signal. As a result, it is possible to suppress an error that occurs in the secret data output from the first anti-tamper circuit.</p><p> Further, the information security device further compares the secret data after error correction output from the error correction means with the secret data output from the first tamper-resistant circuit, thereby performing the first method. An error determining means for determining whether or not an error has occurred in the secret data output from the tamper resistant circuit, and when it is determined that an error has occurred by the error determining means, the first tamper resistant circuit is described. The first PUF circuit includes a reset request means for requesting the reset of a predetermined secret data, and further, when the reset request is received from the reset request means, the first PUF circuit is selected by the selection unit. May be characterized by including a resetting unit that resets the predetermined secret data by executing the above again.</p><p> As a result, when an error occurs in the secret data output by the first anti-tamper circuit, the predetermined secret data is reset to the first anti-tamper circuit, so that the accuracy of error correction can be improved. , The stability of confidential data can be further improved.</p><p> Further, the first PUF circuit further includes a secret data storage unit for storing at least a part of the predetermined secret data, and when the selection unit selects M oscillators. A storage processing unit that stores at least a part of the secret data in the secret data storage unit when it is not possible to select M oscillation units whose oscillation frequency difference is equal to or greater than the first threshold value. When at least a part of the secret data is stored in the secret data storage unit, the determination unit prohibits the determination of the output value, and the secret data storage unit stores the secret data. It may be characterized by including an output control unit that outputs at least a part of the data.</p><p> If the frequency difference of the oscillation signals output from the selected M oscillators is less than the first threshold value regardless of which of the N oscillators is selected, the first PUF The output value from the circuit is prone to error and its reliability is lowered. Therefore, in the present invention, in such a case, at least a part of the predetermined secret data to be output by the first PUF circuit is stored in the secret data storage unit, and at least a part of the secret data is stored. Is output, it is possible to prevent errors in the secret data output from the first anti-tamper circuit and improve reliability.</p><p> Further, the first anti-tamper circuit includes a plurality of the first PUF circuits and a coupling portion for generating secret data by combining output values output from the plurality of first PUF circuits. When the error determining means determines that an error has occurred in the secret data output from the first tamper resistant circuit, the error determining means further outputs an erroneous output value among the plurality of first PUF circuits. The output value is a part of the predetermined secret data for the first PUF circuit which identifies the PUF circuit of 1 and the reset request means is specified to output an erroneous output value. It may be characterized by requesting the resetting of the output value as shown in.</p><p> As a result, the first PUF circuit that outputs an erroneous output value is specified, and the output value of the specified first PUF circuit is reset. It can be properly reconfigured in the tamper circuit.</p><p> Further, the information security device further compares the secret data after error correction output from the error correction means with the secret data before error correction output from the first tamper-resistant circuit. The error determining means for determining whether or not an error has occurred in the secret data before the error correction, and when it is determined that an error has occurred by the error determining means, the first tamper resistant circuit is determined in advance. The first PUF circuit further includes a secret data storage unit for storing at least a part of the predetermined secret data, which comprises a reset request means for requesting the reset of the secret data. When a reset request is received from the reset request means, a storage processing unit that stores at least a part of the secret data in the secret data storage unit and at least the secret data storage unit in the secret data storage unit. When a part of the data is stored, the determination unit prohibits the determination of the output value, and includes an output control unit that outputs at least a part of the secret data stored in the secret data storage unit. It may be a feature.</p><p> If the first PUF circuit outputs an incorrect output value even once, the reliability of the first PUF circuit is doubtful. Therefore, in the present invention, in such a case, at least a part of the predetermined secret data, which is the output value to be output by the first PUF circuit, is stored in the secret data storage unit, and the secret is stored. Since at least a part of the data is output, it is possible to prevent an error in the secret data output from the first anti-tamper circuit and improve the reliability.</p><p> Further, the first PUF circuit further includes a difference determination unit that determines whether or not the frequency difference of the oscillation signals output from the M oscillation units is less than the second threshold value, and the difference determination unit. When it is determined by the unit that the value is less than the second threshold value, the unit includes a resetting unit that resets the predetermined secret data by re-executing the selection by the selection unit. May be good.</p><p> As a result, it is possible to prevent an error in the output value output from the first PUF circuit.</p><p> Further, the first PUF circuit further includes a threshold storage unit that stores at least one of the first and second threshold values, and the first and first threshold storage units that are stored in the threshold storage unit. It may be characterized by including an update unit that updates at least one of the two threshold values.</p><p> As a result, the predetermined secret data can be reset at an appropriate timing.</p><p> Further, in order to achieve the above object, the data generation device according to the present invention is a data generation device that generates the first correction data for correcting an error of the secret data, and is a predetermined secret data. The first measuring means for measuring the output value output from the first tamper-resistant circuit having the tamper resistance set by utilizing the physical characteristics so as to output, and the second correction data are output. It is measured by the second measuring means for measuring the output value output from the second tamper-resistant circuit having the tamper resistance set by utilizing the physical characteristics, and the first and second measuring means. It is provided with a data generation means for generating the first correction data based on the output value, and a storage processing means for storing the first correction data generated by the data generation means in a storage medium. It is characterized by. For example, the data generating means includes a first generating means that generates error correction information by calculating a difference between an output value measured by the first measuring means and a value indicated by the secret data. The second generation means for generating the first correction data by calculating the difference between the output value measured by the second measuring means and the value indicated by the error correction information is provided.</p><p> As a result, the first correction data necessary for generating the error correction information using the second correction data can be appropriately generated.</p><p> The present invention can be realized not only as such an information security device and a data generation device, but also a processing method performed by the device, a program for causing a computer to execute the processing method, and a storage for storing the program. It can also be realized as a medium or an integrated circuit.</p>
<p> The information security device of the present invention can prevent an attacker from knowing the secret data hidden by the PUF even if the information stored in the memory is used, so that the security of the PUF does not deteriorate. Its value is great. Further, according to the information security device of the present invention, the stability of the output bit value against aging is maintained while maintaining the feature that the manufacturing cost is low and the data can be stored securely as in the conventional PUF circuit. There is an effect that it becomes possible to provide an information security device that can be improved.</p>
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1) The information security system 1000 as the first embodiment of the present invention will be described.
FIG. 3 is a diagram showing a configuration of the information security system 1000 according to the first embodiment.
The information security system 1000 includes an information security device 1100 that enhances the stability and confidentiality of confidential data, and an error correction information generation device 1200 that generates error correction partial information and sets it in the information security device 1100. In the present embodiment, the error correction information generation device 1200 is configured as a data generation device.
<Configuration of information security device 1100> FIG. 4 is a diagram showing the configuration of the information security device 1100. The information security device 1100 is an input unit 1101 that accepts data (input data) input, an output unit 1102 that outputs data, a hash generation unit 1103 that calculates a keyed hash value, and a key of a keyed hash function. Information generation PUF unit 1104 that generates a hash key, error correction unit 1105 that corrects an error in the hash key and generates a hash key after correction, error correction PUF unit 1106 that generates error correction PUF information, and errors. It includes an error correction part information storage unit 1107 for storing the correction part information and an error correction information generation unit 1108 for generating the error correction information.
In the present embodiment, the information generation PUF unit 1104 is configured as a first tamper-resistant circuit set to output a preset secret data hash key, and the error correction partial information storage unit 1107. Is configured as a correction data storage means for storing error correction partial information, which is the first correction data. Further, the error correction PUF unit 1106 is configured as a second anti-tamper circuit set to output error correction PUF information which is the second correction data, and the error correction information generation unit 1108 is used for error correction. It is configured as a correction information generation means for generating information. Further, the input unit 1101 is configured as an acquisition means for acquiring the input data, and the hash generation unit 1103 is configured as an encryption means for encrypting the input data.
The input unit 1101 receives the input data input from the outside and inputs it to the hash generation unit 1103. When the input unit 1101 further receives the input data, the input unit 1101 inputs a trigger to the PUF circuit to the information generation PUF unit 1104 and the error correction PUF unit 1106.
The output unit 1102 outputs a hash value with a key.
The hash generation unit 1103 calculates a keyed hash value using the corrected hash key output by the error correction unit 1105 and the input data received by the input unit 1101, and inputs it to the output unit 1102.
The information generation PUF unit 1104 generates a hash key of a hash function with a key.
FIG. 5 is a diagram showing the configuration of the information generation PUF unit 1104.
As shown in FIG. 5, the information generation PUF section 1104 connects the nine first PUF circuits 11041A, 11041B, 11041C, 11041D, 11041E, 11041F, 11041G, 11041H, 11041I with the bits of the first PUF circuit. It is composed of a hash key generation unit 11042 that generates a hash key. The first PUF circuit, which will be described later, outputs 1-bit information, and the information generation PUF unit 1104 concatenates 1-bit information of each of the 9 first PUF circuits and inputs the information to the error correction unit 1105. Although the number of the first PUF circuits is set to 9 here, the number is not limited to 9, and any number of 2 or more can be used.
(About the configuration of the first PUF circuit 11041A, ..., 11041G, 11041H, 11041I) Since the first PUF circuit 11041A, ..., 11041I each have the same configuration, the configuration of the first PUF circuit 11041A will be described below as a representative.
FIG. 6 is a diagram showing the configuration of the first PUF circuit 11041A.
As shown in FIG. 6, the first PUF circuit 11041A includes the first ring oscillator 11041A01, the second ring oscillator 11041A02, ..., The eighth ring oscillator 11041A08, the first ring oscillator selection unit 11041A11, and the second ring oscillator 11041A11. It is composed of a ring oscillator selection unit 11041A12, a first frequency counting unit 11041A21, a second frequency counting unit 11041A22, and an output bit determination unit 11041A30. In this embodiment, the first ring oscillator 11041A01 to the eighth ring oscillator 11041A08 are respectively configured as oscillators that output oscillation signals, and the first ring oscillator selection unit 11041A11 and the second ring oscillator selection unit 11041A12 are Each is configured as a selection unit for selecting an oscillation unit, and an output bit determination unit 11041A30 is configured as a determination unit for determining and outputting the output value of the first PUF circuit 11041A.
The first ring oscillator 11041A01 to the eighth ring oscillator 11041A08 have the same configuration, and each outputs an output signal (oscillation signal) to the trigger signal.
The first ring oscillator selection unit 11041A11 selects a ring oscillator given in advance from the first ring oscillators 11041A01 to 11041A08.
The second ring oscillator selection unit 11041A12 selects a ring oscillator given in advance from the first ring oscillators 11041A01 to 11041A08, unlike the first ring oscillator selection unit 11041A11. The number of ring oscillators was set to 8, but it is not limited to this. The number of ring oscillators may be 2 or more.
The first frequency counting unit 11041A21 measures the frequency of the ring oscillator selected by the first ring oscillator selection unit 11041A11.
The second frequency counting unit 11041A22 measures the frequency of the ring oscillator selected by the second ring oscillator selection unit 11041A12.
The output bit determination unit 11041A30 compares the frequency F1 measured by the first frequency counting unit 11041A21 with the frequency F2 measured by the second frequency counting unit 11041A22, and if F1 F2, it is 0, and if F1 <F2, it is 0. Output "1". In addition, although the frequency is measured here, it is assumed that the frequency is measured not by the frequency itself but by a frequency close to the frequency, for example, the number of times that the output signal of the ring oscillator within a predetermined time becomes equal to the amplitude given in advance. May be good. In this case, the output bits of "0" and "1" may be determined by comparing this number of times instead of the frequency. In the above, "0" is output when F1 F2 and "1" is output when F1 <F2, but "1" may be output when F1 <F2 and "0" may be output when F1 F2. ..
(About the operation of the first PUF circuit 11041A, ..., 11041I) Hereinafter, the operation of the first PUF circuit 11041A will be described as a representative as in the case where the configuration is described.
The first ring oscillator selection unit 11041A11 selects a ring oscillator given in advance. The second ring oscillator selection unit 11041A12 also selects a ring oscillator given in advance. The first frequency counting unit 11041A21 measures the frequency of the ring oscillator selected by the first ring oscillator selection unit 11041A11. The second frequency counting unit 11041A22 measures the frequency of the ring oscillator selected by the second ring oscillator selection unit 11041A12. The output bit determination unit 11041A30 determines the output bit using the frequencies measured by the first frequency counting unit 11041A21 and the second frequency counting unit 11041A22.
(About hash key generator 11042) The hash key generation unit 11042 concatenates the bits of the first PUF circuits 11041A to 11041G, and uses the concatenated bits as a hash key.
The error correction unit 1105 uses the error correction information generated by the error correction information generation unit 1108 to erroneously correct the hash key generated by the information generation PUF unit 1104, and generates the corrected hash key. Any error correction method may be used, but for the sake of simplicity, an example is shown.
(Example of error correction method) In this example, three 3-bit repeat codes are concatenated. The repeat code is a code that encodes 0 as 000 and 1 as 111, and takes a 3-bit majority vote at the time of decoding. For example, if it is "101", the number of 1s is 2, and if a majority vote is taken, it is decoded as "1". That is, if the Hamming weight (number of 1s) of the code is 1 or less, it is decoded as "0", and if it is 2 or more, it is decoded as "1".
The error correction information is set to "010 010 001". The hash key generated by the information generation PUF unit 1104 is set to "101 000 111". The error correction unit 1105 takes the exclusive OR (XOR) of the error correction information and the hash key.
010 010 001 XOR 101 000 111 = 111 010 110 On the other hand, when decrypted, the first repetition code is "111", so "1", the second is "010", so "0", and the third is "110", so "1" Decrypt with ".
Therefore, in this example, the corrected hash key is "101".
The error correction PUF unit 1106 generates error correction PUF information.
FIG. 7 is a diagram showing the configuration of the error correction PUF unit 1106.
As shown in FIG. 7, the error correction PUF section 1106 connects the nine second PUF circuits 11061A, 11061B, 11061C, 11061D, 11061E, 11061F, 11061G, 11061H, 11061I and the bits of the second PUF circuit. It is composed of an error correction PUF information generation unit 11062 that generates error correction PUF information. The second PUF circuit, which will be described later, outputs 3-bit information, and the error correction PUF unit 1106 concatenates the 3-bit information of each of the nine second PUF circuits and inputs it to the error correction information generation unit 1108. .. Although the number of the second PUF circuits is set to 9 here, the number is not limited to 9, and any number may be used as long as it is 2 or more.
(About the configuration of the second PUF circuit 11061A, ..., 11061I) Since the second PUF circuit 11061A, ..., 11061I each have the same configuration, the configuration of the second PUF circuit 11061A is shown below as a representative.
FIG. 8 is a diagram showing the configuration of the second PUF circuit 11061A.
As shown in FIG. 8, the second PUF circuit 11061A includes the first ring oscillator 11061A01, the second ring oscillator 11061A02, ..., The eighth ring oscillator 11061A08, the first ring oscillator selection unit 11061A11, and the second ring oscillator 11061A11. It is composed of a ring oscillator selection unit 11061A12, a first frequency counting unit 11061A21, a second frequency counting unit 11061A22, and an output bit determination unit 11061A30.
The first ring oscillator 11061A01 to the eighth ring oscillator 11061A08 have the same configuration, and each outputs an output signal to the trigger signal.
The first ring oscillator selection unit 11061A11 selects a ring oscillator given in advance from the first ring oscillators 11061A01 to 11061A08.
The second ring oscillator selection unit 11061A12 selects a ring oscillator given in advance from the first ring oscillators 11061A01 to 11061A08, unlike the first ring oscillator selection unit 11061A11. The number of ring oscillators was set to 8, but it is not limited to this. The number of ring oscillators may be 2 or more.
The first frequency counting unit 11061A21 measures the frequency of the ring oscillator selected by the first ring oscillator selection unit 11061A11.
The second frequency counting unit 11061A22 measures the frequency of the ring oscillator selected by the second ring oscillator selection unit 11061A12.
The output bit determination unit 11061A30 compares the frequency F1 measured by the first frequency counting unit 11061A21 with the frequency F2 measured by the second frequency counting unit 11061A22, and from "0" to "7" depending on the difference between F1 and F2. Outputs 3 bits indicating the value of as one element.
FIG. 9 is a diagram showing the mapping of the value (3 bits) to the frequency difference (F2-F1). In FIG. 9, the difference from -300 to 300 is divided into eight equal parts, and each is mapped from 0 to 7. The mapping method is not limited to this. The range may be other than this, for example, from -500 to 500, or may be mapped unequally by value instead of evenly divided.
(About the operation of the second PUF circuit 11061A, ..., 11061I) Hereinafter, the operation of the second PUF circuit 11061A will be described as a representative as in the case where the configuration is described.
The first ring oscillator selection unit 11061A11 selects a ring oscillator given in advance. The second ring oscillator selection unit 11061A12 also selects a ring oscillator given in advance. The first frequency counting unit 11061A21 measures the frequency of the ring oscillator selected by the first ring oscillator selection unit 11061A11. The second frequency counting unit 11061A22 measures the frequency of the ring oscillator selected by the second ring oscillator selection unit 11061A12. The output bit determination unit 11061A30 determines 3 bits to be output using the frequencies measured by the first frequency counting unit 11061A21 and the second frequency counting unit 11061A22. That is, the output bit determination unit 11061A30 determines a 3-bit value according to the difference between the frequency measured by the first frequency counting unit 11061A21 and the second frequency counting unit 11061A22 by using the mapping shown in FIG. For example, the output bit determination unit 11061A30 determines 4 if the difference is 0 or more and less than 75, and determines 5 if the difference is 75 or more and less than 150.
(About PUF information generator 11062 for error correction) The error correction PUF information generation unit 11062 concatenates the elements output from the second PUF circuits 11061A to 11061I, and sets the concatenated element as the error correction PUF information. For example, each element output from the second PUF circuit 11061A to 11061I is "2", "6", "5", "1", "5", "7", "2", "3", If it is "7", the PUF information for error correction is "265 157 237".
The error correction partial information storage unit 1107 stores the error correction partial information which is the partial information of the error correction information. The error correction partial information is generated and stored by the error correction information generator 1200.
The error correction information generation unit 1108 generates error correction information by using the error correction PUF information generated by the error correction PUF unit 1106 and the error correction part information stored in the error correction part information storage unit 1107. To do. An example of how to generate error correction information is shown below. In this example, the error correction PUF information is encoded by a given method in advance, and the exclusive OR of the error correction PUF information and the error correction partial information generated as a result is taken. The method of generating correction information is not limited to this example. The part of the exclusive OR may be changed to multiplication in the Galois field. Further, instead of the exclusive OR, the PUF information for error correction after coding and the error correction partial information may be regarded as integer values and added.
(Example of error correction information generation) It is assumed that the error correction PUF information output by the error correction PUF unit 1106 is 265 157 237 as described above. On the other hand, if the value of this element is 3 or less, it is encoded as "0", and if it is 4 or more, it is encoded as "1", which is a 1-bit value. As a result of encoding, it becomes "011 011 001", which is used as PUF information for error correction after coding. The difference between this and the error correction partial information stored in the error correction partial information storage unit 1107 is taken. When the error correction partial information is "001 001 000", the error correction information is 011 011 001 XOR 001 001 000 = 010 010 001 Is.
The coding is not limited to this, and for example, 4 or more may be encoded as 0 and 3 or less may be encoded as 1.
<Configuration of error correction information generator 1200> FIG. 10 is a diagram showing a configuration of the error correction information generation device 1200. The error correction information generator 1200 includes a PUF circuit measuring unit 1201 that measures the output values of the first PUF circuit and the second PUF circuit in the information security device 1100, and the first PUF circuit and the second PUF circuit. Error correction part information based on the analysis results of the environmental change unit 1202 that changes the surrounding environment, the environmental change analysis unit 1203 that analyzes the distribution of the output value measured by the PUF circuit measurement unit 1201 due to the environmental change, and the environmental change analysis unit 1203. The error correction partial information generation unit 1204 for generating the error correction partial information and the error correction partial information setting unit 1205 for storing the error correction partial information in the error correction partial information storage unit 1107 in the information security device 1100 are provided. In the present embodiment, the PUF circuit measurement unit 1201 is configured as the first measurement means and the second measurement means, the error correction part information generation unit 1204 is configured as the data generation means, and the error correction part information setting unit. 1205 is configured as a storage processing means. Further, the error correction partial information generation unit 1204 in the present embodiment generates the error correction partial information which is the first correction data by using the first generation means for generating the error correction information and the error correction information. It has a second generation means.
The PUF circuit measurement unit 1201 measures the output values of the first PUF circuits 11041A to 11041I and the second PUF circuits 11061A to 11061I.
The environment change unit 1202 changes the environment around the first PUF circuit and the second PUF circuit. Specifically, for example, the ambient temperature is changed.
The environmental change analysis unit 1203 analyzes the distribution of the output values measured by the PUF circuit measurement unit 1201 due to environmental changes. That is, the distribution of the output values of the first PUF circuit and the second PUF circuit for each temperature is obtained.
The error correction partial information generation unit 1204 generates error correction partial information.
(Processing of error correction partial information generation unit 1204) The error correction partial information generation unit 1204 first obtains error correction information based on the distribution of the output values of the first PUF circuit analyzed by the environment change analysis unit 1203.
FIG. 11 is a diagram showing an example of distribution of output values of the first PUF circuit and the second PUF circuit. As a specific example, the output value that appears with the highest probability in the distribution of the output value of the first PUF circuit is coded using an error correction code and the difference between the output value is error-corrected. Use as information. Combined with the above error correction method example and error correction information generation example, the output value that appears with the highest probability is "101 000 110" when the output values of the nine first PUF circuits 11041A to 11041I are arranged. .. Here, as an example, since a 3-bit repeat code is used, the output value that appears with the highest probability is also determined by dividing it into 3 bits. In Fig. 11, the first 3 bits are 100 at 0 ° C, 101 at 10 ° C, and 101 at 20 ° C, so the output value that appears with the highest probability is It is "101". Similarly, the second is "000" and the third is "110". If this output value is encoded using three 3-bit repeat codes arranged side by side, it will be "111 000 111". Therefore, the difference between the output value and the coded one is 101 000 110 XOR 111 000 111 = 010 000 001 This is used as error correction information.
Next, the error correction partial information generation unit 1204 obtains the error correction PUF information based on the distribution of the output values of the second PUF circuit analyzed by the environment change analysis unit 1203. FIG. 11 shows an example of the distribution of output values. The output value of one second PUF circuit is a 3-bit element, but in FIG. 11, the output values of the second PUF circuits 11061A to 11061I are arranged in order from the left. As a specific example of the method of generating the error correction partial information, the output value that appears with the highest probability in each element in the distribution of the output value of the second PUF circuit is encoded by a predetermined method. The difference between the post-error correction PUF information and the error correction information is used as the error correction partial information. In the example of FIG. 11, the first element is 3 at 0 ° C, 2 at 10 ° C, and 2 at 20 ° C, so the output value that appears with the highest probability. Is "2". On the other hand, if the same coding method as in the error correction information generation example is used, the value of this element is encoded as 0 when it is 4 or less, and as 1 when it is 5 or more, which is a 1-bit value. In the example of FIG. 11, since the first element is 2, the coded value is 0. Similarly, if the second and subsequent codes are also coded, the PUF information for error correction after coding will be "011". 011 001 . When the difference between the PUF information for error correction after coding and the error correction information is taken, 010 000 001 XOR 011 011 001 = 001 011 000 Therefore, "001 011 000" is used as the error correction partial information.
The error correction partial information setting unit 1205 stores the error correction partial information generated by the error correction partial information generation unit 1204 in the error correction partial information storage unit 1107 in the information security device 1100.
<Operation of Information Security System 1000> FIG. 12A is a flowchart showing an operation when the error correction information generator 1200 of the information security system 1000 sets the error correction partial information.
The error correction information generator 1200 operates as follows when setting the error correction partial information. The process of generating the error correction partial information and setting it in the error correction partial information storage unit 1107 in the information security device 1100 is performed at the time of manufacturing the information security device 1100.
Step S101: Environment change unit 1202 changes the environment around the first PUF circuit and the second PUF circuit. Further, the environment change unit 1202 inputs the changed environment information to the environment change analysis unit 1203.
Step S102: The PUF circuit measurement unit 1201 measures the output values of the first PUF circuit and the second PUF circuit, and inputs them to the environment change analysis unit 1203.
Step S103: Environmental change analysis unit 1203 obtains the distribution from the environmental information and the output values of the first PUF circuit and the second PUF circuit.
Step S104: The error correction partial information generation unit 1204 generates error correction partial information from the distribution of output values.
Step S105: The error correction partial information setting unit 1205 stores the error correction partial information in the error correction partial information storage unit 1107 in the information security device 1100.
FIG. 12B is a flowchart showing the operation when the information security device 1100 of the information security system 1000 calculates the keyed hash value.
The information security device 1100 operates as follows when calculating the hash value with a key. The process of generating and outputting the keyed hash value for the input data by the information security device 1100 is performed by the input from the user or the trigger from the application program.
Step S201: The input unit 1101 receives the input data input from the outside and inputs it to the hash generation unit 1103. Further, the input unit 1101 inputs a trigger signal to the PUF circuit to the information generation PUF unit 1104 and the error correction PUF unit 1106.
Step S202: The information generation PUF unit 1104 generates a hash key and inputs it to the error correction unit 1105.
Step S203: The error correction PUF unit 1106 generates error correction PUF information and inputs it to the error correction information generation unit 1108.
Step S204: The error correction information generation unit 1108 generates error correction information using the error correction PUF information and the error correction part information stored in the error correction part information storage unit 1107, and causes the error correction part 1105 to generate the error correction information. input.
Step S205: The error correction unit 1105 erroneously corrects the hash key using the error correction information, generates the corrected hash key, and inputs it to the hash generation unit 1103.
Step S206: The hash generation unit 1103 uses the corrected hash key as a key to generate a keyed hash value of the input data and inputs it to the output unit 1102.
Step S207: The output unit 1102 outputs the keyed hash value to the outside.
As described above, in the present embodiment, the information security device 1100 does not directly store the error correction information in the memory, but stores the error correction partial information. Therefore, since the attacker cannot directly access the error correction information, it is difficult for the attacker to obtain the PUF secret, that is, the hash key, and it is safe. Further, by providing the error correction PUF unit 1106 and the error correction information generation unit 1108, the error correction information can be restored from the error correction partial information, and the error correction works correctly.
(Embodiment 2) The hash key error of the information generation PUF unit 1104 in the first embodiment may be caused by a change in the environment, but may also be caused by a secular change in the frequency characteristics of the PUF circuit. In the present embodiment, the hash key output from the information generation PUF unit 1104 is erroneous with respect to the configuration of the information security system 1000 in the first embodiment by further suppressing the output fluctuation of the PUF circuit over time. It is characterized by reducing.
Hereinafter, Embodiment 2 of the present invention will be described with reference to the drawings.
(Configuration of PUF circuit 1) FIG. 13 is a block diagram showing an example of the configuration of the PUF circuit 1 according to the second embodiment of the present invention. The PUF circuit 1 corresponds to each of the first PUF circuits 11041A to 11041I in the first embodiment, and includes the first to eighth ring oscillators 101 to 108, the first to second ring oscillator selection units 111 to 112, and the first to second ring oscillator selection units 111 to 112. 1st to 2nd frequency counting units 121 to 122, output bit determination unit 13, input value storage unit 14, input value setting unit 15, input value resetting determination unit 16, threshold storage unit 17, and output. It consists of a bit control unit 18 and an output bit storage unit 19.
In the present embodiment, the output bit storage unit 19 is configured as a secret data storage unit for storing a part of the hash key which is the secret data, and the output bit control unit 18 stores a part of the hash key. It is configured as a storage processing unit that stores in the output bit storage unit 19, and is also configured as an output control unit that outputs a part of the hash key stored in the output bit storage unit 19. The details of each part will be described below.
(1) 1st to 8th ring oscillators 101 to 108 The 1st to 8th ring oscillators 101 to 108 are oscillation circuits based on a configuration in which an odd number of negative circuits are connected in a ring shape, respectively, and an oscillation signal (output signal) having a predetermined oscillation frequency is obtained by inputting a trigger signal. ) Is output. Since the configurations and operations of these eight ring oscillators are all the same, the configuration and operation thereof will be described below with them as the ring oscillator 100.
FIG. 14 is a block diagram showing an example of the configuration of the ring oscillator 100. The ring oscillator 100 is a seven-stage ring oscillator, and includes a NAND circuit 21 and seven negative circuits 22 to 28. In the present embodiment, the ring oscillator has 7 stages, but the ring oscillator may have any number of stages as long as it has an odd number of stages.
When the trigger signal is not input to the ring oscillator 100, that is, when "0" is input as the trigger signal, the output of the NAND circuit 21 becomes "1". Therefore, the output of the negative circuit 22 is "0", the output of the negative circuit 23 is "1", ..., The output of the negative circuit 27 (that is, one input of the NAND circuit 21) is "1". , The output of the NAND circuit 21 remains "1" because the other input of the NAND circuit 21 is "0". That is, the ring oscillator 100 is stable in the above steady state. At this time, the output of the negative circuit 28, that is, the output signal of the ring oscillator 100 is stable at "0". In summary, when the trigger signal to the ring oscillator 100 is "0", the ring oscillator 100 does not oscillate, and its output signal is stable at "0".
On the other hand, when the trigger signal is input to the ring oscillator 100, that is, when "1" is input as the trigger signal, the output of the NAND circuit 21 becomes "1". Therefore, the output of the negative circuit 22 is "0", the output of the negative circuit 23 is "1", ..., The output of the negative circuit 27 is "1". At this time, since both of the two inputs of the NAND circuit 21 are "1", the output of the NAND circuit 21 transitions from "1" to "0". With this transition, the output of the negative circuit 22 becomes "1", the output of the negative circuit 23 becomes "0", ..., The output of the negative circuit 27 becomes "0". At this time, since one input of the NAND circuit 21 becomes 0, the output of the NAND circuit 21 transitions from 0 to 1 again. As described above, when the trigger signal "1" is input, the internal state of the ring oscillator 100 is not stable, and the output of the NAND circuit 21 oscillates by repeating the transition between "1" and "0". .. At this time, the ring oscillator 100 outputs an oscillation signal having a predetermined oscillation frequency. The oscillation frequency is determined by the number of stages of the ring oscillator, and theoretically, if the ring oscillator has the same number of stages and circuit configuration, it will be the same. However, in reality, even if the ring oscillator has the same configuration, the frequency characteristics of the circuit elements constituting the ring oscillator vary, so that the oscillation frequency also varies slightly. In the above oscillation state, when the trigger signal changes to "0", the output of the NAND circuit 21 stabilizes at "1", so that the oscillation operation stops and the output signal becomes "0".
(2) 1st and 2nd ring oscillator selection units 111 to 112 The 1st to 2nd ring oscillator selection units 111 to 112 respectively select one of the 1st to 8th ring oscillators 101 to 108 based on the 3-bit input value data input from the input value storage unit 14. The oscillation signal output from the selected ring oscillator is acquired and input to the first frequency counting unit 121 or the second frequency counting unit 122. That is, the first ring oscillator selection unit 111 acquires the oscillation signal output from the selected ring oscillator and inputs it to the first frequency counting unit 121, and the second ring oscillator selection unit 112 outputs it from the selected ring oscillator. The oscillation signal to be generated is acquired and input to the second frequency counting unit 122.
The correspondence between the 3-bit input value data and the selected ring oscillator may be any as long as the arbitrary input value data corresponds to a certain ring oscillator. In the form of, it is as follows. The first to second ring oscillator selection units 111 to 112 each select the first ring oscillator 101 for the input value data "000" (binary number). For the input value data "001" (binary number), select the second ring oscillator 102. For the input value data "010" (binary number), select the third ring oscillator 103. ... For the input data "111" (binary), select the 8th ring oscillator 108. The first ring oscillator selection unit 111 and the second ring oscillator selection unit 112 each acquire different input value data and select different ring oscillators.
(3) 1st to 2nd frequency counting units 121 to 122 The 1st to 2nd frequency counting units 121 to 122 measure the oscillation frequency of the oscillation signal input from the 1st ring oscillator selection unit 111 or the 2nd ring oscillator selection unit 112, respectively, and determine the measurement result as an output bit. Enter in Part 13. That is, the first frequency counting unit 121 measures the oscillation frequency of the oscillation signal input from the first ring oscillator selection unit 111, and the second frequency counting unit 122 measures the oscillation input from the second ring oscillator selection unit 112. Measure the oscillation frequency of the signal.
(4) Output bit determination unit 13 The output bit determination unit 13 compares the magnitude relations of the oscillation frequencies input from the first frequency counting unit 121 and the second frequency counting unit 122, respectively, and determines the value of the 1-bit output bit based on the comparison result. Then, the output bit indicating the determined value is input to the output bit control unit 18.
What is the correspondence between the comparison result and the value of the output bit? In this embodiment, (measured frequency of the first frequency counting unit 121) <(measured frequency of the second frequency counting unit 122). If so, it shall be determined as "1", otherwise it shall be determined as "0".
(5) Output bit control unit 18 When a trigger signal is input to the PUF circuit 1 from the outside and an output bit output request is made, the output bit control unit 18 first determines whether or not the output bit is stored in the output bit storage unit 19. To confirm. If the output bit is stored, the stored output bit is output from the PUF circuit 1 to end the process. If the output bit is not stored in the output bit storage unit 19, the following processing is performed after the output bit is input from the output bit determination unit 13.
The output bit control unit 18 first temporarily stores the output bit input from the output bit determination unit 13, and temporarily stores the output bit input value setting unit 15 when a save request signal for the output bit is input. The existing output bit is output as the output bit of the PUF circuit 1 and is output to the output bit storage unit 19. On the other hand, when the save request signal of the output bit is not input from the input value setting unit 15, the temporarily stored output bit is output as the output bit of the PUF circuit 1.
(6) Input value storage unit 14 The input value storage unit 14 stores two 3-bit input value data to be input to the first ring oscillator selection unit 111 and the second ring oscillator selection unit 112. Hereinafter, the 3-bit input value data input to the first ring oscillator selection unit 111 will be referred to as the first input value data, and the 3-bit input value data input to the second ring oscillator selection unit 112 will be referred to as the second input value data. To do.
(7) Input value setting unit 15 The input value setting unit 15 operates at the time of initialization or when an input value reset request signal is input from the input value reset determination unit 16, and is equal to or higher than the input setting threshold stored in the threshold storage unit 17. Input value data (3 bits each) to the first ring oscillator selection unit 111 and the second ring oscillator selection unit 112 is set so that two ring oscillators having a frequency difference are selected.
Specifically, the input value setting unit 15 acquires the output setting value from the outside of the PUF circuit 1 at the time of initialization, and the first ring is such that the output bit indicating the output setting value is output from the PUF circuit 1. Input value data to the oscillator selection unit 111 and the second ring oscillator selection unit 112 are set. At this time, if the output set value is "1", the input value setting unit 15 is (measured frequency of the first frequency counting unit 121) <(measured frequency of the second frequency counting unit 122), and they are Set the two input value data so that the two ring oscillators are selected so that the absolute value of the frequency difference between them is equal to or greater than the input setting threshold. If the output set value is "0", the input value setting unit 15 has (measured frequency of the first frequency counting unit 121) (measured frequency of the second frequency counting unit 122), and the input value setting unit 15 has a value of "0". Set the two input value data so that the two ring oscillators are selected so that the absolute value of the frequency difference is equal to or greater than the input setting threshold.
Further, when the input value setting unit 15 acquires the input value reset request signal, the magnitude relationship between the measured frequency of the first frequency counting unit 121 and the measured frequency of the second frequency counting unit 122, which has already been set. And reset the two input value data so that the two ring oscillators whose absolute value of the difference between the frequencies is equal to or more than the input setting threshold are selected again.
Further, when the determination of the input value data such as selecting two ring oscillators having a frequency difference equal to or more than the input setting threshold fails (that is, a pair of ring oscillators having a frequency difference equal to or greater than the threshold cannot be found). In the case of), the input value setting unit 15 inputs the save request signal of the output bit to the output bit control unit 18.
In the present embodiment, the first ring oscillator selection unit 111, the second ring oscillator selection unit 112, the input value storage unit 14, and the input value setting unit 15 select two ring oscillators from the eight ring oscillators. It is configured as a selection unit. Further, the input value setting unit 15 is configured as a search unit for searching for two ring oscillators whose frequency difference is equal to or higher than the input setting threshold value which is the first threshold value, and the input value storage unit 14 is searched by the search unit. It is configured as a parameter holding unit that holds input value data, which is a selection parameter indicating two ring oscillators. Further, the first ring oscillator selection unit 111 and the second ring oscillator selection unit 112 are respectively configured as selection determination units for determining and selecting the ring oscillator indicated by the input value data as the ring oscillator to be selected.
(8) Input value reset judgment unit 16 The input value reset determination unit 16 observes the oscillation frequency output from the first frequency counting unit 121 and the second frequency counting unit 122, and the absolute value of the frequency difference is the input stored in the threshold value storage unit 17. When the value becomes smaller than the value reset determination threshold value, the input value reset request signal is input to the input value setting unit 15.
In the present embodiment, the input value resetting determination unit 16 determines whether or not the frequency difference is less than the input value resetting determination threshold value, which is the second threshold value, and the above-mentioned selection unit. It is configured as a resetting unit that re-executes the selection by.
(9) Threshold storage unit 17 The threshold value storage unit 17 stores the input setting threshold value and the input value reset determination determination threshold value. These values are positive values. In the present embodiment, these values are written at the time of manufacturing the PUF circuit 1, but they may be written from the outside after the circuit is manufactured, or they can be rewritten from the outside even after the writing. Is also good. In addition, after performing some kind of authentication, writing from the outside may be permitted. In the present embodiment, the threshold value storage unit 17 is configured as a threshold value storage unit that stores an input setting threshold value that is the first threshold value and an input value reset determination threshold value that is the second threshold value. There is.
The operation of the PUF circuit 1 will be described below. The operation of the PUF circuit 1 is roughly classified into three types, "input value data setting", "output bit calculation", and "input value data resetting", and each of them will be described below.
(Setting of input value data) FIG. 15 is a flowchart showing the operation when the PUF circuit 1 sets the input value data.
The input value data setting is a process executed as an initialization process after the PUF circuit 1 is manufactured. The "input value data setting" process is performed as follows.
Step S301: The input value setting unit 15 accepts a 1-bit value input from the outside of the PUF circuit 1 as an output set value. In addition, the input setting threshold value stored in the threshold value storage unit 17 is read.
Step S302: The input value setting unit 15 selects a candidate for the input value data, and causes the first frequency counting unit 121 and the second frequency counting unit 122 to measure the oscillation frequency in the candidate. That is, the input value setting unit 15 selects any one of N1 = 000 (binary number) to 111 (binary number) as a candidate for the first input value data, and N2 as a candidate for the second input value data. Select one of = 000 (binary) to 111 (binary). Then, the input value setting unit 15 uses the ring oscillator selected by the combination of (candidate for first input value data, candidate for second input value data) = (N1, N2), and the first frequency counting unit 121 and The oscillation frequency is measured by the second frequency counting unit 122. Specifically, the PUF circuit 1 executes the following operations.
Step S302a: The input value setting unit 15 generates (N1, N2) as candidates for the first input value data and the second input value data, sets N1 in the first ring oscillator selection unit 111, and sets N1 in the second ring oscillator selection unit. Enter N2 in 112 respectively.
Step S302b: The first ring oscillator selection unit 111 selects one ring oscillator from the first ring oscillator 101 to the eighth ring oscillator 108 according to the rule described above based on the above N1. The second ring oscillator selection unit 112 selects one ring oscillator from the first ring oscillator 101 to the eighth ring oscillator 108 according to the above-mentioned rule based on the N2.
Step S302c: Here, when a trigger signal is input to the two ring oscillators selected in step S302b, the two selected ring oscillators oscillate and output an oscillation signal. At this time, the ring oscillator selected by the first ring oscillator selection unit 111 inputs an oscillation signal to the first frequency counting unit 121 via the first ring oscillator selection unit 111. The ring oscillator selected by the second ring oscillator selection unit 112 inputs an oscillation signal to the second frequency counting unit 122 via the second ring oscillator selection unit 112.
Step S302d: The first frequency counting unit 121 and the second frequency counting unit 122 measure the oscillation frequency from the input oscillation signals, respectively. Here, the first frequency counting unit 121 measures the oscillation frequency F1, and the second frequency counting unit 122 measures the oscillation frequency F2. Then, the measured F1 and F2 are input to the input value setting unit 15.
Step S303: The input value setting unit 15 selects whether or not the input value data candidates selected based on the oscillation frequencies F1 and F2 measured as described above are suitable as the input value data to be set. Determine if the candidate was a failure. Specifically, the input value setting unit 15 calculates the frequency difference D = F2-F1 from the input F1 and F2, and there is no contradiction between the difference D and the output setting value received in step S301. If the absolute value of the difference D is equal to or greater than the input setting threshold value, it is determined that the selected candidate is not a failure. In this case, as described in step S304 described later, the input value setting unit 15 stores the input values for (N1, N2) at that time by using N1 as the first input value data and N2 as the second input value data. Input to Part 14 and erase the output setting value. Here, "there is no contradiction between the difference D and the output setting value" means that when the output setting value is 0, the difference D is a negative value or 0, and the output setting value is 1. In the case of, it means that the difference D is a positive value. If the above conditions are not satisfied, the input value setting unit 15 determines that the selected candidate has failed. In this case, as described in step S305 described later, another candidate (N1, N2) is generated, and steps S302a to S302d are repeatedly executed. If (N1, N2) satisfying the above conditions is not found for all combinations of (N1, N2), the input value setting unit 15 sets the input value setting unit 15 as described in step S306 described later. After inputting the output set value and the input value setting failure signal corresponding to the above-mentioned save request signal to the output bit control unit 18, the output set value is erased.
Step S304: The input value storage unit 14 selects N1 and N2 input from the input value setting unit 15, that is, the first input value data candidate N1 and the second input value data candidate N2 determined not to have failed. It is saved as the first input value data and the second input value data to be set respectively, and the "input value data setting" process is completed.
Step S305: When the input value setting unit 15 determines that the selected first input value data candidate N1 and the second input value data candidate N2 have failed in step S303, the input value setting unit 15 other than the candidates N1 and N2. Determine if there are candidates. Here, when the input value setting unit 15 determines that there is another candidate, the process from step S302 is repeated, and when it is determined that there is no other candidate, the process of step S306 is executed.
Step S306: When the input value setting unit 15 determines that there is no other candidate as described above, the input value setting unit 15 outputs the output setting value and the input value setting failure signal to the output bit control unit 18. The output bit control unit 18 receives the input value setting failure signal and the output setting value, and inputs the output setting value (output bit indicating the output setting value) to the output bit storage unit 19. The output bit storage unit 19 stores the output set value and ends the "input value data setting" process.
(Calculation of output bit) FIG. 16 is a flowchart showing the operation when the PUF circuit 1 calculates the output bit.
The "calculation of output bit" process is executed when a trigger signal is input from outside the PUF circuit 1. By this process, the PUF circuit 1 outputs a 1-bit output bit that is securely held inside to the outside of the PUF circuit 1. Specifically, when a trigger signal is input to the PUF circuit 1, the following series of operations are performed.
Step S401: The output bit control unit 18 checks whether the output setting value (output bit indicating the output setting value) is stored in the output bit storage unit 19, and if it is stored, the output setting. The value (1 bit) is output as an output bit from the PUF circuit 1, and the "calculation of output bit" process is completed. If the output setting value is not saved, the process proceeds to step S402.
Step S402: The input value storage unit 14 inputs the first input value data to be stored internally to the first ring oscillator selection unit 111 and the second input value data to the second ring oscillator selection unit 112.
Step S403: The first ring oscillator selection unit 111 selects one from the first ring oscillator 101 to the eighth ring oscillator 108 based on the first input value data. Further, the second ring oscillator selection unit 112 selects one from the first ring oscillator 101 to the eighth ring oscillator 108 based on the second input value data.
Step S404: A trigger signal is input to each of the two ring oscillators selected in step S403, an oscillation operation is performed, and an oscillation signal is output. At this time, the output oscillation signal is input to the first frequency counting unit 121 and the second frequency counting unit 122 via the first ring oscillator selection unit 111 and the second ring oscillator selection unit 112, respectively.
Step S405: The first frequency counting unit 121 and the second frequency counting unit 122 measure the oscillation frequencies F1 and F2 of the input oscillation signals, respectively, and input them to the output bit determination unit 13 and the input value reset determination unit 16. ..
Step S406: The output bit determination unit 13 compares the magnitude relations of the input oscillation frequencies F1 and F2, determines the output bit of 1 bit according to the determination rule already described based on the comparison result, and outputs the output bit. Input to the bit control unit 18. The output bit control unit 18 temporarily stores the input output bit.
Step S407: The input value resetting determination unit 16 reads out the input value resetting determination threshold value stored in the threshold value storage unit 17. Next, the input value reset determination unit 16 calculates the frequency difference D = F2-F1 from the input oscillation frequencies F1 and F2, and the absolute value of the difference D is equal to or greater than the input value reset determination threshold value. Check if there is. If it is less than the threshold value, the input value reset determination unit 16 inputs the input value reset request signal to the input value setting unit 15. On the other hand, if it is equal to or higher than the threshold value, the input value reset determination unit 16 does nothing.
Step S408: When the input value setting unit 15 receives the input value reset request signal, it executes the input value data resetting process described later. As a result of this processing, "update the first input value data N1 and the second input value data N2 stored in the input value storage unit 14" or "send the input value reset failure signal to the output bit control unit 18". Or is done.
Step S409: The output bit control unit 18 outputs the 1-bit output bit input from the output bit determination unit 13 and temporarily stored as the output bit of the PUF circuit 1. If the input value reset failure signal has not been received from the input value setting unit 15, the output bit control unit 18 ends the calculation of the output bit as it is. When the input value reset failure signal is received, the output bit control unit 18 further inputs the 1-bit output bit to the output bit storage unit 19 as an output setting value. Then, the output bit storage unit 19 stores the output set value internally and ends the "calculation of output bit" process.
(Resetting input value data) FIG. 17 is a flowchart showing the operation when the PUF circuit 1 resets the input value data.
The input value data reset process is a subroutine process executed when the input value setting unit 15 receives the input value reset request signal in the above-mentioned output bit calculation process. The "reset of input value data" process is performed as follows.
Step S501: The input value setting unit 15 specifies the input setting threshold value and the output setting value. That is, the input value setting unit 15 reads the input setting threshold value stored in the threshold value storage unit 17. Further, the input value setting unit 15 sets the oscillation frequency F1 input from the first frequency counting unit 121 and the oscillation frequency F2 input from the second frequency counting unit 122 in step S405 of calculation of output bit. Comparing the magnitude relations, if F2> F1, the output setting value is set to "1", and if not, the output setting value is set to "0".
Step S502: The input value setting unit 15 selects a candidate for the input value data, and causes the first frequency counting unit 121 and the second frequency counting unit 122 to measure the oscillation frequency in the candidate. That is, the input value setting unit 15 selects any one of N1 = 000 (binary number) to 111 (binary number) as a candidate for the first input value data, and N2 as a candidate for the second input value data. Select one of = 000 (binary) to 111 (binary). Then, the input value setting unit 15 uses the ring oscillator selected by the combination of (candidate for first input value data, candidate for second input value data) = (N1, N2), and the first frequency counting unit 121 and The oscillation frequency is measured by the second frequency counting unit 122. Specifically, the PUF circuit 1 executes the following operations.
Step S502a: The input value setting unit 15 generates (N1, N2) as candidates for the first input value data and the second input value data, sets N1 in the first ring oscillator selection unit 111, and sets N1 in the second ring oscillator selection unit. Enter N2 in 112 respectively.
Step S502b: The first ring oscillator selection unit 111 selects one ring oscillator from the first ring oscillator 101 to the eighth ring oscillator 108 according to the rule described above based on the above N1. The second ring oscillator selection unit 112 selects one ring oscillator from the first ring oscillator 101 to the eighth ring oscillator 108 according to the above-mentioned rule based on the N2.
Step S502c: Here, when a trigger signal is input to the two ring oscillators selected in step S502b, the two selected ring oscillators oscillate and output an oscillation signal. At this time, the ring oscillator selected by the first ring oscillator selection unit 111 inputs an oscillation signal to the first frequency counting unit 121 via the first ring oscillator selection unit 111. The ring oscillator selected by the second ring oscillator selection unit 112 inputs an oscillation signal to the second frequency counting unit 122 via the second ring oscillator selection unit 112.
Step S502d: The first frequency counting unit 121 and the second frequency counting unit 122 measure the oscillation frequency from the input oscillation signals, respectively. Here, the first frequency counting unit 121 measures the oscillation frequency F1, and the second frequency counting unit 122 measures the oscillation frequency F2. Then, the measured F1 and F2 are input to the input value setting unit 15.
Step S503: The input value setting unit 15 selects whether or not the input value data candidates selected based on the oscillation frequencies F1 and F2 measured as described above are suitable as the input value data to be set. Determine if the candidate was a failure. Specifically, the input value setting unit 15 calculates the frequency difference D = F2-F1 from the input F1 and F2, and there is no contradiction between the difference D and the output setting value specified in step S501. If the absolute value of the difference D is equal to or greater than the input setting threshold value, it is determined that the selected candidate is not a failure. In this case, as described in step S504 described later, the input value setting unit 15 stores the input values for (N1, N2) at that time by using N1 as the first input value data and N2 as the second input value data. Input to Part 14 and erase the output setting value. Here, "there is no contradiction between the difference D and the output setting value" means that when the output setting value is 0, the difference D is a negative value or 0, and the output setting value is 1. In the case of, it means that the difference D is a positive value. If the above conditions are not satisfied, the input value setting unit 15 determines that the selected candidate has failed. In this case, as described in step S505 described later, another candidate (N1, N2) is generated, and steps S502a to S502d are repeatedly executed. If there is no combination of all (N1, N2) that satisfies the above conditions based on the input setting threshold value, the input value setting unit 15 will be used as described in step S506 described later. , The output set value and the input value reset failure signal corresponding to the above-mentioned save request signal are input to the output bit control unit 18. Then, the output set value is erased.
Step S504: The input value storage unit 14 sets N1 and N2 input from the input value setting unit 15, that is, the first input value data candidate N1 and the second input value data candidate N2 determined not to be a failure. It is saved as the first input data and the second input data to be set respectively, and the "reset input value data" process is completed.
Step S505: When the input value setting unit 15 determines that the selected first input value data candidate N1 and the second input value data candidate N2 have failed in step S503, the input value setting unit 15 other than the candidates N1 and N2. Determine if there are candidates. Here, when the input value setting unit 15 determines that there is another candidate, the process from step S502 is repeated, and when it is determined that there is no other candidate, the process of step S506 is executed.
Step S506: When the input value setting unit 15 determines that there is no other candidate as described above, the input value setting unit 15 outputs the output setting value and the input value reset failure signal to the output bit control unit 18. The output bit control unit 18 receives the input value reset failure signal and the output set value, and inputs the output set value to the output bit storage unit 19. The output bit storage unit 19 stores the output set value and ends the "reset input value data" process.
(Outline of operation of PUF circuit 1) Based on the above operation, the operation of the PUF circuit 1 in the present embodiment is as follows.
After the PUF circuit 1 is manufactured, the PUF circuit 1 performs the "input value data setting" process and sets the output bit of 1 or 0. After that, the PUF circuit 1 performs the "calculation of output bit" process and outputs the 1-bit output bit set by the "setting of input value data" process. At that time, in the PUF circuit 1, the frequency difference between the two ring oscillators selected by the input value data (N1, N2) set in the input value storage unit 14 becomes less than a predetermined threshold due to aging or the like. If it is detected, the "input value data reset" process is performed and the input value data is reset.
In the present embodiment, it is detected that the frequency difference between the two ring oscillators selected by the set input value data becomes less than a predetermined threshold value due to the secular change of the frequency characteristics of the circuits constituting the ring oscillator. Then, the input value data is reset so that the frequency difference becomes equal to or more than a predetermined threshold value. On the other hand, in the past, even if the frequency difference of the ring oscillator becomes smaller due to the above-mentioned secular change and there is a high risk that the frequency relationship will be reversed due to the change in the external environment, the input value data should be reset. It doesn't have a mechanism. Therefore, it can be said that the PUF circuit 1 is improved in terms of output bit stability as compared with the conventional configuration against changes in frequency characteristics due to aging.
Further, in the present embodiment, two values, an input setting threshold value and an input value reset determination threshold value, are introduced and stored in the threshold value storage unit 17. Conventionally, these values are not stored inside the PUF circuit. However, since these values are threshold values related to the absolute value of the frequency difference of the ring oscillator, it is not possible to infer the magnitude relationship of the oscillation frequency of the ring oscillator selected in the output bit calculation process from this value. That is, it is not possible to infer a 1-bit output bit from these values, and the PUF circuit 1 in the present embodiment can safely hold secret data in the same manner as the conventional PUF circuit. ..
Further, in the present embodiment, when the frequency characteristic of the ring oscillator changes due to aging and the ring oscillator pair having a frequency difference equal to or larger than a predetermined threshold value is not found in the input value data resetting process. , The output bit is stored in the output bit storage unit 19, and thereafter, the output bit stored in the output bit storage unit 19 is output. This is because if it is determined that it is difficult to maintain a more stable output bit due to the PUF configuration due to the resetting of the input value data, the stability of the output bit is maintained by retaining the output bit as it is. It is something that tries to keep going. As a result, the security of the output bit is lower than when it is stored in the PUF. However, even if only one bit of secret data of several tens to several hundreds of bits such as key data is analyzed and exposed, it rarely leads to a fatal decrease in security. It does not cause any significant safety issues. The above mechanism may be deleted when realizing a PUF circuit having high safety.
As described above, in the present embodiment, when the PUF circuit detects that the frequency difference of the ring oscillator is less than a predetermined threshold value, the ring oscillator is selected so that the frequency difference becomes equal to or more than the threshold value. Reset the input value data so that. As a result, the stability of the output bit of the PUF circuit can be improved even if the frequency characteristic of the ring oscillator changes over time. That is, it is possible to provide an information security device using a PUF circuit so that the output bit is not inverted even if a change occurs over time.
(Embodiment 3) Next, Embodiment 3 of the present invention will be described with reference to the drawings. In the third embodiment, in addition to the second embodiment, the input value data is reset based on the error correction using the error correction code performed outside the PUF circuit or the error detection result. By adding the configuration to be used, the stability of the output bit of the PUF circuit with respect to the aging of the frequency is further improved.
(Configuration of PUF circuit 4) FIG. 18 is a block diagram showing an example of the internal configuration of the PUF circuit 4 according to the third embodiment. The PUF circuit 4 corresponds to each of the first PUF 11041A to 11041I in the first embodiment and its modified example, and has substantially the same configuration as the PUF circuit 1 in the second embodiment of FIG. That is, the PUF circuit 4 includes the 1st to 8th ring oscillators 101 to 108, the 1st to 2nd ring oscillator selection units 111 to 112, the 1st to 2nd frequency count units 121 to 122, and the output bit determination unit. It is composed of 13, an input value storage unit 14, an input value setting unit 45, an input value reset determination unit 16, a threshold value storage unit 17, an output bit control unit 18, and an output bit storage unit 19.
The only difference from the PUF circuit 1 is that the PUF circuit 4 receives an input value reset request signal from the outside, and the input value setting unit 45 receives the input value reset request signal. That is, the input value setting unit 45 in the present embodiment has the same function as the input setting unit 15 in the second embodiment, and when the input value reset request signal is acquired from the outside of the PUF circuit 4, the input value is input. Similar to when the input value reset request signal is acquired from the reset determination unit 16, the "reset input value data" process in the second embodiment is executed.
The information generation PUF unit in the present embodiment includes nine such PUF circuits 4 and can securely hold a hash key which is 3-bit secret data.
FIG. 19 is a diagram for explaining a method of setting a hash key in the information generation PUF unit in the present embodiment.
The information generation PUF unit 1104a includes nine PUF circuits 4 and a bit connection unit 302 for connecting output bits output from the nine PUF circuits 4. The bit connecting unit 302 has the same function as the hash key generating unit 11042 of the first embodiment. When setting a 3-bit hash key in the information generation PUF unit 1104a, the error correction code generation unit 300 and the bit division unit 301 are used. The hash key setting process is a process performed in a state where the hash key is not set after the information generation PUF unit 1104a is manufactured.
The error correction code generation unit 300 performs error correction coding on the 3-bit hash key to generate an error correction code on the hash key. The bit division unit 301 divides the error correction code generated by the error correction code generation unit 300 into bit units, and inputs each bit to each PUF circuit 4 as an output setting value. Hereinafter, the hash key setting process will be described with reference to a specific example.
First, the hash key M is input to the error correction code generator 300. The error correction code generation unit 300 generates an error correction code (error correction codeword C) for the hash key M as follows. First, let the hash key M be M = (m1, m2, m3). Here, m1, m2, and m3 are 1-bit values, respectively, where m1 is the most significant bit of M, m2 is the second bit from the uppermost bit of M, and m3 is the least significant bit of M. At this time, the error correction code generator 300 determines the error correction codeword C for M as a 9-bit value C = (m1, m1, m1, m2, m2, m2, m3, m3, m3). For example, when M = 101 (binary), C = 111000111 (binary), and when M = 011 (binary), C = 000111111 (binary). The error correction code generation unit 300 inputs the 9-bit error correction codeword C thus obtained into the bit division unit 301. The bit division unit 301 divides the input 9-bit C one bit at a time from the upper level, and inputs each bit to each of the nine PUF circuits 4. Each of the nine PUF circuits 4 uses the input 1-bit data as an output setting value, and performs exactly the same processing as the "input value data setting" processing of the PUF circuit 1 in the second embodiment.
FIG. 20 is a diagram showing a configuration of the information security device 1100a according to the present embodiment.
The information security device 1100a according to the present embodiment includes an information generation PUF unit 1104a, an error correction processing unit 303, an exclusive OR unit 305, a bit division unit 306, a decoding unit 304, and an input unit 1101. , The hash generation unit 1103 and the output unit 1102. The input unit 1101, the hash generation unit 1103, and the output unit 1102 in the present embodiment are the same as the input unit 1101, the hash generation unit 1103, and the output unit 1102 in the information security device 1100 of the first embodiment.
When the trigger signal is input to the nine PUF circuits 4 of the information generation PUF unit 1104a, each PUF circuit 4 performs the same processing as the "calculation of output bit" process in the second embodiment, and each of the PUF circuits 4 performs the same process as the "calculation of output bit" process. Output the output bit. The bit coupling unit 302 is bit-connected so that the output bit of the first PUF circuit 4 is the most significant bit and the output bit of the ninth PUF circuit 4 is the least significant bit according to the sequence of the nine PUF circuits 4. By performing the above, the hash key before error correction is generated as 9-bit data, and is input to the error correction processing unit 303 and the exclusive logical sum unit 305. In the present embodiment, the bit connecting portion 302 is configured as a coupling portion that combines the output values output from the plurality of PUF circuits 4.
The error correction processing unit 303 performs error correction on the input 9-bit data and outputs the resulting 9-bit data.
FIG. 21 is a diagram showing the configuration of the error correction processing unit 303.
The error correction processing unit 303 includes an error correction unit 1105a, an error correction information generation unit 1108, an error correction PUF unit 1106, and an error correction partial information storage unit 1107. The error correction information generation unit 1108, the error correction PUF unit 1106, and the error correction partial information storage unit 1107 in the present embodiment are the error correction information generation unit 1108, the error correction PUF unit 1106, and the error in the first embodiment. It is the same as the correction part information storage unit 1107.
Further, the error correction unit 1105a in the present embodiment executes the exclusive OR operation in the same manner as the error correction unit 1105 in the first embodiment, but the decoding is such that the 3-bit repeat code is changed to 1 bit. Does not execute. That is, the error correction unit 1105a takes the exclusive OR of the 9-bit data which is the hash key before the error correction and the error correction information, and the result 9-bit data is the exclusive OR with the decoding unit 304. Enter in part 305.
The decoding unit 304 divides the 9-bit data input from the error correction processing unit 303 into 3-bit repeating codes, and decodes each 3-bit repeating code into 1 bit. That is, the error correction unit 1105a of the first embodiment is realized by the error correction unit 1105a and the decoding unit 304 of the present embodiment.
Specifically, the decoding unit 304 removes the redundancy added for error correction coding from the 9-bit data of the input error correction result, and outputs a 3-bit corrected hash key. That is, the decoding unit 304 divides the above-mentioned 9-bit data by 3 bits from the upper order, and for each 3-bit data, 0 (binary) in the case of 000 (binary) and 111 (binary) in the case of 111 (binary). Is converted to 1 (binary number) and then concatenated again to obtain 3-bit data. As a result, the same data as the 3-bit hash key set in each PUF circuit 4 in the "input value data setting" process can be obtained. Here, the error correction code used above is a repetition code in which 2 bits having the same value as the information bit are added to the information bit as a redundant bit, and is out of 3 bits (1 information bit and 2 redundant bits). Even if an error occurs in one bit and the data is inverted, the error can be detected and corrected.
The error correction processing unit 303 may perform error correction processing as follows. That is, the error correction processing unit 303 divides the input 9-bit data into 3 bits from the upper order to obtain c1, c2, and c3. Next, the Hamming weight (the number of bits in which 1 stands) is calculated for each of c1, c2, and c3. If the Hamming weight is 2 or more, it is 111 (binary), and if the Hamming weight is 1 or less, it is 000 (binary). For example, if it is 010 (binary), it is 000 (binary), and if it is 110 (binary), it is 111 (binary). The 3 bits x 3 data thus obtained are concatenated in the order of c1 error correction processing result, c2 error correction processing result, and c3 error correction processing result from the top, and the final error correction. The resulting 9-bit data is input to the decoding unit 304 and the exclusive OR unit 305.
The exclusive OR unit 305 performs an exclusive OR operation between the 9-bit data before error correction input from the bit connecting unit 302 and the 9-bit data after error correction input from the error correction processing unit 303. , The 9-bit data which is the calculation result is input to the bit division unit 306. This is the same as performing the process of comparing the data before and after the error correction and setting 1 at the bit position where the error correction was performed. That is, in the present embodiment, the exclusive OR unit 305 is configured as an error determining means for determining whether or not an error has occurred in the hash key output from the information generation PUF unit 1104a.
The bit division unit 306 divides the input 9-bit data one bit at a time from the upper level, and inputs each bit to each PUF circuit 4. As a result, 1-bit data "1" is input as an input value reset request signal to the PUF circuit 4 that outputs the bit that has been error-corrected, and the PUF circuit 4 that outputs the bit that has not been error-corrected. 1-bit data "0" will be input to. That is, in the present embodiment, the bit dividing unit 306 is configured as a resetting requesting means for requesting the information generation PUF unit 1104a to reset the hash key.
The PUF circuit 4 to which the input value reset request signal is input executes the same input value data reset process as in the second embodiment. That is, the PUF circuit 4 executes the process described above with reference to FIG. However, when the input value setting unit 45 of the PUF circuit 4 specifies the output setting value in step S501, since an error has already occurred in the output bit, the input value setting unit 45 specifies the output setting value based on the reverse rule to the above. .. For example, the input value setting unit 45 compares the magnitude relationship between the oscillation frequency F1 input from the first frequency counting unit 121 and the oscillation frequency F2 input from the second frequency counting unit 122, and F2 F1. If so, the output setting value is set to "1", otherwise the output setting value is set to "0".
In the present embodiment, the input value setting unit 45 of the PUF circuit 4 is configured as a resetting unit for resetting the hash key.
In the present embodiment, for the bit detected as having an error (the bit for which the error has been corrected), the PUF circuit that generated the bit value is instructed to reset the input value data. Is a feature. This configuration has the following effects that could not be obtained in the second embodiment. For example, in the case of the second embodiment, when the threshold value for determining the input value reset is R, the frequency characteristic of the ring oscillator changes abruptly, and the difference in oscillation frequency (F2-F1) is originally F2-F1. If what was> R changes to F2-F1 <-R, the output bit value of the PUF circuit will be inverted, and the absolute value of F2-F1 will be R or more. , The input value is not reset. However, in the present embodiment, the inversion of the output bit is detected and the input value is reset, so that the input value data is appropriately reset. As described above, in the present embodiment, the input value data is appropriately reset even for a sudden change in the frequency characteristic of the ring oscillator, and the stability of the output bit is maintained.
In the present embodiment, when an error occurs in the output bit, the PUF circuit 4 that outputs the output bit, that is, the PUF circuit 4 that has acquired the input value reset request signal resets the input value data. However, the value of the output bit to be output, that is, the output set value may be stored in the output bit storage unit 19 without resetting the input value data.
FIG. 22 is a flowchart showing another operation of the PUF circuit 4 that has acquired the input value reset request signal.
First, the input value setting unit 45 that has acquired the input value reset request signal specifies the output set value (step S601). At this time, since the output bit of the input value setting unit 45 has already been erroneous as described above, the oscillation frequency F1 input from the first frequency counting unit 121 and the input value setting unit 45 are input from the second frequency counting unit 122. Comparing the magnitude relationship with the oscillation frequency F2, if F2 F1, the output set value is set to "1", and if not, the output set value is set to "0".
Then, the input value setting unit 45 outputs the specified output setting value and the save request signal to the output bit control unit 18, and then outputs the output setting value (output bit indicating the output setting value) to the output bit control unit 18. ) Is stored in the output bit storage unit 19 (step S602).
In this way, when the PUF circuit 4 that has acquired the input value reset request signal stores the output set value in the output bit storage unit 19 without resetting the input value data, the future processing burden on the PUF circuit 4 Can be reduced and the output bit can be stabilized.
(Modification example) The first to third embodiments described above are examples of the implementation of the present invention, and the present invention is not limited to this embodiment, and the present invention is implemented in various embodiments without departing from that fact. What you get. For example, the following cases are also included in the present invention.
(1) The error correction code used in the information security device and the error correction information generation device is a repetition code, but is not limited to this. Any error correction code may be used. For example, it may be an algebraic code such as a Reed-Solomon code or a convolutional code. Further, the code length (number of bits and elements) was set to 9, and the number of information symbols was set to 3, but this is not limited to this. In terms of security, the corrected hash key should be 80 bits or more.
(2) The information security device outputs a hash value with a key, but it is not limited to this. The converted data obtained by converting the input data using the secret key may be output. The converted data includes a ciphertext, a decryption statement, a signature data, and the like, in addition to the hash value with a key.
(3) Information security devices use PUF circuits, but they are not limited to this. Instead of the PUF circuit, it may be an anti-tamper circuit that can output secret information. Further, it may be an anti-tamper circuit whose output changes due to the environment and deterioration over time. As the tamper-resistant circuit, the identification information generation circuit described in Patent Document 2 (Japanese Unexamined Patent Publication No. 2006-060109) may be used. The identification information generation circuit generates a unique identification code from the logic signals first output from the flip-flops, RAM, and Static RAM memory cells when the power is turned on. The PUF includes an Optical PUF that uses a speckle pattern, a Silicon PUF that uses a gate delay, a Coating PUF that uses a dielectric constant, and an Acoustic PUF that uses noise.
(4) In the environment change section of the error correction information generator, the temperature around the PUF circuit is changed, but other environmental changes, for example, voltage changes may be used. Further, instead of the environmental change, the current environment may be acquired and the environment change analysis unit may be notified of the current environment.
(5) In the second PUF circuit, the rule for converting the difference to the value from "0" to "7" is fixed in advance, but the error correction information generator applies this conversion rule. It may be determined and embedded in the second PUF circuit, or stored in the error correction part information storage unit. Further, the error correction information of the second PUF circuit may be stored in the error correction partial information storage unit. In this case, the error correction information of the second PUF circuit can be used to know the PUF information for error correction, and the attacker can know the error correction information of the first PUF circuit from the error correction partial information. However, since the amount of processing required for attacker analysis is large, it is effective as an improvement in security. Further, PUF circuits may be added as third, fourth, ..., To make it more difficult for an attacker to obtain error correction information.
(6) In the embodiment, the output bit of 1 bit or 3 bits is determined from the magnitude relation of the oscillation frequencies of the two ring oscillators, but this is not limited to two, and three or more ring oscillators. It may be. At this time, for example, when the frequencies of the three ring oscillators are A, B, and C, the correspondence between all the patterns of the magnitude relations of A, B, and C and the output bits may be determined in advance as a rule. At this time, as a judgment method in the input value reset judgment unit, A, B, and C are arranged in descending order of frequency, and then the difference between (1st frequency) and (2nd frequency) and (2nd). The difference between (frequency) and (third frequency) may be calculated, and the determination may be made by checking whether each difference value is equal to or higher than a predetermined threshold value.
(7) In the embodiment, when an input value pair (N1, N2) having a difference equal to or larger than the input value setting threshold is found in the "input value data setting" process and the "input value data reset" process. So, that value was set or reset in the input value storage unit, but this is one of the difference values after first finding the difference value of the frequency for all the input value pairs (N1, N2). Select the largest (N1, N2), and if the difference value at that time is equal to or greater than the input value setting threshold, set or reset the selected value in the input value storage unit, and if it is less than the above threshold, input. A value setting failure signal or an input value reset failure signal may be sent.
(8) The input setting threshold value and the input value reset determination threshold value stored in the threshold value storage unit do not necessarily have to be set at the time of manufacturing the PUF circuit, and may be set after manufacturing. Moreover, even after setting once, it may be possible to reset. That is, at least one of the input setting threshold value and the input value reset determination threshold value may be updated. For example, there is no ring oscillator pair that satisfies the currently set input setting threshold when the threshold is changed or the input value data is reset every time the PUF circuit performs the output bit calculation process a predetermined number of times. In that case, the threshold value may be changed so as to be smaller than the current threshold value.
(9) The input value reset determination by the input value reset determination unit does not have to be performed every time the output bit calculation process is performed, and may be performed every time the output bit calculation process is performed a predetermined number of times, or may be performed externally. It may be performed when the instruction signal from is received.
(10) In this embodiment, the configuration when a ring oscillator is used as the oscillation circuit is shown, but if it is an oscillation circuit such as a solid-state oscillator oscillation circuit, a CR oscillation circuit, or an LC anticoupling oscillation circuit, Anything is fine.
(11) In the embodiment, the data output from one PUF circuit is 1 bit or 3 bits, but this is not limited to 1 bit or 3 bits, and the output bit is determined from the magnitude relation of the oscillation frequency. If the decision rule to be used is decided in advance, it may be 2 bits or 4 bits or more.
(12) Each of the above devices is specifically a computer system composed of a microprocessor, ROM, RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like. A computer program is stored in the RAM or the hard disk unit. When the microprocessor operates according to the computer program, each device achieves its function. Here, a computer program is configured by combining a plurality of instruction codes indicating commands to a computer in order to achieve a predetermined function.
(13) Some or all of the components constituting each of the above devices may be composed of one system LSI (Large Scale Integration). A system LSI is an ultra-multifunctional LSI manufactured by integrating a plurality of components on a single chip. Specifically, it is a computer system including a microprocessor, ROM, RAM, and the like. .. A computer program is stored in the RAM. When the microprocessor operates according to the computer program, the system LSI achieves its function.
(14) Some or all of the components constituting each of the above devices may be composed of an IC (Integrated Circuit) card or a single module that can be attached to and detached from each device. For example, the entire information security device 1100 shown in FIG. 4 may be configured as an IC card, or among the information security devices 1100, the information generation PUF unit 1104, the error correction unit 1105, the error correction information generation unit 1108, and errors may occur. The correction PUF unit 1106 and the error correction part information storage unit 1107 may be configured as an IC card. The IC card or the module is a computer system composed of a microprocessor, ROM, RAM, and the like. The IC card or the module may include the above-mentioned ultra-multifunctional LSI. When the microprocessor operates according to a computer program, the IC card or the module achieves its function. This IC card or this module may be tamper resistant.
(15) The present invention may be the method shown above. Further, it may be a computer program that realizes these methods by a computer, or it may be a digital signal composed of the computer program.
(16) The present invention also relates to a computer-readable recording medium such as a flexible disk, a hard disk, a CD-ROM, a MO, a DVD, a DVD-ROM, a DVD-RAM, or a BD (Blu). -ray Disc), may be recorded on a semiconductor memory, etc. Further, it may be the digital signal recorded on these recording media.
(17) Further, the present invention may transmit the computer program or the digital signal via a telecommunication line, a wireless or wired communication line, a network typified by the Internet, data broadcasting, or the like.
(18) Further, the present invention is a computer system including a microprocessor and a memory, in which the memory stores the computer program, and the microprocessor may operate according to the computer program. ..
(19) Further, another independent computer system by recording and transferring the program or the digital signal on the recording medium, or by transferring the program or the digital signal via the network or the like. It may be carried out by.
(20) The above-described embodiments 1 to 3 and the above-described modifications may be combined.
In the information security device according to the present invention, even if the information stored in the memory is used, the attacker cannot know the secret data such as the key value hidden by the PUF, so that the security of the PUF is not deteriorated. It has the effect of being able to be used, and can be applied to, for example, IC cards. Further, the information security device according to the present invention has a feature of improving the stability of secret data against aging as compared with the prior art while holding secret data such as key data and ID data securely and inexpensively. It is useful for the realization of information security devices that are required to be realized with high security, low cost, and high stability.
<figref num="1">FIG. 1 is a diagram showing a configuration of a conventional PUF circuit.</figref><figref num="2">FIG. 2 is a diagram showing a configuration of an information security device using conventional PUF error correction.</figref><figref num="3">FIG. 3 is a block diagram showing a configuration of an information security system according to the first embodiment of the present invention.</figref><figref num="4">FIG. 4 is a diagram showing the configuration of the same information security device.</figref><figref num="5">FIG. 5 is a diagram showing the configuration of the above-mentioned information generation PUF unit.</figref><figref num="6">FIG. 6 is a diagram showing the configuration of the first PUF circuit of the above.</figref><figref num="7">FIG. 7 is a diagram showing the configuration of the error correction PUF unit as described above.</figref><figref num="8">FIG. 8 is a diagram showing the configuration of the second PUF circuit of the above.</figref><figref num="9">FIG. 9 is a diagram showing the mapping between the difference and the output value of the second PUF circuit of the same as above.</figref><figref num="10">FIG. 10 is a diagram showing the configuration of the error correction information generator as described above.</figref><figref num="11">FIG. 11 is a diagram showing the distribution of output values analyzed by the environmental change analysis unit of the same.</figref><figref num="12A">FIG. 12A is a flowchart showing the operation when the error correction information generator of the above sets the error correction partial information.</figref><figref num="12B">FIG. 12B is a flowchart showing the operation when the same information security device calculates the keyed hash value.</figref><figref num="13">FIG. 13 is a block diagram showing a configuration of a PUF circuit according to a second embodiment of the present invention.</figref><figref num="14">FIG. 14 is a block diagram showing the configuration of the ring oscillator of the above.</figref><figref num="15">FIG. 15 is a flowchart showing the operation when the PUF circuit of the above sets the input value data.</figref><figref num="16">FIG. 16 is a flowchart showing the operation when the PUF circuit of the above calculates the output bit.</figref><figref num="17">FIG. 17 is a flowchart showing the operation when the PUF circuit of the above resets the input value data.</figref><figref num="18">FIG. 18 is a block diagram showing a configuration of a PUF circuit according to a third embodiment of the present invention.</figref><figref num="19">FIG. 19 is a diagram for explaining a method of setting a hash key in the above-mentioned information generation PUF unit.</figref><figref num="20">FIG. 20 is a diagram showing the configuration of the same information security device.</figref><figref num="21">FIG. 21 is a diagram showing the configuration of the error correction processing unit of the above.</figref><figref num="22">FIG. 22 is a diagram showing other operations of the PUF circuit of the same as above.</figref>
1 PUF circuit 13 Output bit determination unit 14 Input value storage unit 15 Input value setting unit 16 Input value reset judgment unit 17 Threshold storage 18 Output bit control unit 19 Output bit storage 101 ~ 108 1st ~ 8th Ring Oscillator 111,112 1st and 2nd ring oscillator selection 121,122 1st and 2nd frequency count section 1000 Information security system 1100,3000 Information security device 1101,3001 Input section 1102,3002 Output section 1103,3003 Hash generator 1104 PUF section for information generation 11041A ~ 11 041I First PUF circuit 11042 Hash key generator 1105,3005 Error correction section 1106 PUF section for error correction 11061A ~ 11061I Second PUF circuit 11062 PUF information generator for error correction 1107 Error correction part Information storage 1108 Error correction information generator 1200 Error correction information generator 1201 PUF circuit measurement unit 1202 Environmental Change Department 1203 Environmental Change Analysis Department 1204 Error correction part Information generator 1205 Error correction part information setting section 2000 PUF circuit 2001 1st Ring Oscillator 2002 2nd Ring Oscillator 2003 3rd Ring Oscillator 2004 4th Ring Oscillator 2005 5th Ring Oscillator 2006 6th Ring Oscillator 2007 7th Ring Oscillator 2008 8th Ring Oscillator 2011 1st Ring Oscillator Selection 2012 2nd Ring Oscillator Selection 2021 1st frequency count 2022 2nd frequency count 2030 output bit determination unit 3004 PUF section 3006 Error correction information storage
6 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6
Every citation, both waysCites: the store holds 4 of 5
| Document | Relation | Office | Cited during |
|---|---|---|---|
| JP2000083019A | Cites | Japan | Examiner |
| JP2005045760A | Cites | Japan | Examiner |
| JP200545760A | Cites | Japan | – |
| JP200083019A | Cites | Japan | – |
| Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srinivas Devadas,“A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication App,VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on,[online],2004年 6月,p.176-179,[retrieved on 2008-01-15], Retrieved from the Internet,URL,<http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1346548> | Non-patent | – | – |
| D. C. Ranasinghe, Daihyun Lim, Srinivas Devadas, Behnam Jamali, Zeng Zhu, Peter H. Cole,“An Integrable Low Cost Hardware Random Number Generator”,PROCEEDINGS OF SPIE - The International Society for Optical Engineering,2005年,volume 5649, Part Two of Two Parts,p.627-639 | Non-patent | – | – |
11 members in 4 offices
Priority claims16
| Document | Office | Kind | Date |
|---|---|---|---|
| 2006299905 | Japan | A | |
| 2006299905 | Japan | A | |
| 2006299905 | Japan | – | |
| 2006299906 | Japan | A | |
| 2006299906 | Japan | A | |
| 2006299906 | Japan | – | |
| 2007071413 | Japan | W | |
| 2007071413 | Japan | W | |
| 2008543059 | Japan | A | |
| 20062006299905 | – | – | – |
| 20062006299906 | – | – | – |
| 2007071413 | – | – | – |
| JP20060299905 | – | – | – |
| JP20060299906 | – | – | – |
| JP20080543059 | – | – | – |
| WO2007JP71413 | – | – | – |
Members11
| Document | Office | Kind | |
|---|---|---|---|
| WO2008056612A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2008056613A1 | World Intellectual Property Organization (WIPO) | A1 | |
| EP2053543A1 | European Patent Office (EPO) | A1 | |
| EP2081170A1 | European Patent Office (EPO) | A1 | |
| US2009271860A1 | United States of America | A1 | |
| US2010031065A1 | United States of America | A1 | |
| JPWO2008056612A1 | Japan | A1 | |
| JPWO2008056613A1 | Japan | A1 | |
| US8347091B2 | United States of America | B2 | |
| JP5113074B2This record | Japan | B2 | |
| US8510608B2 | United States of America | B2 |
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Numbers
- Publication
- 5113074
- Publication, DOCDB
- 5113074
- Publication, EPODOC
- JP5113074B
- Application
- 2008543059
- Application, DOCDB
- 2008543059
- Application, EPODOC
- JP20080543059
Titles2
- Japanese
- 情報セキュリティ装置
- English
- Information security device
Classification
- CPC, 3
- H04L9/3242
- H03K3/0315
- H04L9/0866
- IPC, 2
- G09C1 00
- H04L9 08
