Power conversion device

The present invention relates to a power conversion device that converts DC power into AC power, and in particular, power conversion that converts DC power of a DC power source having a floating capacitance such as a solar cell into three-phase output AC power and outputs it to a load. It is about the device.

A conventional power converter converts DC power from a solar cell into three-phase output AC power, and connects it to a three-phase system with one phase grounded to send AC power to that system. The conversion devices are as shown below. Three sets of half-bridge inverters that are connected between the output terminals of the solar cell and consist of two series switching elements, a single-phase inverter that is connected in series to each AC output line, and two series that divide the voltage of the solar cell. It is equipped with a capacitor, and each output end of each single-phase inverter is connected to each phase of the three-phase system. Then, the half-bridge inverter operates in one pulse every half cycle, each single-phase inverter is PWM-controlled so as to make up for the shortage from the system voltage, and is output to the system by the sum of the outputs of the half-bridge inverter and the single-phase inverter. .. Therefore, the input DC voltage of the half-bridge inverter can be reduced, PWM control by a large voltage is not required, switching loss can be reduced, and the capacitance of the output filter can be reduced (see, for example, Patent Document 1).

<p><patcit num="1"><text>International Publication No. 2008-102552</text></patcit></p>

<p> In the conventional power conversion device as described above, a three-phase two-level inverter is used as the inverter connected to the solar cell, and the DC power supply bus potential fluctuates during the operation of the inverter. On the other hand, the system has wiring with the V phase and the midpoint grounded, and when the DC power supply bus potential fluctuates, the floating capacitance of the DC power supply and the potential fluctuation cause the floating capacitance and the path of the grounding point of the system. Zero-phase current is generated. There was a problem that the earth leakage breaker operated due to this zero-phase current and the device stopped.</p><p> The present invention has been made in order to solve the above-mentioned problems, and is a power conversion device having a small device configuration, low cost, and high conversion efficiency, and has a floating capacitance of a DC power supply. The purpose is to suppress the zero-phase current through the earth leakage breaker and prevent the malfunction of the earth leakage breaker.</p>

<p> The power conversion device according to the present invention is a single-phase three-level inverter connected between the positive and negative terminals of the first DC power supply and one or a plurality of single-phase AC output lines connected in series to each phase AC output line of the three-phase three-level inverter. A phase inverter and a control device are provided, and the sum of the output voltage of the three-phase three-level inverter and the output voltage of each single-phase inverter is output to the load via a smoothing filter. A second DC power supply that is the DC input power supply for the single-phase inverter<u style="single">Is composed of a DC capacitor, and the second DC power supply</u>The voltage of is smaller than the voltage of one level of the above three-phase three-level inverter. Further, the control device is a three-phase three-level inverter so that each phase of the three-phase three-level inverter outputs a voltage of one pulse as a main voltage pulse for a half cycle of each phase output voltage to the load. The pulse width of the main voltage pulse output by the three-phase three-level inverter is controlled so that the output power balance of each half cycle or one cycle of the single-phase inverter becomes 0. By PWM control of the phase inverter, each phase output voltage to the load is 2π / 3 different from the reference potential of the first DC power supply based on the point that it has zero or a constant DC potential. Control to be a sinusoidal wave with the same peak value in phase<u style="single">When the voltage value of the second DC power supply of each of the single-phase inverters is larger than the reference value, the pulse width of the main voltage pulse of the corresponding phase is shortened, and the second DC power supply is used. When the voltage value is smaller than the reference value, the pulse width of the main voltage pulse of the corresponding phase is lengthened.</u>It is a thing.<u style="single"> Further, the power conversion device according to the present invention is connected to a three-phase three-level inverter connected between the positive and negative terminals of the first DC power supply and one or more in series to each phase AC output line of the three-phase three-level inverter. It is equipped with a single-phase inverter and a control device, and outputs the sum of the output voltage of the three-phase three-level inverter and the output voltage of each single-phase inverter to the load via a smoothing filter. The second DC power supply, which is the DC input power supply of the single-phase inverter, is composed of a DC capacitor, and the voltage of the second DC power supply is smaller than the voltage of one level of the three-phase three-level inverter. Further, in the control device, each phase of the three-phase three-level inverter has one main voltage pulse for a half cycle of each phase output voltage to the load, and the vicinity of the rising portion and the standing portion of the main voltage pulse. The above three-phase three-level inverter is controlled so as to output multiple pulses by PWM control in the vicinity of the downlink portion, and the output power balance of each half cycle or one cycle of each of the above single-phase inverters becomes 0. The pulse width of the main voltage pulse output by the three-phase three-level inverter and the voltage output period by the PWM control are controlled, and each single-phase inverter is PWM-controlled to obtain the output voltage of each phase to the load. Based on the point having zero or a constant DC potential from the reference potential of the DC power supply of 1, each phase is controlled to be a sinusoidal wave having the same peak value in different phases by 2π / 3. When the voltage value of the second DC power supply of each single-phase inverter is larger than the reference value, the voltage output period of the three-phase three-level inverter of the corresponding phase is shortened, and the voltage value of the second DC power supply becomes When it is smaller than the reference value, the voltage output period of the above-mentioned three-phase three-level inverter of the corresponding phase is lengthened.</u></p>

<p> The power conversion device according to the present invention has high accuracy in controlling the output voltage as a sine wave having the same peak value with each phase having a different phase of 2π / 3 with reference to a predetermined DC potential point of the first DC power supply. It can be realized and the fluctuation of the bus potential of the first DC power supply can be eliminated. Therefore, it is possible to configure the device so that there is no AC component between the neutral potential of the three-phase output and one potential of the first DC power supply, and the zero phase that flows through the floating capacitance of the first DC power supply. The current can be suppressed and the malfunction of the earth leakage breaker can be prevented. Further, since the output is performed by combining the three-phase three-level inverter and the single-phase inverter, the input DC voltage of the three-phase three-level inverter may be low, and PWM control by a large voltage is not required. Therefore, the device configuration is small, the cost is low, and the power conversion device has high conversion efficiency.</p>

<figref num="1">It is a figure which shows the structure of the power conversion apparatus by Embodiment 1 of this invention.</figref><figref num="2">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 1 of this invention.</figref><figref num="3">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 1 of this invention.</figref><figref num="4">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 1 of this invention.</figref><figref num="5">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 1 of this invention.</figref><figref num="6">It is a waveform diagram explaining the comparative example of the operation of the three-phase inverter circuit by Embodiment 2 of this invention.</figref><figref num="7">It is a waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 2 of this invention.</figref><figref num="8">It is a figure which shows the structure of the power conversion apparatus according to Embodiment 4 of this invention.</figref><figref num="9">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 4 of this invention.</figref><figref num="10">It is a figure which shows the structure of the power conversion apparatus according to Embodiment 5 of this invention.</figref><figref num="11">It is a voltage waveform diagram explaining the comparative example of the operation of the three-phase inverter circuit by Embodiment 5 of this invention.</figref><figref num="12">It is a voltage waveform diagram explaining the comparative example of the operation of the three-phase inverter circuit by Embodiment 5 of this invention.</figref><figref num="13">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 5 of this invention.</figref><figref num="14">It is a voltage waveform diagram explaining the operation of the three-phase inverter circuit by Embodiment 5 of this invention.</figref><figref num="15">It is a figure which shows the structure of the power conversion apparatus according to Embodiment 6 of this invention.</figref><figref num="16">It is a figure explaining the operation of the three-phase inverter circuit by Embodiment 6 of this invention.</figref><figref num="17">It is a figure which shows the structure of the power conversion apparatus according to Embodiment 7 of this invention.</figref><figref num="18">It is a figure which shows the structure of the power conversion apparatus according to Embodiment 8 of this invention.</figref>

Embodiment 1. Hereinafter, the power conversion device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a power conversion device according to a first embodiment of the present invention. The power conversion device includes a three-phase inverter circuit 1 which is a main circuit and an output control device 13. The three-phase inverter circuit 1 converts the DC power from the first DC power supply 2 into three-phase AC power and outputs it to the load 7, and the first DC power supply 2 is a floating capacitance between the first DC power supply 2 and the ground. It is a DC power source such as a solar cell with a capacity of 17. The load 7 is grounded at the load grounding point 16. The three-phase inverter circuit 1 is a three-phase three-level inverter 3 whose bus voltage is the voltage of the first DC power supply 2, and a single-phase inverter 4 connected in series to each phase AC output line of the three-phase three-level inverter 3. And a three-phase smoothing filter 6 connected to the rear stage of the single-phase inverter 4 and composed of a reactor and a capacitor (not shown).

Each phase of the three-phase three-level inverter 3 is composed of four semiconductor switching elements 8 made of IGBTs or the like in which diodes are connected in antiparallel, and two clamp diodes 9. Further, the three-phase three-level inverter 3 includes a first series capacitor 10 and a second series capacitor 11 as two series capacitors for dividing the first DC power supply 2, and the first series capacitor 10 and the second The connection point with the series capacitor 11 of is connected to the connection point of the two clamp diodes 9 of each phase. That is, the connection point between the first series capacitor 10 and the second series capacitor 11 is a neutral point that is a potential point that divides the voltage of the first DC power supply 2 into two, and constitutes the upper and lower arms of each phase. The connection point of the two semiconductor switching elements 8 is clamped to the neutral point potential.

Each single-phase inverter 4 includes a full-bridge inverter 12 composed of four semiconductor switching elements and a DC capacitor 5 as a second DC power supply that holds a voltage. The output voltage of the single-phase inverter 4 of each phase is superimposed on the output voltage of each phase of the three-phase three-level inverter 3, and the sum of the voltage of the output voltage of the three-phase three-level inverter 3 and the output voltage of each single-phase inverter 4 Is output to the load 7 via the smoothing filter 6. The voltage of the DC capacitor 5 of each single-phase inverter 4 is set smaller than 1/2 the voltage of the first DC power supply 2 (or the voltage of the first and second series capacitors 10 and 11). There is. That is, the voltage of the DC capacitor 5 is smaller than the voltage of one level of the three-phase three-level inverter 3. Further, in FIG. 1, for convenience, the circuit configuration of only one phase of the three single-phase inverters 4 is shown, and the other phases are omitted. The three-phase three-level inverter 3 and each single-phase inverter 4 are driven by a three-phase three-level inverter control signal 14 and a single-phase inverter control signal 15 output from an output control device 13 capable of performing calculations by a CPU, DSP, FPGA, or the like. Be controlled.

The operation of the three-phase inverter circuit 1 configured in this way will be described below based on the voltage waveforms shown in FIGS. 2 to 5. The potential of the waveform is a potential based on the neutral point, which is the connection point between the first series capacitor 10 and the second series capacitor 11. In Fig. 2, one phase output by the three-phase inverter circuit 1, for example, the phase voltage command 20 which is a U-phase voltage command, and the voltage waveform output by the U-phase of the three-phase three-level inverter 3 (three-phase three-level inverter). The voltage 21) is shown. The phase voltage command 20 is a sine wave in which each phase has a different phase by 2π / 3 and has the same peak value. The DC voltage output by the first DC power supply 2 is charged in series of the first series capacitor 10 and the second series capacitor 11. The voltages of the first DC power supply 2, the first series capacitor 10, and the second series capacitor 11 are detected, and each detected voltage value is transmitted to the output control device 13.

By the three-phase three-level inverter control signal 14 from the output control device 13, each phase of the three-phase three-level inverter 3 uses the DC voltage of the first series capacitor 10 and the second series capacitor 11 as the input voltage, and the first The peak value corresponding to each voltage value of the series capacitor 10 and the voltage value of the second series capacitor 11 (or the voltage value of 1/2 of the voltage of the first DC power supply 2), in this case, the voltage of 200V. A pulse is output at a rate of 1 pulse in a half cycle with respect to the phase voltage command 20. The voltage pulse of one pulse in this half cycle is hereinafter referred to as the main voltage pulse 21a. Here, in one cycle of the phase voltage command 20, one pulse is output to the positive side of the phase voltage command 20 and one pulse is output to the main voltage pulse 21a on the negative side. The main voltage pulse 21a is output so that the power balance of the single-phase inverter 4 in a half cycle (or one cycle) becomes 0, and the details of this control will be described later.

FIG. 3 shows the output voltage command of the single-phase inverter 4 (single-phase inverter voltage command 22). This single-phase inverter voltage command 22 is obtained by subtracting the three-phase three-level inverter voltage 21 of each phase from the phase voltage command 20 of the three-phase inverter circuit 1. In each single-phase inverter 4, the difference between the phase voltage command 20 required for the three-phase inverter circuit 1 and the output voltage of each phase of the three-phase three-level inverter 3 by the single-phase inverter control signal 15 from the output control device 13. High-frequency PWM control is performed to supplement the output. Further, each single-phase inverter 4 is controlled so that the output current of each phase to the load 7 becomes a sine wave in this PWM control. Figure 4 shows the single-phase inverter voltage command of each phase single-phase inverter 4, 22a is the U-phase single-phase inverter voltage command, 22b is the V-phase single-phase inverter voltage command, and 22c is the W-phase single-phase inverter voltage command. is there. In this case, the waveform peak value is ± 125V, and the bus voltage of each single-phase inverter 4 needs to be 125V or more in order to output the voltage of this voltage command.

The output voltage of the single-phase inverter 4 of each phase is superimposed on the output voltage of each phase of the three-phase three-level inverter 3, and the sum of the voltage of the output voltage of the three-phase three-level inverter 3 and the output voltage of each single-phase inverter 4 Is output to the load 7 via the smoothing filter 6. FIG. 5 shows each phase output voltage of the three-phase inverter circuit 1, which is the sum of the voltage of the output voltage of the three-phase three-level inverter 3 and the output voltage of each single-phase inverter 4. 23 is the output voltage of each phase, and 24 is the average voltage waveform of the output voltage 23 of each phase. The output voltage waveform 24 of each phase to the load 7 has the same voltage waveform as the phase voltage command 20 of each phase, that is, the neutral point which is the connection point between the first series capacitor 10 and the second series capacitor 11. Each phase is a sine wave with the same peak value with a different phase of 2π / 3 based on the potential of.

Next, the output control of the main voltage pulse 21a of the three-phase three-level inverter 3 and the power balance of the single-phase inverter 4 will be described below with reference to FIG. As described above, the main voltage pulse 21a is output so that the power balance of the single-phase inverter 4 for half cycle or one cycle becomes 0. Since the single-phase inverter 4 outputs so as to compensate for the difference between the phase voltage command 20 and the output voltage of each phase of the three-phase three-level inverter 3, the three-phase three-level inverter 3 outputs the power output by the phase voltage command 20. It is sufficient to output the same power as the main voltage pulse 21a. When controlling the phase of the output current to match the phase of the output voltage (power factor 1 operation), the peak voltage of the phase voltage command 20 is Vp, and the DC voltage input to the three-phase inverter circuit 1 (here, the first one). If Ed is 1/2 of the voltage of the DC power supply 2 or the sum of the voltage of the first series capacitor 10 and the voltage of the second series capacitor 11, Vp can be expressed by the following equation (1). However, θ1 (0 &lt;θ1 &lt;π / 2) is the phase in which the main voltage pulse 21a rises.

<maths num="1"><img file="JP5097828B2_D0001.tif" /></maths>

From the above equation (1), the phase θ1 at which the main voltage pulse 21a rises is given by the following equation (2).

<maths num="2"><img file="JP5097828B2_D0002.tif" /></maths>

The voltage pulse having a pulse width of (π-2θ1) rising at the phase (nπ + θ1) calculated in this way becomes the main voltage pulse 21a. The output control device 13 performs the above calculation, sends a three-phase three-level inverter control signal 14 based on the calculation result to the three-phase three-level inverter 3, and controls the output of the three-phase three-level inverter 3. In the above calculation, the phase θ1 at which the main voltage pulse 21a rises is calculated, but determining this phase θ1 is the same as determining the pulse width (π-2 θ1).

In this embodiment, a three-phase three-level inverter 3 is used as the inverter connected to the first DC power supply 2, and the entire three-phase inverter circuit 1 is connected to the first series capacitor 10 and the second series capacitor 11. Based on the potential of the neutral point, which is a point, each phase was controlled to be a sine wave with the same peak value in different phases of 2π / 3. In such a configuration, the neutral point potential becomes stable, the bus potential of the first DC power supply 2 does not fluctuate, and output voltage control that obtains a desired voltage waveform can be realized with high accuracy, and the total output voltage of the three phases can be realized. Becomes 0. Therefore, there is no AC component between the neutral potential of the three-phase output and one potential of the first DC power supply 2, and the zero-phase current flows through the floating capacitance 17 of the first DC power supply 2. Can be suppressed. The zero-phase current is normally detected as an earth leakage current by the earth leakage breaker arranged in front of the load 7, but since the zero-phase current can be suppressed, the malfunction of the earth leakage breaker can be prevented and the earth leakage current is reduced. Therefore, the power conversion efficiency of the three-phase inverter circuit 1 is improved.

Further, since the three-phase inverter circuit 1 outputs a voltage obtained by adding the output voltage of the three-phase three-level inverter 3 and the output voltage of each single-phase inverter 4, it is the first DC input voltage of the three-phase inverter circuit 1. It can output a voltage higher than the voltage of the DC power supply 2 of. Further, since each phase of the three-phase three-level inverter 3 is operated by one pulse in a half cycle, almost no switching loss occurs. Since the DC voltage of the single-phase inverter 4 that is PWM-controlled at high frequencies is selected to a relatively small value, the switching loss due to PWM control may be small and the capacity of the smoothing filter 6 may be small. Therefore, the three-phase inverter circuit 1 has a device configuration that is small in size, low in cost, and has high conversion efficiency.

Further, in this embodiment, since the three-phase inverter circuit 1 is controlled so that the power balance of each single-phase inverter 4 becomes 0 in half cycle or one cycle, the DC capacitor 5 of each single-phase inverter 4 is external. It is possible to have a simple configuration that does not have a DC power supply that transfers power from the inverter.

Embodiment 2. In the first embodiment, the three-phase three-level inverter 3 outputs the power equivalent to the power output by the phase voltage command 20 by the main voltage pulse 21a, so that the pulse width (or rising phase) of the main voltage pulse 21a is output. ) Has been determined, but the pulse width can also be determined by other methods. In this embodiment, the integrated power value of the single-phase inverter 4 for half cycle or one cycle is calculated, and the pulse width of the main voltage pulse 21a is obtained so that the integrated power value becomes 0. The relationship between the pulse width of the main voltage pulse 21a of the three-phase three-level inverter 3 and the output power of the single-phase inverter 4 will be described below with reference to FIGS. 6 and 7. FIG. 6 shows a comparative example in which the half-cycle power integrated value of the single-phase inverter 4 is positive, and FIG. 7 shows a half of the single-phase inverter 4 by expanding the pulse width of the main voltage pulse 21a as compared with the case of FIG. The case where the integrated power value of the cycle is set to 0 is shown. For convenience, only the half-cycle waveform is shown.

As shown in FIGS. 6 (a) and 7 (a), for each phase output voltage waveform 24 of the three-phase inverter circuit 1, the three-phase three-level inverter 3 outputs a main voltage pulse 21a of one pulse in a half cycle. Output. Then, as shown in FIGS. 6 (b) and 7 (b), the single-phase is obtained so that the voltage waveform of the difference between the main voltage pulse 21a of the three-phase three-level inverter 3 and the output voltage waveform 24 of each phase can be obtained. Inverter 4 outputs an average voltage of 22d by PWM control. For example, when the three-phase three-level inverter 3 is a solar power conditioner, the output current to the load 7 often has a power factor of 1. When the power factor is 1, the current waveform of the output current 25 is a sine wave having the same phase as the output voltage waveform 24 of each phase.

The output power 26 of the single-phase inverter 4, which is the product of the output voltage 22d and the output current 25, has the waveforms shown in FIGS. 6 (c) and 7 (c). In FIG. 6 (c), since the integrated value of the output power 26 of the single-phase inverter 4 for half a cycle is positive, the DC capacitor 5 of the single-phase inverter 4 requires an external power supply. In FIG. 7 (c), the pulse width of the main voltage pulse 21a is expanded, and in this case, the negative output power 26 of the single-phase inverter 4 increases, and the half-cycle power integrated value becomes zero.

In this embodiment, the pulse width of the main voltage pulse 21a is determined so that the integrated power value of the half cycle or one cycle of the single-phase inverter 4 becomes 0. Since the power balance of each single-phase inverter 4 is controlled to be 0 for half cycle or one cycle, the DC capacitor 5 of each single-phase inverter 4 can have a simple configuration without a DC power supply that receives and receives power from the outside. ..

Embodiment 3. In the first and second embodiments, the pulse width of the main voltage pulse 21a is determined so that the power balance of the single-phase inverter 4 for half cycle or one cycle becomes 0. In this embodiment, the pulse width of the main voltage pulse 21a is finely adjusted. In this case, each voltage detector 32 (see FIG. 10) is provided to measure the voltage of each DC capacitor 5 of each single-phase inverter 4. First, as in the above embodiments 1 and 2, the pulse width of the main voltage pulse 21a is determined so that the power balance of the single-phase inverter 4 for half cycle or one cycle becomes 0, and the three-phase inverter circuit 1 is output. Control. In this output control, if the power balance of the single-phase inverter 4 is out of balance due to some cause, for example, a sudden change in the input DC voltage or a sudden change in the load 7, the voltage of the DC capacitor 5 of the single-phase inverter 4 fluctuates.

Each voltage detector 32 detects the voltage of each DC capacitor 5 of each single-phase inverter 4, and the detected voltage value of each DC capacitor 5 is transmitted to the output control device 13. In the output controller 13, when the voltage value of the DC capacitor 5 is larger than the preset reference value, the pulse width of the main voltage pulse 21a of the corresponding phase is shortened, and when it is larger than the reference value, the pulse width is set. The three-phase three-level inverter 3 is controlled so that the voltage value of the DC capacitor 5 approaches the reference value by lengthening the length.

As described in the second embodiment, the power integration value of the single-phase inverter 4 for half cycle or one cycle increases when the pulse width of the main voltage pulse 21a is shortened, and increases when the pulse width of the main voltage pulse 21a is increased. Reduce. Therefore, when the voltage value of the DC capacitor 5 is larger than the reference value, the power integrated value of the single-phase inverter 4 is increased by shortening the pulse width of the main voltage pulse 21a of the corresponding phase, and the DC capacitor 5 Reduce the voltage. When the voltage value of the DC capacitor 5 is smaller than the reference value, the voltage of the DC capacitor 5 is reduced by increasing the pulse width of the main voltage pulse 21a of the corresponding phase to reduce the integrated power value of the single-phase inverter 4. To increase.

By adjusting the pulse width of the main voltage pulse 21a output by the three-phase three-level inverter 3 in this way, feedback control is performed so that the voltage of the DC capacitor 5 of each single-phase inverter 4 becomes a reference value. As a result, the power balance of each single-phase inverter 4 for half cycle or one cycle can be reliably controlled to 0. Therefore, it is possible to prevent insufficient output voltage of the single-phase inverter 4, overcharging of the DC capacitor 5, and dielectric breakdown of the single-phase inverter 4 due to overcharging, and to obtain a three-phase inverter circuit 1 having a stable output. Can be done.

Embodiment 4. Next, the power conversion device according to the fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a diagram showing a configuration of a power conversion device according to a fourth embodiment of the present invention. In the three-phase inverter circuit 1 of this embodiment, a plurality of single-phase inverters 4 and 4a (two in this case) are connected in series to each phase AC output line of the three-phase three-level inverter 3. The two single-phase inverters 4 and 4a of each phase have the same configuration, and for convenience, the circuit configuration of only one single-phase inverter 4 is shown, and the others are omitted. The three-phase three-level inverter 3 and the single-phase inverters 4 and 4a are the three-phase three-level inverter control signal 14 and the single-phase inverter control output from the output control device 13a capable of performing calculations by the CPU, DSP, FPGA, and the like. It is driven and controlled by signals 15 and 15a. Other configurations are the same as those shown in FIG. 1 of the first embodiment.

Next, the operation will be described. Each phase of the three-phase three-level inverter 3 outputs a main voltage pulse 21a at a rate of one pulse in a half cycle with respect to the phase voltage command 20 as in the first embodiment. The main voltage pulse 21a is output after the pulse width is determined so that the power balance of the half cycle (or one cycle) of the single-phase inverter 4 becomes 0. Each of the single-phase inverters 4 and 4a outputs under high-frequency PWM control so as to compensate for the difference between the phase voltage command 20 required for the three-phase inverter circuit 1 and the output voltage of each phase of the three-phase three-level inverter 3. In this case, the sum of the output voltages of the two single-phase inverters 4 and 4a in each phase compensates for the difference between the phase voltage command 20 and the output voltage of each phase of the three-phase three-level inverter 3. Further, each of the single-phase inverters 4 and 4a is controlled so that the output current becomes a sine wave in this PWM control.

The output voltage of the two single-phase inverters 4 and 4a of each phase is superimposed on the output voltage of each phase of the three-phase three-level inverter 3, and the output voltage of the three-phase three-level inverter 3 and each single-phase inverter 4 and 4a The sum of the voltages with the output voltage of is output to the load 7 via the smoothing filter 6. FIG. 9 shows each phase output voltage of the three-phase inverter circuit 1, which is the sum of the output voltage of the three-phase three-level inverter 3 and the output voltages of the two single-phase inverters 4 and 4a. 23a shows the output voltage of each phase, and 24 shows the average voltage waveform of the output voltage 23 of each phase. In this case, the two single-phase inverters 4 and 4a connected in series output the switching timing by shifting the phase of the carrier wave by 180 °, for example. The output voltage waveform 24 of each phase to the load 7 has the same voltage waveform as the phase voltage command 20 of each phase as in the first embodiment, that is, the first series capacitor 10 and the second series capacitor 11 Based on the potential of the neutral point, which is the connection point with, each phase becomes a sine wave with the same peak value with a different phase of 2π / 3.

Also in this embodiment, as in the first embodiment, the neutral point potential is stable, the bus potential of the first DC power supply 2 does not fluctuate, and the output voltage control that obtains a desired voltage waveform is highly accurate. The total output voltage of the three phases becomes 0. Therefore, there is no AC component between the neutral potential of the three-phase output and one potential of the first DC power supply 2, and the zero-phase current flows through the floating capacitance 17 of the first DC power supply 2. Can be suppressed. In addition, since multiple single-phase inverters 4 and 4a (two in this case) are connected in series to each phase AC output line of the three-phase three-level inverter 3, the voltage output by each single-phase inverter 4 and 4a is reduced. It can reduce switching loss. Further, by increasing the number of single-phase inverters 4 and 4a in series, the frequency of the carrier wave may be lowered, and the switching loss is further reduced.

Of the two single-phase inverters 4 and 4a connected in series, one single-phase inverter 4 outputs a few pulses or less in a half cycle, and only the other single-phase inverter 4a outputs with high-frequency PWM control. May be good. At this time, the DC voltage of the single-phase inverter 4a controlled by PWM may be lower than the DC voltage of the single-phase inverter 4.

Embodiment 5. Next, the power conversion device according to the fifth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a diagram showing a configuration of a power conversion device according to a fifth embodiment of the present invention. In this embodiment, a voltage detector 30 provided in parallel to measure the voltage of the first series capacitor 10 and a voltage detector provided in parallel to measure the voltage of the second series capacitor 11. A device 31 and each voltage detector 32 provided for measuring the voltage of each DC capacitor 5 of each single-phase inverter 4 are provided. The voltage values 30a to 32a detected by these voltage detectors 30 to 32 are transmitted to the output control device 13, and the output control device 13 is a three-phase three-level inverter based on the detected voltage values 30a to 32a. Control 3 and each single-phase inverter 4. Other configurations are the same as those shown in FIG. 1 of the first embodiment.

In the first embodiment, the three-phase three-level inverter 3 outputs only one pulse main voltage pulse 21a in a half cycle, but in the fifth embodiment, the three-phase three-level inverter 3 operates differently. do. 11 to 14 are diagrams showing voltage waveforms for explaining the operation of the three-phase inverter circuit 1 according to the fifth embodiment. The potential of the waveform is a potential based on the neutral point, which is the connection point between the first series capacitor 10 and the second series capacitor 11. 11 and 12 show comparative examples, and FIGS. 13 and 14 are voltage waveforms of the three-phase inverter circuit 1 according to the fifth embodiment.

If the same operation as in the first embodiment is performed, the phase voltage command 20 (each phase output voltage waveform 24) of the three-phase inverter circuit 1 and the voltage waveform output by each phase of the three-phase three-level inverter 3 (three). The phase 3-level inverter voltage 21) is shown in Fig. 11. The voltage of the main voltage pulse 21a output to the positive side of the phase voltage command 20 is the voltage value 30a of the first series capacitor 10, and the voltage of the main voltage pulse 21a output to the negative side of the phase voltage command 20 ( (Absolute value) is the voltage value 31a of the second series capacitor 11. In this case, the case where the voltage of the first DC power supply 2 is higher than the normal case shown in FIG. 2 and the voltage values 30a and 31a of the first and second series capacitors 10 and 11 are higher is shown. There is. As described above, the pulse width of the main voltage pulse 21a is determined so that the power balance of the single-phase inverter 4 for half cycle or one cycle becomes 0, so that the DC input voltage of the three-phase three-level inverter 3 is large. Then, as shown in the figure, the pulse width becomes shorter.

When each phase of the three-phase three-level inverter 3 outputs the three-phase three-level inverter voltage 21 as shown in FIG. 11, the output voltage command of the single-phase inverter 4 (single-phase inverter voltage command 22) is shown in FIG. Shown. This single-phase inverter voltage command 22 is obtained by subtracting the three-phase three-level inverter voltage 21 from the phase voltage command 20 of the three-phase inverter circuit 1. The single-phase inverter 4 needs to generate a difference voltage between the phase voltage command 20 of the three-phase inverter circuit 1 and the three-phase three-level inverter voltage 21, and this difference voltage is the first and second series capacitors 10. , 11 When the voltage values 30a and 31a increase and the pulse width of the main voltage pulse 21a becomes shorter, it increases. Therefore, as shown in the figure, a voltage 36 exceeding the output voltage limit value 35 of the single-phase inverter 4 is required during the period near the rising portion and the falling portion of the main voltage pulse 21a. The magnitude of the output voltage limit value 35 is the voltage value 32a of the DC capacitor 5 of the single-phase inverter 4.

FIG. 13 is a diagram showing an output voltage command (single-phase inverter voltage command 37) of the single-phase inverter 4 according to this embodiment, and FIG. 14 is a diagram showing each phase of the three-phase three-level inverter 3 according to this embodiment. The output voltage waveform (three-phase three-level inverter voltage) is shown. Since the single-phase inverter 4 cannot output a voltage 36 exceeding the output voltage limit value 35 as shown in FIG. 12, during the period when a voltage 36 exceeding the output voltage limit value 35 is required, as shown in FIG. The shortage of the output voltage of the single-phase inverter 4 is borne by the three-phase three-level inverter 3. That is, during the period near the rising portion and the falling portion of the main voltage pulse 21a, the three-phase three-level inverter 3 outputs the partial PWM voltage 38, which is the voltage controlled by PWM, and the output voltage of the single-phase inverter 4. Then, the insufficient voltage is output.

The partial PWM voltage 38 is output according to the voltage values 30a and 31a of the first and second series capacitors 10 and 11 and the voltage value 32a of the DC capacitor 5. That is, the voltage of the first and second series capacitors 10 and 11 is not so high, or the voltage of the DC capacitor 5 is sufficiently high, so that the main voltage pulse 21a of the three-phase three-level inverter 3 and the output of the single-phase inverter 4 are output. When a sinusoidal voltage waveform can be obtained only by combining with a voltage, the same control as in the first embodiment is adopted, and if necessary, the control is switched to a control that outputs a partial PWM voltage 38.

As described above, in this embodiment, the partial PWM voltage 38 is in the vicinity of the rising portion and the falling portion of the main voltage pulse 21a in which each phase of the three-phase three-level inverter 3 outputs one pulse in a half cycle. Can be output. Therefore, even if the voltage of the first DC power supply 2 increases and the voltages of the first and second series capacitors 10 and 11 increase, a sinusoidal voltage waveform similar to that of the phase voltage command 20 can be obtained. Therefore, the neutral point potential becomes stable, the bus potential of the first DC power supply 2 does not fluctuate, and a desired voltage waveform can be obtained more stably and with high accuracy. Therefore, the suppression of the zero-phase current flowing through the stray capacitance 17 of the first DC power supply 2 can be stably and surely realized.

In the above embodiment, the period during which the three-phase three-level inverter 3 outputs the partial PWM voltage 38 is the period during which the single-phase inverter 4 is required to have a voltage 36 exceeding the output voltage limit value 35. Is controlled as follows with a margin. That is, the absolute value of the difference voltage between the phase voltage command 20 (each phase output voltage waveform) and the three-phase three-level inverter voltage 21 consisting of only the main voltage pulse 21a is subtracted from the voltage value 32a of the DC capacitor 5. The partial PWM voltage 38 is output during the period when the value is equal to or less than the predetermined value. As a result, the difference voltage between the phase voltage command 20 (each phase output voltage waveform) and the three-phase three-level inverter voltage 21 consisting only of the main voltage pulse 21a can be reliably output from the single-phase inverter 4, and the phase voltage command A sine wave voltage waveform similar to 20 can be obtained.

Further, also in this embodiment, the pulse width and portion of the main voltage pulse 21a output by the three-phase three-level inverter 3 so that the output power balance of each half cycle or one cycle of the single-phase inverter becomes 0. The output period of the PWM voltage 38 is controlled.

Further, similarly to the third embodiment, even if the voltage output period of the three-phase three-level inverter 3 is finely adjusted and feedback control is performed so that the voltage of the DC capacitor 5 of each single-phase inverter 4 becomes a reference value. good. In this case, the voltage output period of the three-phase three-level inverter 3 consists of the pulse width of the main voltage pulse 21a and the output period of the partial PWM voltage 38, and when the voltage value of the DC capacitor 5 is larger than the reference value, it is three-phase. Shorten the voltage output period of the corresponding phase of the 3-level inverter 3, and lengthen the voltage output period when it is larger than the reference value. As a result, even if the power balance of each single-phase inverter 4 deviates from 0 in the half cycle or one cycle when switching between the control of only the main voltage pulse 21a and the control of generating the partial PWM voltage 38, etc. Can be controlled to return to 0. Therefore, it is possible to prevent insufficient output voltage of the single-phase inverter 4, overcharging of the DC capacitor 5, and dielectric breakdown of the single-phase inverter 4 due to overcharging, and to obtain a three-phase inverter circuit 1 having a stable output. Can be done.

Embodiment 6. Next, the power conversion device according to the sixth embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a diagram showing a configuration of a power conversion device according to a sixth embodiment of the present invention. In this embodiment, the three-phase inverter circuit 1 is provided with a booster circuit 40 that boosts the voltage of the first DC power supply 2, and the output voltage of the booster circuit 40 is the DC input voltage of the three-phase three-level inverter 3. The booster circuit 40 includes, for example, a reactor 41, a switch 42 connected between the high-voltage side bus and the low-voltage bus of the first DC power supply 2, and a first and second series capacitor through which a one-way current flows. It is composed of a diode 43 that charges 10 and 11. Other configurations are the same as the configuration shown in FIG. 10 of the above-described fifth embodiment, and the three-phase three-level inverter 3 and each single-phase inverter 4 are controlled in the same manner as the above-described fifth embodiment.

When the first DC power source 2 is a power source that uses natural energy such as a solar cell, the output voltage always changes due to changes in weather or the like. With solar cells, the output voltage drops in the morning and evening when it is cloudy. The outputable AC voltage of the three-phase three-level inverter 3 is determined by the voltage value 30a of the first series capacitor 10 and the voltage value 31a of the second series capacitor 11, which are the bus voltage values of the three-phase three-level inverter 3. .. FIG. 16 is a diagram showing the relationship between the voltage of the first DC power supply 2 and the pulse width of the main voltage pulse 21a output by the three-phase three-level inverter 3. The output voltage to load 7 was set to three-phase, 200 Vrms. As shown in FIG. 16, when the first DC power supply voltage is lower than 256.51V, the booster circuit 40 boosts the voltage to 256.51V. When the first DC power supply voltage becomes 256.51V or more, the pulse width of the main voltage pulse 21a is shortened, and when it becomes 362.7V or more, the control is switched to output the partial PWM voltage 38.

In this embodiment, the voltage value 30a of the first series capacitor 10 and the second series are used as the DC input voltage of the three-phase three-level inverter 3 by boosting the voltage of the first DC power supply 2 by the booster circuit 40. The voltage value 31a of the capacitor 11 was increased to a voltage at which the desired AC voltage could be output. Therefore, the waveform output of the three-phase inverter circuit 1 becomes possible from a low voltage of the first DC power supply 2, and the operable range of the three-phase inverter circuit 1 is expanded.

In this embodiment, the control shown in the fifth embodiment is used, but each of the first to fourth embodiments may be applied.

Embodiment 7. Next, the power conversion device according to the seventh embodiment of the present invention will be described with reference to FIG. As shown in FIG. 17, a capacitor 44 having a capacitance equal to or greater than the amount of charge output by the three-phase inverter circuit 1 is connected in series between each phase output of the three-phase inverter circuit 1 and the load 7. The low voltage side of the output terminal of the first DC power supply 2 is grounded at the grounding point 45. Other configurations are the same as those shown in FIG. 1 of the above-described first embodiment, but may be applied to each of the other above-mentioned embodiments.

When the first DC power supply 2 is grounded, the output voltage of each phase of the three-phase inverter circuit 1 is half the voltage of the first DC power supply 2 or the voltage value of the second series capacitor 11. Is output as a neutral point potential, so a waveform added by the DC voltage is output. In this embodiment, since the capacitors 44 are provided in each phase, these capacitors 44 cut the DC component and output only the AC component to the load 7. Since the DC voltage component output to the load 7 is cut off in this way, it can be output to the system that becomes the load 7 and connected to the system.

Embodiment 8. Next, the power conversion device according to the eighth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 18, an isolation transformer 46 capable of insulation is arranged between the three-phase inverter circuit 1 and the load 7, and the low-voltage side of the output terminal of the first DC power supply 2 is grounded at the grounding point 45. Will be done. The isolation transformer 46 may have a general step-up function based on the number of turns. In this case, since the zero-phase current path is cut off by the isolation transformer 46, the zero-phase current does not flow. When the first DC power supply 2 is grounded, the output voltage of each phase of the three-phase inverter circuit 1 is half the voltage of the first DC power supply 2 or the voltage value of the second series capacitor 11. Is output as a neutral point potential, so a waveform added by the DC voltage is output. In this embodiment, since the isolation transformer 46 is provided, the DC component is cut by the isolation transformer 46, and only the AC component is output to the load 7. Since the DC voltage component output to the load 7 is cut off in this way, it can be output to the system that becomes the load 7 and connected to the system. Further, when the voltage is boosted by the isolation transformer 46, a high AC voltage can be output.