Power amplifier employing thin film ferroelectric phase shift element
9 claims: 4 independent, 5 dependent
- 1入力信号を受信し、少なくとも第1および第2分割信号を生成するように動作可能な信号スプリッタと、 前記第1分割信号を受信し、第1増幅信号を生成するよう機能する第1増幅器と、 前記第2分割信号を受信し、第2増幅信号を生成するよう機能する第2増幅器と、 前記第1増幅信号および前記第2増幅信号の和である出力信号を生成するよう機能する結合回路と、 前記第1および第2増幅器の1つの信号路に配置された位相制御回路であって、前記位相制御回路によって提供される位相シフトの量が、それに印加される制御信号の関数として選択的に可変であり、少なくとも1つの薄膜強誘電性素子を含む位相制御回路とを含み、 前記制御信号が前記入力信号の周波数の 実質的に線形な 関数である、増幅器。
- 2前記位相制御回路が前記第1増幅器の出力に連結されている、請求項1に記載の増幅器。
- 3前記位相制御回路が前記第1増幅器の信号路に配置され、前記増幅器がさらに、前記第2増幅器の信号路に配置された第2位相制御回路を含み、前記第2位相制御回路によって提供される位相シフトの量が、それに印加される第2制御信号の関数として選択的に可変であり、前記第2位相制御回路が少なくとも1つの薄膜強誘電性素子を含む、請求項1に記載の増幅器。
- 4前記入力信号の少なくとも一部を受信し、前記入力信号の周波数を表す検出器信号を生成するよう機能する周波数検出器回路をさらに備え、前記制御信号が前記検出器信号の関数である、請求項1に記載の増幅器。
- 5前記出力信号を受信し、前記出力信号と比較して所望量だけ位相がシフトされた位相シフト出力信号を生成する機能する第2位相制御回路をさらに含む、請求項1に記載の増幅器。
- 6前記出力信号を受信し、前記出力信号と比較して所望量だけ位相がシフトされた位相シフト出力信号を生成するよう機能する第2位相制御回路をさらに備え、前記出力信号の位相シフトの量が、それに印加される第2制御信号の関数として選択的に可変であり、前記第2位相制御回路が少なくとも1つの薄膜強誘電性素子を含む、請求項1に記載の増幅器。
- 7前記少なくとも1つの位相制御回路が、 前記位相制御回路の入力ノードと第1ノードの間に直列に接続された第1インダクタと、 前記第1ノードと共通ノードの間に接続された第1コンデンサと、 前記第1コンデンサと並列に接続された第1可変コンデンサと、 前記第1ノードと第2ノードの間に接続された第2インダクタと、 前記第2ノードと前記共通ノードの間に接続された第2可変コンデンサと、 前記第2可変コンデンサと並列に接続された第2コンデンサと、 前記第2ノードと出力ノードの間に接続された第3インダクタを含む、請求項1に記載の増幅器。
- 8前記信号スプリッタが、前記入力信号が印加される前記電力増幅器の入力部と第1ノードとの間に接続された第1相互接続素子、前記第1ノードと前記第1分割信号が生成される第2ノードとの間に接続された第2相互接続素子、および前記第1ノードと前記第2分割信号が生成される第3ノードとの間に接続された第3相互接続素子を含む、請求項1に記載の増幅器。
- 9少なくとも1つの増幅器を含む集積回路であって、前記少なくとも1つの増幅器が 入力信号を受信し、少なくとも第1および第2分割信号を生成するように動作可能な信号スプリッタと、 前記第1分割信号を受信し、第1増幅信号を生成するよう機能する第1増幅器と、 前記第2分割信号を受信し、第2増幅信号を生成するよう機能する第2増幅器と、 前記第1増幅信号および前記第2増幅信号の和である出力信号を生成するよう機能する結合回路と、 前記第1および第2増幅器の1つの信号路に配置された位相制御回路であって、前記位相制御回路によって提供される位相シフトの量が、それに印加される制御信号の関数として選択的に可変であり、少なくとも1つの薄膜強誘電性素子を含む位相制御回路とを含み、 前記制御信号が前記入力信号の周波数の 実質的に線形な 関数である、集積回路。
Independent claims9
26 paragraphs, as filed
The present invention relates to amplifiers as a whole, and more particularly to techniques for extending the useful frequency range of power amplifiers without significantly reducing the linearity and / or efficiency of the amplifiers.
Due to the increasing importance of spectral efficiency in wireless communication systems, the linearity and efficiency of radio frequency (RF) power amplifiers is often required to support higher data capacities and higher data transmission rates, especially composite digital. It has become an important design issue for implementing modulation schemes. Linearity can be improved by well-known linearization techniques such as feedforward linearization, but this improvement comes at the expense of reduced amplifier efficiency.
Doherty amplifiers, well known in the art, have been shown to achieve higher efficiency than traditional power amplifier designs. A standard Doherty amplifier 100 is shown in Figure 1. As is clear from the figure, the standard Doherty amplifier 100 consists of a carrier amplifier 102 and a peak amplifier 104, which are normally biased to class A and class C, respectively. The quadrature 3-decibel (dB) hybrid circuit 106 can be employed to split the input signal applied to the Doherty amplifier 100 equally to both the carrier and peak amplifiers, but 90 degrees out of phase. The amplified output signals generated by the carrier and peak amplifiers 102, 104 are homeomorphically coupled at the quarter wavelength transformer 108 output coupled to the output of the carrier amplifier.
The operation of the Doherty amplifier can be divided into two main parts. In the first region, the input power is less than the threshold of the peak amplifier 104, so only the carrier amplifier 102 is connected to the output of the Doherty amplifier 100 with the efficiency originally determined by class A operation.<sub>L</sub>Supply output power to. When the input signal further increases to a level just below the saturation point of the carrier amplifier 102, the peak amplifier 104 operates and the operation of the second region begins. With the connection of the quarter wavelength transformer 108, the power supplied by the peak amplifier 104 effectively reduces the apparent load impedance seen by the carrier amplifier 102. This reduction in impedance allows the carrier amplifier 102 to supply more power to the output load 110 while keeping its voltage saturated. In this way, the carrier amplifier 102, and thus the entire Doherty amplifier 100, is maintained with high efficiency throughout the second region until the peak amplifier 104 reaches its saturation threshold.
Doherty amplifiers can generally achieve higher efficiencies than traditional power amplifier designs, but this increased efficiency comes at the expense of reduced linearity. This is because, at least in part, Doherty amplifiers typically employ fixed wire length and / or phase shift elements to achieve proper fading between the two signal paths. These fixed line lengths have associated static phase characteristics that change non-linearly with frequency. This reduced linearity severely limits the bandwidth of conventional Doherty amplifiers.<nplcit num="1"><text>B. Acikel et al., High Performans Phase Shifters Using (Ba, Sr) TiO3 Thin Films NNUN Abstracts 2002 / Electronics, p. 39</text></nplcit>
<p> Therefore, there is a need for a power amplifier with a wider operating frequency range compared to conventional power amplifiers, which does not suffer from one or more of the problems presented by conventional power amplifiers.</p>
<p> The present invention is a technique for beneficially extending the effective frequency range of a power amplifier by using one or more thin film ferroelectric phase shift elements in at least one signal path of the amplifier in an exemplary embodiment. I will provide a. The use of thin film ferroelectric materials is very linear compared to conventional phase control elements, and in addition the point at which phase conversion occurs in the power amplifier can be adjusted, which allows the linearity and / or of the power amplifier. It provides an extended effective frequency range without a significant reduction in efficiency.</p><p> According to one aspect of the invention, the amplifier receives an input signal and operates to generate at least first and second split signals, and receives a first received signal and produces a first amplified signal. It includes a first amplifier designed to do so and a second amplifier designed to receive a second split signal and generate a second amplified signal. The coupling circuit is adapted to generate an output signal that is the sum of the first amplified signal and the second amplified signal. The amplifier further includes a phase control circuit located in one signal path of the first and second amplifiers, which phase control circuit comprises at least one thin film ferroelectric element. The amount of phase shift provided by the phase control circuit is selectively variable as a function of the control signal applied to it.</p><p> These and other features and advantages of the present invention will become apparent from the following detailed description of embodiments for the purposes of the present invention that should be read in connection with the accompanying drawings.</p>
The present invention is described herein in the context of, for example, a Doherty amplifier circuit for illustration purposes that can be used in power amplifier applications. However, it should be understood that the present invention is not limited to the particular amplifier architecture shown and the techniques of the present invention are not limited to any particular application. Rather, the present invention can be applied globally to extend the frequency range of a power amplifier without significantly reducing the linearity and / or efficiency of the amplifier. Here, the term "linearity" as used herein can be defined as a correspondence between an input signal and an output signal such that the output signal is substantially independent of the input signal level. The frequency range of this power amplifier utilizes a phase control circuit with one or more thin film ferroelectric elements to selectively control the phase shift of one or more signal paths of the power amplifier. Can be expanded. As used herein, the term "amplifier" essentially refers to a circuit for multiplying an input signal applied to a circuit by a given gain greater than or equal to one.
FIG. 2 is a circuit diagram showing a Doherty amplifier 200 in which the technique of the present invention can be carried out. The Doherty amplifier 200 includes a splitter 206 for splitting the input signal IN given to the Doherty amplifier into two signals, and the first and second amplifiers 202 and 204, respectively. The divided signals are provided to the inputs 202 and 204 of the first and second amplifiers by transmission lines 214 and 216, respectively. The first amplifier 202 is biased to class A operation and the second amplifier 204 is biased to class C operation. The Doherty amplifier 200 further includes a first fixed phase shift element 210 connected to the output of the first amplifier 202 for shifting the phase of the first amplified signal generated by the first amplifier by a predetermined amount. The phase shift signal generated by the phase shift element 210 in the first signal path is then summed by the combiner 208 with the second amplified signal generated by the second amplifier 204 in the second signal path. The coupled signal generated by the combiner 208 can be passed through a second fixed phase shift element 212 to adjust the phase and / or impedance matching of the output signal OUT of the Doherty amplifier 200 if desired.
As mentioned above, standard Doherty amplifiers employ fixed phase shift elements (eg 210, 212) to achieve proper fading between the two signal paths. These fixed phase shift devices have associated static phase characteristics that change non-linearly with frequency. The reduced linearity of the phase shift element severely limits the bandwidth of the Doherty amplifier. Therefore, the Doherty amplifier shown in FIG. 2 has a phase control circuit in at least one of the signal paths in order to selectively control the amount of phase shift in the signal path in response to the control signal, as described below. Is preferably modified according to the embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an exemplary power amplifier 300 in which the technique of the invention can be practiced, according to an embodiment for the description of the invention. An exemplary power amplifier 300 includes a signal splitter 302 that produces at least two signals from the input signal IN given to the power amplifier, and at least two amplifiers 308 and 310 that can operate in different modes. The split signal is provided as an input to each of the two amplifiers 308, 310 coupled via transmission lines 304 and 306 to the signal splitter 302, respectively. The power amplifier 300 configured as a Doherty amplifier preferably biases the first amplifier 308 to class A operation and the second amplifier 310 to class C operation. The present invention also contemplates alternative amplifier architectures such as, but not limited to, balanced amplifier configurations in which such bias configurations can be modified as desired. For example, in a balanced amplifier configuration, both the first and second amplifiers 308, 310 are preferably biased towards class A operation.
The power amplifier 300 is provided by the first amplifier as the output from the second amplifier 310 begins to contribute to the power amplifier output as the first amplifier 308 approaches the maximum output it can create (eg, just before saturation). It is preferably configured to supplement the power provided by the power amplifier, thereby expanding the range of input power to which the power amplifier supplies output power. In addition, the power supplied by the second amplifier 310 effectively reduces the apparent load impedance seen by the first amplifier 308. This reduction in impedance allows the first amplifier 308 to supply more power to the output section, which improves the efficiency of the first amplifier.
To facilitate the integration of silicon chips, the signal splitter 302 can include three interconnect elements such as resistors R1, R2 and R3 connected in a Y configuration as shown, for example. A signal splitter is preferred, but other common-mode power split configurations suitable for use with the present invention are also conceivable. Assuming the resistors R1, R2 and R3 have the same value, the input signal IN is split equally between the two amplifiers 308, 310. In order to minimize the loss of the signal passing through the signal splitter 302, the resistors R1, R2 and R3 can be replaced with a substantially zero ohm device, such as in a direct connection configuration. These zero ohm devices can be made, for example, from metal or polysilicon interconnect layers. Alternatively, the signal splitter 302 may be configured to shift at least one phase of the split signal by a selected amount, for example 90 degrees, as in the case of the orthogonal 3 dB hybrid circuit 106 shown in FIG. it can.
The exemplary power amplifier 300 further includes a first phase control circuit 312 coupled to the output of the first amplifier 308. The first phase control circuit 312 can operate to selectively change the phase of the output signal generated by the first amplifier 308 in response to the control signal VCNTRL applied to the first phase control circuit. preferable. The coupling circuit 314 sums the phase shift signal generated by the first phase control circuit 312 with the output signal generated by the second amplifier 310. The output signal generated by the coupling circuit 314 may optionally pass through the second phase control circuit 316 in order to selectively change the phase of the output signal OUT generated by the power amplifier 300 if desired. it can. This may be useful, for example, to provide frequency rejection, impedance conversion (eg, impedance matching), etc. to extend the maximum useful frequency range of the power amplifier 300.
To facilitate the integration of silicon chips, the coupling circuit 314, such as the signal splitter 302, can include three resistors R4, R5 and R6 connected in a Y configuration as shown. A phase signal coupler is preferred, but other in-phase coupled circuit configurations suitable for use with the present invention are also conceivable. Assuming the resistors R4, R5 and R6 have the same value, the signals from the two signal paths are equally summed. Instead, the coupling circuit 314 may be configured to sum the signals in non-uniform proportions. Further, the coupling circuit 314 shifts at least one phase of the signal by a selected amount, for example 90 degrees, as in the case of the quarter wavelength transformer 108 shown in FIG. Can also be configured.
According to one aspect of the present invention, the phase control circuit 312,<u style="single">316</u>Each of these preferably comprises at least one thin film ferroelectric element for selectively changing the phase of the input signal given to the phase control circuit. In a preferred embodiment of the invention, the thin film ferroelectric element comprises a barium titanate strontium (BST) capacitor, but as is known to those skilled in the art, alternative thin film ferroelectric materials (eg, lead zirconate titanate). , Bismus strontium tantanate, etc.) can be adopted in the same manner. By applying a bias, the capacitance value of the BST capacitor can be adjusted and thus the phase characteristics of the phase control circuit can be changed. BST thin films can be highly non-linear, such as standard adjustable devices such as varicaps and pin diodes (eg, the disclosure of which is incorporated herein by reference, such as B. Acikel, ". High Performance Phase Shifters Using (Ba, Sr) TiO<sub>3</sub> Compared to Thin Films , NNUN Abstracts 2002 / Electronics, page 39), it is more adjustable, has relatively low losses, and has faster switching speeds, making it particularly suitable for use in phase control circuits. In addition, BST thin films are very insensitive to RF power fluctuations and are useful for use in power amplifier applications.
The exemplary power amplifier 300 preferably includes a frequency detector 318. The frequency detector 318 is adapted to receive at least a portion of the input signal IN and generate a frequency dependent signal VC representing the frequency of the input signal. In an exemplary embodiment of the invention, the frequency detector 318 comprises a resistor R7 connected to node N1 at the first end and receiving at least a portion of the input signal IN at the second end. The capacitor C1 is preferably connected between the node N1 and the ground. The frequency detector 318 further includes a diode D1 having an anode connected to node N1 and a cathode connected to node N2. The resistor R8 is preferably connected between node N2 and the ground. The frequency-dependent signal VC is generated at node N2.
The operation of the frequency detector 318 is described here as a mere example and without loss of wholeness. The RF signal is taken out from the input of the power amplifier 300, such as through the coupling element 320 of the signal splitter 302. The RF signal passes through a resistor-capacitor (RC) lowpass filter consisting of resistor R7 and capacitor C1. This circuit configuration is essentially a type of frequency discriminator in which low frequencies are passed to node N1 with low loss and high frequencies are passed with greater loss. These different levels of RF signal at node N1 pass through the frequency detector diode D1 to produce a rectified DC current. The rectified DC current flows through resistor R8 to produce an output voltage at node 2, which is a function of the frequency of the input signal. DC return current due to coupling element 320 path) can be provided. If a coupling element that does not provide a DC return path is used, a resistor or inductor (not shown) can be added in parallel with capacitor C1. It will be appreciated that the present invention is not limited to the illustrated frequency detectors. Rather, as will be apparent to those skilled in the art, alternative circuits for generating frequency dependent signals can be similarly employed in the exemplary power amplifier 300.
With reference to FIG. 4, the frequency-dependent signal VC is preferably supplied to the explanatory processing circuit 400 for generating the control signal VCNTRL, which is a function of the input signal frequency. As a mere example, the processing circuit 400 can include an operational amplifier 402 configured as a non-inverting amplifier. In this example, the control signal VCNTRL generated by the processing circuit 400 is related to the frequency-dependent signal VC according to the relationship of VCNTRL = K · VC. However, the gain K of the non-inverting amplifier is equal to 1+ (R1 / R2). It should be appreciated that the present invention is not limited to circuit configurations for any particular gain and / or processing circuit 400, and various other circuit configurations (eg, inverting amplifiers, etc.) can be considered as well.
Seeing FIG. 3 again, if the second phase control circuit 316 is used, this is not a requirement of the power amplifier 300, but the second phase control to receive the same control signal VCNTRL as the first phase control circuit 312. It is preferable to configure the circuit 316. The first and second phase control circuits are used for different purposes, the first phase control circuit 312 is used to control the phase of the signals generated in the first signal path for the purpose of summing, and the second The phase control circuit 316 is used to control the phase of the output signal OUT for the purpose of impedance matching. Therefore, the amount of phase shift produced by each of the first and second phase control circuits need not be the same. An additional processing circuit (not shown) can be included in the power amplifier 300 to generate a second control signal for independently controlling the phase shift of the second phase control circuit 316. The second control signal may be a function having a different frequency of the input signal IN as compared with the control signal VCNTRL.
FIG. 5 is a circuit diagram showing an exemplary phase control circuit 500 for illustration, formed according to an embodiment of the present invention. An exemplary phase control circuit 500 can be employed to implement the first and / or second phase control circuits 312, 316 of the power amplifier 300 shown in FIG. The exemplary phase control circuit 500 includes a first inductor L1 connected in series between the input node IN and the first node N1 and a ground-connectable first capacitor C1 connected between the node N1 and the common node. To be equipped. The first variable capacitor CBST1 is preferably connected in parallel with the capacitor C1. The phase control circuit 500 further includes a second inductor L2 connected between the node N1 and the second node N2. The second variable capacitor CBST2 is preferably connected between the node N2 and the common node. The second capacitor C2 is connected in parallel with the second variable capacitor CBST2, and the third inductor L3 is connected between the node N2 and the output node OUT. The two variable capacitors CBST1 and CBST2 are preferably composed of a BST thin film having a capacitance value that can be selectively changed as a function of the control signal VCNTRL, or an alternative ferroelectric thin film material, respectively.
As shown in the exemplary graph display shown in FIG. 6, the relationship 602 between the frequency dependent voltage VC and the frequency F of the input signal is preferably substantially linear over at least the desired range of input frequencies. By using a ferroelectric thin film device in the (various) phase control circuits, the relationship 602 is substantially between the amount φ of the phase shift generated by the (various) phase control circuits and the control signal VCNTRL applied to it. Is preferably translated into a linear relationship 604.
The techniques of the present invention can be employed to provide power amplifiers with a wider operating frequency range without significant reductions in efficiency and / or linearity as compared to conventional power amplifier configurations. It should be understood that the present invention is not limited to the particular power amplifier architecture shown. For example, the exemplary power amplifier 300 shown in FIG. 3 includes a phase control circuit 312 in the first signal path, but can also include an additional phase circuit (not shown) in the second signal path. The amount of phase shift produced by the additional phase control circuit is different from the amount of phase shift produced by the phase control circuit 312. As will be apparent to those skilled in the art, alternative power amplifier configurations according to the present invention are similarly conceivable.
At least a portion of the power amplifier of the present invention can be implemented in an integrated circuit. In forming an integrated circuit, a plurality of identical dies are usually formed on the surface of a semiconductor wafer in an iterative pattern. Each die includes the devices described herein and may include other structures or circuits. The individual dies are cut or diced from the wafer and then packaged as an integrated circuit. Those skilled in the art will know how to dice wafers and package dies to make integrated circuits. The integrated circuit manufactured in this way is considered to be a part of the present invention.
Although embodiments for explaining the present invention have been described herein with reference to the accompanying drawings, the invention is not limited to these exact embodiments and deviates from the scope and spirit of the invention. It will be appreciated that various other modifications and modifications can be made to embodiments of the invention by those skilled in the art without doing so.
<figref num="1">It is a circuit diagram which shows the conventional Doherty amplifier.</figref><figref num="2">It is a circuit diagram which shows the Doherty amplifier which adopted the fixed phase shift circuit.</figref><figref num="3">FIG. 6 is a circuit diagram illustrating an exemplary power amplifier, formed according to an embodiment for the description of the present invention.</figref><figref num="4">FIG. 5 is a circuit diagram illustrating an exemplary phase control signal generator circuit suitable for use with the power amplifier shown in FIG. 3 according to an embodiment of the present invention.</figref><figref num="5">FIG. 5 is a circuit diagram illustrating at least a portion of an exemplary phase control circuit suitable for use with the power amplifier shown in FIG. 3 according to an embodiment of the present invention.</figref><figref num="6">FIG. 5 is a graph showing an exemplary voltage-to-frequency response and an exemplary phase-to-control voltage response for the circuits shown in FIGS. 4 and 5.</figref>
6 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US9918806B2 | Cited by | United States of America | Applicant |
| US9776912B2 | Cited by | United States of America | Applicant |
| US9321674B2 | Cited by | United States of America | Applicant |
| US10358380B2 | Cited by | United States of America | Applicant |
| US9757311B2 | Cited by | United States of America | Applicant |
| JP2001196870A | Cites | Japan | – |
| JP2004173231A | Cites | Japan | – |
| JP03195134A | Cites | Japan | – |
| JP05037255A | Cites | Japan | – |
| US05014023A | Cites | United States of America | – |
| JP03071711A | Cites | Japan | – |
| JP2005295412A | Cites | Japan | – |
| JP2000101345A | Cites | Japan | – |
| JP2003526313A | Cites | Japan | – |
| JP05251965A | Cites | Japan | – |
| JP2002124840A | Cites | Japan | – |
| WO2003065494A1 | Cites | World Intellectual Property Organization (WIPO) | – |
6 members in 3 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 11025088 | United States of America | – | |
| 2508804 | United States of America | A | |
| 2508804 | United States of America | A | |
| 2004025088 | – | – | – |
| US20040025088 | – | – | – |
Members6
| Document | Office | Kind | |
|---|---|---|---|
| US2006139091A1 | United States of America | A1 | |
| KR20060076246A | Republic of Korea | A | |
| JP2006191581A | Japan | A | |
| US7248108B2 | United States of America | B2 | |
| KR101156285B1 | Republic of Korea | B1 | |
| JP5094017B2This record | Japan | B2 |
25 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Written notification of registration of transferJAPANESE INTERMEDIATE CODE: R350R350 | R350 | |
| Request for change of ownership or part of ownershipJAPANESE INTERMEDIATE CODE: R313113S111 | S111 | |
| Transfer withdrawnWithdrawnJAPANESE INTERMEDIATE CODE: R371R371 | R371 | |
| Request for change of ownership or part of ownershipJAPANESE INTERMEDIATE CODE: R313113S111 | S111 | |
| Transfer withdrawnWithdrawnJAPANESE INTERMEDIATE CODE: R371R371 | R371 | |
| Written notification of registration of transferJAPANESE INTERMEDIATE CODE: R350R350 | R350 | |
| Request for change of ownership or part of ownershipJAPANESE INTERMEDIATE CODE: R313113S111 | S111 | |
| Written request for registration of change of nameJAPANESE INTERMEDIATE CODE: R313533S533 | S533 | |
| Cancellation because of no payment of annual feesLAPS | LAPS | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Decision of grant or rejection writtenTRDD | TRDD | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Written permission of extension of timeJAPANESE INTERMEDIATE CODE: A602A602 | A602 | |
| Written request for extension of timeJAPANESE INTERMEDIATE CODE: A601A601 | A601 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Written permission of extension of timeJAPANESE INTERMEDIATE CODE: A602A602 | A602 | |
| Written request for extension of timeJAPANESE INTERMEDIATE CODE: A601A601 | A601 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Report on retrievalJAPANESE INTERMEDIATE CODE: A971007A977 | A977 | |
| Written request for application examinationJAPANESE INTERMEDIATE CODE: A621A621 | A621 |
Numbers
- Publication
- 5094017
- Publication, DOCDB
- 5094017
- Publication, EPODOC
- JP5094017B
- Application
- 371534
- Application, DOCDB
- 2005371534
- Application, EPODOC
- JP20050371534
Titles2
- Japanese
- 薄膜強誘電性位相シフト素子を採用した電力増幅器
- English
- Power amplifier with thin film ferroelectric phase shift element
Classification
- CPC, 5
- H03F1/0288
- H03F1/07
- H03F3/211
- H03F3/602
- H03F2200/423
- IPC, 6
- H03F1 07
- H03F1 42
- H03F3 60
- H03F3 68
- H03H7 20
- H01G4 33
