Low voltage diode with reduced parasitic resistance and method for fabricating

The present invention relates to diodes and, in particular, to diodes exhibiting low on-state forward voltage and small parasitic resistance.

A diode is an electronic component that limits the direction of movement of charge carriers. Diodes essentially allow current to flow in one direction, but effectively prevent it from flowing in the opposite direction.

Diode rectifiers are one of the most widely used devices in low voltage switching, power supply and power converter applications and related applications. For efficient operation, such diodes have a low on-state voltage (0.1 to 0.4 V or less, forward voltage drop V)._f), Low reverse leakage current, 20-30V voltage blocking capability and high switching speeds are desirable. These features are important to achieve the ultimate goal of low voltage rectifiers, high conversion efficiency.

The most common diodes are based on semiconductor pn junctions in which impurity elements have been introduced to change the operating characteristics of the diodes in a controlled manner, and silicon (Si) is commonly used for this semiconductor pn junction. The diode can also be formed from other semiconductor materials such as gallium arsenide (GaAs) and silicon carbide (SiC). In a pn diode, a defined current can flow from the p-type side (anode) to the n-type side (cathode), but not in the opposite direction.

The current-voltage, or IV characteristic curve, of a semiconductor diode is based on the depletion layer or zone present at the pn junction between different semiconductor layers. When the pn junction is first formed, the conduction band (movable) electrons in the n-type doped region (n-type doped region) diffuse into the p-type doped region (p-type doped region). There is a large group of holes (electron positions where no electrons are present), and the electrons can "rebond" with those holes. When the movable electron recombines with the hole, the hole disappears and the electron no longer moves. That is, two charge carriers are removed. The area around the pn junction loses charge carriers and therefore behaves as an insulator.

However, the width of the depletion zone does not grow endlessly. Each time a recombination produces an electron-hole pair, a positively charged dopant ion is left in the n-type doped region and a negatively charged dopant ion is left in the p-type doped region. As the recombination progresses and more ions are produced, an increasingly large electric field develops in the depletion zone, which acts to slow down the recombination and eventually stop the recombination. At this point, a "built-in" potential is created between the ends of the depletion zone.

When an external voltage with the same polarity as the built-in potential is applied between the terminals of the diode, the depletion zone continues to function as an insulator, preventing significant current from flowing. This is the reverse bias phenomenon. However, if the polarity of the external voltage is opposite to the built-in potential, the recombination can proceed again and a significant amount of current will flow through the pn junction. For silicon diodes, this built-in potential is about 0.6V. Therefore, when an external current is flowing through the diode, a voltage of about 0.6V appears between the terminals of the diode, which makes the p-type doping region positive with respect to the n-type doping region. When having a forward bias, the diode is said to be "turned on".

The IV characteristics of a diode can be approximated by two operating regions. When the potential difference between two leads attached to a diode is less than a certain potential difference, the depletion layer has a considerable width and this diode can be thought of as an open (non-conductive) circuit. Increasing this potential difference makes the diode conductive at some point, allowing charge to flow. At this time, the diode can be regarded as a circuit component having zero resistance (or at least very small). With a normal silicon diode, at rated current, the voltage drop between the terminals of the conducting diode is about 0.6 to 0.7 volts.

In the reverse bias region of a typical pn rectifier diode, the current through the device is very small (in the μA range) for all reverse voltages up to a point called peak reverse voltage (PIV). Beyond this point, a process called reverse yield occurs, which damages the device and accompanies a significant increase in current.

One drawback of junction diodes is that during forward conductivity, the diode's power loss can be excessive for large current flows. Schottky barrier diodes, other types of diodes, utilize a rectifying metal-semiconductor barrier instead of a pn junction. The junction between the metal and the semiconductor establishes a barrier region that improves the switching performance of the diode by minimizing the charge accumulation effect and shortening its turn-off time when properly manufactured (Non-Patent Document 1). ..

Typical Schottky diodes have a lower forward voltage drop than pn junction diodes, so applications where the energy loss of the diode has a significant negative impact on system performance, such as diode switching. Desirable over pn junction diodes in applications used as power output rectifiers. For such applications, it is highly desirable to provide the rectifier with very low forward voltage drop (0.1-0.4V), small reverse leakage current, low voltage blocking capability (20-30V), and high switching speed. .. These features are important to achieve the ultimate goal of high conversion efficiencies for rectifiers used for low voltages.

Schottky diodes can be used as low-loss rectifiers, but their reverse leakage current is generally much higher than in other rectifier designs. Schottky diodes are multi-carrier devices and therefore do not have the problem of minority carrier accumulation that slows down most of the usual diodes. Schottky diodes also tend to have much lower junction capacitance than pn diodes, which contributes to the higher switching speeds of Schottky diodes.

One way to lower the on-state voltage of a conventional Schottky diode below 0.5V is to lower the surface barrier potential of the diode. However, lowering the barrier potential creates a trade-off of increased reverse leakage current. In addition, low barrier potentials can reduce operation at high temperatures and provide soft yielding characteristics under reverse bias operation.

Furthermore, for Schottky diodes made from GaAs, one drawback of this material is that the Fermi level (or surface potential) is fixed at about 0.7 volts (Si Schottky diodes also have some of this limitation). ). As a result, the on-state forward voltage (V)_f) Is fixed. Regardless of the type of metal used to contact the semiconductor, lower the surface potential of such diodes to V_fCannot be reduced.

One solution to this limitation of GaAs is the gallium nitride (GaN) material system. GaN has a wide direct bandgap of 3.4 eV and a high electron velocity (2 x 10).⁷cm / s), high dielectric breakdown field (2 x 10)⁶V / cm), and has heterostructure availability. GaN-based low-voltage diodes can achieve a smaller forward voltage drop compared to traditional Schottky diode rectifiers (eg, as described herein by reference in their entirety). See Patent Document 1, which is incorporated and assigned to a common assignee).

However, GaN low voltage diodes can generally be manufactured on SiC or GaN substrates. For vertical diode devices, the substrate is in the conductive path and contributes to the voltage drop. The general resistivity value of a SiC / GaN substrate is about 20 to 30 mohm-cm, and for a substrate with a thickness of 200 μm, 100 A / cm.²A voltage drop of 40 to 60 mV is added at the operating current density of. This additional voltage drop is unacceptable because the target for the total voltage drop at operating current is less than 200 mV. In addition, for the most commonly used SiC substrates (GaN substrates are expensive and have a small diameter), there are additional barriers at the GaN epi-SiC substrate interface. There are techniques used to mitigate this barrier, but they can also add extra complexity and contribute to increased resistance.

Therefore, there is a need in the art for diodes that can operate with a lower forward voltage drop.

<patcit num="1"><text>U.S. Patent Application No. 10/445130, Parikh et al., Gallium Nitride Based Diodes with Low Forward voltage and Low Reverse Current Operation, filed May 20, 2003.</text></patcit><patcit num="2"><text>U.S. Pat. No. Re.34861</text></patcit><patcit num="3"><text>U.S. Pat. No. 4,946547</text></patcit><patcit num="4"><text>U.S. Pat. No. 5200022</text></patcit><nplcit num="1"><text>LP Hunter, Physics of Semiconductor Materials, Devices, and Circuits, Semiconductor Devices, Page 1-10 (1970)</text></nplcit>

<p> The present invention provides a semiconductor diode structure and a method of manufacturing the same, which significantly reduces the parasitic resistance of the diode and eliminates the associated resistance voltage drop.</p>

<p> The method for manufacturing a diode includes a step of attaching an n + semi-conductive buffer layer on a substrate, a step of attaching an n-semi-conductive layer on the n + layer, and a semi-conductive barrier layer on the n-layer. It includes a step of adhering and a step of adhering a dielectric layer on the barrier layer. A portion of the dielectric layer is then removed and a Schottky metal is attached onto the barrier layer in the cavity left by the removed portion of the dielectric layer. The dielectric layer and Schottky metal are attached to the conductive support layer by a metal bonding layer, the substrate is removed to expose the n + layer, and the n +, n- and barrier layer parts are selectively removed to make the dielectric. A mesa-shaped diode structure covering the Schottky metal is formed on the layer, and ohmic contact is attached on the n + layer.</p><p> The second method of manufacturing a diode is to deposit a Schottky metal on the barrier layer and then remove the selected parts of the n + and n- layers to form a mesa-shaped diode structure under the Schottky metal. It is the same as the first method except that the substrate under the diode structure is removed to form a via and ohmic contacts are attached to the surface of the n + layer in the via.</p><p> A third method of manufacturing diodes is to thin the GaN substrate to reduce parasitic substrate resistance after the substrate is a GaN substrate and the selected parts of the n + and n- layers are removed to form a mesa diode structure. However, it is the same as the second method except that ohmic contacts are attached to the surface of this thinned substrate.</p><p> In a more specific embodiment, the n +, n- and barrier layers contain Group III nitrides. The nucleation layer may be attached onto the substrate prior to the step of attaching the n + layer onto the substrate. The nucleation layer is Al_xGa_1-xCan be N, where the n + layer is an n + doped GaN layer, specifically 5 × 10.¹⁷/cm³From 5x10¹⁹/cm³It can be a GaN layer with a thickness of 0.5 to 5 μm doped so as to have the impurity concentration of.</p><p> The n-layer is an n-doped GaN layer, specifically 1x10.¹⁵/cm³From 1x10¹⁷/cm³It can be a GaN layer with a thickness of 0.5 to 5 μm doped so as to have the impurity concentration of. The barrier layer is an AlGaN layer, specifically Al containing 30% Al._xGa_1-xIt can be N layers (15 x 45). The thickness of the barrier layer can be 0 to 30 Å, specifically 5 Å. Dielectric layer is SiO₂It can be a dielectric layer. The Schottky metal can be selected from the group consisting of Cr, Ge, Fe, Mn, Nb, Ni, NiCr, Sn, Ta, Ti and W, and is preferably Cr.</p><p> The conductive support layer can be metal-coated Si, and the dielectric layer can be attached to the support layer by the metal bonding layer using the Au-Sn eutectic wafer bonding process. Ohmic contact materials can be selected from the group consisting of Al / Au and Ti / Au, or can be other suitable ohmic contacts for the n + GaN layer. The step of removing the substrate and exposing the n + layer can be performed using reactive ion etching. After the dielectric layer is attached to the support layer by the metal bonding layer, the back surface bonding layer can be attached to the support layer on the opposite side of the dielectric layer.</p>

The present invention is used in applications such as high efficiency power supplies, as well as other applications such as low voltage switching power supplies, power converters, etc., with very low forward voltage (V)._f) Provide a rectifying diode having a value.

One embodiment of the method according to the invention provides whole wafer bonding of a gallium nitride device on a surface-processed SiC substrate to a metal-coated carrier wafer. The SiC substrate is removed and ohmic contacts are placed directly on the n + GaN epitaxial layer. It eliminates the GaN-SiC interface barrier / resistance path as well as the SiC substrate resistance path. This helps to minimize or reduce the resistive parasitic voltage drop.

When an element such as a layer, region or substrate is described as being "above" another element, it is understood that the element may be directly on that other element or may have intervening elements. I want to be. Further, in the present specification, "inner", "outer", "upper", "upper", "lower", "lower", "lower", etc. are used to describe the relationship between one layer or another. Relative words may be used. It should be understood that these terms are intended to cover different directions of the device, not just the directions shown in the figure.

In the present specification, an embodiment of the present invention will be described with reference to a sectional view which is a schematic view of an idealized embodiment of the present invention. Thus, variations from the shape of the figure are expected, for example as a result of manufacturing techniques and / or tolerances. The embodiments of the present invention should not be construed as being limited to a particular shape of the region shown herein, and embodiments of the present invention include, for example, deviations in shape due to manufacture. Represented as squares or rectangles, the areas described generally have curled or curved features due to normal manufacturing tolerances. Therefore, the areas shown in the figures are substantially schematic and their shapes are not intended to indicate the exact shape of the area of the device and also limit the scope of the invention. Not even intended to be.

FIG. 1 shows an embodiment of a Schottky diode 100 constructed according to the present invention, which diode can be manufactured from many different material systems. For ease of description and understanding, the diode 100 is shown as a single device, but as will be described later, multiple diodes 100 are generally manufactured at the wafer level, then a single piece from the wafer to the individual device. Is made. Thousands of devices are typically manufactured from a single wafer-level process.

The preferred diode 100 is manufactured using a Group III nitride-based material system. Group III nitrides include Group III elements of the Periodic Table, usually aluminum (Al), gallium (Ga) and semiconductor compounds formed between indium (In) and nitrogen. This group also includes ternary and tertiary compounds such as AlGaN and AlInGaN. Preferred materials for this diode are GaN and AlGaN.

The diode 100 includes a conductive substrate 102, which can be made from a variety of materials, preferably metal-coated silicon (Si) that acts as a conductive support layer for the device. The metal bonding layer 104 connects the support layer 102 to the Schottky metal layer 106. A semi-conductive AlGaN barrier layer 108 is arranged on the Schottky layer on the opposite side of the bonding layer, and an n-semi-conductive GaN layer 110 is arranged on the barrier layer. An n + semi-conductive GaN buffer layer 112 is arranged on this n-layer. Finally, on the layer 112, an ohmic contact 114 is placed that provides an electrical connection to the diode through the layer 112.

One method of manufacturing the diode shown in FIG. 1 is shown in FIGS. 2 to 10. Although this method is described herein for a single device, it should be understood that this method is equally applicable to multiple devices manufactured at the wafer level. Although this method is described for certain materials with a particular composition, it should be understood that different materials with different compositions can be used.

As shown in FIG. 2, this method uses Al on substrate 118._xGa_1-xStarting with the attachment of the N nucleation layer 116, the nucleation layer 116 is preferably an AlN composition (ie x = 1). Various materials for the substrate 118, such as silicon, sapphire, and silicon carbide, can be used for the substrate. However, the substrate 118 is preferably silicon carbide (SiC), which has a crystal lattice alignment much closer to the Group III nitride than sapphire and adheres a higher quality Group III nitride film. SiC substrates are available from Cree Reserach, Inc., Inc. (Durham, NC, USA), and methods for producing them are described in scientific literature, as well as, for example, Patent Documents 2-4.

Next, as shown in FIG. 3, an n + semi-conductive buffer layer 112 is attached onto the nucleation layer 116. This buffer layer is 5x10¹⁷/cm³From 5x10¹⁹/cm³It is preferably a GaN layer having a thickness of 0.5 to 5 μm doped so as to have the impurity concentration of.

In FIG. 4, the n-semi-conductive layer 110 is attached onto the buffer layer 112. Layer 110 is 1x10¹⁵/cm³From 1x10¹⁷/cm³It is preferably formed from 0.5 to 5 μm thick GaN doped to have the impurity concentration of.

As shown in FIG. 5, on the n-layer 110, Al_xGa_1-xN Semi-conductive barrier layer 108 is attached. The barrier layer 108 preferably has a thickness of 5 Å and a composition in the range of 15 x 45. These n +, n- and barrier layers can be adhered by adhesion techniques known in the field of semiconductor manufacturing technology, including, for example, metalorganic chemical vapor deposition (MOCVD).

Next, SiO on the barrier layer 108, as shown in FIG.₂A dielectric layer 120 is attached, and then, as shown in FIG. 7, a part of the dielectric layer is removed, and a Schottky metal 106 is placed in a cavity remaining after removing a part of the dielectric layer, and a barrier layer. Adhere to make electrical contact with 108. Standard metallization techniques known in the field of semiconductor manufacturing technology can be used to form Schottky metals, preferably Cr, but other metals are used to reduce the height of the barrier. Also preferred materials are Cr, Fe, Mn, Nb, Ni, NiCr, Sn, Ta, Ti, Ge and W. Schottky metals with different work functions give different barrier potentials. Cr is V_fProvides an acceptable barrier potential for a diode of about 0.2V and can be easily adhered by conventional methods.

Metals have low Schottky barrier potential and low V_fMust be selected to provide, but Schottky barrier potential and V_fMust be high enough to keep the reverse current low. If the selected metal has a work function equal to, for example, the electron affinity of the semiconductor, the barrier potential (except for tunnel diodes) approaches zero, resulting in V._fWill approach zero and increase the diode's reverse current, which will effectively make the diode ohmic and will not provide rectification.

The dielectric layer 120 is used as a protective layer and can be selectively removed at various points in the process. Alternatively, the Schottky metal can be attached as a complete layer and later etched to define the Schottky barrier contacts.

As shown in FIG. 8, at this point the structure is turned over and its dielectric layer / Schottky metal is transferred to a Si conductive support layer 102 metal-coated with a metal bonding layer 104, preferably Au-Sn. Join using a eutectic wafer joining process. This bonding layer is a thick metal that exhibits a higher coefficient of thermal expansion than Si. Therefore, when the bonded wafer cools after the bonding process, this difference in thermal expansion can cause tensile stress in the bonding layer. If the substrate 118 is removed later as described below, the tensile stress in the junction layer can cause the support layer 102 and the remaining layers to bend. This distortion of these layers is undesirable for subsequent manufacturing steps, especially those involving photolithography.

The effect of this tensile stress can be ameliorated by adding an optional back bonding layer 122 to the back surface of the layer 104 (this back bonding layer allows the back bonding layer to adhere only to the support layer 102 and the bonding tool. Must be contacted by a non-metallic surface during the joining process) to ensure that it does not adhere to. With this additional bonding layer, tensile stress is introduced into both bonding layers during cooling. The stress in the back bonding layer cancels the stress introduced by the bonding layer 102 and minimizes bending of the substrate 118 after removal.

Next, as shown in FIG. 9, the SiC substrate 118 and the nucleation layer 116 are thinned and removed. Various removal methods based on the present invention can be used. In one embodiment, most of the SiC substrate is removed by grinding, leaving only a thin layer (eg 10-30 microns). This thin layer can be removed by reactive ion etching or other dry etching such as inductively coupled plasma etching (ICP).

Then, as shown in FIG. 10, the selected parts of n +, n- and the barrier layer are removed and SiO is removed.₂A mesa-shaped diode structure covering the Schottky metal 106 is formed on the dielectric layer 120. This removal can be achieved by several etching techniques known in the field of semiconductor manufacturing technology, including, for example, chemical etching, reactive ion etching (RIE) and ion mill etching. Finally, an ohmic contact 114 is attached onto the n + layer 112 to complete the diode.

1x10 by the above method¹⁸/cm³2 μm thick n + layer and 1 × 10¹⁶/cm³1 μm thick n-layer doped with aluminum and an approximate composition of Al_0.3Ga_0.7A low voltage diode with a thin barrier layer of 5 Å, which is N, was manufactured. Al / Au Ohmic contact was used. Standard dicing techniques were performed to obtain individual devices.

Forward voltage V on the horizontal axis_fForward current I on the vertical axis with respect to (V)_f(A / cm²), Figure 11 and Table 1 below show the performance demonstrated by these devices.

<tables num="1"><img file="JP5011069B2_D0001.tif" /></tables>

This diode structure exhibits a very small parasitic resistance. Besides giving low Vf, these diodes are 100A / cm²It can operate at higher current densities, thus improving capacitance per unit amperage. Since the total metal thickness of ohmic contacts was less than 0.5 μm, these devices began to show the effect of current spread at the 1A level. Metal thickening, which makes the ohmic metal thicker than 2 μm, should remedy this problem. Due to the low intrinsic barriers of these devices, these devices, 200 A / cm²It can be operated with a high forward current of the above, thereby gaining the advantage of capacitance.

These devices were then implemented using standard Ag-Sn-based die bonding techniques. The result of the mounted diode is shown in Fig. 12. FIG. 12 shows the forward voltage (V) on the horizontal axis as in FIG._f) On the vertical axis forward current (I)_f) Is a plot.

The diode of the present invention can also be manufactured in an alternative embodiment. Instead of removing the substrate completely, for example, the substrate can be etched with a via to remove the material under the active device and the rest of the substrate material can be maintained for mechanical support. A diode 200 manufactured according to this second embodiment is shown in FIG. 13, similar to FIG. The diode 200 is manufactured in a manner similar to the process described with respect to FIGS. 2-7. The nucleation layer 216 is attached onto the SiC substrate 218, and then the n + semi-conductive buffer layer 212 is attached onto the nucleation layer. The n-semi-conductive layer 210 is attached on the buffer layer 212, and the semi-conductive barrier layer 208 is attached on the n-layer 210. A Schottky metal layer 206 is attached onto the barrier layer 208.

The n +, n- and selected portions of the buffer layer are then removed to form a mesa-shaped diode structure beneath the Schottky metal. Finally, the lower part of the mesa-shaped diode structure of the substrate 218 and the nucleation layer 216 is removed to form a via, and then the ohmic contact layer 214 is electrically placed on the surface of the substrate and in the via with the n + layer 212. Attach to connect to.

A third embodiment of the diode can be implemented on a bulk GaN wafer, which is subsequently thinned to reduce parasitic substrate resistance. Since there is no heterostructure epi-board interface as in the case of GaN diodes manufactured on SiC substrates, it is not necessary to completely remove the bulk GaN wafer. The reduction of substrate parasitism other than the elimination of this interfacial voltage drop is a function of the degree of thinning of the GaN substrate wafer.

This third embodiment is shown as a diode 300, as shown in FIG. 14, which is also similar to FIG. This embodiment, like the second embodiment, is manufactured using a process similar to the process described in connection with FIGS. 2-7. A nucleation layer 316 is attached onto the GaN substrate 318, and then an n + semi-conductive buffer layer 312 is attached onto the nucleation layer. The n-semi-conductive layer 310 is attached on the buffer layer 312, and the semi-conductive barrier layer 308 is attached on the n-layer 310. A Schottky metal layer 306 is attached onto the barrier layer 308.

The n +, n- and selected portions of the buffer layer are then removed to form a mesa-shaped diode structure beneath the Schottky metal. The GaN substrate 318 is thinned enough to reduce the parasitic resistance associated with the substrate, and then the ohmic contact layer 314 is attached to the surface of the substrate.

Preferred embodiments of the present invention have been shown and described. However, those skilled in the art will undoubtedly see changes and additional embodiments. Further, instead of the described elements, equivalent elements can be used, the parts or connections can be reversed, or interchanged in other ways, and some features of the invention are with other features. Can be used independently. Therefore, these exemplary embodiments are for illustration purposes only and should not be considered inclusive, and the appended claims indicate the full scope of the invention.

<figref num="1">It is sectional drawing of one Embodiment of the diode constructed according to this invention.</figref><figref num="2">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="3">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="4">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="5">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="6">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="7">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="8">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="9">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="10">It is sectional drawing which shows one step of the process of manufacturing a diode based on this invention.</figref><figref num="11">It is a graph which shows the measured performance of the diode constructed according to this invention.</figref><figref num="12">It is a graph which shows the measured performance of the diode constructed according to this invention.</figref><figref num="13">FIG. 5 is a cross-sectional view similar to FIG. 1 showing an alternative embodiment of a diode constructed according to the present invention.</figref><figref num="14">FIG. 3 is a cross-sectional view similar to FIG. 1 showing another alternative embodiment of a diode constructed according to the present invention.</figref>