A method of dynamically adjusting the power of a transmitter in response to the bit error rate of a training sequence.

The present invention relates to high-speed links, and more particularly to power saving related to high-speed links.

As computers have evolved, they have moved from the realm of simple computing to media centers for a large number of media and non-media related applications. As a result, computer systems often have a large number of peripheral and / or input / output devices. In addition, advances in semiconductor processing and computer design have allowed computer systems to have more transistors and processing power in a single physical processor, while many in a single system. It has also become possible for a physical processor to exist.

As a result of advances in integrated circuits and their processing power, interconnects between devices have also evolved to provide sufficient bandwidth for high-performance components. As a particular example, components in the architecture may be combined using point-to-point links.

However, transmitters on these links are often designed to operate at power levels that meet the highest values in the specification guidelines. For example, there may be a specification for a physical link, i.e. a transmission line between a transmitter and a receiver, which defines both length and other attributes. As a result, transmitters often operate at high power levels that ensure correct data transmission over the longest transmission line, even if the actual link / transmission line is shorter than the specified maximum. As a result, extra power may be consumed to ensure accurate data transmission compared to the power used for data transmission of the same accuracy.

The present invention is illustrated by the accompanying drawings, but is not intended to be limited.

<figref num="1">An embodiment of a system including a plurality of processors coupled to a chipset utilizing a point-to-point interconnect and other possible interconnects coupled to the chipset is shown.</figref>

<figref num="2">An embodiment of a block diagram of a bidirectional interconnect architecture using a layered interconnect stack is shown.</figref>

<figref num="3">An embodiment of a flowchart of a method of determining the optimum transmitter amplitude based on the error rate is shown.</figref>

<figref num="4">An embodiment of an example training stage for determining the operating amplitude of the transmitter is shown.</figref>

In the following description, in order to provide a complete understanding of the present invention, for example, specific interconnects, specific sigma values, specific signal amplitudes and their scaling factors, specific types, numbers, and test pattern sizes are described. be written. However, those skilled in the art will appreciate that these particular details are not always required to carry out the present invention. In other examples, well-known components or methods such as specific transmitter and receiver logic, checksums, and bit error rate detection algorithms, other behavioral details of the interconnect, and related logic. , To avoid unnecessarily obscuring the present invention, no detailed description will be given.

The methods and devices described herein are intended to adjust the amplitude of the transmitter to optimize power consumption. In particular, adjusting the power of the transmitter will be mainly described by taking links such as the point-to-point coherent interconnect architecture as an example. However, the methods and devices for adjusting the power of the transmitter are not limited to being implemented by known interconnects such as any of the interconnects as shown in FIG. It may be implemented by any other known interconnect utilized in.

FIG. 1 shows an embodiment of a system having a plurality of different interconnects. The system in Figure 1 also has several processors, of which only two processors 105 and 110 are shown for clarity. As shown in the figure, the processors 105 and 110 have two processing units 106 and 107, 111 and 112, respectively, but the processors 105 and 110 may have any number of processing units.

A processing unit is a thread unit, processing unit, context, logical processor, hardware thread, core, and / or any other component that holds the state of the processor, such as the running or structural state. It is a member that can be made. In other words, the processing unit in one embodiment refers to any hardware that can be individually associated with code, such as software threads, operating systems, applications, or other code. As an example, a physical processor generally refers to an integrated circuit that can have any number of other processing units, such as cores or hardware threads.

A core often refers to logic placed in an integrated circuit that can maintain an independent structural state, each of which is maintained individually in at least some dedicated execution resource. Be associated. Hardware threads, sometimes referred to as physical threads, as opposed to cores, generally refer to any logic located in an integrated circuit that can maintain a separate structural state. Structural states maintained in share access to execution resources. Thus, as described above, a multi-software thread, such as a multi-replica of a single-threaded application in one embodiment, is parallel to the plurality of processing units, including any combination of the processing units, such as core or hardware threads. Can be executed.

As shown in the figure, processors 105, 110 generally have resources 108, 113 including registers, units, logic, firmware, memory and other resources that execute code or interface with other devices. As described above, some of the resources 108 and 113 may be partially or completely dedicated to the processing unit, and other resources may be shared between the processing units. For example, small resources such as instruction pointers and renaming logic may be replicated to physical threads. ILTB (instruction lookaside translation), a buffer for reordering / retirement equipment Some resources such as buffer), load / store buffers, and queues may be shared by partitioning. Other resources such as general-purpose internal registers, page table-based registers, low-level data caches, data TLBs, execution units, and fault units may be fully shared between threads. In contrast, the core may have its own resources to execute, while sharing at least part of a higher level cache, such as a second level cache (L2).

In one embodiment, resources 108, 113 have a processor pipeline that can include any number of pipeline stages. Common examples of pipeline stages are instruction pointer stage, fetch stage, decode stage, drive stage, allocation stage, rename stage, queue stage, reorder stage, schedule stage, dispatch stage, execution stage, memory access stage, And includes a register access stage. The stages listed here are typical of processor pipeline stages and are not exhaustive and any known pipeline stage may be included in processor 100.

Processors 105, 110 may also have a memory controller or local memory controller hub (MCH) that appropriately interfaces with memory 109, 114. Memories 109, 114 include any memory device such as RAM (random access memory), cache memory, flash memory, or other memory device. In one embodiment, memory 114 includes a higher level cache memory and resource 113 includes a lower level cache memory. In another embodiment, the memory 109 includes a DRAM (Dynamic Random Access Memory) associated with the processor 105, which has a cache memory for caching data from the DRAM 109. Note that this is an exemplary embodiment and memories 109, 114 may include any style of memory device.

In one embodiment, if the memories 109, 114 are included in any of the processors 105, 110, or have cache memory outside the processors 105, 110 as shown, the processors 105, 110 are peer cached. It can be a home node similar to a node. For example, if a transaction refers to a memory location in memory 109, the agent responsible for memory 109, ie processor 105, may be determined to be the home agent with respect to the transaction and memory location. Similarly, if a transaction references another memory location, such as its location in memory 114, processor 105 may be determined to be a peer cache agent.

As described above, the point-to-point links 120 to 124 connect the components to each other in a point-to-point manner. In one embodiment, the physical links 120-124 each have a bidirectional differential signaling interconnect, such as a physical link associated with the physical layer described below with reference to FIG. As a result, processors 105, 110, and chipset 130 can communicate directly with each other. The transmitter in one embodiment can adjust the power based on the error rate as described below. Further, the receiver in one embodiment can receive the pattern and determine if an error has occurred in the pattern. Here, the receiver can efficiently determine the optimum power setting of the transmitter by feeding back to the transmitter.

Chipset 130 generally refers to multiple integrated circuits, such as a memory controller hub coupled to an input / output (I / O) hub. However, in one embodiment, the chipset 130 refers to an I / O hub or other controller hub if the agent includes each version of a memory controller hub for interfacing with memory. In one embodiment, as described above, the chipset 130 is a non-cache agent that participates in or is involved in a transaction. However, the chipset 130 is not limited to this, and in other embodiments, the chipset 130 is a cache agent that includes cache memory and / or a home agent that includes memory that has an initial memory location repository of data.

As shown in the figure, the chipset 130 is a PCI (Peripheral Component Interconnect) or PCI-E (PCI Express) device 161, IDE (Integrated Device Electronics) or ATA (Advanced Transfer Attachment) device 162, USB (Universal Serial Bus). I / O devices as described herein, such as device 163, LAN (Local Area Network) or WLAN (wireless LAN) device 164, audio device 165, and other I / O devices 166. Interface multiple interconnects and I / O devices that may include other interconnect architectures for coupling. As described above, any of the above interconnects may have a transmitter and a receiver capable of determining the optimum power based on the error rate described below.

With reference to FIG. 2, an embodiment of a block diagram of a bidirectional interconnect architecture using a layered interconnect stack is shown. With reference to the layer of FIG. 2, such physical layer 202 includes a discussion of general layers that can be implemented within different agents such as physical layer 202a and physical layer 202b. As shown in the figure, the interconnect stack is divided into five layers, one or more of which may be optional depending on the embodiment of the design. For example, in one embodiment, the routing layer 204 is incorporated into the function of the link layer 203, and therefore, in one embodiment, the routing layer is not a separate and separate layer.

In one embodiment, the physical layer 202 serves to electrically transfer information in the physical medium. For example, a physical point-to-point link is used between the link layer entities 203a and 203b. As an example, the physical link takes a differential signaling scheme that includes bidirectional differential signaling pairs 251 and 252. Here, the physical layer may be logically divided into electrical and logical subblocks to isolate the rest of the stack from electrical transfer of information and communicate with link layer 203. It should be noted that the transmitters 250a, 250b in one embodiment are capable of adjusting the amplitude of the transmitted signal, thereby consuming their power based on the error rate as described below. ..

In one embodiment, link layer 203 abstracts physical layer 202 from the top of the stack, providing reliable data transfer and flow control between connected agents / entities, and multiple virtual channels and message classes for physical channels / interfaces. Provides link-related services such as virtualizing to. Here, the virtual channel may be viewed as multiple virtual networks used in the upper layers of the stack. For example, protocol layer 206 may map protocol messages to message classes depending on the extraction performed by link layer 203, resulting in one or more virtual channels.

In one embodiment, the routing layer 204 provides a flexible way of routing packets from source to destination. As mentioned above, in a very simple topology, the routing layer 204 does not have to be well separated, but rather may be integrated into the function of the link layer 203. For example, the routing layer 204 may route packets by designating a pair of &lt;spots, virtual networks&gt; depending on the extraction of the link layer 203.

In one embodiment, the routing layer 204, or the logic associated with the routing layer 204 and its functions, retains routing information such as a routing table. In certain examples, the routing table may contain entries for each goal in the interconnect architecture. In this case, the entry may hold any type of information, such as one or more ports routing packets associated with the target agent. The routing table and related information are described in more detail below.

In one embodiment, the transport layer 205 provides an end-to-end reliable transmission service. Like the routing layer 204, the transport layer 205 is optional based on design embodiments. For example, transport layer 205 relies on routing layer 204 services to provide reliable support for protocol layer 206. In one embodiment in the interconnect architecture, a subset of components includes transport layer 205. As a result, a subset of this component defines packet subfields for transport layer 205, while other components do not have to define those subfields.

In one embodiment, protocol layer 206 implements higher level communication protocols between nodes / agents such as cache coherence, ordering, peer-to-peer communication, interrupt delivery, and so on. In other words, protocol layer 206 appropriately specifies acceptable messages, requests, responses, phases, coherence states, etc. for nodes or agents such as home nodes, peer nodes, cache nodes, and non-cache nodes. Examples of messages such as home node messages, snoop messages, and response messages are described below.

Note that the layer discussion and the logic associated with it may be combined in any way. For example, protocol logic can be said to be combined with the physical layer, ie, transmit or receive logic. Here, as can be seen from FIG. 2, in one embodiment, the protocol logic may be coupled via the logic of another layer rather than being directly coupled with the physical layer logic. Further, in one embodiment, the interconnect stack initiates proper cache coherence operation by combining with internal component logic such as cache control or cache memory logic. It should also be noted that the description of the interconnect stack and bidirectional serial link is merely exemplary and the transmitters described below may be implemented in known interconnects.

With reference to FIG. 3, one embodiment of a block diagram of a method of adjusting the power of the transmitter based on the error rate by adjusting the amplitude is shown. At block 305, the transmitter transmits the pattern with one amplitude at the link. In one embodiment, the transmitter may have any transmission logic associated with an integrated circuit that transmits bits, symbols, and / or patterns. These bits, symbols, and patterns may be used interchangeably with each other in some embodiments. Often, the symbol refers to some representation of the number of bits, but in simple embodiments, the symbol may also refer to a signal logic value.

The transmitter may be located within any device or agent, such as within an interconnect agent / node that is coupled via an interconnect with another device, such as a receiving agent. Common examples of a pair of interconnect agents that can be either transmit or receive agents, depending on the transaction, are a processor and a memory controller hub, both processors, a root interconnect hub and an interconnect device, an I / O controller hub and an I / O. Includes O-devices, both I / O devices, or any other pair of agents / devices known to be coupled to each other via links or interconnects.

The link includes any known interconnect that couples the integrated circuits. For example, a link may physically be like a single transmission line or a combination of multiple transmission lines. Earlier link embodiments in materials such as FR4 included copper or other conductive material. Overall, the link may include a parallel multi-drop bus, a serial link / interconnect, a point-to-point link, a cache coherent link, other known interconnects, or a combination thereof. As mentioned above, a link or interconnect may be formed from multiple pairs of transmitters, such as multiple I / O circuits in one device coupled to multiple I / O circuits in other devices. Please note. In one embodiment, the individual transmitters may adjust the power / voltage separately. In other embodiments, the plurality of I / O circuits, including the transmitter, can be tuned to a single matching voltage.

In one embodiment, the amplitude at which a bit, pattern, or value is transmitted refers to the magnitude of the vibration of the wave. For example, bits, namely logics 0 and 1, are transmitted using different voltage levels that represent logic values. For illustrative purposes, high voltage levels above the threshold include logic 1 and low voltage levels below the threshold include logic 0.

As a result, in one embodiment, the amplitude refers to the differential voltage, i.e. the difference between the maximum and minimum target voltages. For example, if the maximum voltage is 800 mv, i.e. the target voltage of logic 1, then the minimum voltage is 200 mv, i.e. the target voltage of logic 0, and the differential voltage is 600 mv. In other words, the wave has an amplitude of 600 mv. It deviates slightly from the target voltage due to transmission line effects such as cross-coupling, impedance mismatch, and other factors, which are often referred to in terms such as undershoot, overshoot, and ringing. Therefore, as described above, since power is a function of voltage, the more voltage is used to transmit the wave pattern, the more power is consumed. Further, the differential voltage or amplitude correction may be made indirectly, such as by increasing / decreasing the operating voltage of the integrated circuit, and the generated wave has the corrected amplitude.

In one embodiment, the pattern transmitted by the transmitter comprises a normal interconnect value transmitted during normal operation of the transmitter or I / O circuit. Alternatively, in other embodiments, the pattern is initialized, tested, and / or during the training phase of the system, initialization, testing, and / or during the training phase of the integrated circuit / agent including the transmitter. Or, in particular, include test patterns during the initialization, testing, and / or training stages of the transmitter itself. Here, the test pattern is any such as a predetermined pattern, a random pattern, or any other known combination of bits, symbols, or patterns that applies pressure to the transmitter or initializes the transmitter. It may include a pattern. For example, in a USB (Universal Serial Bus) interconnect, the test pattern or message may include a complete scrambler output with zero plus single bit pattern input data.

In one embodiment, which will be described in more detail below, the pattern length is optimized to reduce the confidence level that determines the correct amplitude / differential voltage level and the training, testing, or initialization time. Provides a balance between doing. For example, gaining very high reliability at the differential voltage level of the transmitter means that in this example the receiver is 1/10.^-12Includes receiving multiples of bits to accurately identify the bit error rate (BER). In this case, 8^*(1/10^-12) Training sequences may provide 8 sigma confidence levels in mathematical distributions such as normal or Gaussian distributions. However, for example, 8x10^-121/10 like a bit^-12Bit multiples have very long patterns and can be too long to initialize or train the device in many systems.

In contrast, 8^*(1/10^-5) May be used to reduce the length of training, testing, and / or initialization. However, the length of the pattern as in this example provides a 4 sigma confidence level instead of an 8 sigma confidence level. Therefore, in one embodiment, the length of the pattern, i.e., the number of bits in the pattern, is selected to be associated with a high or different confidence level than the predetermined confidence level. Training is performed using a pattern associated with a low confidence level, and voltage / amplitude scaling is performed to obtain an approximate higher confidence level, as described below.

In one embodiment, the transmitter dynamically adjusts the amplitude of transmitting the signal based on the error rate associated with the pattern. One embodiment of such dynamic adjustment is shown in blocks 310-325. The decision block 310 determines whether the receiver receiving the pattern has detected an error. Any known error detection method / algorithm may be used. For example, Cyclic Redundancy Check (CRC) may be used to detect errors. CRC often captures an input data stream or bit pattern and outputs a value of a particular size. This output value is sent to the receiver and compared to the CRC generated by the receiver. This checksum allows the receiver to determine if a transmission error has occurred.

For example, if the amplitude or differential voltage is too low for the transmitted logic 1, the receiver may interpret the low value as logic 0 instead of the correct logic 1. If the receiver calculates a new CRC value, it indicates that an error has occurred during transmission, unlike the original CRC value. However, any known checksum, error detection code, verification, error detection mechanism, or a combination thereof may be used to detect errors in patterns generated by the transmitter and received by the receiver. Also, "any" error detection in block 310 may detect fewer errors than a predetermined number of errors.

If an error is detected, at block 315 the transmitter amplitude is stepped up or down or dynamically adjusted and the flow returns to block 305. Note that any initial amplitude may be used for raising / lowering / adjusting the signal in the transmitter, just as any interval of amplitude / voltage may be used. In one embodiment, the initial amplitude may be the minimum voltage differential that can be transmitted by the transmitter. In other embodiments, the initial amplitude may be the calculated minimum amplitude.

To provide an example, the specification for the interconnect provides the minimum transmission line length for the link, while the receiving agent exceeds it so that the signal is correctly interpreted by the receiver. Specifies noise or threshold specs. Here, the minimum amplitude may include the noise level represented by the attenuation calculated by the minimum length of the voltage plus channel / transmission line. In other words, the minimum voltage level through the attenuation of the shortest particular transmission line in the transmitter is decipherable by the receiver. To provide a numerical example, it is assumed that the receiver requires a differential voltage of 20 mv to interpret the wave and the shortest calculated channel length is approximately 80 mv attenuation. As a result, in this example, the minimum amplitude level may be set to 100 mv.

However, the use of the shortest channel length and receiver specs is just an example, and the designer of the I / O circuit, whether it is optional or calculated based on a large number of interconnect related variables. , Any initial voltage may be selected to perform the training sequence. Similarly, raising or lowering or adjusting the amplitude may be optional or calculated. For example, the designer may choose to step up and down the differential voltage of a minimum of 100mv to 10mv, 20mv, 50mv, 100mv, 200mv, etc., as well as step by step based on the percentage. When a 20% percentage is used, the first step rises from 100mv to 120mv and the second step rises from 120mv to 144mv.

Therefore, its stepwise elevation as an initial voltage differential may depend on the design, and more generally, the flow between blocks 305, 310, and 315 is until no errors are detected, or In other embodiments, it has been observed that block 310 can continue until the number of errors is less than a predetermined number. In one embodiment, if the pattern length is associated with a confidence level lower than a predetermined confidence level, such as a high confidence level, the amplitude determined in block 320 if no error is detected in determination block 310. Is scaled to give a higher level of confidence. In other words, the minimum voltage of the transmitter is determined during the shortened training, i.e. the shortened pattern length, in which case no error is received. However, the differential voltage is increased to buffer the confidence level associated with the shortened pattern length, thereby providing a buffer at that confidence level.

In one embodiment, the scaling at block 320 is based on the confidence level associated with the pattern length. Here, for example, the ratio or ratio of high or predetermined confidence levels to selected / low confidence levels associated with the shortened pattern length is used for scaling. Continuing, to provide a simplified numerical example, assume that block 305 starts with an initial voltage differential of 100 mV. However, the flow continues through blocks 305, 310, and 315, going up and down 50 mV each time with an amplitude of 200 mV until no errors are detected. Assuming that the shortened pattern length is associated with a 4-sigma confidence level in the Gaussian distribution and a predetermined high confidence level is associated with a 7-sigma confidence level, the amplitude scales by 7/4. That is, the amplitude is about 350 mV. Here, the newly scaled 350 mV amplitude at the transmitter provides a higher confidence level approximation of 7 sigma, while saving time during the training phase by utilizing shorter training patterns.

With reference to FIG. 4, an embodiment of a training sequence that adjusts the power of the transmitter to the optimum level is shown. Note that the training patterns shown are just examples and are very simplistic. However, here the transmitter transmits a pattern such as a training pattern with an initial amplitude such as 100 mV. The receiver detects the error as soon as it receives the pattern and, as a result, sends a message to the transmitter that the error has been detected. Depending on the error detected, the transmitter scales / raises / decreases the amplitude of the generated signal to a second amplitude, for example 150 mV.

Here, the same or different patterns may be transmitted with a second scaled amplitude. Similarly, an error is detected and the transmitter receives another error message from the receiver indicating that the error was detected during the training sequence. However, no error is detected at the next ascent / descent, that is, the third amplitude of 200 mV. Assuming the pattern length provides 4 sigma confidence levels in the Gaussian distribution and the target / predetermined confidence level is 7 sigma, the third amplitude is scaled by the ratio of confidence levels, i.e. 7/4. , Obtain an amplitude of 350 mV.

As a result, this scaled amplitude is used during normal operation in both block 325 in FIG. 3 and the example in FIG. As mentioned above, similar transmitter amplitude, voltage, and / or power adjustments may be made during normal operation with normal traffic rather than training sequences or random patterns. As a result, the operating transmitter in one embodiment dynamically adjusts its power consumption based on the error rate. Here, if the receiver begins to detect too many errors, the receiver sends an error signal to the transmitter, which scales the voltage accordingly.

Therefore, as described above, the transmitter may determine the optimum power setting based on the actual physical interconnect configuration instead of operating at high power, thereby ensuring compliance with the maximum interconnect specifications. In addition, short training patterns use long periods of time to save initialization time, but confidence level-based amplitude scaling provides adequate high confidence levels for error rate specifications. As a result, initialization time and power are saved without sacrificing transmission accuracy and its reliability.

Modules used herein refer to any hardware, software, firmware, or a combination thereof. The boundaries of the modules shown separately may often change and overlap. For example, the first and second modules may share hardware, software, firmware, or a combination thereof, but may retain some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic devices. However, in other embodiments, the logic also includes software or code that is integrated into the hardware, such as firmware or microcode.

Values used herein include known representations of numbers, states, logical states, or binary logical states. Logical levels, the use of logical values, are often indicated as "1" and "0", which represent just binary logical states. For example, 1 indicates a high logic level and 0 indicates a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, can hold a single logical value or multiple logical values. However, other representations of values in computer systems are also used. For example, the decimal number 10 may be represented as a binary value of 1010 and the hexadecimal character A. Therefore, a value of 1 includes any representation of information that can be held in a computer system.

In addition, the state may be represented by a value or part of a value. For example, a first value such as logic 1 may represent the default or initial state, and a second value such as logic 0 may represent the non-default state. Further, the terms reset and set in one embodiment refer to default and update states or values, respectively. For example, the default value may include a high logical value, i.e. a reset, and the update value may include a low logical value, i.e. a set. Note that any combination of values may be used to indicate the number of states.

The above methods, hardware, software, firmware or code embodiments may be implemented by instructions or codes stored on a machine-accessible or machine-readable medium that can be executed by a processor. Machine-accessible / readable media includes any mechanism that provides (ie, stores and / or transmits) information in a machine-readable form, such as a computer or electronic system. For example, machine-accessible media include RAM (random access memory) such as SRAM (static RAM) or DRAM (dynamic RAM), ROM, magnetic or optical storage media, flash memory devices, electrical storage devices, optical storage devices, acoustics. Includes storage devices, or storage devices in other forms of propagated signals (carriers, infrared signals, digital signals, etc.). For example, the machine may access the storage device from a medium capable of holding the information to be transmitted in the propagated signal by receiving the propagated signal.

As used herein, "one embodiment" or "one embodiment" includes specific features, structures, or properties described in connection with an embodiment in at least one embodiment of the invention. Means to be. Therefore, the phrases "in one embodiment" or "in one embodiment" that are ubiquitous throughout the specification do not necessarily refer to the same embodiment. Moreover, specific features, structures, or properties may be combined in any suitable manner in one or more embodiments.

In the above specification, details have been described in relation to specific exemplary embodiments. However, it will be clear that various modifications and modifications can be made without departing from the spirit and scope of the invention as set forth in the appended claims. Therefore, the specification and drawings are merely examples and have no limiting meaning. Furthermore, the wording used in the above embodiments and other examples does not necessarily refer to the same embodiment and the same example, but may refer to the same embodiment, but may refer to different distinct embodiments.